MC74VHC4051, MC74VHC4052, MC74VHC4053 Analog Multiplexers / Demultiplexers High−Performance Silicon−Gate CMOS http://onsemi.com The MC74VHC4051, MC74VHC4052 and MC74VHC4053 utilize silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The VHC4051, VHC4052 and VHC4053 are identical in pinout to the high−speed HC4051A, HC4052A and HC4053A, and the metal−gate MC14051B, MC14052B and MC14053B. The Channel−Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel−Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal−gate CMOS analog switches. • Fast Switching and Propagation Speeds • Low Crosstalk Between Switches • Diode Protection on All Inputs/Outputs • Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V • Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V • Improved Linearity and Lower ON Resistance Than Metal−Gate Counterparts • Low Noise • Chip Complexity: VHC4051 — 184 FETs or 46 Equivalent Gates VHC4052 — 168 FETs or 42 Equivalent Gates VHC4053 — 156 FETs or 39 Equivalent Gates • These Devices are Pb−Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2014 September, 2014 − Rev. 7 1 MARKING DIAGRAMS 16 SOIC−16 D SUFFIX CASE 751B 9 VHC405xG AWLYYWW 1 8 16 9 VHC 405x TSSOP−16 DT SUFFIX CASE 948F ALYWG G 1 8 VHC405x = Specific Device Code (x = 1, 2 or 3) A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. Publication Order Number: MC74VHC4051/D MC74VHC4051, MC74VHC4052, MC74VHC4053 13 X0 14 X1 15 X2 ANALOG 12 MULTIPLEXER/ INPUTS/ X3 DEMULTIPLEXER OUTPUTS X4 1 5 X5 2 X6 4 X7 11 A CHANNEL 10 B SELECT 9 INPUTS C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND 3 X COMMON OUTPUT/ INPUT MC74VHC4051 Single−Pole, 8−Position Plus Common Off 12 ANALOG INPUTS/OUTPUTS CHANNEL‐SELECT INPUTS X0 14 X1 15 X2 11 X3 Y0 Y1 Y2 Y3 A B ENABLE 13 X SWITCH X COMMON OUTPUTS/INPUTS 1 5 2 3 Y SWITCH Y 4 10 9 PIN 16 = VCC PIN 7 = VEE PIN 8 = GND 6 MC74VHC4052 Double−Pole, 4−Position Plus Common Off 12 X0 13 X1 14 X SWITCH 2 ANALOG INPUTS/OUTPUTS Y0 1 Y1 15 Y SWITCH 5 Z0 3 Z1 4 Z SWITCH X Y COMMON OUTPUTS/INPUTS Z 11 A 10 B 9 C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND CHANNEL‐SELECT INPUTS NOTE: This device allows independent control of each switch. Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch and Input C controls the Z−Switch MC74VHC4053 Triple Single−Pole, Double−Position Plus Common Off Figure 1. Logic Diagrams http://onsemi.com 2 MC74VHC4051, MC74VHC4052, MC74VHC4053 FUNCTION TABLE − MC74VHC4051 VCC X2 X1 X0 X3 A B C 16 15 14 13 12 11 10 9 1 2 3 4 5 X4 X6 X X7 X5 6 7 Enable VEE Control Inputs Enable C L L L L L L L L H L L L L H H H H X 8 GND Figure 2. Pinout: MC74VHC4051 (Top View) Select B A ON Channels X0 X1 X2 X3 X4 X5 X6 X7 NONE L H L H L H L H X L L H H L L H H X X = Don’t Care VCC X2 X1 X X0 X3 A B 16 15 14 13 12 11 10 9 FUNCTION TABLE − MC74VHC4052 Control Inputs Select 1 2 3 4 5 Y0 Y2 Y Y3 Y1 6 7 Enable VEE 8 GND Enable B A ON Channels L L L L H L L H H X L H L H X Y0 Y1 Y2 Y3 X0 X1 X2 X3 NONE X = Don’t Care Figure 3. Pinout: MC74VHC4052 (Top View) FUNCTION TABLE − MC74VHC4053 VCC Y X X1 X0 A B C 16 15 14 13 12 11 10 9 1 2 3 4 5 Y1 Y0 Z1 Z Z0 6 7 Enable VEE Control Inputs 8 GND Figure 4. Pinout: MC74VHC4053 (Top View) Enable C L L L L L L L L H L L L L H H H H X X = Don’t Care http://onsemi.com 3 Select B A L L H H L L H H X L H L H L H L H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1 MC74VHC4051, MC74VHC4052, MC74VHC4053 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 7.0 – 0.5 to + 14.0 V Negative DC Supply Voltage (Referenced to GND) – 7.0 to + 5.0 V VIS Analog Input Voltage VEE − 0.5 to VCC + 0.5 V Vin Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V ± 25 mA 500 450 mW – 65 to + 150 _C 260 _C VCC Positive DC Supply Voltage VEE I (Referenced to GND) (Referenced to VEE) DC Current, Into or Out of Any Pin PD Power Dissipation in Still Air SOIC Package† TSSOP Package† Tstg Storage Temperature Range TL Lead Temperature, 1 mm from Case for 10 Seconds This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Parameter (Referenced to GND) (Referenced to VEE) Min Max Unit 2.0 2.0 6.0 12.0 V VCC Positive DC Supply Voltage VEE Negative DC Supply Voltage, Output (Referenced to GND) − 6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch 1.2 V – 55 + 125 _C 0 0 0 0 1000 800 500 400 ns TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. *For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. http://onsemi.com 4 MC74VHC4051, MC74VHC4052, MC74VHC4053 DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Symbol Parameter Condition Guaranteed Limit VCC V −55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High−Level Input Voltage, Channel−Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low−Level Input Voltage, Channel−Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V Iin Maximum Input Leakage Current, Channel−Select or Enable Inputs Vin = VCC or GND, VEE = − 6.0 V 6.0 ± 0.1 ± 1.0 ± 1.0 μA ICC Maximum Quiescent Supply Current (per Package) Channel Select, Enable and VEE = GND VIS = VCC or GND; VIO = 0 V VEE = − 6.0 6.0 6.0 1 4 10 40 40 80 μA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS Analog Section Guaranteed Limit Symbol Ron Parameter Maximum “ON” Resistance VCC V VEE V – 55 to 25_C v 85_C v 125_C Unit Vin = VIL or VIH VIS = VCC to VEE IS v 2.0 mA (Figures 5 through 11) 3.0 4.5 4.5 6.0 0.0 0.0 – 4.5 – 6.0 200 160 120 100 240 200 150 125 320 280 170 140 Ω Vin = VIL or VIH VIS = VCC or VEE (Endpoints) IS v 2.0 mA (Figures 5 through11) 3.0 4.5 4.5 6.0 0.0 0.0 – 4.5 – 6.0 150 110 90 80 180 140 120 100 230 190 140 115 3.0 4.5 4.5 6.0 0.0 0.0 – 4.5 – 6.0 40 20 10 10 50 25 15 12 80 40 18 14 Test Conditions ΔRon Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIL or VIH VIS = 1/2 (VCC − VEE) IS v 2.0 mA Ioff Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 12) 6.0 − 6.0 0.1 0.5 1.0 Maximum Off−Channel VHC4051 Vin = VIL or VIH; Leakage Current, VHC4052 VIO = VCC − VEE; Common Channel VHC4053 Switch Off (Figure 13) 6.0 6.0 6.0 − 6.0 − 6.0 − 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Maximum On−Channel VHC4051 Vin = VIL or VIH; Leakage Current, VHC4052 Switch−to−Switch = Channel−to−Channel VHC4053 VCC − VEE; (Figure 14) 6.0 6.0 6.0 − 6.0 − 6.0 − 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Ion μA http://onsemi.com 5 Ω μA MC74VHC4051, MC74VHC4052, MC74VHC4053 AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC V −55 to 25°C ≤85°C ≤125°C Unit Symbol Parameter tPLH, tPHL Maximum Propagation Delay, Channel−Select to Analog Output (Figures 18, 19) 2.0 3.0 4.5 6.0 270 90 59 45 320 110 79 65 350 125 85 75 ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figures 20, 21) 2.0 3.0 4.5 6.0 40 25 12 10 60 30 15 13 70 32 18 15 ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figures 22, 23) 2.0 3.0 4.5 6.0 160 70 48 39 200 95 63 55 220 110 76 63 ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figures 22, 23) 2.0 3.0 4.5 6.0 245 115 49 39 315 145 69 58 345 155 83 67 ns Cin Maximum Input Capacitance, Channel−Select or Enable Inputs 10 10 10 pF CI/O Maximum Capacitance Analog I/O 35 35 35 pF Common O/I: VHC4051 VHC4052 VHC4053 130 80 50 130 80 50 130 80 50 Feedthrough 1.0 1.0 1.0 (All Switches Off) Typical @ 25°C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Figure 25)* VHC4051 VHC4052 VHC4053 * Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . http://onsemi.com 6 45 80 45 pF MC74VHC4051, MC74VHC4052, MC74VHC4053 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) VCC V Symbol Parameter Condition BW Maximum On−Channel Bandwidth or Minimum Frequency Response (Figure 15) fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain 0dBm at VOS; Increase fin Frequency Until dB Meter Reads −3dB; RL = 50Ω, CL = 10pF Off−Channel Feedthrough Isolation (Figure 16) — — Feedthrough Noise. Channel−Select Input to Common I/O (Figure 17) — Crosstalk Between Any Two Switches (Figure 24) (Test does not apply to VHC4051) THD Total Harmonic Distortion (Figure 26) Limit* VEE V 25°C ‘52 ‘53 80 80 80 95 95 95 120 120 120 2.25 4.50 6.00 −2.25 −4.50 −6.00 fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600Ω, CL = 50pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −50 −50 −50 fin = 1.0MHz, RL = 50Ω, CL = 10pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −40 −40 −40 Vin ≤ 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600Ω, CL = 50pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 25 105 135 RL = 10kΩ, CL = 10pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 35 145 190 fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600Ω, CL = 50pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −50 −50 −50 fin = 1.0MHz, RL = 50Ω, CL = 10pF 2.25 4.50 6.00 −2.25 −4.50 −6.00 −60 −60 −60 fin = 1kHz, RL = 10kΩ, CL = 50pF THD = THDmeasured − THDsource VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave VIS = 11.0VPP sine wave Unit ‘51 MHz dB mVPP dB % 2.25 4.50 6.00 −2.25 −4.50 −6.00 0.10 0.08 0.05 *Limits not tested. Determined by design and verified by qualification. 180 160 250 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 300 200 125°C 150 25°C -55°C 100 50 140 120 125°C 100 80 25°C 60 -55°C 40 20 0 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 0 2.25 0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 5. Typical On Resistance, VCC − VEE = 2.0 V Figure 6. Typical On Resistance, VCC − VEE = 3.0 V http://onsemi.com 7 120 105 100 90 80 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) MC74VHC4051, MC74VHC4052, MC74VHC4053 125°C 60 25°C 40 -55°C 20 0 75 125°C 60 25°C 45 -55°C 30 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 4.5 0 0.5 Figure 7. Typical On Resistance, VCC − VEE = 4.5 V 3.0 3.5 4.0 4.5 5.0 5.5 6.0 60 70 60 50 125°C 40 30 25°C 20 -55°C 50 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 2.0 2.5 Figure 8. Typical On Resistance, VCC − VEE = 6.0 V 80 125°C 40 25°C 30 -55°C 20 10 10 0 -4.5 1.0 1.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 4.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 2.0 3.0 4.0 5.0 6.0 Figure 10. Typical On Resistance, VCC − VEE = 12.0 V PLOTTER - 1.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 9. Typical On Resistance, VCC − VEE = 9.0 V PROGRAMMABLE POWER SUPPLY 0 MINI COMPUTER DC ANALYZER + VCC DEVICE UNDER TEST ANALOG IN COMMON OUT VEE GND Figure 11. On Resistance Test Set−Up http://onsemi.com 8 MC74VHC4051, MC74VHC4052, MC74VHC4053 VCC VCC VCC 16 VEE ANALOG I/O OFF A VCC VIH OFF VCC COMMON O/I OFF NC OFF VIH 6 7 8 VEE COMMON O/I 6 7 8 VEE Figure 12. Maximum Off Channel Leakage Current, Any One Channel, Test Set−Up Figure 13. Maximum Off Channel Leakage Current, Common Channel, Test Set−Up VCC VCC VCC 16 A VEE fin COMMON O/I OFF VOS 16 0.1μF ON VCC VCC 16 VEE dB METER ON N/C RL CL* ANALOG I/O VIL 6 7 8 6 7 8 VEE VEE Figure 14. Maximum On Channel Leakage Current, Channel to Channel, Test Set−Up VCC VIS fin VCC dB METER OFF RL Figure 15. Maximum On Channel Bandwidth, Test Set−Up VOS 16 0.1μF *Includes all probe and jig capacitance CL* 16 RL ON/OFF COMMON O/I ANALOG I/O RL OFF/ON RL RL 6 7 8 VEE VIL or VIH VCC GND CHANNEL SELECT Vin ≤ 1 MHz tr = tf = 6 ns 6 7 8 VEE TEST POINT CL* VCC 11 CHANNEL SELECT *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 16. Off Channel Feedthrough Isolation, Test Set−Up Figure 17. Feedthrough Noise, Channel Select to Common Out, Test Set−Up http://onsemi.com 9 MC74VHC4051, MC74VHC4052, MC74VHC4053 VCC VCC 16 VCC CHANNEL SELECT ON/OFF 50% COMMON O/I ANALOG I/O OFF/ON GND tPLH TEST POINT CL* tPHL ANALOG OUT 6 7 8 50% CHANNEL SELECT *Includes all probe and jig capacitance Figure 18. Propagation Delays, Channel Select to Analog Out Figure 19. Propagation Delay, Test Set−Up Channel Select to Analog Out VCC 16 VCC ANALOG IN COMMON O/I ANALOG I/O ON 50% TEST POINT CL* GND tPHL tPLH ANALOG OUT 6 7 8 50% *Includes all probe and jig capacitance Figure 20. Propagation Delays, Analog In to Analog Out tf tr tPZL POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL 2 GND tPLZ HIGH IMPEDANCE 10% VCC VCC 16 1 TEST POINT ON/OFF CL* VOL tPHZ ENABLE VOH 90% 1kΩ ANALOG I/O 2 50% tPZH ANALOG OUT 1 VCC 90% 50% 10% ENABLE ANALOG OUT Figure 21. Propagation Delay, Test Set−Up Analog In to Analog Out 50% 6 7 8 HIGH IMPEDANCE Figure 22. Propagation Delays, Enable to Analog Out Figure 23. Propagation Delay, Test Set−Up Enable to Analog Out http://onsemi.com 10 MC74VHC4051, MC74VHC4052, MC74VHC4053 VCC VIS A VCC 16 RL fin 16 VOS ON/OFF ON COMMON O/I NC ANALOG I/O 0.1μF OFF/ON OFF VEE RL RL CL* RL CL* 6 7 8 VEE VCC 6 7 8 11 CHANNEL SELECT *Includes all probe and jig capacitance Figure 24. Crosstalk Between Any Two Switches, Test Set−Up Figure 25. Power Dissipation Capacitance, Test Set−Up 0 VIS VCC fin ON CL* -20 TO DISTORTION METER -30 -40 dB RL FUNDAMENTAL FREQUENCY -10 VOS 16 0.1μF -50 DEVICE -60 6 7 8 VEE SOURCE -70 -80 -90 *Includes all probe and jig capacitance - 100 1.0 2.0 3.125 FREQUENCY (kHz) Figure 26. Total Harmonic Distortion, Test Set−Up Figure 27. Plot, Harmonic Distortion APPLICATIONS INFORMATION outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC − GND = 2 to 6 volts VEE − GND = 0 to −6 volts VCC − VEE = 2 to 12 volts and VEE ≤ GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 29. These diodes should be able to absorb the maximum anticipated current surges during clipping. The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic high GND = 0V = logic low The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration of Figure 28, a maximum analog signal of ten volts peak−to−peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and http://onsemi.com 11 MC74VHC4051, MC74VHC4052, MC74VHC4053 VCC +5V 16 +5V ANALOG SIGNAL -5V ON 6 7 8 Dx +5V ANALOG SIGNAL VCC 16 Dx Dx VEE VEE 7 8 -5V VEE Figure 28. Application Example Figure 29. External Germanium or Schottky Clipping Diodes +5V +5V 16 +5V ANALOG SIGNAL VEE ON/OFF 6 7 8 VEE Dx ON/OFF -5V TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS 11 10 9 VCC ANALOG SIGNAL +5V * R R 11 10 9 +5V +5V VEE VEE 16 ANALOG SIGNAL ON/OFF +5V ANALOG SIGNAL R VEE +5V 6 7 8 LSTTL/NMOS CIRCUITRY VEE * 2K ≤ R ≤ 10K a. Using Pull−Up Resistors 11 10 9 LSTTL/NMOS CIRCUITRY HCT BUFFER b. Using HCT Interface Figure 30. Interfacing LSTTL/NMOS to CMOS Inputs A 11 13 LEVEL SHIFTER 14 B 10 15 LEVEL SHIFTER 12 C 9 1 LEVEL SHIFTER 5 ENABLE 6 2 LEVEL SHIFTER 4 3 Figure 31. Function Diagram, VHC4051 http://onsemi.com 12 X0 X1 X2 X3 X4 X5 X6 X7 X MC74VHC4051, MC74VHC4052, MC74VHC4053 A 10 12 LEVEL SHIFTER 14 B 9 15 LEVEL SHIFTER 11 13 ENABLE 6 1 LEVEL SHIFTER 5 2 4 3 X0 X1 X2 X3 X Y0 Y1 Y2 Y3 Y Figure 33. Function Diagram, VHC4052 A 11 13 LEVEL SHIFTER 12 14 B 10 1 LEVEL SHIFTER 2 15 C 9 3 LEVEL SHIFTER 5 4 ENABLE 6 LEVEL SHIFTER Figure 32. Function Diagram, VHC4053 http://onsemi.com 13 X1 X0 X Y1 Y0 Y Z1 Z0 Z MC74VHC4051, MC74VHC4052, MC74VHC4053 ORDERING & SHIPPING INFORMATION Device Package Shipping† SOIC−16 (Pb−Free) 2500 / Tape & Reel TSSOP−16 (Pb−Free) 2500 / Tape & Reel MC74VHC4051DR2G MC74VHC4052DR2G MC74VHC4053DR2G MC74VHC4051DTR2G MC74VHC4052DTR2G MC74VHC4053DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 14 MC74VHC4051, MC74VHC4052, MC74VHC4053 PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 1 8 −B− P 8 PL 0.25 (0.010) B M S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS http://onsemi.com 15 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC74VHC4051, MC74VHC4052, MC74VHC4053 PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 SECTION N−N B −U− L J PIN 1 IDENT. N 0.25 (0.010) 8 1 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DETAIL E G SOLDERING FOOTPRINT DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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