Octal, 16-Bit nanoDAC+ with I2C Interface AD5675 Data Sheet FEATURES GENERAL DESCRIPTION High performance High relative accuracy (INL): ±3 LSB maximum at 16 bits Total unadjusted error (TUE): ±0.14% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.06% of FSR maximum Wide operating ranges −40°C to +125°C temperature range 2.7 V to 5.5 V power supply Easy implementation User selectable gain of 1 or 2 (GAIN pin/bit) 1.8 V logic compatibility I2C-compatible serial interface Robust 2 kV HBM and 1.5 kV FICDM ESD rating 20-lead TSSOP and LFCSP RoHS-compliant packages The AD5675 is a low power, octal, 16-bit buffered voltage output digital-to-analog converter (DAC). The device includes a gain select pin, giving a full-scale output of VREF (gain = 1) or 2 × VREF (gain = 2). The device operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. The AD5675 is available in 20-lead TSSOP and LFCSP packages. The power-on reset circuit and a RSTSEL pin ensure that the output DACs power up to zero scale or midscale and remain there until a valid write takes place. The AD5675 contains a power-down mode, reducing the current consumption to 1 µA typical while in power-down mode. The AD5675 uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz, and includes a VLOGIC pin intended for 1.8 V to 5.5 V logic. Table 1. Octal nanoDAC+® Devices APPLICATIONS Interface SPI Optical transceivers Base station power amplifiers Process control (PLC input/output cards) Industrial automation Data acquisition systems Reference Internal External Internal I2C 16-Bit AD5676R AD5676 AD5675R 12-Bit AD5672R Not applicable AD5671R FUNCTIONAL BLOCK DIAGRAM VLOGIC VREF VDD AD5675 2.5V REF DAC REGISTER STRING DAC 0 INPUT REGISTER DAC REGISTER STRING DAC 1 INPUT REGISTER DAC REGISTER STRING DAC 2 INPUT REGISTER DAC REGISTER STRING DAC 3 INPUT REGISTER DAC REGISTER STRING DAC 4 A0 INPUT REGISTER DAC REGISTER STRING DAC 5 LDAC INPUT REGISTER DAC REGISTER STRING DAC 6 RESET INPUT REGISTER DAC REGISTER STRING DAC 7 SDA A1 INTERFACE LOGIC SCL BUFFER VOUT0 BUFFER VOUT1 BUFFER VOUT2 BUFFER VOUT3 BUFFER VOUT4 BUFFER VOUT5 BUFFER VOUT6 BUFFER VOUT7 GAIN ×1/×2 POWER-ON RESET RSTSEL GAIN POWER-DOWN LOGIC GND 12550-001 INPUT REGISTER Figure 1. Rev. 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Technica l Support www.analog.com AD5675* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Design Resources View a parametric search of comparable parts • AD5675 and AD5676R Evaluation Board • • • • Documentation Discussions Data Sheet View all AD5675 EngineerZone Discussions Evaluation Kits • AD5675: Octal, 16-Bit nanoDAC+ with I2C Interface Data Sheet User Guides • UG-815: Evaluating the AD5675/AD5675R Octal, 16-Bit nanoDAC+ Tools and Simulations AD5675 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number • AD5675/AD5675R IBIS Model * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. 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AD5675 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 I2C Slave Address ........................................................................ 20 Applications ....................................................................................... 1 Serial Operation ......................................................................... 20 General Description ......................................................................... 1 Write Operation.......................................................................... 20 Functional Block Diagram .............................................................. 1 Read Operation........................................................................... 21 Revision History ............................................................................... 2 Multiple DAC Readback Sequence .......................................... 21 Specifications..................................................................................... 3 Power-Down Operation ............................................................ 22 AC Characteristics........................................................................ 5 Load DAC (Hardware LDAC Pin) ........................................... 22 Timing Characteristics ................................................................ 5 LDAC Mask Register ................................................................. 23 Absolute Maximum Ratings............................................................ 7 Hardware Reset (RESET) .......................................................... 24 Thermal Resistance ...................................................................... 7 Reset Select Pin (RSTSEL) ........................................................ 24 ESD Caution .................................................................................. 7 Amplifier Gain Selection on LFCSP Package ......................... 24 Pin Configuration and Function Descriptions ............................. 8 Applications Information .............................................................. 25 Typical Performance Characteristics ........................................... 10 Power Supply Recommendations............................................. 25 Terminology .................................................................................... 16 Microprocessor Interfacing ....................................................... 25 Theory of Operation ...................................................................... 18 AD5675 to ADSP-BF531 Interface ........................................... 25 Digital-to-Analog Converter .................................................... 18 Layout Guidelines....................................................................... 25 Transfer Function ....................................................................... 18 Galvanically Isolated Interface ................................................. 25 DAC Architecture ....................................................................... 18 Outline Dimensions ....................................................................... 26 Serial Interface ............................................................................ 19 Ordering Guide .......................................................................... 26 Write and Update Commands .................................................. 20 REVISION HISTORY 8/2016—Rev. A to Rev. B Change to Output Noise Spectral Density Parameter; Table 3... 5 10/2015—Rev. 0 to Rev. A Added 20-Lead LFCSP....................................................... Universal Changes to Features Section and General Description Section ... 1 Changes to Table 2 ............................................................................ 3 Change to Table 5 ............................................................................. 7 Added Table 6; Renumbered Sequentially .................................... 9 Change to Figure 4 Caption and Table 6 Title .............................. 8 Added Figure 5; Renumbered Sequentially and Table 7 ............. 9 Change to Figure 19 Caption ........................................................ 12 Change to Figure 33 ....................................................................... 14 Change to Table 8 ........................................................................... 19 Change to Read Operation Section.............................................. 21 Changes to LDAC Mask Register Section and Table 13 ............... 23 Added Amplifier Gain Selection on LFCSP Package Section, Table 15, and Table 16 .................................................................... 24 Added Figure 52, Outline Dimensions ........................................ 26 Changes to Ordering Guide .......................................................... 26 1/2015—Revision 0: Initial Version Rev. B | Page 2 of 26 Data Sheet AD5675 SPECIFICATIONS VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications TA = −40°C to +125°C, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 1 Resolution Relative Accuracy/Integral Nonlinearity (INL) 2 Min 16 Differential Nonlinearity (DNL)2 Zero Code Error 2 Offset Error 2 Full-Scale Error 2 Gain Error 2 TUE Offset Error Drift 2, 3 DC Power Supply Rejection Ratio (PSRR)2, 3 DC Crosstalk2, 3 OUTPUT CHARACTERISTICS3 Output Voltage Range Reference Input Impedance B Grade Typ Max 16 Unit Test Conditions/Comments ±8 ±1.8 ±3 Bits LSB Gain = 1 ±1.7 ±0.7 ±8 ±1 ±1.7 ±0.7 ±3 ±1 LSB LSB Gain = 2 Gain = 1 ±0.5 0.8 −0.75 −0.1 −0.018 −0.013 +0.04 −0.02 ±0.03 ±0.006 ±1 0.25 ±1 4 ±6 ±4 ±0.28 ±0.14 ±0.24 ±0.12 ±0.3 ±0.25 ±0.5 0.8 −0.75 −0.1 −0.018 −0.013 +0.04 −0.02 ±0.03 ±0.006 ±1 0.25 ±1 1.6 ±2 ±1.5 ±0.14 ±0.07 ±0.12 ±0.06 ±0.18 ±0.14 LSB mV mV mV % of FSR % of FSR % of FSR % of FSR % of FSR % of FSR µV/°C mV/V Gain = 2 Gain = 1 or gain = 2 Gain = 1 Gain = 2 Gain = 1 Gain = 2 Gain = 1 Gain = 2 Gain = 1 Gain = 2 Due to single channel, full-scale output change Due to load current change Due to powering down (per channel) ±2 ±2 µV ±3 ±2 ±3 ±2 µV/mA µV VREF 2 × VREF 15 0 0 VREF 2 × VREF 15 DAC code = midscale, VDD = 5 V ± 10% 183 183 V V mA nF nF kΩ µV/mA 177 177 µV/mA 40 25 2.5 40 25 2.5 mA Ω µs Exiting power-down mode, VDD = 5 V 398 789 398 789 µA µA V V kΩ kΩ VREF = VDD = VLOGIC = 5.5 V, gain = 1 VREF = VDD = VLOGIC = 5.5 V, gain = 2 Gain = 1 Gain = 2 Gain = 1 Gain = 2 2 10 2 10 1 Short-Circuit Current 5 Load Impedance at Rails 6 Power-Up Time REFERENCE INPUT Reference Input Current Reference Input Range Min ±1.8 0 0 Output Current Drive Capacitive Load Stability Resistive Load 4 Load Regulation A Grade Typ Max 1 1 1 VDD VDD /2 14 7 1 1 VDD VDD /2 14 7 Rev. B | Page 3 of 26 Gain = 1 Gain = 2 RL = ∞ RL = 1 kΩ VDD = 5 V ± 10%, DAC code = midscale, −30 mA ≤ I OUT ≤ +30 mA VDD = 3 V ± 10%, DAC code = midscale, −20 mA ≤ I OUT ≤ +20 mA AD5675 Parameter LOGIC INPUTS3 Input Current Input Voltage Low, VINL High, VINH Pin Capacitance LOGIC OUTPUTS (SDA)3 Output Voltage Low, VOL High, VOH Floating State Output Capacitance POWER REQUIREMENTS VLOGIC I LOGIC VDD I DD Normal Mode 7 All Power-Down Modes 8 Data Sheet Min A Grade Typ Max Min B Grade Typ Max Per pin ±1 µA 0.3 × VLOGIC 0.3 × VLOGIC V 0.7 × VLOGIC 3 V 3 0.4 VLOGIC − 0.4 pF 0.4 VLOGIC − 0.4 4 4 5.5 3 3 3 3 5.5 5.5 2.7 VREF + 1.5 Test Conditions/Comments ±1 0.7 × VLOGIC 1.8 Unit 1.8 2.7 VREF + 1.5 V V pF 5.5 3 3 3 3 5.5 5.5 V µA µA µA µA V V 1.1 1.1 1 1 1 1 1.26 1.3 1.7 1.7 2.5 2.5 1.1 1.1 1 1 1 1 1.26 1.3 1.7 1.7 2.5 2.5 mA mA µA µA µA µA 1 1 5.5 5.5 1 1 5.5 5.5 µA µA 1 I SINK = 200 μA I SOURCE = 200 μA Power-on, −40°C to +105°C Power-on, −40°C to +125°C Power-down, −40°C to +105°C Power-down, −40°C to +125°C Gain = 1 Gain = 2 VIH = VDD , VIL = GND, VDD = 2.7 V to 5.5 V −40°C to +85°C −40°C to +125°C Tristate to 1 kΩ, −40°C to +85°C Power down to 1 kΩ, −40°C to +85°C Tristate to 1 kΩ, −40°C to +105°C Power down to 1 kΩ, −40°C to +105°C Tristate to 1 kΩ, −40°C to +125°C Power down to 1 kΩ, −40°C to +125°C DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280. 2 See the Terminology section. 3 Guaranteed by design and characterization; not production tested. 4 Together, Channel 0, Channel 1, Channel 2, and Channel 3 can source or sink 40 mA. Similarly, together, Channel 4, Channel 5, Channel 6, and Channel 7 can source or sink 40 mA up to a junction temperature of 125°C. 5V DD = 5 V. The AD5675 includes current limiting to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. Operation above the specified maximum operation junction temperature may impair device reliability. 6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV. 7 Interface inactive. All DACs active. DAC outputs unloaded. 8 All DACs powered down. Rev. B | Page 4 of 26 Data Sheet AD5675 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 1.8 V ≤ VLOGIC ≤ 5.5 V, all specifications TA = −40°C to +125°C, unless otherwise noted. Guaranteed by design and characterization; not production tested. Table 3. Parameter Output Voltage Settling Time 1 Slew Rate Digital-to-Analog Glitch Impulse 1 Digital Feedthrough1 Digital Crosstalk1 Analog Crosstalk1 Min DAC-to-DAC Crosstalk1 Total Harmonic Distortion (THD)1, 2 Output Noise Spectral Density (NSD)1 Output Noise Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Signal-to-Noise-and-Distortion Ratio (SINAD) Typ 5 0.8 1.4 0.13 0.1 −0.25 −1.3 −2.0 −80 80 6 90 83 80 Max 8 Unit µs V/µs nV-sec nV-sec nV-sec nV-sec nV-sec nV-sec dB nV/√Hz µV p-p dB dB dB Test Conditions/Comments ¼ to ¾ scale settling to ±2 LSB 1 LSB change around major carry (gain = 1) Gain = 1 Gain = 2 Gain = 2 TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz DAC code = midscale, bandwidth = 10 kHz, gain = 1 and 2 0.1 Hz to 10 Hz, gain = 1 TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz 1 See 2 the Terminology section. Digitally generated sine wave at 1 kHz. TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, all specifications −40°C to +125°C, unless otherwise noted. Table 4. Parameter 1, 2 t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t 10 4 t 11 4, 5 t 12 Min 0.92 0.11 0.44 0.04 40 −0.04 −0.045 0.195 0.12 0 20 + 0.1 CB 20 t 13 t 14 t 15 t SP 6 CB5 Max Unit µs µs µs µs ns µs µs µs µs ns ns ns Description SCL cycle time t HIGH , SCL high time t LOW, SCL low time t HD,STA, start/repeated start hold time t SU,DAT, data setup time t HD,DAT, data hold time t SU,STA, repeated start setup time t SU,STO, stop condition setup time t BUF, bus free time between a stop condition and a start condition t R, rise time of SCL and SDA when receiving t F, fall time of SCL and SDA when transmitting/receiving LDAC pulse width 0.4 4.8 ns ns 6.2 132 ns ns SCL rising edge to LDAC rising edge RESET minimum pulse width low, 1.8 V ≤ VLOGIC ≤ 2.7 V RESET minimum pulse width low, 2.7 V ≤ VLOGIC ≤ 5.5 V RESET activation time, 1.8 V ≤ VLOGIC ≤ 2.7 V 80 0 ns ns pF RESET activation time, 2.7 V ≤ VLOGIC ≤ 5.5 V Pulse width of suppressed spike Capacitive load for each bus line 400 1 See Figure 2 and Figure 3. Guaranteed by design and characterization; not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the minimum VIH of the SCL signal) to bridge the undefined region of the SCL falling edge. 4 t and t are measured from 0.3 × V R F DD to 0.7 × VDD. 5 C is the total capacitance of one bus line in picofarads. B 6 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns. 2 Rev. B | Page 5 of 26 AD5675 Data Sheet Timing Diagrams START CONDITION REPEATED START CONDITION STOP CONDITION SDA t9 t10 t11 t4 t3 SCL t4 t2 t6 t5 t7 t1 t8 t12 t13 LDAC1 t12 LDAC2 12550-002 NOTES 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. Figure 2. Two-Wire Serial Interface Timing Diagram VOUTx t14 t15 12550-102 RESET Figure 3. RESET Timing Diagram Rev. B | Page 6 of 26 Data Sheet AD5675 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 5. The design of the thermal board requires close attention. Thermal resistance is highly impacted by the printed circuit board (PCB) being used, layout, and environmental conditions. Parameter VDD to GND VLOGIC to GND VOUTx to GND VREF to GND Digital Input Voltage to GND Operating Temperature Range Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb-Free (J-STD-020) ESD Ratings Human Body Model (HBM) Field Induced Charged Device Model (FICDM) Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VLOGIC + 0.3 V −40°C to +125°C −65°C to +150°C 125°C 260°C 2 kV 1.5 kV Table 6. Thermal Resistance Package Type 20-Lead TSSOP (RU-20)1 20-Lead LFCSP (CP-20-8)2 1 θJA 98.65 θJB 44.39 θJC 17.58 ΨJT 1.77 ΨJB 43.9 Unit 82 16.67 32.5 0.43 22 °C/W °C/W Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD51 2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with nine thermal vias. See JEDEC JESD51. ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 7 of 26 AD5675 Data Sheet VOUT1 1 20 VOUT2 VOUT0 2 19 VOUT3 VDD 3 18 VREF VLOGIC 4 17 RESET SCL 5 A0 6 A1 AD5675 16 SDA 15 LDAC 7 14 RSTSEL GAIN 8 13 GND VOUT7 9 12 VOUT4 VOUT6 10 11 VOUT5 TOP VIEW (Not to Scale) 12550-006 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. TSSOP Pin Configuration Table 7. TSSOP Pin Function Descriptions Pin No. 1 2 3 Mnemonic VOUT1 VOUT0 VDD 4 5 VLOGIC SCL 6 7 8 A0 A1 GAIN 9 10 11 12 13 14 VOUT7 VOUT6 VOUT5 VOUT4 GND RSTSEL 15 LDAC 16 SDA 17 RESET 18 19 20 VREF VOUT3 VOUT2 Description Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation. Power Supply Input. The AD5675 operates from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V. Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 24-bit input shift register. Address Input. This pin sets the first LSB of the 7-bit slave address. Address Input. This pin sets the second LSB of the 7-bit slave address. Span Set. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF. Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Device. Power-On Reset. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to power up all eight DACs to midscale. Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data, which allows all DAC outputs to simultaneously update. This pin can also be tied permanently low. Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift register. SDA is a bidirectional, open-drain data line that must be pulled to the supply with an external pull-up resistor. Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. Reference Input Voltage. Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation. Rev. B | Page 8 of 26 AD5675 20 19 18 17 16 VOUT0 VOUT1 VOUT2 VOUT3 NIC Data Sheet 1 2 3 4 5 AD5675 TOP VIEW (Not to Scale) 15 14 13 12 11 VREF RESET SDA LDAC GND NOTES 1. NIC = NO INTERNAL CONNECTION. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE TIED TO GND. 12550-005 VOUT7 VOUT6 VOUT5 VOUT4 NIC 6 7 8 9 10 VDD VLOGIC SCL A0 A1 Figure 5. LFCSP Pin Configuration Table 8. LFCSP Function Descriptions Pin No. 1 Mnemonic VDD 2 3 VLOGIC SCL 4 5 6 7 8 9 10, 16 11 12 A0 A1 VOUT7 VOUT6 VOUT5 VOUT4 NIC GND LDAC 13 SDA 14 RESET 15 17 18 19 20 VREF VOUT3 VOUT2 VOUT1 VOUT0 EPAD Description Power Supply Input. The AD5675 operates from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V. Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 24-bit input shift register. Address Input. Sets the first LSB of the 7-bit slave address. Address Input. Sets the second LSB of the 7-bit slave address. Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation. No Internal Connection. Ground Reference Point for All Circuitry on the Device. Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data, which allows all DAC outputs to simultaneously update. This pin can also be tied permanently low. Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift register. SDA is a bidirectional, open-drain data line that must be pulled to the supply with an external pull-up resistor. Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. Reference Input Voltage. Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation. Exposed Pad. The exposed pad must be tied to GND. Rev. B | Page 9 of 26 AD5675 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 10 2.0 8 1.5 6 INL ERROR (LSB) INL ERROR (LSB) 1.0 0.5 0 –0.5 4 2 0 –2 –4 –1.0 10000 20000 30000 40000 50000 60000 70000 CODE VDD = 5V TA = 25°C –10 –40 –20 0.8 8 0.6 6 DNL ERROR (LSB) 0.4 0.2 0 –0.2 100 120 100 120 100 120 0 –2 –0.6 –6 –0.8 –8 –1.0 –10 –40 50000 80 4 –4 30000 40000 CODE 60 2 –0.4 60000 70000 12550-009 DNL ERROR (LSB) 10 20000 40 Figure 9. INL Error vs. Temperature 1.0 10000 20 TEMPERATURE (°C) Figure 6. INL Error vs. Code 0 0 VDD = 5V TA = 25°C 0 –20 20 40 60 80 TEMPERATURE (°C) Figure 7. DNL Error vs. Code 12550-015 0 12550-007 –2.0 –8 12550-013 –6 –1.5 Figure 10. DNL Error vs. Temperature 0.10 0.04 0.09 0.08 0.07 TUE (% OF FSR) 0.02 0.01 0 0.06 0.05 0.04 VDD = 5V TA = 25°C 0.03 0.02 –0.01 –0.02 0 10000 20000 30000 40000 CODE 50000 60000 70000 Figure 8. TUE vs. Code 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 11. TUE vs. Temperature Rev. B | Page 10 of 26 12550-017 0.01 12550-011 TUE (% OF FSR) 0.03 AD5675 10 0.10 8 0.08 6 0.06 4 0.04 ERROR (% OF FSR) 2 0 –2 –4 –6 –0.04 3.2 3.7 4.2 4.7 5.2 –0.10 –40 0 20 40 60 80 100 120 Figure 15. Gain Error and Full-Scale Error vs. Temperature 10 0.10 8 0.08 6 0.06 4 0.04 ERROR (% OF FSR) DNL ERROR (LSB) –20 TEMPERATURE (°C) Figure 12. INL Error vs. Supply Voltage 2 0 –2 –4 VDD = 5V TA = 25°C 0.02 GAIN ERROR 0 –0.02 FULL-SCALE ERROR –0.04 –0.06 –0.08 –8 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) VDD = 5V TA = 25°C –0.10 2.7 3.2 12550-027 –10 2.7 VDD = 5V TA = 25°C –0.08 SUPPLY VOLTAGE (V) –6 GAIN ERROR –0.02 12550-031 –10 2.7 FULL-SCALE ERROR 0 –0.06 VDD = 5V TA = 25°C 12550-025 –8 0.02 3.7 4.2 4.7 12550-033 INL ERROR (LSB) Data Sheet 5.2 SUPPLY VOLTAGE (V) Figure 13. DNL Error vs. Supply Voltage Figure 16. Gain Error and Full-Scale Error vs. Supply Voltage 0.10 1.8 0.08 1.5 VDD = 5V TA = 25°C 0.06 1.2 ERROR (mV) 0.02 0 –0.02 ZERO CODE ERROR 0.9 0.6 OFFSET ERROR 0.3 –0.04 0 VDD = 5V TA = 25°C –0.3 –0.08 –0.10 2.7 3.2 3.7 4.2 4.7 SUPPLY VOLTAGE (V) 5.2 Figure 14. TUE vs. Supply Voltage –0.6 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 Figure 17. Zero Code Error and Offset Error vs. Temperature Rev. B | Page 11 of 26 12550-035 –0.06 12550-029 TUE (% OF FSR) 0.04 AD5675 Data Sheet 1.5 6 0xFFFF 5 1.0 ZERO CODE ERROR 4 0xC000 0.5 ERROR (mV) 3 VOUT (V) OFFSET ERROR 0 0x8000 2 0x4000 1 –0.5 0x0000 0 VDD = 5V TA = 25°C 3.2 3.7 4.2 4.7 –2 –0.06 12550-037 –1.5 2.7 –1 5.2 SUPPLY VOLTAGE (V) 100 –0.02 0 0.02 0.04 0.06 LOAD CURRENT (A) Figure 18. Zero Code Error and Offset Error vs. Supply Voltage 120 –0.04 12550-042 –1.0 Figure 21. Source and Sink Capability at 5 V 4.0 VDD = 5V TA = 25°C REFERENCE = 2.5V 3.5 3.0 VOUT (V) HITS 0xFFFF 2.5 80 60 2.0 0xC000 1.5 0x8000 1.0 0x4000 40 0.5 0x0000 0 20 0.85 0.87 0.89 0.91 0.93 0.95 0.97 0.99 1.01 IDD FULL SCALE (mA) –1.0 –0.06 12550-023 0.83 Figure 19. Supply Current (IDD) Histogram –0.02 0 0.02 LOAD CURRENT (A) 0.04 0.06 Figure 22. Source and Sink Capability at 3 V 1.4 1.6 1.0 SINKING, VDD = –2.7V SINKING, VDD = –3.0V SINKING, VDD = –5.0V SOURCING, VDD = –5.0V SOURCING, VDD = –3.0V SOURCING, VDD = –2.7V 0.6 DEVICE 1 DEVICE 2 DEVICE 3 1.5 1.4 IDD (mA) 0.2 –0.2 1.3 1.2 –0.6 –1.4 0 0.005 0.010 0.015 0.020 0.025 0.030 LOAD CURRENT (A) Figure 20. Headroom/Footroom (ΔVOUT) vs. Load Current 1.0 0 10000 20000 30000 40000 CODE 50000 60000 Figure 23. Supply Current (IDD) vs. Code Rev. B | Page 12 of 26 70000 12550-044 1.1 –1.0 12550-041 ΔVOUT (V) –0.04 12550-043 –0.5 0 Data Sheet AD5675 2.0 2.0 1.8 1.8 FULL SCALE 1.6 1.6 DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 1.4 VOUT (V) IDD (mA) 1.4 ZERO CODE 1.2 0.8 EXTERNAL REFERENCE, FULL SCALE 1.0 1.2 1.0 0.6 0.8 0.4 0.2 20 40 60 80 100 TEMPERATURE (°C) 120 0 80 6 1.8 5 1.6 180 200 0.006 0.005 VDD (V) VOUT0 (V) VOUT1 (V) VOUT2 (V) VOUT3 (V) VOUT4 (V) VOUT5 (V) VOUT6 (V) VOUT7 (V) 4 FULL SCALE VDD (V) 1.4 IDD (mA) 160 Figure 27. Full-Scale Settling Time 2.0 ZERO CODE 3 2 EXTERNAL REFERENCE, FULL SCALE 1.0 140 TIME (µs) Figure 24. Supply Current (IDD) vs. Temperature 1.2 120 100 0.004 0.003 0.002 1 0.001 0 0 VOUT (V) 0 –20 12550-045 0.4 –40 VDD = 5.5V GAIN = 1 1/4 TO 3/4 SCALE 12550-048 0.6 0.8 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V) –1 0 2 4 6 –0.001 10 8 12550-049 0.4 2.7 12550-046 0.6 TIME (ms) Figure 28. Power-On Reset to 0 V and Midscale Figure 25. Supply Current (IDD) vs. Supply Voltage 3.0 2.2 2.0 MIDSCALE, GAIN = 2 2.5 FULL SCALE 1.8 VOUT (V) 2.0 1.4 ZERO CODE 1.2 EXTERNAL REFERENCE, FULL SCALE 1.0 RESET 1.5 MIDSCALE, GAIN = 1 1.0 0.8 0.5 0.6 VDD = 5V TA = 25°C 3.2 3.7 4.2 4.7 5.2 INPUT LOGIC VOLTAGE (V) 0 –5 0 5 TIME (µs) Figure 29. Exiting Power-Down to Midscale Figure 26. Supply Current (IDD) vs. Input Logic Voltage Rev. B | Page 13 of 26 10 12550-050 0.4 2.7 12550-047 IDD (mA) 1.6 AD5675 Data Sheet 0.004 0.003 0.002 1 VOUT (V) 0.001 0 VDD = 5V GAIN = 1 TA = 25°C REFERENCE = 2.5V CODE = 7FFF TO 8000 ENERGY = 1.209376nV-sec –0.003 –0.004 15 16 17 18 20 19 2 22 21 TIME (µs) 12550-051 –0.002 CH1 5µV M1.00s A CH1 401mV 12550-054 –0.001 Figure 33. 0.1 Hz to 10 Hz Output Noise Plot Figure 30. Digital-to-Analog Glitch Impulse 1200 0.003 VDD = 5V TA = 25°C GAIN = 1 FULL SCALE MIDSCALE ZERO SCALE 0.002 1000 0.001 800 NSD (nV/√Hz) VOUT (V) 0 –0.001 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 –0.002 –0.003 –0.004 600 400 200 0 2 4 6 8 10 12 14 16 18 20 TIME (µs) 0 10 12550-052 –0.006 Figure 31. Analog Crosstalk 1M Figure 34. Noise Spectral Density (NSD) 0 0.012 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 0.010 0.008 0.006 VDD = 5V TA = 25°C –20 –40 –60 THD (dBV) 0.004 0.002 0 –0.002 –80 –100 –120 –0.004 –140 –0.006 –0.010 0 2 4 6 8 10 12 14 TIME (µs) 16 18 20 –180 0 2 4 6 8 10 12 14 16 18 FREQUENCY (kHz) Figure 35. Total Harmonic Distortion (THD) at 1 kHz Figure 32. DAC-to-DAC Crosstalk Rev. B | Page 14 of 26 20 12550-056 –160 –0.008 12550-053 VOUT (V) 100k 1k 10k FREQUENCY (Hz) 100 12550-055 –0.005 Data Sheet AD5675 2.0 3 0.3 2 0.2 1.9 VOUT (V) 1.6 VOUT AT MIDSCALE (V) CL = 0nF CL = 0.1nF CL = 1nF CL = 4.7nF CL = 10nF 1.7 1.5 1.4 1.3 RESET MIDSCALE, GAIN = 1 0.1 1 VOUT AT ZERO SCALE (V) 1.8 1.2 1.1 ZERO SCALE, GAIN = 1 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20 TIME (ms) 0 0 60 40 TIME (µs) Figure 36. Settling Time vs. Capacitive Load Figure 38. Hardware Reset 2.0 4.0 1.8 3.5 3.0 1.6 DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 1.0 0.8 2.0 0xC000 1.5 0x8000 1.0 0x4000 0.5 0.4 0 0.2 –0.5 0 80 100 120 140 160 TIME (µs) 180 200 12550-058 0.6 Figure 37. Settling Time, 5.5 V –1.0 –0.06 0x0000 –0.04 –0.02 0 0.02 LOAD CURRENT (A) Figure 39. Multiplying Bandwidth Rev. B | Page 15 of 26 0.04 0.06 12550-043 1.2 0xFFFF 2.5 VOUT (V) 1.4 VOUT (V) 20 12550-059 0.11 0 –20 12550-057 1.0 0.10 AD5675 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For a DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Zero Code Error Zero code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. The ideal output is 0 V. The zero code error is always positive because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero code error is expressed in mV. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. The ideal output is VDD − 1 LSB. Full-scale error is expressed in percent of full-scale range (% of FSR). Gain Error Gain error is a measure of the span error of a DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % of FSR. Offset Error Drift Offset error drift is a measurement of the change in offset error with a change in temperature. It is expressed in µV/°C. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured with Code 256 loaded in the DAC register. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) The dc PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for the full-scale output of the DAC. It is measured in mV/V. VREF is held at 2 V, and VDD is varied by ±10%. Output Voltage Settling Time The output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Noise Spectral Density (NSD) NSD is a measurement of the internally generated random noise. Random noise is characterized as spectral density (nV/√Hz). To measure NSD, load the DAC to midscale and measure the noise at the output. It is measured in nV/√Hz. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has on another DAC kept at midscale. It is expressed in μV/mA. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-sec. Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. To measure analog crosstalk, first load one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). Then, execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa), using the write to and update commands while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-sec. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). Rev. B | Page 16 of 26 Data Sheet AD5675 Multiplying Bandwidth The multiplying bandwidth is a measure of the finite bandwidth of the amplifiers within the DAC. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. THD is measured in dB. Rev. B | Page 17 of 26 AD5675 Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER VREF The AD5675 is an octal, 16-bit, serial input, voltage output DAC. The AD5675 operates from a supply voltage of 2.7 V to 5.5 V. Data is written to the AD5675 in a 24-bit word format via a 2-wire serial interface. The AD5675 incorporates a power-on reset circuit to ensure that the DAC output powers up to a known output state. The device also has a software power-down mode that reduces the typical current consumption to 1 µA. R R R TO OUTPUT AMPLIFIER TRANSFER FUNCTION The gain of the output amplifier is set to ×1 or ×2 using the gain select pin (GAIN). When the gain select pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. When the gain select pin is tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF. R 12550-067 R DAC ARCHITECTURE The AD5675 implements a segmented string DAC architecture with an internal output buffer. Figure 40 shows the internal block diagram. VREF REF (+) DAC REGISTER RESISTOR STRING REF (–) GND VOUTx GAIN (GAIN = 1 OR 2) 12550-144 INPUT REGISTER Figure 40. Single DAC Channel Architecture Block Diagram The simplified segmented resistor string DAC structure is shown in Figure 41. The code loaded to the DAC register determines the node on the string where the voltage is tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches and connecting the string to the amplifier. Because each resistance in the string has the same value, R, the string DAC is guaranteed monotonic. Figure 41. Resistor String Structure Output Amplifier The output buffer amplifier generates rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. The actual range depends on the value of VREF, the GAIN pin, the offset error, and the gain error. The GAIN pin selects the gain of the output. If the GAIN pin is tied to GND, all eight outputs have a gain of 1, and the output range is 0 V to VREF. If the GAIN pin is tied to VLOGIC, all eight outputs have a gain of 2, and the output range is 0 V to 2 × VREF. This amplifier can drive a load of 1 kΩ in parallel with 10 nF to GND. The slew rate is 0.8 V/µs with a typical ¼ to ¾ scale settling time of 5 µs. Rev. B | Page 18 of 26 Data Sheet AD5675 SERIAL INTERFACE Table 9. Command Definitions Command The AD5675 uses a 2-wire, I C-compatible serial interface. The device can be connected to an I2C bus as a slave device under the control of the master devices. The AD5675 supports standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. 2 C3 0 0 C2 0 0 C1 0 0 C0 0 1 0 0 1 0 The data-word comprises a 16-bit input code (see Figure 42). These data bits are transferred to the input register on the 24 falling edges of SCL. 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 Commands execute on individual DAC channels, combined DAC channels, or on all DACs, depending on the address bits selected. 1 0 1 1 1 … 1 1 … 1 0 … 1 0 … 1 Input Shift Register The input shift register of the AD5675 is 24 bits wide. Data is loaded MSB first (DB23), and the first four bits are the command bits, C3 to C0 (see Table 9), followed by the 4-bit DAC address bits, A3 to A0 (see Table 10), and finally, the 16bit data-word. Description No operation Write to Input Register n (where n = 0 to 7, depending on the DAC selected from the address bits in Table 10, dependent on LDAC ) Update DAC Register n with the contents of Input Register n Write to and update DAC Channel n Power down/power up the DAC Hardware LDAC mask register Software reset (power-on reset) Gain setup register (LFCSP package only) Reserved Reserved Update all channels of the input register simultaneously with the input data Update all channels of the DAC register and input register simultaneously with the input data Reserved Reserved Table 10. Address Commands A3 0 0 0 0 0 0 0 0 A0 0 1 0 1 0 1 0 1 Selected DAC Channel DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 C3 C2 C1 COMMAND C0 A3 A2 A1 DAC ADDRESS COMMAND BYTE A0 D15 D14 D13 D12 D11 D10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE Figure 42. Input Shift Register Content Rev. B | Page 19 of 26 12550-302 Channel Address, Bits[3:0] A2 A1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 AD5675 Data Sheet WRITE AND UPDATE COMMANDS SERIAL OPERATION Write to Input Register n (Dependent on LDAC) The 2-wire I2C serial bus protocol operates as follows: Command 0001 allows the user to write to the dedicated input register of each DAC individually. When LDAC is low, the input register is transparent, if not controlled by the LDAC mask register. 1. Update DAC Register n with Contents of Input Register n 2. Command 0010 loads the DAC registers and outputs with the contents of the selected input registers and updates the DAC outputs directly. Write to and Update DAC Channel n (Independent of LDAC) 3. Command 0011 allows the user to write to the DAC registers and updates the DAC outputs directly. I2C SLAVE ADDRESS 4. The AD5675 has a 7-bit I2C slave address. The five MSBs are 00011, and the two LSBs (A1 and A0) are set by the state of the A1 and A0 address pins. The ability to make hardwired changes to A1 and A0 allows the user to incorporate up to four AD5675 devices on one bus (see Table 11). Table 11. Device Address Selection A1 Pin Connection GND GND VLOGIC VLOGIC A0 Pin Connection GND VLOGIC GND VLOGIC A1 0 0 1 1 A0 0 1 0 1 1 The master initiates a data transfer by establishing a start condition when a high to low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave device with the transmitted address responds by pulling SDA low during the ninth clock pulse (this is called the acknowledge bit, or ACK). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its input shift register. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). Transitions on the SDA line must occur during the low period of SCL; SDA must remain stable during the high period of SCL. After all data bits are read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge (NACK) for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, and then high again during the 10th clock pulse to establish a stop condition. WRITE OPERATION When writing to the AD5675, begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The AD5675 require two bytes of data for the DAC, and a command byte that controls various DAC functions. Three bytes of data must, therefore, be written to the DAC with the command byte followed by the most significant data byte and the least significant data byte, as shown in Figure 43. All these data bytes are acknowledged by the AD5675. A stop condition follows. 9 1 9 SCL 0 SDA 0 0 1 1 A1 A0 DB23 R/W DB22 DB21 DB20 DB19 DB18 DB17 ACK BY AD5675 START BY MASTER DB16 ACK BY AD5675 FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 1 9 SCL (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 FRAME 3 MOST SIGNIFICANT DATA BYTE DB9 DB8 DB7 DB6 ACK BY AD5675 Figure 43. I2C Write Operation Rev. B | Page 20 of 26 DB5 DB4 DB3 DB2 FRAME 4 LEAST SIGNIFICANT DATA BYTE DB1 DB0 ACK BY AD5675 STOP BY MASTER 12550-303 SDA (CONTINUED) Data Sheet AD5675 READ OPERATION MULTIPLE DAC READBACK SEQUENCE When reading data back from the AD5675, begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte must be followed by the command byte, which determines both the read command that is to follow and the pointer address to read from; the command byte is also acknowledged by the DAC. The user configures the channel to read back the contents of one or more DAC input registers and sets the readback command to active using the command byte. When reading data back from multiple AD5675 DACs, the user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte must be followed by the command byte, which is also acknowledged by the DAC. The user selects the first channel to read back using the command byte. Following this sequence, the master establishes a repeated start condition, and the address is resent with R/W = 1. This byte is acknowledged by the DAC, indicating that it is prepared to transmit data. The first two bytes of data are then read from DAC Input Register n (selected using the command byte), MSB first, as shown in Figure 44. The next two bytes read back are the contents of DAC Input Register n + 1, and the next bytes read back are the contents of DAC Input Register n + 2. Data is read from the DAC input registers in this auto-incremented fashion until a NACK followed by a stop condition follows. If the contents of DAC Input Register 7 are read out, the next two bytes of data read are the contents of DAC Input Register 0. Then, the master establishes a repeated start condition, and the address is resent with R/W = 1. This byte is acknowledged by the DAC, indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC, as shown in Figure 44. A NACK condition from the master, followed by a stop condition, completes the read sequence. If more than one DAC is selected, DAC 0 is read back by default. 1 9 1 9 SCL 0 SDA 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 ACK BY AD5675 START BY MASTER ACK BY AD5675 FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 1 9 SCL 0 SDA 0 0 REPEATED START BY MASTER 1 1 A1 A0 R/W DB15 DB14 DB13 ACK BY AD5675 FRAME 3 SLAVE ADDRESS 1 DB12 DB11 DB10 DB9 DB8 ACK BY MASTER FRAME 4 MOST SIGNIFICANT DATA BYTE n 9 1 9 SCL (CONTINUED) DB7 DB6 DB5 DB4 DB3 DB2 FRAME 5 LEAST SIGNIFICANT DATA BYTE n DB1 DB0 DB15 DB14 DB13 DB12 ACK BY MASTER Figure 44. I2C Read Operation Rev. B | Page 21 of 26 DB11 DB10 FRAME 6 MOST SIGNIFICANT DATA BYTE n + 1 DB9 DB8 NACK BY MASTER STOP BY MASTER 12550-304 SDA (CONTINUED) AD5675 Data Sheet POWER-DOWN OPERATION The AD5675 contains two separate power-down modes. Command 0100 is designated for the power-down function (see Table 9). These power-down modes are software programmable by setting 16 bits, Bit DB15 to Bit DB0, in the input shift register. There are two bits associated with each DAC channel. Table 12 shows how the state of the two bits corresponds to the mode of operation of the device. Any or all DACs (DAC 0 to DAC 7) power down to the selected mode by setting the corresponding bits. See Table 13 for the contents of the input shift register during the power-down/ power-up operation. Table 12. Modes of Operation The AD5675 DACs have a double buffered interface consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers. Updates to the DAC registers are controlled by the LDAC pin. Instantaneous DAC Updating (LDAC Held Low) PD1 0 PD0 0 For instantaneous updating of the DACs, LDAC is held low while data is clocked into the input register using Command 0001. Both the addressed input register and the DAC register are updated on the 24th clock, and the output changes immediately. 0 1 1 1 Deferred DAC Updating (LDAC is Pulsed Low) When both Bit PD1 and Bit PD0 in the input shift register are set to 0, the device works normally with its normal power consumption of typically 1 mA at 5 V. However, for the two power-down modes, the supply current falls to typically 1 μA. In addition to this fall, the output stage switches internally from the amplifier output to a resistor network of known values. This has the advantage that the output impedance of the device is known while the device is in power-down mode. There are two different power-down options. The output is connected internally to GND through either a 1 kΩ resistor, or it is left open-circuited (tristate). The output stage is shown in Figure 45. AMPLIFIER DAC LOAD DAC (HARDWARE LDAC PIN) For deferred updating of the DACs, LDAC is held high while data is clocked into the input register using Command 0001. All DAC outputs are asynchronously updated by pulling LDAC low after the 24th clock. The update occurs on the falling edge of LDAC. AMPLIFIER VREF LDAC VOUTx DAC REGISTER INPUT REGISTER VOUTx SCL SDA INTERFACE LOGIC Figure 46. Simplified Diagram of Input Loading Circuitry for a Single DAC RESISTOR NETWORK 12550-071 POWER-DOWN CIRCUITRY 16-BIT DAC 12550-072 Operating Mode Normal Operation Power-Down Modes 1 kΩ to GND Tristate The bias generator, output amplifier, resistor string, and other associated linear circuitry shut down when power-down mode is activated. However, the contents of the DAC registers are unaffected when in power-down mode. The DAC registers can be updated while the device is in power-down mode. The time required to exit power-down is typically 2.5 μs for VDD = 5 V. Figure 45. Output Stage During Power-Down Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation [DB23:DB20] 0100 1 DB19 0 [DB18:DB16] XXX1 DAC 7 [DB15:DB14] [PD1:PD0] DAC 6 [DB13:DB12] [PD1:PD0] DAC 5 [DB11:DB10] [PD1:PD0] X means don’t care. Rev. B | Page 22 of 26 DAC 4 [DB9:DB8] [PD1:PD0] DAC 3 [DB7:DB6] [PD1:PD0] DAC 2 [DB5:DB4] [PD1:PD0] DAC 1 [DB3:DB2] [PD1:PD0] DAC 0 [DB1:DB0] [PD1:PD0] Data Sheet AD5675 LDAC MASK REGISTER Command 0101 is reserved for this hardware LDAC function. The address bits are ignored. Writing to the DAC using Command 0101 loads the 8-bit LDAC register (DB7 to DB0). The default for each channel is 0, that is, the LDAC pin works normally. Setting the bits to 1 forces this DAC channel to ignore transitions on the LDAC pin, regardless of the state of the hardware LDAC pin. This flexibility is useful in applications where the user wants to select which channels respond to the LDAC pin. The LDAC register gives the user extra flexibility and control over the hardware LDAC pin (see Table 15). Setting the LDAC bits (DB0 to DB7) to 0 for a DAC channel means that the update for this channel is controlled by the hardware LDAC pin. Table 14. LDAC Overwrite Definition Load LDAC Register LDAC Bits (DB7 to DB0) 00000000 LDAC Pin 1 or 0 LDAC Operation Determined by the LDAC pin. 11111111 X1 DAC channels update and override the LDAC pin. DAC channels see LDAC as 1. 1 X means don’t care. Table 15. Write Commands and LDAC Pin Truth Table 1 Command 0001 0010 0011 Description Write to Input Register n (dependent on LDAC ) Update DAC Register n with the contents of Input Register n Write to and update DAC Channel n Hardware LDAC Pin State Input Register Contents DAC Register Contents VLOGIC GND 2 VLOGIC Data update Data update No change No change (no update) Data update Updated with input register contents GND No change Updated with input register contents VLOGIC GND Data update Data update Data update Data update 1 A high to low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked (blocked) by the LDAC mask register. 2 When LDAC is permanently tied low, the LDAC mask bits are ignored. Rev. B | Page 23 of 26 AD5675 Data Sheet HARDWARE RESET (RESET) The RESET pin is an active low reset that allows the outputs to be cleared to either zero scale or midscale. The clear code value is user selectable via the RSTSEL pin. Keep RESET low for a minimum of 2 µs to complete the operation (see Figure 2). When the RESET signal is returned high, the output remains at the cleared value until a new value is programmed. While the RESET pin is low, the outputs cannot be updated with a new value. A software executable reset function is also available that resets the DAC to the power-on reset code. Command 0110 is designated for this software reset function (see Table 9). Any events on LDAC or RESET during power-on reset are ignored. RESET SELECT PIN (RSTSEL) low, the output powers up to zero scale. Note that this power-up is outside the linear region of the DAC; by connecting the RSTSEL pin high, the VOUTx pins power up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. AMPLIFIER GAIN SELECTION ON LFCSP PACKAGE The output amplifier gain setting for the LFCSP package is determined by the state of Bit DB2 in the gain setup register (see Table 16 and Table 17). Table 16. Gain Setup Register Bit DB2 The AD5675 contains a power-on reset circuit that controls the output voltage during power-up. By connecting the RSTSEL pin Description Amplifier gain setting DB2 = 0; amplifier gain = 1 (default) DB2 = 1; amplifier gain = 2 Table 17. 24-Bit Input Shift Register Contents for Gain Setup Command DB23 (MSB) 0 DB22 1 DB21 1 DB20 1 DB19 to DB3 Don’t care DB2 Gain Rev. B | Page 24 of 26 DB1 Reserved; set to 0 DB0 (LSB) Reserved; set to 0 Data Sheet AD5675 APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS The AD5675 is typically powered by the following supplies: VDD = 3.3 V and VLOGIC = 1.8 V. The ADP7118 can be used to power the VDD pin. The ADP160 can be used to power the VLOGIC pin. This setup is shown in Figure 47. The ADP7118 can operate from input voltages up to 20 V. The ADP160 can operate from input voltages up to 5.5 V. ADP7118 3.3V: VDD LDO ADP160 1.8V: VLOGIC LDO In systems where many devices are on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. The GND plane on the device can be increased (as shown in Figure 49) to provide a natural heat sinking effect. AD5675 12550-176 5V INPUT which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Figure 47. Low Noise Power Solution for the AD5675 MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5675 is performed via a serial bus that uses a standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 2-wire interface consisting of a clock signal and a data signal. The I2C interface of the AD5675 is designed for easy connection to industry-standard DSPs and microcontrollers. Figure 48 shows the AD5675 connected to the Analog Devices, Inc., Blackfin® processor. The Blackfin processor has an integrated I2C port that can be connected directly to the I2C pins of the AD5675. AD5675 ADSP-BF531 PF9 PF8 SCL SDA LDAC RESET 12550-077 GPIO1 GPIO2 Figure 49. Pad Connection to Board GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. iCoupler® products from Analog Devices provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5675 makes the device ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 50 shows a 4-channel isolated interface to the AD5675 using an ADuM1251. For further information, visit www.analog.com/icoupler. CONTROLLER Figure 48. AD5675 to ADSP-BF531 Interface LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the printed circuit board (PCB) on which the AD5675 is mounted so that the device lies on the analog plane. 12550-078 BOARD ADuM12511 DECODE ENCODE SDA ENCODE DECODE TO SDA SCL ENCODE DECODE TO SCL 1ADDITIONAL PINS OMITTED FOR CLARITY. The AD5675 must have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor must have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, Rev. B | Page 25 of 26 Figure 50. Isolated Interface 12550-079 AD5675 TO ADSP-BF531 INTERFACE GND PLANE AD5675 Data Sheet OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 51. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.75 2.60 SQ 2.35 11 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 5 10 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 020509-B PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 52. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-20-8) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5675ARUZ AD5675ARUZ-REEL7 AD5675BRUZ AD5675BRUZ-REEL7 AD5675ACPZ-REEL7 AD5675BCPZ-REEL7 EVAL-AD5675SDZ 1 Resolution (Bits) 16 16 16 16 16 16 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Accuracy ±8 LSB INL ±8 LSB INL ±3 LSB INL ±3 LSB INL ±8 LSB INL ±3 LSB INL Package Description 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP] 20-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12550-0-8/16(B) Rev. B | Page 26 of 26 Package Option RU-20 RU-20 RU-20 RU-20 CP-20-8 CP-20-8