Intersil ISL9016IRUJJZ-T 150ma dual ldo with low noise, high psrr, and low iq Datasheet

ISL9016
®
Data Sheet
January 22, 2009
150mA Dual LDO with Low Noise, High
PSRR, and Low IQ
ISL9016 is a high performance dual LDO capable of providing
up to 150mA current on each channel. It features a low
standby current and very high PSRR and is stable with output
capacitance of 1µF to 4.7µF with an ESR of up to 200mΩ.
The device integrates a separate enable function for each
output. The quiescent current is typically 49µA when only
one LDO is enabled and typically 80µA when both LDOs are
enabled. When both LDOs are under shutdown condition,
the drawing current is typically less than 1µA.
FN6832.0
Features
• Dual Integrated 150mA High Performance LDOs
• High PSRR: 80dB @ 1kHz and 45dB @ 1MHz
• Reverse Current Protection
• Low Quiescent Current
- 49µA (Single LDO Enabled)/80µA (Dual LDOs Enabled)
• Excellent Load Transient Response
• Typically ±0.8% Output Voltage Accuracy
• Low Output Noise: Typically 25µVRMS
ISL9016 provides a wide input voltage range from 1.8V to
6.5V. It also has a high PSRR of 80dB at 1kHz and 45dB at
1MHz. ISL9016 also provides output current limit, overheat
protection, reverse current protection, as well as excellent
load transient response.
• Wide Input Voltage Capability: 1.8V to 6.5V
ISL9016 is offered in a tiny 1.6mmx1.6mm 6 Ld µTDFN
package. Output voltage options are available from 1.2V to
3.3V. Several combinations of voltage outputs are standard
and others may be available upon request.
• Soft-start to Limit Input Current Surge During Enable
Pinout
• Pb-free (RoHS Compliant)
• Low Dropout Voltage: Typically 120mV @ 150mA
• Separate Enable Control for each LDO
• Stable with 1µF to 4.7µF Ceramic Output Capacitors
• Current Limit and Overheat Protection
• Tiny 6 Ld 1.6mmx1.6mm µTDFN package
ISL9016
(6 LD 1.6x1.6 µTDFN)
TOP VIEW
Applications
VIN 1
6 VOUT1
• Portable Instruments, MP3/4 Players, PMP, DSC
GND 2
5 VOUT2
• Handheld Devices including Medical Handhelds
EN2 3
4 EN1
1
• PDAs, Cell Phones and Smart Phones
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL9016
Ordering Information
PART NUMBER
(Notes 1, 3)
PART MARKING
VO1 VOLTAGE
(V) (Note 2)
VO2 VOLTAGE
(V) (Note 2)
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG
DWG. #
ISL9016IRUWCZ-T
N7
1.2
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUWGZ-T
N6
1.2
2.7
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUWJZ-T
N2
1.2
2.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUWKZ-T
N1
1.2
2.85
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUBWZ-T
R7
1.5
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUBBZ-T
R6
1.5
1.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUCWZ-T
R5
1.8
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUCBZ-T
R4
1.8
1.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUFWZ-T
R3
2.5
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUFBZ-T
N8
2.5
1.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUFCZ-T
N9
2.5
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUFFZ-T
P0
2.5
2.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUGWZ-T
P1
2.7
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUGCZ-T
R2
2.7
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUGGZ-T
N3
2.7
2.7
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUJWZ-T
P2
2.8
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUJBZ-T
P3
2.8
1.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUJCZ-T
N4
2.8
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUJJZ-T
N0
2.8
2.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUKWZ-T
P5
2.85
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUKFZ-T
P4
2.85
2.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUKKZ-T
N5
2.85
2.85
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUMWZ-T
P6
3.0
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUMBZ-T
P7
3.0
1.5
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUMCZ-T
P8
3.0
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUMKZ-T
P9
3.0
2.85
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUNWZ-T
R0
3.3
1.2
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
ISL9016IRUNCZ-T
R1
3.3
1.8
-40 to +85
6 Ld µTDFN
L6.1.6x1.6A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. For other output voltages, contact Intersil marketing or local sales office.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6832.0
January 22, 2009
ISL9016
Absolute Maximum Ratings
Thermal Information
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.1V
All Other Pins to GND . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V
Thermal Resistance
Recommended Operating Conditions
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 6.5V
Each LDO Load Current . . . . . . . . . . . . . . . . . . . . . . . .up to 150mA
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C
θJA (°C/W)
6 Ld μTDFN Package (Note 4) . . . . . . . . . . . . . . .
117.5
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = +25°C; VIN = (VO + 0.5V) to 6.5V with
a minimum VIN of 1.8V; CIN = 1µF; CO = 1µF. Parameters with MIN and/or MAX limits are 100% tested at
+25°C, unless otherwise specified. Temperature limits established by characterization and are not production
tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
6.5
V
1.710
1.775
V
DC CHARACTERISTICS
Supply Voltage
VIN
UVLO Threshold
1.8
VUV+
VUV-
1.55
1.62
Quiescent condition: IO1 = 0µA; IO2 = 0µA
Input Quiescent Current
Shutdown Current
IDD1
One LDO active
49
67
µA
IDD2
Both LDO active
80
100
µA
IDDS
@ +25°C
0.1
1.0
µA
Regulation Voltage Accuracy
Maximum Output Current
IMAX
Internal Current Limit
ILIM
Dropout Voltage (Note 5)
Thermal Shutdown Temperature
VIN = VO + 0.5V to 6.5V, IO = 10µA to 150mA, TA = +25°C
-0.8
+0.8
%
VIN = VO + 0.5V to 6.5V, IO = 10µA to 150mA, TA = -40°C to
+85°C
-1.8
+1.8
%
Each LDO, Continuous
150
175
mA
265
355
mA
250
425
mV
VDO1
IO = 150mA; 1.2V ≤ VO ≤ 2.1V
VDO2
IO = 150mA; 2.1V ≤ VO ≤ 2.8V
200
325
mV
VDO3
IO = 150mA; 2.8V ≤ VO
120
200
mV
TSD+
145
°C
TSD-
110
°C
@ 1kHz
80
dB
@ 10kHz
60
dB
@ 100kHz
50
dB
@ 1MHz
45
dB
VIN = 4.2V, IO = 10mA, TA = +25°C, BW = 10Hz to 100kHz
25
µVRMS
Time from assertion of the ENx pin to when the output voltage
reaches 95% of the VO(nom)
400
AC CHARACTERISTICS
IO = 10mA, VIN = 3.7V(min), VO = 2.7V, TA = +25°C
Ripple Rejection
Output Noise Voltage
DEVICE START-UP CHARACTERISTICS
Device Enable Time
tEN
3
600
µs
FN6832.0
January 22, 2009
ISL9016
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = +25°C; VIN = (VO + 0.5V) to 6.5V with
a minimum VIN of 1.8V; CIN = 1µF; CO = 1µF. Parameters with MIN and/or MAX limits are 100% tested at
+25°C, unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER
SYMBOL
LDO Soft-Start Ramp Rate
tSSR
TEST CONDITIONS
MIN
TYP
MAX
UNITS
30
60
µs/V
-0.3
0.4
V
1.1
VIN + 0.3
V
0.1
µA
15
µA
Slope of linear portion of LDO output voltage ramp during
start-up
EN PIN CHARACTERISTICS
Input Low Voltage
VIL
Input High Voltage
VIH
Input Leakage Current
TA = -20°C to +85°
IIL, IIH
REVERSE CURRENT CHARACTERISTICS
Output Reverse Leakage Current
(Note 6)
IORLC
VIN = 0V, VOUT = 5.5V
8
NOTES:
5. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.80V.
6. Output reverse leakage current is measured with VIN pin grounded and VOUT pin connected to 5.5V.
4
FN6832.0
January 22, 2009
ISL9016
Typical Operating Performance
55
55
50
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (µA)
T = +85°C
T = +85°C
T = +50°C
T = +25°C
45
40
T = 0°C
35
T = -25°C
T = +50°C
50
T = +25°C
45
40
T = 0°C
35
T = -25°C
T = -40°C
T = -40°C
30
2.4
3.6
4.8
30
2.4
6.0
FIGURE 1. QUIESCENT CURRENT vs INPUT VOLTAGE
(VOUT1 = 2.1V, ONLY LDO1 ENABLED)
6.0
FIGURE 2. QUIESCENT CURRENT vs INPUT VOLTAGE
(VOUT2 = 2.1V, ONLY LDO2 ENABLED)
T = +85°C
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (µA)
4.8
55
85
T = +50°C
80
T = +25°C
75
70
T = 0°C
65
T = -25°C
T = +25°C
60
2.4
3.6
T = +50°C
T = +85°C
50
45
40
T = 0°C
T = -25°C
35
T = -40°C
T = -40°C
4.8
30
3.6
6.0
4.4
5.2
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 4. QUIESCENT CURRENT vs INPUT VOLTAGE
(VOUT1 = 3.3V, ONLY LDO1 ENABLED)
FIGURE 3. QUIESCENT CURRENT vs INPUT VOLTAGE
(VOUT1 = VOUT2 = 2.1V, LDO1 AND LDO2
ENABLED)
55
85
T = +25°C
T = +50°C
T = +85°C
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (µA)
3.6
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
50
45
40
T = 0°C
T = -25°C
35
T = +25°C
80
T = +85°C
T = +50°C
75
T = 0°C
70
T = -25°C
65
T = -40°C
T = -40°C
60
30
3.6
4.4
5.2
INPUT VOLTAGE (V)
FIGURE 5. QUIESCENT CURRENT vs INPUT VOLTAGE
(VOUT2 = 3.3V, ONLY LDO2 ENABLED)
5
6.0
3.6
4.4
5.2
6.0
INPUT VOLTAGE (V)
FIGURE 6. QUIESCENT CURRENT vs INPUT VOLTAGE
(VOUT1 = VOUT2 = 3.3V, LDO1 AND LDO2
ENABLED)
FN6832.0
January 22, 2009
ISL9016
Typical Operating Performance
10
15
T = +85°C
10
T = +25°C
0
ΔVO (mV)
5
ΔVO (mV)
T = +85°C
5
0
-5
T = +25°C
-5
-10
T = -40°C
-15
-10
T = -40°C
-20
-15
1.5
3.0
4.5
1.5
6.0
2.5
4.5
5.5
FIGURE 7. ΔVOUT vs INPUT VOLTAGE
(VOUT_NOMINAL = 1.2V, IOUT = 50mA)
FIGURE 8. ΔVOUT vs INPUT VOLTAGE
(VOUT_NOMINAL = 1.2V, IOUT = 150mA)
1.22
3.32
OUTPUT VOLTAGE (V)
1.21
1.20
T = +25°C
1.19
T = +25°C
3.31
T = +85°C
OUTPUT VOLTAGE (V)
3.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3.30
T = +85°C
3.29
3.28
T = -40°C
3.27
3.26
T = -40°C
1.18
3.25
0
30
60
90
120
150
0
30
LOAD CURRENT (mA)
FIGURE 9. LOAD REGULATION (VIN = 1.8V, VOUT = 1.2V)
EN1 = EN2
120
150
FIGURE 10. LOAD REGULATION (VIN = 4.5V, VOUT = 3.3V)
5V/DIV
5V/DIV
60
90
LOAD CURRENT (mA)
VIN
VOUT1 (AC COUPLED)
50mV/DIV
1V/DIV
VOUT1
50mV/DIV
200mA/DIV
1V/DIV
VOUT2
100µs/DIV
FIGURE 11. ENABLE OPERATION (VIN = 3.6V,
VOUT1 = VOUT1 = 1.2V)
6
VOUT2 (AC COUPLED)
IOUT1
1ms/DIV
FIGURE 12. LOAD TRANSIENT RESPONSE (VIN = 3.6V,
VOUT1 = VOUT2 = 1.2V, IOUT1 0.01mA TO 150mA)
FN6832.0
January 22, 2009
ISL9016
Typical Operating Performance
5V/DIV
VIN
5V/DIV
VIN
VOUT1 (AC COUPLED)
50mV/DIV
50mV/DIV
VOUT1 (AC COUPLED)
1ms/DIV
VOUT2 (AC COUPLED)
50mV/DIV
50mV/DIV
IOUT1
VOUT2 (AC COUPLED)
IOUT1
200mA/DIV
200mA/DIV
1ms/DIV
1ms/DIV
FIGURE 13. LOAD TRANSIENT RESPONSE (VIN = 3.6V,
VOUT1 = VOUT2 = 1.2V, IOUT2 0.01mA TO 150mA)
FIGURE 14. LOAD TRANSIENT RESPONSE (VIN = 3.6V,
VOUT1 = VOUT2 = 3.3V, IOUT1 0.01mA TO 150mA)
VOUT1 (AC COUPLED)
VOUT (AC COUPLED)
50mV/DIV
100mV/DIV
VOUT2 (AC COUPLED)
20mV/DIV
IOUT1
IOUT
100mA/DIV
1ms/DIV
di/dt = 150mA/µs
FIGURE 15. LOAD TRANSIENT RESPONSE (VIN = 1.8V,
VOUT1 = VOUT2 = 1.2V, IOUT1 0.01mA TO 150mA)
7
100mA/DIV
1ms/DIV
di/dt = 150mA/µs
FIGURE 16. LOAD TRANSIENT RESPONSE (VIN = 3.3V,
VOUT1 = VOUT2 = 1.2V, IOUT1 0.01mA TO 150mA)
FN6832.0
January 22, 2009
ISL9016
Pin Descriptions
PIN #
PIN
NAME
1
VIN
Supply Voltage/LDO Input. Connect a 1µF capacitor to GND.
2
GND
GND is the connection to system ground. Connect to PCB Ground plane.
3
EN2
LDO2 Enable pin. Enable = High, Disable = Low. A 100k resistor should be connected between EN2 and the control voltage
rail. Do NOT leave it floating.
4
EN1
LDO1 Enable pin. Enable = High, Disable = Low. A 100k resistor should be connected between EN1 and the control voltage
rail. Do NOT leave it floating.
5
VOUT2
LDO2 Output. Connect capacitor with a value from 1µF to 4.7µF to GND (1µF recommended).
6
VOUT1
LDO1 Output. Connect capacitor with a value from 1µF to 4.7µF to GND (1µF recommended).
-
E-Pad
Connect the e-pad to the system ground.
DESCRIPTION
Typical Application Diagram
ISL9016
VOUT1
1.2V~3.3V, 0~150mA
VIN (1.8V TO 6.5V)
VIN
VOUT1
VOUT2
1.2V~3.3V, 0~150mA
C1
R1
GND
VOUT2
EN2
EN1
C2
ON
OFF
ON
C3
R2
OFF
C1, C2, C3:1µF, X5R (or X7R) CERAMIC CAPACITOR
R1, R2: 100k
8
FN6832.0
January 22, 2009
ISL9016
Block Diagram
VOUT2
VIN
VOUT1
REVERSE CURRENT
PROTECTION
VIN
VOUT1
EN1
UNDERVOLTAGE
LOCKOUT
EN2
SHORT CIRCUIT
THERMAL PROTECTION
SOFT-START
CONTROL
LOGIC
EN1
VREF1
+
LDO-2
LDO-1
VREF2
VREF1
BANDGAP
TEMP-SENSOR
VREF3
REFERENCE
VOLTAGES
GND
Functional Description
ISL9016 contains two high performance LDO’s. High
performance is achieved through a circuit which delivers fast
transient response to varying load conditions. In a quiescent
condition, the ISL9016 adjusts its biasing to achieve the
lowest standby current consumption.
The device also integrates current limit protection, thermal
shutdown protection, reverse current protection and soft-start.
Thermal shutdown protects the device against overheating.
Soft-start limits the start-up input current surges. In some
certain application circuits, the output voltage may be
externally held up, meanwhile, the input voltage could be
connected to ground, or connected to some voltage lower
than the output side, or be left open circuit. ISL9016 features
the reverse current protection; it can limit the current flow from
output to input. This protection will automatically initiate when
VOUT is detected to be higher than VIN. When VIN is pulled to
ground and VOUT is held at 5.5V, the current flow from VOUT
to VIN is typically less than 8µA.
Enable Control
The ISL9016 has two separate enable pins, EN1 and EN2,
which independently enable/disable each of the LDO
outputs. When both EN1 and EN2 are low, the whole device
is in shutdown mode. In this condition, all on-chip circuits are
off, and the device draws minimum current, typically less
than 0.1mA. When one or both the EN pins go high, the
9
LDO1 and/or LDO2 will be enabled accordingly based on the
voltage signal applied on its related EN pin and start from the
soft-start. Likewise, when one or both EN pins go low, LDO1
and/or LDO2 will be disabled based on the signal applied on
its related EN pin. A 100kΩ (or above) pull-up resistor should
be connected between ENx pin and the external control
voltage (as shown in the “Typical Application Diagram” on
page 8).
LDO Protections
ISL9016 offers several protections which make it ideal for
using in battery-powered application circuits.
ISL9016 provides short-circuit protection by limiting the
output current to typical 265mA. When short circuit happens,
the circuit is limited at 265mA (typical). If the short circuit
lasts long enough, the die temperature increases, and the
over-temperature protection circuit will turn off the output.
When the die temperature reaches about +145°C, the thermal
protection starts working. Under the overheat condition, only
the LDO sourcing more than 50mA will be shut off. This does
not affect the operation of the other LDO. If both LDOs source
more than 50mA and an overheat condition occurs, both LDO
outputs will be disabled. Once the die temperature falls back
to about +110°C, the disabled LDO(s) are re-enabled and
soft-start automatically takes place.
In certain applications, the following input/output situations
may occur:
FN6832.0
January 22, 2009
ISL9016
With output voltage externally held up higher than the input
voltage:
1. Input is pulled to ground;
2. input is left open circuit; and
3. input is pulled to some intermediate voltage
ISL9016 provides the reverse current protection to limit the
current flow from output to input under these situations. When
input is pulled to ground and output is held to 5.5V, the typical
reverse current from output to input side is less than 8µA.
Input and Output Capacitors
The ISL9016 provides a linear regulator that has low
quiescent current, fast transient response, and overall stability
across the recommended operating conditions. A ceramic
capacitor (X5R or X7R) with a capacitance of 1µF to 4.7µF
with an ESR up to 200mΩ is suitable for ISL9016 to maintain
its output stability. The ground connection of the output
capacitor should be connected directly to the GND pin of the
device, and also placed close to the device. Similarly for the
input capacitor, usually a 1µF ceramic capacitor (X5R or X7R)
is suitable for most cases, but if large, fast rising-time load
transient condition is expected, a higher value input capacitor
may be necessary to achieve better performance.
Board Layout Recommendations
A good PCB layout will be an important step to achieve good
performance. It is recommended to design the board with
separate ground planes for input and output, and connect
both ground planes at the GND pin of the device.
Consideration should be taken when placing the
components and route the trace to minimize the ground
impedance, as well as keep the parasitic inductance low.
Usually the input/output capacitors should be placed close to
the device with good ground connection.
10
FN6832.0
January 22, 2009
ISL9016
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
A
A
E
6
B
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
4
MILLIMETERS
D
PIN 1
REFERENCE
2X
0.15 C
1
2X
L6.1.6x1.6A
3
MIN
NOMINAL
MAX
NOTES
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
A1
TOP VIEW
e
1.00 REF
4
6
L
CO.2
0.15
0.20
0.25
-
D
1.55
1.60
1.65
4
D2
0.40
0.45
0.50
-
E
1.55
1.60
1.65
4
E2
0.95
1.00
1.05
-
0.50 BSC
e
L
3
1
b 6X
0.10 M C A B
E2
-
b
DAP SIZE 1.30 x 0.76
0.25
0.30
0.35
Rev. 1 6/06
NOTES:
1. Dimensions are in mm. Angles in degrees.
BOTTOM VIEW
DETAIL A
6X
0.127 REF
A3
0.15 C
D2
SYMBOL
2. Coplanarity applies to the exposed pad as well as the terminals.
Coplanarity shall not exceed 0.08mm.
0.10 C
3. Warpage shall not exceed 0.10mm.
0.08 C
4. Package length/package width are considered as special
characteristics.
5. JEDEC Reference MO-229.
A3
SIDE VIEW
C
SEATING
PLANE
6. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
0.127±0.008
0.127 +0.058
-0.008
TERMINAL THICKNESS
A1
DETAIL A
0.25
0.50
1.00
0.45
1.00
2.00
0.30
1.25
LAND PATTERN
6
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN6832.0
January 22, 2009
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