Document Number: MMA68xx Rev. 5, 03/2012 Freescale Semiconductor Data Sheet: Technical Data Dual-Axis SPI Inertial Sensor MMA68xx, a SafeAssure solution, is a SPI-based, 2-axis, medium-g, overdamped lateral accelerometer designed for use in automotive airbag systems. MMA68xx Features • • • • • • • • Bottom View ±20g to ±120g full-scale range, independently specified for each axis 3.3V or 5V single supply operation SPI-compatible serial interface 10-bit digital signed or unsigned SPI data output Independent programmable arming functions for each axis Twelve low-pass filter options, ranging from 50 Hz to 1000 Hz Optional offset cancellation with > 6s averaging period and < 0.25 LSB/s slew rate Pb-Free 16-Pin QFN-6 by 6 Package 16 LEAD QFN 6 mm by 6 mm CASE 2086-01 Referenced Documents VSSA N/C N/C Top View AECQ100, Revision G, dated May 14, 2007 (http://www.aecouncil.com/) VSSA • 16 15 14 13 VREGA 1 Shipping MMA6811BKW ±60g ±25g Tubes MMA6813BKW ±50g ±50g Tubes MMA6821BKW ±120g ±25g Tubes MMA6823BKW ±120g ±60g Tubes MMA6825BKW ±100g ±100g Tubes MMA6826BKW ±60g ±60g Tubes MMA6827BKW ±120g ±120g Tubes MMA6811BKWR2 ±60g ±25g Tape & Reel MMA6813BKWR2 ±50g ±50g Tape & Reel MMA6821BKWR2 ±120g ±25g Tape & Reel MMA6823BKWR2 ±120g ±60g Tape & Reel MMA6825BKWR2 ±100g ±100g Tape & Reel MMA6826BKWR2 ±60g ±60g Tape & Reel MMA6827BKWR2 ±120g ±120g Tape & Reel © 2010-2012 Freescale Semiconductor, Inc. All rights reserved. 9 VCC VSS 4 5 6 7 8 MISO Y-Axis Range TEST/VPP X-Axis Range 11 MOSI 10 SCLK ARM_X/PCM_X Device VSS 2 VREG 3 ARM_Y/PCM_Y ORDERING INFORMATION 12 CS 17 Pin Connections Application Diagram VCC VCC C1 CS CS_A CS_D VREG SCLK SCLK1 SCLK2 SCLK VREGA MOSI MOSI1 MOSI2 MOSI MISO MISO1 MISO2 MISO C3 C2 CS Main MCU MMA68xx Deployment IC VSSA VSS VPP/TEST ARM_X DEPLOY_EN1 ARM_Y DEPLOY_EN2 Figure 1. Application Diagram Table 1. External Component Recommendations Ref Des Type Description Purpose C1 Ceramic 0.1 μF, 10%, 10V Minimum, X7R VCC Power Supply Decoupling C2 Ceramic 1 μF, 10%, 10V Minimum, X7R Voltage Regulator Output Capacitor (CREG) C3 Ceramic 1 μF, 10%, 10V Minimum, X7R Voltage Regulator Output Capacitor (CREGA) xxxxxxx xxxxxxx X: 0g Y: -1g X: +1g Y: 0g xxxxxxx xxxxxxx xxxxxxx xxxxxxx Device Orientation X: 0g Y: +1g xxxxxxx xxxxxxx X: -1g Y: 0g X: 0g Y: 0g X: 0g Y: 0g EARTH GROUND Figure 2. Device Orientation Diagram MMA68xx 2 Sensors Freescale Semiconductor, Inc. Internal Block Diagram VPP VCC VREG VSS VREGA SINC Filter Over-Damped Y-Axis g-Cell Low-Pass Filter VSSA Offset IIR Compensation Linear Interpolation Cancellation Output Scaling ARM_Y ARM_Y Offset Monitor Clock CRC Generation Y-Axis Register Array ΣΔ Converter VREG Clock & bias Generator SPI Mismatch Verification VREGA VCC CS SPI 1 MHz Self Test Analog Regulator 1 MHz 8 MHz Digital Oscillator Regulator VREGA Voltage Monitoring OTP Array I/O Memory SCLK MOSI MISO VREG Clock & bias Generator Over-Damped X-Axis g-Cell Y-Axis SPI ΣΔ Converter X-Axis Register Array Clock CRC Clock Generation Monitoring SPI Offset Monitor IIR SINC Filter Low-Pass Filter Compensation X-Axis Linear Interpolation Offset Cancellation Output Scaling ARM_X ARM_X Figure 3. Block Diagram MMA68xx Sensors Freescale Semiconductor, Inc. 3 VSSA N/C N/C Pin Connections VSSA 1 16 15 14 13 VREGA 1 12 CS 17 VSS 2 11 MOSI VREG 3 10 SCLK 6 7 8 ARM_X/PCM_X TEST/VPP MISO 9 VCC 5 ARM_Y/PCM_Y VSS 4 Figure 4. 16-Pin QFN Package, Top View Table 2. Pin Description Pin Pin Name 1 VREGA Analog Supply 2 VSS Digital GND 3 VREG Digital Supply 4 VSS Digital GND This pin is the power supply return node for the digital circuitry. 5 ARM_Y/ PCM_Y Y-Axis Arm Output / PCM Output The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.5. When the arming output is selected, ARM_Y can be configured as an open drain, active low output with a pullup current; or an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a digital output with PCM signal proportional to the Y axis acceleration data. Reference Section 3.8.9 and Section 3.8.9.1. If unused, this pin must be left unconnected. 6 ARM_X/ PCM_X X-Axis Arm Output / PCM Output The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.5. When the arming output is selected, ARM_X can be configured as an open drain, active low output with a pullup current; or an open drain, active high output with a pulldown current. Alternatively, this pin can be configured as a digital output with a PCM signal proportional to the X-axis acceleration data. Reference Section 3.8.9 and Section 3.8.9.1. If unused, this pin must be left unconnected. 7 TEST/ VPP Programming This pin provides the power for factory programming of the OTP registers. This pin must be connected to VSS Voltage in the application. 8 MISO SPI Data Out This pin functions as the serial data output for the SPI port. 9 VCC 10 11 Formal Name Definition This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between this pin and VSSA. Reference Figure 1. This pin is the power supply return node for the digital circuitry. This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between this pin and VSS. Reference Figure 1. Supply This pin supplies power to the device. An external capacitor must be connected between this pin and VSS. Reference Figure 1. SCLK SPI Clock This input pin provides the serial clock to the SPI port. An internal pulldown device is connected to this pin. MOSI SPI Data In This pin functions as the serial data input to the SPI port. An internal pulldown device is connected to this pin. 12 CS Chip Select This input pin provides the chip select for the SPI port. An internal pullup device is connected to this pin. 13 VSSA Analog GND This pin is the power supply return node for analog circuitry. 14 N/C No Connect No Connection 15 N/C No Connect No Connection 16 VSSA Analog GND This pin is the power supply return node for analog circuitry. 17 PAD Corner Pads Die Attach Pad This pin is the die attach flag, and is internally connected to VSS. Corner Pads The corner pads are internally connected to VSS. MMA68xx 4 Sensors Freescale Semiconductor, Inc. 2 Electrical Characteristics 2.1 Maximum Ratings Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. # Symbol Value Unit 1 Supply Voltage Rating VCC -0.3 to +7.0 V (3) 2 CREG, CREGA VREG -0.3 to +3.0 V (3) 3 SCLK, CS, MOSI,VPP/TEST VIN -0.3 to VCC + 0.3 V (3) 4 ARM_X, ARM_Y VIN -0.3 to VCC + 0.3 V (3) 5 MISO (high impedance state) VIN -0.3 to VCC + 0.3 V (3) 6 Acceleration without hitting internal g-cell stops ggcell_Clip ±500 g (3, 18) 7 Acceleration without saturation of internal circuitry gADC_Clip ±375 g (3) 8 Powered Shock (six sides, 0.5 ms duration) gpms ±1500 g (5, 18) 9 Unpowered Shock (six sides, 0.5 ms duration) gshock ±2000 g (5, 18) 10 Drop Shock (to concrete surface) hDROP 1.2 m (5) Electrostatic Discharge 11 Human Body Model (HBM) 12 Charge Device Model (CDM) 13 Machine Model (MM) VESD VESD VESD ±2000 ±750 ±200 V V V (5) (5) (5) 14 Storage Temperature Range Tstg -40 to +125 °C (5) 15 Thermal Resistance - Junction to Case θJC 2.5 °C/W (14) 2.2 Operating Range The operating ratings are the limits normally expected in the application and define the range of operation. # Characteristic Supply Voltage 16 Standard Operating Voltage, 3.3V 17 Standard Operating Voltage, 5.0V 18 Operating Ambient Temperature Range Verified by 100% Final Test 19 Power-on Ramp Rate (VCC) Symbol Min Typ Max VCC VL +3.135 VTYP +3.3 +5.0 VH +5.25 Units TA TL -40 ⎯ TH +105 C (1) VCC_r 0.000033 ⎯ 3300 V/μs (19) V V (15) (15) MMA68xx Sensors Freescale Semiconductor, Inc. 5 2.3 Electrical Characteristics - Power Supply and I/O VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified # Characteristic 20 Supply Current Power Supply Monitor Thresholds (See Figure 8) VCC Undervoltage (Falling) VREG Undervoltage (Falling) VREG Overvoltage (Rising) VREGA Undervoltage (Falling) VREGA Overvoltage (Rising) Power Supply Monitor Hysteresis VCC Undervoltage (Falling) 26 VREG Undervoltage, VREG Overvoltage 27 VREGA Undervoltage, VREGA Overvoltage 28 21 22 23 24 25 Power Supply RESET Thresholds (See Figure 5, and Figure 8) 29 VREG Undervoltage RESET (Falling) VREG Undervoltage RESET (Rising) 30 VREG RESET Hysteresis 31 32 33 Internally Regulated Voltages VREG VREGA 34 35 External Filter Capacitor (CREG, CREGA) Value ESR (including interconnect resistance) 36 37 Power Supply Coupling 50 kHz ≤ fn ≤ 300 kHz 4 MHz ≤ fn ≤ 100 MHz Symbol Min Typ Max Units * IDD 4.0 ⎯ 9.0 mA (1) * * * * * VCC_UV_f VREG_UV_f VREG_OV_r VREGA_UV_f VREGA_OV_r 2.74 2.10 2.65 2.20 2.65 ⎯ ⎯ ⎯ ⎯ ⎯ 3.02 2.25 2.85 2.35 2.85 V V V V V (3, 6) (3, 6) (3, 6) (3, 6) (3, 6) VHYST VHYST VHYST 65 20 20 100 100 100 110 210 150 mV mV mV (3) (3) (3) * * VREG_UVR_f VREG_UVR_r VHYST 1.764 1.876 80 ⎯ ⎯ ⎯ 2.024 2.152 140 V V mV (3, 6) (3, 6) (3) * * VREG VREGA 2.42 2.42 2.50 2.50 2.58 2.58 V V (1, 3) (1, 3) CREG ESR 700 ⎯ 1000 ⎯ 1500 400 nF mΩ (19) (19) ⎯ ⎯ ⎯ ⎯ 0.004 0.004 LSB/mv LSB/mv (19) (19) Output High Voltage (MISO, PCM_X, PCM_Y) 38 3.15V ≤ (VCC - VSS) ≤ 3.45V (ILoad = -1 mA) 39 4.75V ≤ (VCC - VSS) ≤ 5.25V (ILoad = -1 mA) * * VOH_3 VOH_5 VCC - 0.2 VCC - 0.4 ⎯ ⎯ ⎯ ⎯ V V (2,3) (2,3) Output Low Voltage (MISO, PCM_X, PCM_Y) 40 3.15V ≤ (VCC - VSS) ≤ 3.45V (ILoad = 1 mA) 41 4.75V ≤ (VCC - VSS) ≤ 5.25V (ILoad = 1 mA) * * VOL_3 VOL_5 ⎯ ⎯ ⎯ ⎯ 0.2 0.4 V V (2, 3) (2, 3) Open Drain Output High Voltage (ARM_X, ARM_Y) 42 3.15V ≤ (VCC - VSS) ≤ 3.45V (IARM = -1 mA) 43 4.75V ≤ (VCC - VSS) ≤ 5.25V (IARM = -1 mA) * * VODH_3 VODH_5 VCC - 0.2 VCC - 0.4 ⎯ ⎯ ⎯ ⎯ V V (2, 3) (2, 3) Open Drain Output Pulldown Current (ARM_X, ARM_Y) 44 3.15V ≤ (VCC - VSS) ≤ 3.45V (VARM = 1.5 V) 45 4.75V ≤ (VCC - VSS) ≤ 5.25V (VARM = 1.5 V) * * IODPD_3 IODPD_5 50 50 ⎯ ⎯ 100 100 μA μA (2, 3) (2,3) Open Drain Output Low Voltage (ARM_X, ARM_Y) 46 3.15V ≤ (VCC - VSS) ≤ 3.45V (IARM = 1 mA) 47 4.75V ≤ (VCC - VSS) ≤ 5.25V (IARM = 1 mA) * * VODH_3 VODH_5 ⎯ ⎯ ⎯ ⎯ 0.2 0.4 V V (2, 3) (2, 3) Open Drain Output Pullup Current (ARM_X, ARM_Y) 48 3.15V ≤ (VCC - VSS) ≤ 3.45V (VARM = 1.5 V) 49 4.75V ≤ (VCC - VSS) ≤ 5.25V (VARM = 1.5 V) * * IODPU_3 IODPU_5 -100 -100 ⎯ ⎯ -50 -50 μA μA (2, 3) (2, 3) 50 Input High Voltage CS, SCLK, MOSI * VIH 2.0 ⎯ ⎯ V (3, 6) 51 Input Low Voltage CS, SCLK, MOSI * VIL ⎯ ⎯ 1.0 V (3, 6) 52 Input Voltage Hysteresis CS, SCLK * VI_HYST 0.125 ⎯ 0.500 V (19) Input Current High (at VIH) (SCLK, MOSI) Low (at VIL) (CS) * * IIH IIL -260 30 -50 50 -30 260 μA μA (2, 3) (2, 3) 53 54 MMA68xx 6 Sensors Freescale Semiconductor, Inc. 2.4 Electrical Characteristics - Sensor and Signal Chain VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified # Characteristic Symbol Min Typ Max Units SENS SENS SENS SENS ⎯ ⎯ ⎯ ⎯ 9.766 8.192 4.883 4.096 ⎯ ⎯ ⎯ ⎯ LSB/g LSB/g LSB/g LSB/g (1, 9) (1, 9) (1, 9) (1, 9) SENS SENS SENS SENS ⎯ ⎯ ⎯ ⎯ 20.479 9.766 8.192 4.883 ⎯ ⎯ ⎯ ⎯ LSB/g LSB/g LSB/g LSB/g (1, 9) (1, 9) (1, 9) (1, 9) 55 56 57 58 X-Axis Digital Sensitivity (SPI, 10-bit Output) 50g (MMA6813) 60g (MMA6811, MMA6826) 100g (MMA6825) 120g (MMA6821, MMA6823) * 59 60 61 62 Y-Axis Digital Sensitivity (SPI, 10-bit Output) 25g (MMA6811, MMA6821) 50g (MMA6813QR) 60g (MMA6823, MMA6826) 100g (MMA6825) * 63 64 65 Sensitivity Error TA = 25°C -40°C ≤ TA ≤ 105°C -40°C ≤ TA ≤ 105°C,VCC_UV_f ≤ VCC - VSS ≤ VL * * ΔSENS ΔSENS ΔSENS -4 -5 -5 ⎯ ⎯ ⎯ +4 +5 +5 % % % (1) (1) (3) 66 67 68 69 Offset at 0g (No Offset Cancellation) 10-bits, unsigned 10-bits, signed 10-bits, unsigned, VCC_UV_f ≤ VCC - VSS ≤ VL 10-bits, signed, VCC_UV_f ≤ VCC - VSS ≤ VL * * OFFSET OFFSET OFFSET OFFSET 452 -60 452 -60 512 0 512 0 572 +60 572 +60 LSB LSB LSB LSB (1) (1) (3) (3) 70 71 Offset Monitor Thresholds Positive Threshold (10-bits, unsigned) Negative Threshold (10-bits, unsigned) ⎯ ⎯ 612 412 ⎯ ⎯ LSB LSB (7) (7) 72 73 74 75 Range of Output (SPI, 10-bits unsigned) Normal Fault Response Code Unused Codes Unused Codes RANGE FAULT UNUSED UNUSED 32 — 1 993 — 0 ⎯ ⎯ 992 — 31 1023 LSB LSB LSB LSB (7) (7) (7) (7) 76 77 78 79 Range of Output (SPI, 10-bits, signed) Normal Fault Response Code Unused Codes Unused Codes RANGE FAULT UNUSED UNUSED -480 — -511 481 — -512 — — 480 — -481 511 LSB LSB LSB LSB (7) (7) (7) (7) NLOUT -1 — 1 % FSR (3) nRMS nP-P — — — — 0.5 1.0 LSB LSB (3) (3) * * * * VZX VYX VZY VXY -4 -4 -4 -4 — — — — +4 +4 +4 +4 % % % % (3) (3) (3) (3) * * * * ΔSTLow25 ΔSTLow ΔSTHI25 ΔSTHI ΔSTMIN 11.25 10.68 22.5 21.37 ΔSTNOM 15 15 30 30 ΔSTMAX 18.75 19.69 37.5 39.38 g g g g (1) (1) (1) (1) ΔSTLow 10.68 15 19.69 g (3) ΔSTHI 21.37 30 39.38 g (3) ΔSTCrossAxis ΔSTCrossAxis -10 -10 ⎯ ⎯ +10 +10 LSB LSB (1) (1) gg-cell_Clip 500 560 600 g (19) 80 Nonlinearity * * * * * * OFFTHRPOS OFFTHRNEG * System Output Noise 81 RMS (10-bit, All Ranges, 400 Hz, 4-pole LPF) 82 Peak to Peak (10-bit, All Ranges, 400 Hz, 4-pole LPF) 83 84 85 86 Cross-Axis Sensitivity VZX VYX VZY VXY Self-Test Output Change (Ref Section 3.6) STMAG_X, STMAG_Y = 0, TA = 25°C STMAG_X, STMAG_Y = 0, -40°C ≤ TA ≤ 105°C STMAG_X, STMAG_Y = 1, TA = 25°C STMAG_X, STMAG_Y = 1, -40°C ≤ TA ≤ 105°C STMAG_X, STMAG_Y = 0, -40°C ≤ TA ≤ 105°C VCC_UV_f ≤ VCC - VSS ≤ VL STMAG_X, STMAG_Y = 1, -40°C ≤ TA ≤ 105°C 92 VCC_UV_f ≤ VCC - VSS ≤ VL 87 88 89 90 91 Self-Test Cross Axis Output 93 Y-Axis Output with X-Axis Self-Test 94 X-Axis Output with Y-Axis Self-Test 95 Acceleration (without hitting internal g-cell stops) X/Y-Axis, Any Range Positive/Negative MMA68xx Sensors Freescale Semiconductor, Inc. 7 2.5 Dynamic Electrical Characteristics - Signal Chain VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified # 96 97 98 Characteristic DSP Sample Rate (LPF 0, 1, 2, 3, 4, 5) DSP Sample Rate (LPF 8, 9, 10, 11, 12, 13) Interpolation Sample Rate Symbol Min Typ Max Units tS tS tINTERP ⎯ ⎯ ⎯ 64/fOSC 128/fOSC tS/2 ⎯ ⎯ ⎯ s s s (7) (7) (7) 99 100 Datapath Latency (excluding g-cell and Low Pass Filter) TS = 64/fOSC TS = 128/fOSC * * tDataPath_8 tDataPath_16 33.0 51.9 34.8 54.6 36.5 57.4 μs μs (7, 16) (7, 16) 101 102 103 104 105 106 Low-Pass Filter (ts = 8μs) Cutoff frequency 0: 100 Hz, 4-pole Cutoff frequency 1: 300 Hz, 4-pole Cutoff frequency 2: 400 Hz, 4-pole Cutoff frequency 3: 800 Hz, 4-pole Cutoff frequency 4: 1000 Hz, 4-pole Cutoff frequency 5: 400 Hz, 3-pole * * * * * * fC0(LPF) fC1(LPF) fC2(LPF) fC3(LPF) fC4(LPF) fC5(LPF) 95 285 380 760 950 380 100 300 400 800 1000 400 105 315 420 840 1050 420 Hz Hz Hz Hz Hz Hz (3, 7, 17) (7, 17) (7, 17) (7, 17) (7, 17) (7, 17) 107 108 109 110 111 112 Low-Pass Filter (ts = 16μs) Cutoff frequency 8: 50 Hz, 4-pole Cutoff frequency 9: 150 Hz, 4-pole Cutoff frequency 10: 200 Hz, 4-pole Cutoff frequency 11: 400 Hz, 4-pole Cutoff frequency 12: 500 Hz, 4-pole Cutoff frequency 13: 200 Hz, 3-pole * * * * * * fC8(LPF) fC9(LPF) fC10(LPF) fC11(LPF) fC12(LPF) fC13(LPF) 47.5 142.5 190 380 475 190 50 150 200 400 500 200 52.5 157.5 210 420 525 210 Hz Hz Hz Hz Hz Hz (7, 17) (7, 17) (7, 17) (7, 17) (7, 17) (7, 17) 113 114 115 116 117 118 119 Offset Cancellation (Normal Mode, 10-bit Output) Offset Averaging Period Offset Slew Rate Offset Update Rate Offset Correction Value per Update Positive Offset Correction Value per Update Negative Offset Correction Threshold Positive Offset Correction Threshold Negative * * * * * * * OFFAVEPER OFFSLEW OFFRATE OFFCORRP OFFCORRN OFFTHP OFFTHN ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 6.291456 0.2384 1049 0.25 -0.25 0.125 0.125 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ s LSB/s ms LSB LSB LSB LSB (7) (7) (7) (7) (7) (7) (7) 120 Offset Monitor Bypass Time after Self-Test Deactivation tST_OMB ⎯ 320 ⎯ tS (3, 7) 121 Time Between Acceleration Data Requests (Same Axis) tACC_REQ 15 ⎯ ⎯ μs (3, 7, 20) 122 123 124 Arming Output Activation Time (ARM_X, ARM_Y, IARM = 200μA) Moving Average and Count Arming Modes (2, 3, 4, 5) Unfiltered Mode Activation Delay (Reference Figure 27) Unfiltered Mode Arm Assertion Time (Reference Figure 27) tARM tARM_UF_DLY tARM_UF_ASSERT 0 0 5.00 ⎯ ⎯ ⎯ 1.05 1.05 6.579 μs μs μs (3, 12) (3, 12) (3) 125 Sensing Element Natural Frequency (-40°C ≤ TA ≤ 105°C) fgcell 10791 ⎯ 15879 Hz (19) 126 Sensing Element Cutoff Frequency (-3 dB ref. to 0 Hz, -40°C ≤ TA ≤ 105°C) fgcell 0.851 ⎯ 2.29 kHz (19) 127 Sensing Element Damping Ratio (-40°C ≤ TA ≤ 105°C) ζgcell 2.46 ⎯ 9.36 ⎯ (19) 128 Sensing Element Delay (@100 Hz, -40°C ≤ TA ≤ 105°C) fgcell_delay 70 ⎯ 187 μs (19) 129 Package Resonance Frequency fPackage 100 ⎯ ⎯ kHz (19) 130 Package Quality Factor qPackage 1 ⎯ 5 (19) MMA68xx 8 Sensors Freescale Semiconductor, Inc. 2.6 Dynamic Electrical Characteristics - Supply and SPI VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified # Characteristic Symbol Min Typ Max Units tOP tOP ⎯ ⎯ ⎯ ⎯ 10 840 ms μs (3) (3, 7) * fOSC fOSCTST 7.6 0.95 8 1 8.4 1.05 MHz MHz (7) (1) * * * tSCLK tSCLKH tSCLKL tSCLKR tSCLKF tLEAD 120 40 40 ⎯ ⎯ 60 ⎯ 20 10 0 ⎯ 60 ⎯ 526 60 60 ⎯ ⎯ ⎯ 15 15 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 40 28 ⎯ 60 ⎯ ⎯ ⎯ 40 ⎯ 60 ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) (3) (3) (19) (19) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (19) 131 Power-On Recovery Time(VCC = VCCMIN to first SPI access) 132 Power-On Recovery Time(Internal POR to first SPI access) 133 Internal Oscillator Frequency 134 Test Frequency - Divided from Internal Oscillator 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Serial Interface Timing (See Figure 6, CMISO ≤ 80pF, RMISO ≥ 10kΩ) Clock (SCLK) period (10% of VCC to 10% of VCC) Clock (SCLK) high time (90% of VCC to 90% of VCC) Clock (SCLK) low time (10% of VCC to 10% of VCC) Clock (SCLK) rise time (10% of VCC to 90% of VCC) Clock (SCLK) fall time (90% of VCC to 10% of VCC) CS asserted to SCLK high (CS = 10% of VCC to SCLK = 10% of VCC) CS asserted to MISO valid (CS = 10% of VCC to MISO = 10/90% of VCC) Data setup time (MOSI = 10/90% of VCC to SCLK = 10% of VCC) MOSI Data hold time (SCLK = 90% of VCC to MOSI = 10/90% of VCC) MISO Data hold time (SCLK = 90% of VCC to MISO = 10/90% of VCC) SCLK low to data valid (SCLK = 10% of VCC to MISO = 10/90% of VCC) SCLK low to CS high (SCLK = 10% of VCC to CS = 90% of VCC) CS high to MISO disable (CS = 90% of VCC to MISO = Hi Z) CS high to CS low (CS = 90% of VCC to CS = 90% of VCC) SCLK low to CS low (SCLK = 10% of VCC to CS = 90% of VCC) CS high to SCLK high (CS = 90% of VCC to SCLK = 90% of VCC) * * * * * * * * * * tACCESS tSETUP tHOLD_IN tHOLD_OUT tVALID tLAG tDISABLE tCSN tCLKCS tCSCLK 1. Parameters tested 100% at final test. 2. Parameters tested 100% at wafer probe. 3. Parameters verified by characterization 4. (*) Indicates a critical characteristic. 5. Verified by qualification testing. 6. Parameters verified by pass/fail testing in production. 7. Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing is determined by internal system clock frequency. 8. N/A 9. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Response is corrected to 0 Hz response. 10.Low-pass filter cutoff frequencies shown are -3dB referenced to 0 Hz response. 11.Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible. 12.Time from falling edge of CS to ARM_X, ARM_Y output valid. 13.N/A 14.Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad. 15.Device characterized at all values of VL and VH. Production test is conducted at all typical voltages (VTYP) unless otherwise noted. 16.Data path Latency is the signal latency from g-cell to SPI output disregarding filter group delays. 17.Filter characteristics are specified independently, and do not include g-cell frequency response. 18.Electrostatic Deflection Test completed during wafer probe. 19.Verified by simulation. 20.Acceleration Data Request timing constraint only applies for proper operation of the Arming Function. MMA68xx Sensors Freescale Semiconductor, Inc. 9 VCC_UV_r VCC VCC_UV_f VREGA_UV_r VREGA_UV_f VREGA Note: VREGA & VREG rise and fall slopes will be dependent on output capacitance and load current VREG_UVR_r VREG_UVR_f VREG POR DEVRES Flag Cleared by User DEVRES Time Figure 5. Powerup Timing CS tLEAD tSCLKR tSCLK tSCLKF tCSN tSCLKH tCSCLK SCLK tSCLKL tLAG tACCESS tVALID tHOLD_OUT tCLKCS tDISABLE MISO tHOLD_IN tSETUP MOSI Figure 6. Serial Interface Timing MMA68xx 10 Sensors Freescale Semiconductor, Inc. 3 Functional Description 3.1 Customer Accessible Data Array A customer accessible data array allows for each device to be customized. The array consists of an OTP factory programmable block and read/write registers for device programmability and status. The OTP and writable register blocks incorporate independent CRC circuitry for fault detection (reference Section 3.2). The writable register block includes a locking mechanism to prevent unintended changes during normal operation. Portions of the array are reserved for factory-programmed trim values. The customer accessible data is shown in Table 3. Table 3. Customer Accessible Data Location Addr Register Bit Function 7 6 5 4 3 2 1 Type 0 $00 SN0 SN[7] SN[6] SN[5] SN[4] SN[3] SN[2] SN[1] SN[0] $01 SN1 SN[15] SN[14] SN[13] SN[12] SN[11] SN[10] SN[9] SN[8] $02 SN2 SN[23] SN[22] SN[21] SN[20] SN[19] SN[18] SN[17] SN[16] $03 SN3 SN[31] SN[30] SN[29] SN[28] SN[27] SN[26] SN[25] SN[24] $04 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $05 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $06 FCTCFG_X STMAG_X 0 0 0 0 0 0 1 $07 FCTCFG_Y STMAG_Y 0 0 0 0 0 0 1 $08 PN PN[7] PN[6] PN[5] PN[4] PN[3] PN[2] PN[1] PN[0] $09 F Invalid Address: ”Invalid Register Request” $0A DEVCTL RES_1 RES_0 Reserved Reserved Reserved Reserved Reserved Reserved $0B DEVCFG Reserved Reserved ENDINIT SD OFMON A_CFG[2] A_CFG[1] A_CFG[0] $0C DEVCFG_X ST_X Reserved Reserved Reserved LPF_X[3] LPF_X[2] LPF_X[1] LPF_X[0] $0D DEVCFG_Y ST_Y Reserved Reserved Reserved LPF_Y[3] LPF_Y[2] LPF_Y[1] LPF_Y[0] $0E ARMCFGX Reserved Reserved APS_X[1] APS_X[0] AWS_XN[1] AWS_XN[0] AWS_XP[1] AWS_XP[0] $0F ARMCFGY Reserved Reserved APS_Y[1] APS_Y[0] AWS_YN[1] AWS_YN[0] AWS_YP[1] AWS_YP[0] $10 ARMT_XP AT_XP[7] AT_XP[6] AT_XP[5] AT_XP[4] AT_XP[3] AT_XP[2] AT_XP[1] AT_XP[0] $11 ARMT_YP AT_YP[7] AT_YP[6] AT_YP[5] AT_YP[4] AT_YP[3] AT_YP[2] AT_YP[1] AT_YP[0] $12 ARMT_XN AT_XN[7] AT_XN[6] AT_XN[5] AT_XN[4] AT_XN[3] AT_XN[2] AT_XN[1] AT_XN[0] AT_YN[0] $13 ARMT_YN AT_YN[7] AT_YN[6] AT_YN[5] AT_YN[4] AT_YN[3] AT_YN[2] AT_YN[1] $14 DEVSTAT UNUSED IDE SDOV DEVINIT MISOERR OFF_Y OFF_X DEVRES $15 COUNT COUNT[7] COUNT[6] COUNT[5] COUNT[4] COUNT[3] COUNT[2] COUNT[1] COUNT[0] $16 OFFCORR_X OFFCORR_X[7] OFFCORR_X[6] OFFCORR_X[5] OFFCORR_X[4] OFFCORR_X[3] OFFCORR_X[2] OFFCORR_X[1] OFFCORR_X[0] $17 OFF_CORR_Y OFFCORR_Y[7] OFFCORR_Y[6] OFFCORR_Y[5] OFFCORR_Y[4] OFFCORR_Y[3] OFFCORR_Y[2] OFFCORR_Y[1] OFFCORR_Y[0] $1C Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $1D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W R Type Codes: F: Factory programmed OTP location R/W:Read/Write register R:Read-only register N/A:Not applicable MMA68xx Sensors Freescale Semiconductor, Inc. 11 3.1.1 Device Serial Number Registers A unique serial number is programmed into the serial number registers of each MMA68xx device during manufacturing. The serial number is composed of the following information: Bit Range Content S12 - S0 Serial Number S31 - S13 Lot Number Serial numbers begin at 1 for all produced devices in each lot, and are sequentially assigned. Lot numbers begin at 1 and are sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number. Depending on lot size and quantities, all possible lot numbers and serial numbers may not be assigned. The serial number registers are included in the OTP shadow register array CRC verification. Reference Section 3.2.1 for details regarding the CRC verification. Beyond this, the contents of the serial number registers have no impact on device operation or performance, and are only used for traceability purposes. 3.1.2 Reserved Registers These reserved registers are read-only and have no impact on device operation or performance. Table 4. Reserved Registers Location Bit Address Register 7 6 5 4 3 2 1 0 $04 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $05 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 3.1.3 Factory Configuration Registers The factory configuration registers are one time programmable, read only registers which contain customer specific device configuration information that is programmed by Freescale. Table 5. Factory Configuration Registers Location Bit Address Register 7 6 5 4 3 2 1 0 $06 FCTCFG_X STMAG_X 0 0 0 0 0 0 1 $07 FCTCFG_Y STMAG_Y 0 0 0 0 0 0 1 3.1.3.1 Self-Test Magnitude Selection Bits (STMAG_Y, STMAG_X) The self-test magnitude selection bits indicate if the nominal self-test deflection value is set to the low or high value as shown in the table below. The Self-Test Magnitude is selected independently for each axis. STMAG_X / STMAG_Y Full-Scale Acceleration Range Nominal Self-Test Deflection Value (Reference Section 2.4) 0 ℜ ≤ 60g ΔSTLow 1 > 60g ΔSTHI MMA68xx 12 Sensors Freescale Semiconductor, Inc. 3.1.4 Part Number Register (PN) The part number register is a one time programmable, read only register which contains two digits of the device part number to identify the axis and range information. The contents of this register have no impact on device operation or performance. Table 6. Part Number Register Location Address $08 Bit Register 7 PN PN[7] 6 PN[6] PN Register Value 5 PN[5] 4 PN[4] 3 2 PN[3] PN[2] Decimal HEX X-Axis Range Reference Section 2.4 1 $01 20 20 2 $02 20 35 3 $03 20 50 4 $04 20 75 5 $05 25 120 6 $06 35 20 7 $07 35 35 8 $08 35 50 9 $09 35 75 10 $0A 35 100 11 $0B 60 25 12 $0C 50 35 13 $0D 50 50 14 $0E 50 75 15 $0F 50 100 16 $10 75 20 17 $11 75 35 18 $12 75 50 19 $13 75 75 1 0 PN[1] PN[0] Y-Axis Range Reference Section 2.4 20 $14 75 100 21 $15 120 25 22 $16 100 35 23 $17 120 60 24 $18 100 75 25 $19 100 100 26 $1A 60 60 27 $1B 120 120 28 $1C 60 120 MMA68xx Sensors Freescale Semiconductor, Inc. 13 3.1.5 Device Control Register (DEVCTL) The device control register is a read-write register which contains device control operations that can be applied during both initialization and normal operation. Table 7. Device Control Register Location Bit Address Register 7 6 5 4 3 2 1 0 $0A DEVCTL RES_1 RES_0 Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reset Value 3.1.5.1 Reset Control (RES_1, RES_0) A series of three consecutive register write operations to the reset control bits in the DEVCTL register will cause a device reset. To reset the internal digital circuitry, the following register write operations must be performed in the order shown below. The register write operations must be consecutive SPI commands in the order shown or the device will not be reset. Register Write to DEVCTL RES_1 RES_0 Effect SPI Register Write 1 0 0 No Effect SPI Register Write 2 1 1 No Effect SPI Register Write 3 0 1 Device RESET The response to the Register Write returns ’0’ for RES_1 and RES_0. A Register Read of RES_1 and RES_0 returns ’0’ and terminates the reset sequence. 3.1.5.2 Reserved Bits (DEVCTL[5:0]) Bits 5 through 0 of the DEVCTL register are reserved. A write to the reserved bits must always be logic ’0’ for normal device operation and performance. 3.1.6 Device Configuration Register (DEVCFG) The device configuration register is a read/write register which contains data for general device configuration. The register can be written during initialization but is locked once the ENDINIT bit is set. This register is included in the writable register CRC check. Refer to Section 3.2.2 for details. Table 8. Device Configuration Register Location Bit Address Register 7 6 5 4 3 2 1 0 $0B DEVCFG Reserved Reserved ENDINIT SD OFMON A_CFG[2] A_CFG[1] A_CFG[0] 0 0 0 0 0 0 0 0 Reset Value 3.1.6.1 Reserved Bits (Reserved) Bits 6 and 7 of the DEVCFG register are reserved. A write to the reserved bits must always be logic ’0’ for normal device operation and performance. 3.1.6.2 End of Initialization Bit (ENDINIT) The ENDINIT bit is a control bit used to indicate that the user has completed all device and system level initialization tests, and that MMA68xx will operate in normal mode. Once the ENDINIT bit is set, writes to all writable register bits are inhibited except for the DEVCTL register. Once written, the ENDINIT bit can only be cleared by a device reset. The writable register CRC check (reference Section 3.2.2) is only enabled when the ENDINIT bit is set. MMA68xx 14 Sensors Freescale Semiconductor, Inc. 3.1.6.3 SD Bit The SD bit determines the format of acceleration data results. If the SD bit is set to a logic ’1’, unsigned results are transmitted, with the zero-g level represented by a nominal value of 512. If the SD bit is cleared, signed results are transmitted, with the zerog level represented by a nominal value of 0. 3.1.6.4 SD Operating Mode 1 Unsigned Data Output 0 Signed Data Output OFMON Bit The OFMON bit determines if the offset monitor circuit is enabled. If the OFMON bit is set to a logic ’1’, the offset monitor is enabled. Refer to Section 3.8.5 for more information. If the OFMON bit is cleared, the offset monitor is disabled. 3.1.6.5 OFMON Operating Mode 1 Offset Monitor Circuit Enabled 0 Offset Monitor Circuit Disabled ARM Configuration Bits (A_CFG[2:0]) The ARM Configuration Bits (A_CFG[2:0]) select the mode of operation for the ARM_X/PCM_X, ARM_Y/PCM_Y pins. Table 9. Arming Output Configuration A_CFG[2] A_CFG[1] A-CFG[0] Operating Mode Output Type 0 0 0 Arm Output Disabled Hi Impedance 0 0 1 PCM Output Digital Output Reference Section 3.8.9.1 0 1 0 Moving Average Mode Active High with Pulldown Current Section 3.8.9.1 0 1 1 Moving Average Mode Active Low with Pullup Current Section 3.8.9.1 1 0 0 Count Mode Active High with Pulldown Current Section 3.8.9.2 1 0 1 Count Mode Active Low with Pullup Current Section 3.8.9.2 1 1 0 Unfiltered Mode Active High with Pulldown Current Section 3.8.9.3 1 1 1 Unfiltered Mode Active Low with Pullup Current Section 3.8.9.3 3.1.7 Axis Configuration Registers (DEVCFG_X, DEVCFG_Y) The Axis configuration registers are read/write registers which contain axis specific configuration information. These registers can be written during initialization, but are locked once the ENDINIT bit is set. These registers are included in the writable register CRC check. Refer to Section 3.2.2 for details. Table 10. Axis Configuration Registers Location Bit Address Register 7 6 5 4 3 2 1 0 $0C DEVCFG_X ST_X Reserved Reserved Reserved LPF_X[3] LPF_X[2] LPF_X[1] LPF_X[0] $0D DEVCFG_Y ST_Y Reserved Reserved Reserved LPF_Y[3] LPF_Y[2] LPF_Y[1] LPF_Y[0] 0 0 0 0 0 0 0 0 Reset Value MMA68xx Sensors Freescale Semiconductor, Inc. 15 3.1.7.1 Self-Test Control (ST_X, ST_Y) The ST_X and ST_Y bits enable and disable the self-test circuitry for their respective axes. Self-Test circuitry is enabled if a logic ’1’ is written to ST_X, or ST_Y and the ENDINIT bit has not been set. Enabling the self-test circuitry results in a positive acceleration value on the enabled axis. Self-test deflection values are specified in Section 2.4. ST_X and ST_Y are always cleared following internal reset. When the self-test circuitry is active, the offset cancellation block and the offset monitor status are suspended, and the status bits in the Acceleration Data Request Response will indicate ”Self-Test Active”. Reference Section 3.8.4 and Section 4.2 for details. When the self-test circuitry is disabled by clearing the ST_X or ST_Y bit, the offset monitor remains disabled until the time tST_OMB, specified in Section 2.5, expires. However, the status bits in the Acceleration Data Request Response will immediately indicate that self-test has been deactivated. 3.1.7.2 Reserved Bits (Reserved) Bits 6 through 4 of the DEVCFG_X and DEVCFG_Y registers are reserved. A write to the reserved bits must always be logic ’0’ for normal device operation and performance. 3.1.7.3 Low-Pass Filter Selection Bits (LPF_X[3:0], LPF_Y[3:0]) The Low Pass Filter selection bits independently select a low-pass filter for each axis as shown in Table 11. Refer to Section 3.8.3 for details regarding filter configurations. Table 11. Low Pass Filter Selection Bits LPF_X[3] / LPF_Y[3] LPF_X[2] / LPF_Y[2] LPF_X[1] / LPF_Y[1] LPF_X[0] / LPF_Y[0] 0 0 0 0 100 Hz, 4 pole 8 0 0 0 1 300 Hz, 4 Pole 8 0 0 1 0 400 Hz, 4 Pole 8 0 0 1 1 800 Hz, 4 Pole 8 0 1 0 0 1000 Hz, 4 pole 8 0 1 0 1 400 Hz, 3 Pole 8 0 1 1 0 Reserved Reserved 0 1 1 1 Reserved Reserved 1 0 0 0 50 Hz, 4 pole 16 1 0 0 1 150 Hz, 4 Pole 16 1 0 1 0 200 Hz, 4 Pole 16 1 0 1 1 400 Hz, 4 Pole 16 1 1 0 0 500 Hz, 4 Pole 16 1 1 0 1 200 Hz, 3 Pole 16 1 1 1 0 Reserved Reserved 1 Reserved Reserved 1 1 1 Note: Filter characteristics do not include g-cell frequency response. 3.1.8 Low Pass Filter Selected Nominal Sample Rate (μs) Arming Configuration Registers (ARMCFGX, ARMCFGY) The arming configuration registers contain configuration information for the arming function. The values in these registers are only relevant if the arming function is operating in moving average mode, or count mode. These registers can be written during initialization but are locked once the ENDINIT bit is set. Refer to Section 3.1.6.2. These registers are included in the writable register CRC check. Refer to Section 3.2.2 for details. Table 12. Arming Configuration Register Location Bit Address Register 7 6 5 4 $0E ARMCFGX Reserved Reserved APS_X[1] APS_X[0] $0F ARMCFGY Reserved Reserved APS_Y[1] APS_Y[0] 0 0 0 0 Reset Value 3 1 0 AWS_XN[1] AWS_XN[0] AWS_XP[1] AWS_XP[0] AWS_YN[1] AWS_YN[0] AWS_YP[1] AWS_YP[0] 1 1 1 2 1 MMA68xx 16 Sensors Freescale Semiconductor, Inc. 3.1.8.1 Reserved Bits (Reserved) Bits 7 through 6 of the ARMCFGX and ARMCFGY registers are reserved. A write to the reserved bits must always be logic ’0’ for normal device operation and performance. 3.1.8.2 Arming Pulse Stretch (APS_X[1:0], APS_Y[1:0]) The APS_X[1:0] and APS_Y[1:0] bits set the programmable pulse stretch time for the arming outputs. Refer to Section 3.8.9 for more details regarding the arming function. Table 13. Arming Pulse Stretch Definitions APS_X[1], APS_Y[1] APS_X[0], APS_Y[0] Pulse Stretch Time(1) (Typical Oscillator) 0 0 0 mS 0 1 16.256 ms - 16.384 ms 1 0 65.408 ms - 65.536 ms 1 1 261.888 ms - 262.016 ms 1.Pulse stretch times are derived from the internal oscillator, so the tolerance on this oscillator applies. 3.1.8.3 Arming Window Size (AWS_Xx[1:0], AWS_Yx[1:0]) The AWS_Xx[1:0] and AWS_Yx[1:0] bits have a different function depending on the state of the A_CFG bits in the DEVCFG register. If the arming function is set to moving average mode, the AWS bits set the number of acceleration samples used for the arming function moving average. The number of samples is set independently for each axis and polarity. If the arming function is set to count mode, the AWS bits set the sample count limit for the arming function. The sample count limit is set independently for each axis. Refer to Section 3.8.9 for more details regarding the arming function. Table 14. X-Axis Positive Arming Window Size Definitions (Moving Average Mode) AWS_XP[1] AWS_XP[0] X-Axis Positive Window Size 0 0 2 0 1 4 1 0 8 1 1 16 Table 15. X-Axis Negative Arming Window Size Definitions (Moving Average Mode) AWS_XN[1] AWS_XN[0] X-Axis Negative Window Size 0 0 2 0 1 4 1 0 8 1 1 16 Table 16. Y-Axis Positive Arming Window Size Definitions (Moving Average Mode) AWS_YP[1] AWS_YP[0] Y-Axis Positive Window Size 0 0 2 0 1 4 1 0 8 1 1 16 MMA68xx Sensors Freescale Semiconductor, Inc. 17 Table 17. Y-Axis Negative Arming Window Size Definitions (Moving Average Mode) AWS_YN[1] AWS_YN[0] Y-Axis Negative Window Size 0 0 2 0 1 4 1 0 8 1 1 16 Table 18. Arming Count Limit Definitions (Count Mode) AWS_XN[1] AWS_XN[0] AWS_XP[1] AWS_XP[0] X-Axis Sample Count Limit Don’t Care Don’t Care 0 0 1 Don’t Care Don’t Care 0 1 3 Don’t Care Don’t Care 1 0 7 Don’t Care Don’t Care 1 1 15 Table 19. Arming Count Limit Definitions (Count Mode) AWS_YN[1] AWS_YN[0] AWS_YP[1] AWS_YP[0] Y-Axis Sample Count Limit Don’t Care Don’t Care 0 0 1 Don’t Care Don’t Care 0 1 3 Don’t Care Don’t Care 1 0 7 Don’t Care Don’t Care 1 1 15 MMA68xx 18 Sensors Freescale Semiconductor, Inc. 3.1.9 Arming Threshold Registers (ARMT_XP, ARMT_XN, ARMT_YP, ARMT_YN) These registers contain the X-axis and Y-axis positive and negative thresholds to be used by the arming function. Refer to Section 3.8.9 for more details regarding the arming function. These registers can be written during initialization but are locked once the ENDINIT bit is set. Refer to Section 3.1.6.2. These registers are included in the writable register CRC check. Refer to Section 3.2.2 for details. Table 20. Arming Threshold Registers Location Bit Address Register 7 6 5 4 3 2 1 0 $10 ARMT_XP AT_XP[7] AT_XP[6] AT_XP[5] AT_XP[4] AT_XP[3] AT_XP[2] AT_XP[1] AT_XP[0] $11 ARMT_YP AT_YP[7] AT_YP[6] AT_YP[5] AT_YP[4] AT_YP[3] AT_YP[2] AT_YP[1] AT_YP[0] $12 ARMT_XN AT_XN[7] AT_XN[6] AT_XN[5] AT_XN[4] AT_XN[3] AT_XN[2] AT_XN[1] AT_XN[0] $13 ARMT_YN AT_YN[7] AT_YN[6] AT_YN[5] AT_YN[4] AT_YN[3] AT_YN[2] AT_YN[1] AT_YN[0] 0 0 0 0 0 0 0 0 Reset Value The values programmed into the threshold registers are the threshold values used for the arming function as described in Section 3.8.9. The threshold registers hold independent unsigned 8-bit values for each axis and polarity. Each threshold increment is equivalent to one output LSB. Table 21 shows examples of some threshold register values and the corresponding threshold. Table 21. Threshold Register Value Examples Axis Type Programmed Thresholds Range (g) Sensitivity (g/LSB) Positive (Decimal) Negative (Decimal) Positive Threshold (g) Negative Threshold (g) 20 0.04097 100 50 4.10 -2.05 20 0.04097 255 0 10.45 Disabled 50 0.1024 50 20 5.12 -2.05 120 0.24414 20 10 4.88 -2.44 If either the positive or negative threshold for one axis is programmed to $00, comparisons are disabled for only that polarity. The arming function still operates for the opposite polarity. If both the positive and negative arming thresholds for one axis are programmed to $00, the Arming function for the associated axis is disabled, and the associated output pin is disabled, regardless of the value of the A_CFG bits in the DEVCFG register. 3.1.10 Device Status Register (DEVSTAT) The device status register is a read-only register. A read of this register clears the status flags affected by transient conditions. Reference Section 4.5 for details on the MMA68xx response for each status condition. Table 22. Device Status Register Location Bit Address Register 7 6 5 4 3 2 1 0 $14 DEVSTAT UNUSED IDE SDOV DEVINIT MISOERR OFF_Y OFF_X DEVRES 3.1.10.1 Unused Bit (UNUSED) The unused bit has no impact on operation or performance. When read this bit may be ’1’ or ’0’. 3.1.10.2 Internal Data Error Flag (IDE) The internal data error flag is set if a customer or OTP register data CRC fault or other internal fault is detected as defined in Section 4.5.5. The internal data error flag is cleared by a read of the DEVSTAT register. If the error is associated with a CRC fault in the writable register array, the fault will be re-asserted and will require a device reset to clear. If the error is associated with the data stored in the fuse array, the fault will be re-asserted even after a device reset. MMA68xx Sensors Freescale Semiconductor, Inc. 19 3.1.10.3 Sigma Delta Modulator Over Range Flag (SDOV) The sigma delta modulator over range flag is set if the sigma delta modulator for either axis becomes saturated. The SDOV flag is cleared by a read of the DEVSTAT register. 3.1.10.4 Device Initialization Flag (DEVINIT) The device initialization flag is set during the interval between negation of internal reset and completion of internal device initialization. DEVINIT is cleared automatically. The device initialization flag is not affected by a read of the DEVSTAT register. 3.1.10.5 SPI MISO Data Mismatch Error Flag (MISOERR) The MISO data mismatch flag is set when a MISO Data mismatch fault occurs as specified in Section 4.5.2. The MISOERR flag is cleared by a read of the DEVSTAT register. 3.1.10.6 Offset Monitor Over Range Flags (OFF_X, OFFSET_Y) The offset monitor over range flags are set if the acceleration signal of the associated axis reaches the specified offset limit. The offset monitor over range flags are cleared by a read of the DEVSTAT register. 3.1.10.7 Device Reset Flag (DEVRES) The device reset flag is set during device initialization following a device reset. The device reset flag is cleared by a read of the DEVSTAT register. 3.1.11 Count Register (COUNT) The count register is a read-only register which provides the current value of a free-running 8-bit counter derived from the primary oscillator. A 10-bit pre-scaler divides the primary oscillator frequency by 1024. Thus, the value in the register increases by one count every 128 μs and the counter rolls over every 32.768 ms. Table 23. Count Register Location Bit Address Register 7 6 5 4 3 2 1 0 $15 COUNT COUNT[7] COUNT[6] COUNT[5] COUNT[4] COUNT[3] COUNT[2] COUNT[1] COUNT[0] 0 0 0 0 0 0 0 0 Reset Value 3.1.12 Offset Correction Value Registers (OFFCORR_X, OFFCORR_Y) The offset correction value registers are read-only registers which contain the most recent offset correction increment / decrement value from the offset cancellation circuit. The values stored in these registers indicate the amount of offset correction being applied to the SPI output data. The values have a resolution of 1 LSB. Table 24. Offset Correction Value Register Location Address $16 Register Bit 7 6 5 4 3 2 1 0 OFFCORR_X OFFCORR_X[7] OFFCORR_X[6] OFFCORR_X[5] OFFCORR_X[4] OFFCORR_X[3] OFFCORR_X[2] OFFCORR_X[1] OFFCORR_X[0] $17 OFFCORR_Y OFFCORR_Y[7] OFFCORR_Y[6] OFFCORR_Y[5] OFFCORR_Y[4] OFFCORR_Y[3] OFFCORR_Y[2] OFFCORR_Y[1] OFFCORR_Y[0] Reset Value 0 0 0 0 0 0 0 0 3.1.13 Reserved Registers (Reserved) Registers $1C and $1D are reserved. A write to the reserved bits must always be logic ’0’ for normal device operation and performance. Table 25. Reserved Registers Location Bit Address Register 7 6 5 4 3 2 1 0 $1C Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved $1D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reset Value MMA68xx 20 Sensors Freescale Semiconductor, Inc. 3.2 Customer Accessible Data Array CRC Verification 3.2.1 OTP Shadow Register Array CRC Verification The OTP shadow register array is verified for errors using a 3-bit CRC. The CRC verification uses a generator polynomial of g(x) = X 3+ X + 1, with a seed value = ’111’. If a CRC error is detected in the OTP array, the IDE bit is set in the DEVSTAT register. 3.2.2 Writable Register CRC Verification The writable registers in the data array are verified for errors using a 3-bit CRC. The CRC verification is enabled only when the ENDINIT bit is set in the DEVCFG register. The CRC verification uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = ’111’. If a CRC error is detected in the writable register array, the IDE bit is set in the DEVSTAT register. MMA68xx Sensors Freescale Semiconductor, Inc. 21 3.3 Voltage Regulators Separate internal voltage regulators supply the analog and digital circuitry. External filter capacitors are required, as shown in Figure 1. The voltage regulator module includes voltage monitoring circuitry which indicates a device reset until the external supply and all internal regulated voltages are within predetermined limits. A reference generator provides a stable voltage which is used by the ΣΔ converters. VCC BANDGAP REFERENCE VREGA = 2.50 V VOLTAGE REGULATOR CREGA PRIMARY OSCILLATOR BIAS GENERATOR TRIM TRIM ΣΔ CONVERTER REFERENCE GENERATOR VREF = 1.250 V DIGITAL LOGIC DSP TRACKING REGULATOR Tracks VREGA OTP ARRAY VREG = 2.50 V CREG Figure 7. Power Supply VCCUV VCC VREG VREGOV VREGUV MONITOR BANDGAP GROUND LOSS MONITOR VBGMON VREGA SET DEVRES Flag VREGAUV VREGAOV VREG VREF VREFOV VREFUV VPORREF POR Note: No external access to reference voltage Limits verified by characterization only Figure 8. Voltage Monitoring MMA68xx 22 Sensors Freescale Semiconductor, Inc. 3.3.1 CREG Failure Detection The digital supply voltage regulator is designed to be unstable with low capacitance. If the connection to the VREG capacitor becomes open, the digital supply voltage will oscillate and cause either an undervoltage, or overvoltage failure within one internal sample time. This failure will result in one of the following: 1. The DEVRES flag in the DEVSTAT register will be set. MMA68xx will respond to SPI acceleration requests as defined in Table 30. 2. MMA68xx will be held in RESET and be non-responsive to SPI requests. 3.3.2 CREGA Failure Detection The analog supply voltage regulator is designed to be unstable with low capacitance. If the connection to the VREGA capacitor becomes open, the analog supply voltage will oscillate and cause either an undervoltage, or overvoltage failure within one internal sample time. The DEVRES flag in the DEVSTAT register will be set. MMA68xx will respond to SPI acceleration requests as defined in Table 30. Note: This feature is only supported with a VCC supply voltage in the range of 4.75V to 5.25V. 3.3.3 VSS and VSSA Ground Loss Monitor MMA68xx detects the loss of ground connection to either VSS or VSSA. A loss of ground connection to VSS will result in a VREG overvoltage failure. A loss of ground connection to VSSA will result in a VREG undervoltage failure. Both failures result in a device reset. 3.3.4 SPI Initiated Reset In addition to voltage monitoring, a device reset can be initiated by a specific series of three write operations involving the RES_1 and RES_0 bits in the DEVCTL register. Reference Section 3.1.5.1. for details regarding the SPI initiated reset. 3.4 Internal Oscillator MMA68xx includes a factory trimmed oscillator as specified in Section 2.6. 3.4.1 Oscillator Monitor The COUNT register in the customer accessible array is a read-only register which provides the current value of a free-running 8-bit counter derived from the primary oscillator. A 10-bit pre-scaler divides the primary oscillator by 1024. Thus, the value in the COUNT register increases by one count every 128 μs, and the register rolls over every 32.768 ms. The SPI master can periodically read the COUNT register, and verify the difference between subsequent register reads against the system time base. 1. The SPI access rates and deviations must be taken into account for this oscillator verification. 3.5 Transducer The MMA68xx transducer is an overdamped mass-spring-damper system described by the following transfer function: 2 ωn H ( s ) = -------------------------------------------------------2 2 s + 2 ⋅ ξ ⋅ ωn ⋅ s + ωn where: ζ = Damping Ratio ωn = Natural Frequency = 2∗Π∗fn Reference Section 2.4 for transducer parameters. MMA68xx Sensors Freescale Semiconductor, Inc. 23 3.6 Self-Test Interface The self-test interface applies a voltage to the g-cell, causing deflection of the proof mass. The self-test interface is controlled through SPI write operations to the DEVCFG_X and DEVCFG_Y registers described in Section 3.1.7. The ENDINIT bit in the DEVCFG register must also be low to enable self-test. A diagram of the self-test interface is shown in Figure 9. ST_Y ENDINIT Y-AXIS g-CELL SELF-TEST VOLTAGE GENERATOR X-AXIS g-CELL ENDINIT ENDINIT ST_X Figure 9. Self-Test Interface The raw self-test deflection can be verified against raw self-test limits using the following equations: ΔST MINLIMIT = FLOOR ⋅ ( ΔST MIN ) ⋅ [ SENS ⋅ ( 1 – ΔSENS ) ] ΔST MAXLIMIT = CEIL ⋅ ( ΔST MAX ) ⋅ [ SENS ⋅ ( 1 + ΔSENS ) ] where: ΔSTMIN The minimum self-test deflection over temperature as specified in Section 2.4. ΔSTMAX The maximum self-test deflection over temperature as specified in Section 2.4. SENS ΔSENS The sensitivity of the device The sensitivity tolerance MMA68xx 24 Sensors Freescale Semiconductor, Inc. 3.7 ΣΔ Converters Two sigma delta converters provide the interface between the g-cell and the DSP. The output of each ΣΔ converter is a data stream at a nominal frequency of 1 MHz. g-CELL α1= CTOP VX FIRST INTEGRATOR CINT1 z-1 SECOND INTEGRATOR α2 z-1 1 - z-1 CBOT 1-BIT QUANTIZER ΣΔ_OUT 1 - z-1 ADC ΔC = CTOP - CBOT β1 β2 DAC V = ΔC x VX / CINT1 V = ℜ±2 ℜ× VREF Figure 10. ΣΔ Converter Block Diagram 3.8 Digital Signal Processing Block A digital signal processing (DSP) block is used to perform signal filtering and compensation operations. A diagram illustrating the signal processing flow is shown in Figure 11. Arm/PCM Output Section 3.8.9 Section 3.8.10 A ΣΔ_OUT SINC Filter Section 3.8.2 B Low Pass Filter Section 3.8.3 C Compensation D Section 3.8.6 Interpolation Section 3.8.7 E Offset Cancellation Section 3.8.4 F Offset Cancellation Output Scaling Raw Output Scaling I To ARM_x G To SPI H To SPI Figure 11. Signal Chain Diagram Table 26. MMA68xx Signal Chain Characteristics Description Sample Time (μs) Data Width Bits A SD 1 B SINC Filter C Over Bits Effective Bits Rounding Resolution Bits Typical Block Latency Reference 1 1 — 3.2 μs Section 3.7 8 14 13 — 11.2 μs Section 3.8.2 Low Pass Filter 8/16 20 6 10 4 Reference Section 3.8.3 Section 3.8.3 D Compensation 8/16 20 6 10 4 7.875 μs Section 3.8.6 E Interpolation 4/8 20 6 10 4 ts / 2 Section 3.8.7 F Offset Cancellation 256 20 6 10 4 N/A Section 3.8.4 G, H SPI Output 4/8 — — 10 — ts / 2 — I PCM Output 4/8 — — 9 — — Section 3.8.10 MMA68xx Sensors Freescale Semiconductor, Inc. 25 3.8.1 DSP Clock The DSP is clocked at 8 MHz, with an effective 6MHz operating frequency. The clock to the DSP is disabled for 1 clock prior to each edge of the ΣΔ modulator clock to minimize noise during data conversion. The bit streams from the two ΣΔ converters are processed through independent data paths within the DSP. 8 MHz OSC 6 MHz Digital 1MHz Modulator Figure 12. Clock Generation 3.8.2 Decimation Sinc Filter The serial data stream produced by the ΣΔ converter is decimated and converted to parallel values by a 3rd order 16:1 sinc filter with a decimation factor of 8 or 16, depending on the Low Pass Filter selected. 3 1 – z – 16 H ( z ) = ------------------------------------16 × ( 1 – z – 1 ) Figure 13. Sinc Filter Response, tS = 8 μs MMA68xx 26 Sensors Freescale Semiconductor, Inc. 3.8.3 Low Pass Filter Data from the Sinc filter is processed by an infinite impulse response (IIR) low pass filter. n0 + ( n1 ⋅ z –1 ) + ( n2 ⋅ z –2 ) + ( n3 ⋅ z –3 ) + ( n4 ⋅ z –4 ) H ( z ) = ---------------------------------------------------------------------------------------------------------------------------------------d0 + ( d1 ⋅ z –1 ) + ( d2 ⋅ z –2 ) + ( d3 ⋅ z –3 ) + ( d4 ⋅ z –4 ) MMA68xx provides the option for one of twelve low-pass filters. The filter is selected independently for each axis with the LPF_X[3:0] and LPF_Y[3:0] bits in the DEVCFG_X and DEVCFG_Y registers. The filter selection options are listed in Section 3.1.7.3, Table 11. Response parameters for the low-pass filter are specified in Section 2.4. Filter characteristics are illustrated in Figures 14, 15, 16, 17, 18 and 19. Table 27. Low Pass Filter Coefficients Description 50 Hz LPF Sample Time (μs) 16 100 Hz LPF 8 150 Hz LPF 16 300 Hz LPF 200 Hz LPF 8 16 400 Hz LPF 8 200 Hz LPF 3-pole 16 400 Hz LPF 3-pole 400 Hz LPF 8 16 800 Hz LPF 8 500 Hz LPF 16 1000 Hz LPF 8 Filter Coefficients Group Delay n0 2.08729034056887e-10 d0 1 n1 8.349134489240434e-10 d1 -3.976249694824219 n2 1.25237777794924e-09 d2 5.929003009577855 n3 8.349103355433541e-10 d3 -3.929255528257727 n4 2.087307211059861e-10 d4 0.9765022168437554 n0 1.639127731323242e-08 d0 1 n1 6.556510925292969e-08 d1 -3.928921222686768 n2 9.834768482194806e-08 d2 5.789028996785419 n3 6.556510372902331e-08 d3 -3.791257019240902 n4 1.639128257923422e-08 d4 0.9311495074496179 n0 5.124509334564209e-08 d0 1 n1 2.049803733825684e-07 d1 -3.905343055725098 n2 3.074705789151505e-07 d2 5.72004239520561 n3 2.049803958150164e-07 d3 -3.723967810019985 n4 5.124510693742625e-08 d4 0.9092692903507213 n0 2.720393240451813e-06 d0 1 n1 8.161179721355438e-06 d1 -2.931681632995605 n2 8.161180123840722e-06 d2 2.865296718275204 n3 2.720393634345496e-06 d3 -0.9335933215174919 n4 0 d4 0 n0 7.822513580322266e-07 d0 1 n1 3.129005432128906e-06 d1 -3.811614513397217 n2 4.693508163398543e-06 d2 5.450666051045118 n3 3.129005428784364e-06 d3 -3.465805771100349 n4 7.822513604678875e-07 d4 0.8267667478030489 n0 1.865386962890625e-06 d0 1 n1 7.4615478515625e-06 d1 -3.765105724334717 n2 1.119232176112846e-05 d2 5.319861050818872 n3 7.4615478515625e-06 d3 -3.34309015036024 n4 1.865386966264658e-06 d4 0.7883646729233078 26816/fosc 9024/fosc 6784/fosc 5632/fosc 3392/fosc 2688/fosc Note: Low Pass Filter Figures do not include g-cell frequency response. MMA68xx Sensors Freescale Semiconductor, Inc. 27 Figure 14. Low-Pass Filter Characteristics: fC = 100 Hz, Poles = 4, tS = 8 μs MMA68xx 28 Sensors Freescale Semiconductor, Inc. Figure 15. Low-Pass Filter Characteristics: fC = 300 Hz, Poles = 4, tS = 8 μs MMA68xx Sensors Freescale Semiconductor, Inc. 29 Figure 16. Low-Pass Filter Characteristics: fC = 400 Hz, Poles = 4, tS = 8 μs MMA68xx 30 Sensors Freescale Semiconductor, Inc. Figure 17. Low-Pass Filter Characteristics: fC = 400 Hz, Poles = 3, tS = 8 μs MMA68xx Sensors Freescale Semiconductor, Inc. 31 Figure 18. Low-Pass Filter Characteristics: fC = 800 Hz, Poles = 4, tS = 8 μs MMA68xx 32 Sensors Freescale Semiconductor, Inc. Figure 19. Low-Pass Filter Characteristics: fC = 1000 Hz, Poles = 4, tS = 8 μs MMA68xx Sensors Freescale Semiconductor, Inc. 33 3.8.4 Offset Cancellation MMA68xx provides the option to read offset cancelled acceleration data via the SPI by clearing the OC bit in the SPI command (reference Section 4.1). A block diagram of the offset cancellation is shown in Figure 20, and response parameters are specified in Section 2.4 and in Table 28. LPFOUT OFFTHRNEG Accumulator Shift T1 T2 T3 T4 T5 OFF_ERR T6 up to 4096 samples Downsampled to 256μs OFF_ERR OFFTHRPOS OFFTHN INC Offset Inc/Dec OFF_CORR_VALUE OFFCORRP OFFCORRN DEC OFFTHP OCOUT Correction for Start Phase Figure 20. Offset Cancellation Block Diagram In normal operation, the offset cancellation circuit computes a 24,576 sample running average of the acceleration data downsampled to 256 μs. The running average is compared against positive and negative thresholds to determine the offset correction value that will be applied to the acceleration data. During start up, three phases of moving average sizes are used to allow for faster convergence of misuse input signals. Reference Table 28 for offset cancellation timing information during startup and normal operation. Table 28. Offset Cancellation Timing Specifications Phase Start Time of Typical # of Samples in Phase Time in Phase Phase (from POR) (ms) Samples Averaged OFF_CORR_VALUE Averaging Maximum Update Rate Period Slew Rate (ms) (ms) (LSB/s) Averaging Filter -3dB Frequency (Hz) Start 1 tOP 524.288 2048 48 2.048 12.288 122.1 36.05 Start 2 tOP + 524.288 524.288 2048 384 16.38 98.304 15.26 4.506 Start 3 tOP + 1048.576 524.288 2048 3072 131.1 786.432 1.907 0.5632 Normal tOP + 1572.864 — — 24576 1049 6291.456 0.2384 0.07040 When the self-test circuitry is active, the offset cancellation block and the offset monitor block are suspended, and the offset correction value is constant. Once the self-test circuitry is disabled, the offset cancellation block remains suspended for the time tST_OMB to allow the acceleration output to return to its nominal offset. 3.8.5 Offset Monitor MMA68xx provides the option for an offset monitor circuit. The offset monitor circuit is enabled when the OFMON bit in the DEVCFG register is programmed to a logic ‘1’. The output of the offset cancellation circuit is compared against a high and low threshold. If the offset correction value exceeds either the OFFTHRPOS, or OFFTHRNEG threshold, an Offset Over Range condition is indicated. The offset correction value update rate is listed in Table 28: “Maximum Slew Rate”. Because the offset monitor uses this value, the offset monitor will also update at this rate. The time to indicate an Offset Over Range is dependent upon the input signal. The offset monitor status remains frozen during self-test, because the offset monitor is based on the offset cancellation circuit, which is also suspended during self-test. The offset monitor is disabled for 2.1 seconds following reset regardless of the state of the OFMON bit. 3.8.6 Signal Compensation MMA68xx includes internal OTP and signal processing to compensate for sensitivity error and offset error. This compensation is necessary to achieve the specified parameters in Section 2.4. MMA68xx 34 Sensors Freescale Semiconductor, Inc. 3.8.7 Data Interpolation MMA68xx includes 2 to 1 data interpolation to minimize the system sample jitter. Each result produced by the digital signal processing chain is delayed one half of a sample time, and the interpolated value of successive samples is provided between sample times. This operation is illustrated in Figure 21. Sn-3 Sn-2 Sn-1 Sn Internal Sample Rate t ts ts Sn-3 Sn – 3 + Sn – 2 -------------------------------2 ts Sn – 2 + Sn – 1 ------------------------------2 Sn-2 Sn-1 Sn – 1 + Sn -----------------------2 Output Sample Rate t Response to SPI acceleration request occurring in this window receives interpolated sample Response to SPI acceleration request occurring in this window receives true sample. Figure 21. Data Interpolation Timing The effect of this interpolation at the system level is a 50% reduction in sample jitter. Figure 22 shows the resulting output data for an input signal. 80 75 Internally Sampled Values 70 Counts 65 60 Fixed Latency: tS / 2 Earliest Transmission Point of Interpolated Values 55 Earliest Transmission Point of Internally Sampled Values 50 45 Window of Transmission for Interpolated Values (Maximum: tS / 2) Window of Transmission for = Signal Jitter = Sampled Values (Maximum: tS / 2) 40 0 5 10 Input Signal Internally Sampled Signal Interpolated Samples 15 20 25 30 35 40 Time Figure 22. Data Interpolation Example MMA68xx Sensors Freescale Semiconductor, Inc. 35 3.8.8 Acceleration Data Timing The MMA68xx SPI uses a request/response protocol, where a SPI transfer is completed through a sequence of 2 phases. Reference Section 4 for more details regarding the SPI protocol. In order to provide the most recent acceleration data for each request, MMA68xx latches the associated data for an acceleration request at the falling edge of CS for the acceleration response message (the subsequent SPI transfer). The most recent sample available from the DSP (including interpolation), is latched, providing a maximum latency of 1* tS relative to the falling edge of CS. SCLK CS MOSI Request X-Axis Request Y-Axis Request X-Axis Request Y-Axis X-Axis Response Y-Axis Response X-Axis Response MISO X-Axis Data Latched X-Axis Arm Function updated if applicable Y-Axis Data Latched Y-Axis Arm Function updated if applicable MMA68xx 36 Sensors Freescale Semiconductor, Inc. 3.8.9 Arming Function MMA68xx provides the option for an arming function with 3 modes of operation. The operation of the arming function is selected by the state of the A_CFG bits in the DEVCFG register. Reference Section 4.5 for the operation of the Arming function with exception conditions. Error conditions do not impact prior arming function responses. If an error occurs after an arming activation, the corresponding pulse stretch for the existing arming condition will continue. However, new acceleration reads will not update the arming function regardless of the acceleration value. 3.8.9.1 Arming Function: Moving Average Mode In moving average mode, the arming function runs a moving average on the offset cancelled output of each acceleration axis. The number of samples used for the moving average (k) is programmable via the AWS_Xx[1:0] and ARM_Yx[1:0] bits in the ARMCFGX and ARMCFGY registers. Reference Section 3.1.8 for register details. ARM_MAn = (OCn + OCn-1 + ... + OCn+1-k)/k Where n is the current sample. The sample rate for each axis is determined by the SPI acceleration data sample rate. At the falling edge of CS for an acceleration data SPI response, the moving average for the associated axis is updated with a new sample. Reference Figure 25. The SPI acceleration data sample rate must meet the minimum time between requests (tACC_REQ_x) specified in Section 2.5. The moving average output is compared against positive and negative 8-bit thresholds that are individually programmed for each axis via the ARMT_Xx and ARMT_Yx registers. Reference Section 3.1.9 for register details. If the moving average equals or exceeds either threshold, an arming condition is indicated, the ARM_X or ARM_Y output is asserted for the associated axis, and the pulse stretch counter is set as described in Section 3.8.9.4. The ARM_X or ARM_Y output is de-asserted only when the pulse stretch counter expires. Figure 25 shows the arming output operation for different SPI conditions. ARMT_xP[7:0] Positive Moving Average AWS_xP[1:0] Offset Cancellation Pulse Stretch OffCanc_ARM_x[10:0] Gating I/O ARM_x Negative Moving Average AWS_xN[1:0] ARMT_xN[7:0] APS_x[1:0] Figure 23. Arming Function Block Diagram - Moving Average Mode MMA68xx Sensors Freescale Semiconductor, Inc. 37 3.8.9.2 Arming Function: Count Mode In count mode, the arming function compares each input sample against positive and negative thresholds that are individually programmed for each axis via the ARMT_Xx and ARMT_Yx registers. Reference Section 3.1.9 for register details. If the sample equals or exceeds either threshold, a sample counter is incremented. If the sample does not exceed either threshold, the sample counter is reset to zero. The sample rate for each axis is determined by the SPI acceleration data sample rate. At the falling edge of CS for an acceleration data SPI response, a new sample for the associated axis is compared against the thresholds. Reference Figure 25. The SPI acceleration data sample rate must meet the minimum time between requests (tACC_REQ_x) specified in Section 2.5. A sample count limit is programmable via the AWS_Xx[1:0] and AWS_Yx[1:0] bits in the ARMCFGX and ARMCFGY registers. If the sample count reaches the programmable sample count limit, an arming condition is indicated, the ARM_X or ARM_Y output is asserted for the associated axis, and the pulse stretch counter is set as described in Section 3.8.9.4. The ARM_X or ARM_Y output is de-asserted only when the pulse stretch counter expires. Figure 25 shows the arming output operation for different SPI conditions. AWS_xP[1:0] ARMT_xP[7:0] Offset Cancellation 1-4 Sample Pulse Stretch Counter OffCanc_ARM_x[10:0] Gating I/O ARM_x ARMT_xN[7:0] APS_x[1:0] Figure 24. Arming Function Block Diagram - Count Mode SCLK CS MOSI Request X-Axis Request Y-Axis Request X-Axis Request Y-Axis Y-Axis Response X-Axis Response Y-Axis Response X-Axis Response Y-Axis Arm Condition Not Present X-Axis Arm Condition Present Y-Axis Arm Condition Present X-Axis Arm Condition Not Present MISO ARM_X ARM_Y X-Axis Data Latched for Arm Function and SPI tARM Y-Axis Data Latched for Arm Function and SPI X-Axis Data Latched for Arm Function and SPI tARM Y-Axis Pulse Stretch X-Axis Pulse Stretch Figure 25. X and Y Axis Arming Conditions, Moving Average and Count Mode MMA68xx 38 Sensors Freescale Semiconductor, Inc. 3.8.9.3 Arming Function: Unfiltered Mode On the falling edge of CS for an acceleration response, the most recent available DSP sample for the requested axis is compared against positive and negative thresholds that are individually programmed for each axis via the ARMT_Xx and ARMT_Yx registers. Reference Section 3.1.9 for register details. If the sample equals or exceeds either threshold, an arming condition is indicated. Once an arming condition is indicated for the X-Axis, the ARM_X output is asserted when CS is asserted and the MISO data includes an acceleration response for that axis. Once an arming condition is indicated for the Y-Axis, the ARM_Y output is asserted when CS is asserted and the MISO data includes an acceleration response for that axis. The pulse stretch function is not applied in Unfiltered mode. Figure 26 contains a block diagram of the Arming Function operation in Unfiltered Mode. Figure 27 shows the Arming output operation under the different SPI request conditions. ACFG[2] ACFG[1] CS I/O AXIS Select ARM_x ARMING FUNCTION Interpolated Sample Rate Figure 26. Arming Function Block Diagram - Unfiltered Mode SCLK CS MOSI Request X-Axis Request Y-Axis Request X-Axis Request Y-Axis Y-Axis Response X-Axis Response Y-Axis Response X-Axis Response Y-Axis Arm Condition Not Present X-Axis Arm Condition Present Y-Axis Arm Condition Present X-Axis Arm Condition Not Present MISO ARM_X ARM_Y X-Axis Data Latched for Arm Function and SPI tARM_UF_DLY tARM_UF_ASSERT Y-Axis Data Latched for Arm Function and SPI X-Axis Data Latched for Arm Function and SPI tARM_UF_DLY tARM_UF_ASSERT Figure 27. X and Y Axis Arming Conditions, Unfiltered Mode MMA68xx Sensors Freescale Semiconductor, Inc. 39 3.8.9.4 Arming Pulse Stretch Function A pulse stretch function can be applied to the arming outputs in moving average mode, or count mode. If the pulse stretch function is not used (APS_X[1:0] = ’00’ or APS_Y[1:0] = ’00’), the arming output is asserted if and only if an arming condition exists for the associated axis after the most recent evaluated sample. The arming output is de-asserted if and only if an arming condition does not exist for the associated axis after the most recent evaluated sample. If the pulse stretch function is used, (APS_X[1:0] not equal ’00’ or APS_Y[1:0] not equal ’00’), the arming output is controlled only by the value of the pulse stretch timer value. If the pulse stretch timer value is non-zero, the arming output is asserted. If the pulse stretch timer is zero, the arming output is de-asserted. The pulse stretch counter continuously decrements until it reaches zero. The pulse stretch counter is reset to the programmed pulse stretch value if and only if an arming condition exists for the associated axis after the most recent evaluated sample. Reference Figure 25. The desired pulse stretch time is individually programmable for each axis via the APS_X[1:0] and APS_Y[1:0] bits in the ARMCFG register. Exception conditions listed in Section 4.5 do not impact prior arming function responses. If an exception occurs after an arming activation, the corresponding pulse stretch for the existing arming condition will continue. However, new acceleration reads will not reset the pulse stretch counter regardless of the acceleration value. 3.8.9.5 Arming Pin Output Structure The arming output pin structure can be set to active high, or active low with the A_CFG bits in the DEVCFG register as described in Section 3.1.6.5. The active high and active low pin output structures are shown in Figure 28. Open Drain, Active High Open Drain, Active Low VCC Arm Function Gating VCC ARM ARM Arm Function Gating Figure 28. Arming Function - Pin Output Structure 3.8.10 PCM Output Function MMA68xx provides the option for a PCM output function. The PCM output is enabled by setting the A_CFG bits in the DEVCFG register to the appropriate state as described in Section 3.1.6.5. When the PCM function is enabled, the upper 9 bits of the 10bit, offset cancelled, output scaled acceleration values are used to generate 8 MHz Pulse Code Modulated signals proportional to the respective acceleration onto the PCM_X and PCM_Y pins. A block diagram of the PCM output is shown in Figure 29. Exception conditions affect the PCM output as listed in Section 4.5. Output Scaling 9 A CARRY ARM/PCM OC[9:1] 9 Bit ADDER 9 Sample updated every 8μS B SUM D Q D Q D fCLK = 8 MHz 9 Q DFF Q DFF Q DFF Q DFF Q CLK Q DFF Q CLK Q FF D Q CLK Q FF CLK QFF CLK Q FF CLK Q CLK Q CLK Q CLK Q Figure 29. PCM Output Function Block Diagram MMA68xx 40 Sensors Freescale Semiconductor, Inc. 3.9 Serial Peripheral Interface MMA68xx includes a Serial Peripheral Interface (SPI) to provide access to the configuration registers and digital data. Reference Section 4 for details regarding the SPI protocol and available commands. To maximize independence between the X and Y channels, MMA68xx includes two interface blocks, one for each axis. The X-axis interface block responds only to X-axis acceleration requests, or even addressed register commands. The Y-axis interface block responds only to Y-axis acceleration requests, or odd addressed register commands. To the SPI master, MMA68xx operates as a single device. The internal independent blocks are transparent. Each SPI block has an independent shift register. Once a message is received (rising edge of CS), the contents of the two shift registers are compared. If the contents do not match, the Y-Axis SPI block will not respond, and the X-Axis SPI block will respond with a SPI Error as shown in Table 30. If the contents match, each SPI block decodes the message, and the appropriate block enables MISO for a response during the next SPI message. Figure 30 shows an internal diagram of the MMA68xx SPI. Registers X SPI If Bit 13 == ’1’ If Bit 13 = ’0’ & Bit 14 == ’0’ & A0 == ’0’ SPI Master Even Address Regs X SPI Shift Register X-Axis Raw Data X-Axis OC Data CS_M SPI Mismatch Error (SPI Error) CS CS SCLKM SCLK SCLK MOSIM MOSI MOSI MISOM MISO MISO I/O Odd Address Regs Y SPI Shift Register Y-Axis Raw Data Y-Axis OC Data Y SPI If Bit 13 == ’1’ If Bit 13 = ’0’ & Bit 14 == ’1’ & A0 == ’1’ Figure 30. SPI Diagram MMA68xx Sensors Freescale Semiconductor, Inc. 41 3.10 Device Initialization Following powerup, undervoltage reset, or a SPI reset command sequence, MMA68xx proceeds through an internal initialization process as shown below. Figure 31 also shows the MMA68xx performance for an example external system level initialization procedure. Internal Initialization OTP Copy to Offset Cancellation Offset Cancellation Offset Cancellation Offset Cancellation Mirror Registers Startup Phase 1 Startup Phase 2 Startup Phase 3 Normal Mode tOC_PHASE1 tOC_PHASE2 tOC_PHASE3 External Initialization Delay Read DEVSTAT Verify X-Axis to clear flags Self-Test & Verify X-Axis Re-read DEVSTAT ARM_X Asserted Dly to verify Status Dly Offset Verify Y-Axis Initialize R/W Offset & ARM_Y Registers to Deasserted Desired State Dly Re-Initialize Verify X-Axis Offset & ARM_X R/W Registers Normal Deasserted (if needed) Dly Mode Verify Y-Axis Verify Y-Axis and Self-Test & Offset & ARM_Y Set ENDINIT ARM_Y Asserted Deasserted Verify X-Axis Offset & ARM_X Deasserted tSTRISE tOP X_ST Assertion Dependent on Arming Mode X_ARM Deassertion Dependent on Pulse Stretch and/or Arming Mode tST_OMB Y_ST tSTFALL Assertion Dependent on Arming Mode Y_ARM POR Ready for SPI Command ENDINIT Clear Internal Offset Error Corrected to ’0’ Activate X-Axis Self-Test Deactivate X-Axis Self -Test Activate Y-Axis Self-Test Deassertion Dependent on Pulse Stretch and/or Arming Mode Deactivate Y-Axis Self-Test Notes:1) X-Axis and Y-Axis Self-Test can be enabled and evaluated simultaneously to reduce test time. For failure mode coverage of the arming pins and of potential common axis failures, Freescale recommends independent self-test activation. 2) tSTRISE and tSTFALL are dependent on the selected LPF group delay. Figure 31. Initialization Process MMA68xx 42 Sensors Freescale Semiconductor, Inc. 3.11 Overload Response 3.11.1 Overload Performance MMA68xx is designed to operate within a specified range. Acceleration beyond that range (overload) impacts the output of the sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the device that is dependent upon the overload frequency and amplitude. The MMA68xx g-cell is overdamped, providing the optimal design for overload performance. However, the performance of the device during an overload condition is affected by many other parameters, including: • g-cell damping • Non-linearity • Clipping limits • Symmetry Figure 32 shows the g-cell, ADC and output clipping of MMA68xx over frequency. The relevant parameters are specified in Section 2.1, and Section 2.6. g-cellRolloff Acceleration (g) Region Clipped by Output LPFRolloff ion Reg cell y gb d pe Clip Determined by g-cell roll-off and ADC clipping to d ue ion nearity t r o ist Li p al D NonClip Sign y and i on f g o e R etr ion Reg Asymm gg-cell_Clip yA ed b gADC_Clip DC Determined by g-cell roll-off and full scale range gRange_Norm Region of Interest fLPF Region of No Signal Distortion Beyond Specification fg-Cell 5kHz 10kHz Frequency (kHz) Figure 32. Output Clipping Vs. Frequency 3.11.2 Sigma Delta Over Range Response Over range conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits of the DSP. The ΣΔ converter can saturate at levels above those specified in Section 2.1 (GADC_CLIP). The DSP operates predictably under all cases of over range, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. MMA68xx Sensors Freescale Semiconductor, Inc. 43 4 SPI Communications Communication with MMA68xx is completed through synchronous serial transfers via SPI. MMA68xx is a slave device configured for CPOL = 0, CPHA = 0, MSB first. SPI transfers are completed through a sequence of two phases. During the first phase, the type of transfer and associated control information is transmitted from the SPI master to MMA68xx. Data from MMA68xx is transmitted during the second phase. Any activity on MOSI or SCLK is ignored when CS is negated. Consequently, intermediate transfers involving other SPI devices may occur between phase one and phase two. Reference Figure 33. SCLK CS MOSI Phase One: Command Phase Two: Response Phase One: Response -Previous Command MISO SCLK CS MOSI T1P1 T2P1 T3P1 T1P2 T2P2 T3P2 MISO Figure 33. SPI Transfer Detail MMA68xx 44 Sensors Freescale Semiconductor, Inc. 4.1 SPI Command Format Commands are transferred from the SPI master to MMA68xx. Valid commands fall into two categories: register operations, and acceleration data requests. Table 29. SPI Command Message Summary MSB 15 0 LSB 14 AX 13 A 12 11 OC 0 10 9 0 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 0 SD AR M P Command Type Reference AX= Axis Selection 0 X-Axis Acceleration Data 1 Y-Axis Acceleration Data A = Acceleration Data Request 0 Register Operation 1 Acceleration Data Request OC = Offset Cancelled Data Request 0 Offset Cancelled Data Request 1 Raw Acceleration Data Request SD = Signed Data Confirmation Signed Data Enabled 0 Unsigned Data Enabled 1 ARM = ARM Function Status Confirmation Disabled / PCM Output Enabled 0 Arming Function Enabled 1 P = Odd Parity 0 AX A OC 0 0 0 0 0 0 0 0 0 SD AR M P Accel Data 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 X-Axis OC, Signed Data, Disabled/PCM 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 X-Axis OC, Signed Data, ARM Enabled 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 X-Axis OC, Unsigned Data, Disabled/PCM 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 X-Axis OC, Unsigned Data, ARM Enabled 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 X-Axis Raw, Signed Data, Disabled/PCM 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 X-Axis Raw, Signed Data, ARM Enabled 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 X-Axis Raw, Unsigned Data, Disabled/ PCM 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 X-Axis Raw, Unsigned Data, ARM Enabled 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 Y-Axis OC, Signed Data, Disabled/PCM 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 Y-Axis OC, Signed Data, ARM Enabled 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 Y-Axis OC, Unsigned Data, Disabled/PCM 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 Y-Axis OC, Unsigned Data, ARM Enabled 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Y-Axis Raw, Signed Data, Disabled/PCM 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 Y-Axis Raw, Signed Data, ARM Enabled 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 Y-Axis Raw, Unsigned Data, Disabled/ PCM 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 Y-Axis Raw, Unsigned Data, ARM Enabled P AX A D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Command Type Reference A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 Register Read Section 4.4 D7 D6 D5 D4 D3 D2 D1 D0 Register Write Section 4.4 P 0 0 Register Address A4 P 1 A3 A2 A1 A0 0 Register Address Data to be Written to Register P = Odd Parity MMA68xx Sensors Freescale Semiconductor, Inc. 45 4.2 SPI Response Format Table 30. SPI Response Message Summary MSB 15 CMD A AX LSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D4 D3 D2 D1 D0 D3 D2 D1 D0 Response to Valid Acceleration Request OC 0 AX P S1 S0 D9 D8 D7 D6 D5 Data Type Reference Data Type Reference OC = Offset Cancelled Data Requested 0 Transferred Accel Data is Offset Cancelled Data 1 Transferred Accel Data is Raw Data AX = Axis Requested 0 X-Axis Acceleration Data Response 1 Y-Axis Acceleration Data Response P = Odd Parity S[1:0] = Device Status CMD Valid Accel Data Request 0 0 0 1 Normal Data Request 1 0 ST Active, ΣΔ/Offset Over range Present 1 1 A AX OC 0 AX P S1 S0 1 OC 0 0 P 0 1 0 In Initialization (ENDINIT = ’0’) Internal Error Present / SPI Error D9 D8 D7 D6 D5 D4 X- Axis Acceleration Data Accel 1 0 OC 0 0 P 1 0 X- Axis Self-Test Active Acceleration Data Accel 1 0 OC 0 0 P 0 0 X- Axis Acceleration Data, Initialization in Process (ENDINIT=’0’) Accel 1 1 OC 0 1 P 0 1 Y-Axis Acceleration Data Accel 1 1 OC 0 1 P 1 0 Y-Axis Self-Test Active Acceleration Data Accel 1 1 OC 0 1 P 0 0 Y- Axis Acceleration Data, Initialization in Process (ENDINIT=’0’) Accel 14 13 12 11 10 MSB 15 CMD A AX LSB 9 8 7 6 5 4 3 2 1 0 D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0 D1 D0 Response to Valid Register Access D15 D14 AX P D11 D10 D9 D8 Register Write 0 1 0 0 1 P 1 1 1 0 Register Read 0 0 0 1 0 P 1 1 1 0 14 13 12 11 10 9 8 D7 D6 D7 D6 New Contents of Register D7 D6 D5 D4 D3 D2 Reference x Register Setting Mismatch Section 4.3 IDE Bit Set (Excl. Self-Test), Section 4.5.5 DEVINIT Bit Set DEVRES Bit Set x x MISO Error x x x Register Write Section 4.4.1 Data Type A AX Internal Error Present SPI Error Reference Section 4.4.2 Contents of Register MSB Invalid Accel x Request Data Type Register Read 15 CMD Section 4.3 LSB 7 6 5 4 3 2 1 0 D6 D5 D4 D3 D2 D1 D0 Error Responses D15 0 D14 0 AX 0 P P D11 1 D10 D9 D8 D7 SD = 1: 00 0000 0000 SD = 0: 10 0000 0000 1 MISO Error on Previous Msg Section 4.5.2 x MOSI Parity CMD Bit 15 = 1 SPI Timing Err Section 4.5.1 SPI Mismatch Err SPI Protocol Errs Invalid Reg Addr, Write while ENDINIT set, Write to R/O Reg Section 4.4 IDE Bit set due to SelfTest Error Section 4.5.5 Invalid Register Request 0 x 0 0 0 0 1 1 Self-Test Error 0 x 0 0 1 P 1 1 1 0 0 0 0 0 0 SD = 1: 00 0000 0000 SD = 0: 10 0000 0000 0 0 0 MMA68xx 46 Sensors Freescale Semiconductor, Inc. 4.3 Acceleration Data Transfers Acceleration data requests are initiated when the Acceleration bit of the SPI command message (A) is set to a logic ’1’. The Axis Selection bit (AX) and the Offset Cancellation Selection bit (OC) of the command message select the type of acceleration data requested, as shown in Table 31. Table 31. Acceleration Data Request Acceleration Data Request Command Information Data Type Axis Selection Bit (AX) Offset Cancellation Select (OC) 0 0 X-Axis Offset Cancelled Data 0 1 X-Axis Raw Data 1 0 Y-Axis Offset Cancelled Data 1 1 Y-Axis Raw Data To verify that MMA68xx is configured as expected, each acceleration data request includes the configuration information that impacts the output data. The requested configuration is compared against the data programmed in the writable register array. Details are shown in Table 32. Table 32. Acceleration Data Request Configuration Information Programmable Option Command Message Bit Writable Register Information Signed or Unsigned Data SD DEVCFG[4] (SD) Arming Function or PCM Output ARM DEVCFG[2] || DEVCFG[1] (A_CFG[2] || A_CFG[1]) If the data listed in Table 32 does not does not match, an Acceleration Data Request Mismatch failure is detected and no acceleration data is transmitted. Reference Section 4.5.3.1. Acceleration data request commands include a parity bit (P). Odd parity is employed. The number of logic ’1’ bits in the acceleration data request command must be an odd number. Acceleration data is transmitted on the next SPI message if and only if all of the following conditions are met: • The DEVINIT bit in the DEVSTAT register is not set • The DEVRES bit in the DEVSTAT register is not set • The IDE bit in the DEVSTAT register is not set (Reference Section 4.5.5) • No SPI Error is detected (Reference Section 4.5.1) • No MISO Error is detected (Reference Section 4.5.2) • No Acceleration Data Request Mismatch failure is detected (Reference Section 4.5.3.1) • No Self-Test Error is present (reference Section 4.5.5.2) If the above conditions are met, MMA68xx responds with a “valid acceleration data request” response as shown in Table 30. Otherwise, MMA68xx responds as specified in Section 4.5. 4.4 Register Access Operations Two types of register access operations are supported; register write, and register read. Register access operations are initiated when the acceleration bit (A) of the command message is set to a logic ’0’. The operation to be performed is indicated by the Access Selection bit (AX) of the command message. Access Selection Bit (AX) Operation 0 Register Read 1 Register Write Register Access operations include a parity bit (P). Odd parity is employed. The number of logic ’1’ bits in the Register Access operation must be an odd number. MMA68xx Sensors Freescale Semiconductor, Inc. 47 4.4.1 Register Write Request During a register write request, bits 12 through 8 contain a five-bit address, and bits 7 through 0 contain the data value to be written. Writable registers are defined in Table 3. The response to a register write operation is shown in Table 30. The response is transmitted on the next SPI message if and only if all of the following conditions are met: • No SPI Error is detected (Reference Section 4.5.1) • No MISO Error is detected (Reference Section 4.5.2) • The ENDINIT bit is cleared (Reference Section 3.1.6.2) – This applies to all registers with the exception of the DEVCTL register • No Invalid Register Request is detected (Reference Section 4.5.3.2) If the above conditions are met, MMA68xx responds to the register write request as shown in Table 30. Otherwise, MMA68xx Responds as specified in Section 4.5. Register write operations do not occur internally until the transfer during which they are requested has been completed. In the event that a SPI Error is detected during a register write transfer, the write operation is not completed. 4.4.2 Register Read Request During a register read request, bits 12 through 8 contain the five-bit address for the register to be read. Bits 7 through 0 must be logic ’0’. Readable registers are defined in Table 3. The response to a register read operation is shown in Table 30. The response is transmitted on the next SPI message if and only if all of the following conditions are met: • No SPI Error is detected (Reference Section 4.5.1) • No MISO Error is detected (Reference Section 4.5.2) • No Invalid Register Request is detected (Reference Section 4.5.3.2) If the above conditions are met, MMA68xx responds to the register read request as shown in Table 30. Otherwise, MMA68xx responds as specified in Section 4.5. 4.5 Exception Handling The following sections describe the conditions for each detectable exception, and the MMA68xx response for each exception. In the event that multiple exceptions exist, the exception response is determined by the priority listed in Table 33. Table 33. SPI Error Response Priority Error Priority Exception 1 SPI Error Effect on Data SPI Data Arming Output PCM Output Error Response No Update No Effect 2 SPI MISO Error Error Response No Update No Effect 3 Invalid Request Error Response No Update No Effect 4 DEVINIT Bit Set Error Response No Update Disabled 5 DEVRES Error Error Response No Update Disabled 6 CRC Error Error Response No Update No Effect 7 Self-Test Error Error Response No Update No Effect 8 Offset Monitor Over Range No Effect No Effect No Effect 9 ΣΔ Over Range No Effect No Effect No Effect MMA68xx 48 Sensors Freescale Semiconductor, Inc. 4.5.1 SPI Error The following SPI conditions result in a SPI error: • SCLK is high when CS is asserted the number of SCLK rising edges detected while CS is asserted is not equal to 16 • SCLK is high when CS is negated • Command message parity error (MOSI) • Bit 15 of Acceleration Data Request is not equal to ‘0’ • Bits 3 through 11 of an Acceleration Request are not equal to ‘0’ • Bits 0 through 7 of a Register Read Request are not equal to ‘0’ MMA68xx responds to a SPI error with a “SPI Error” response as shown in Table 30. This applies to both acceleration data request SPI errors, and Register Access SPI errors. The arming function will not be updated if a SPI Error is detected. The PCM output is not affected by a SPI Error. 4.5.2 SPI Data Output Verification Error MMA68xx includes a function to verify the integrity of the data output to the MISO pin. The function reads the data transmitted on the MISO pin and compares it against the data intended to be transmitted. If any one bit doesn’t match, a SPI MISO Mismatch Fault is detected and the MISOERR flag in the DEVSTAT register is set. If a valid SPI acceleration request message is received during the SPI transfer with the MISO mismatch failure, the SPI acceleration request message is ignored and MMA68xx responds with a “MISO Error” response during the subsequent SPI message (reference Table 30). The Arming function is not updated if a MISO mismatch failure occurs. The PCM function is not affected by the MISO mismatch failure. If a valid SPI register write request message is received during the SPI transfer with the MISO mismatch failure, the register write is completed as requested, but MMA68xx responds with a “MISO Error” response as shown in Table 30, during the subsequent SPI message. If a valid SPI register read request message is received during the SPI transfer with the MISO mismatch failure, the register read is ignored and MMA68xx responds with a “MISO Error” response as shown in Table 30, during the subsequent SPI message. If the register read request is for the DEVSTAT register, the DEVSTAT register will not be cleared. In all cases, the MISOERR flag in the DEVSTAT register will remain set until a successful SPI Register Read Request of the DEVSTAT register is completed. SPI DATA OUT SHIFT REGISTER D DATA OUT BUFFER Q D Q MISO R D Q MISO ERR SCLK R Figure 34. SPI Data Output Verification 4.5.3 4.5.3.1 Invalid Requests Acceleration Data Request Mismatch Failure MMA68xx detects an “Acceleration Data Request Mismatch” error if the SPI “Acceleration Data Request” Command data listed in Table 32 does not match the internal register settings. MMA68xx responds to an “Acceleration Data Request Mismatch” error with an “Invalid Accel Request” response as specified in Table 30 on the subsequent SPI message only. No internal fault is recorded. The arming function will not be updated if an “Acceleration Data Request Mismatch” Error is detected. The PCM output is not affected by the “Acceleration Data Request Mismatch” error. Register operations will be executed as specified in Section 4.4. MMA68xx Sensors Freescale Semiconductor, Inc. 49 4.5.3.2 Invalid Register Request The following conditions result in an “Invalid Register Request” error: • An attempt is made to write to an un-writable register (Writable registers are defined in Section 3.1, Table 3). • An attempt is made to write to a register while the ENDINIT bit in the DEVCFG register is set – This applies to all registers with the exception of the DEVCTL register • An attempt is made to read an un-readable register (Readable registers are defined in Section 3.1, Table 3). MMA68xx responds to an “Invalid Register Request” error with an “Invalid Register Request” response as shown in Table 30. 4.5.4 Device Reset Indications If the DEVINIT, or DEVRES bit is set in the DEVSTAT register as described in Section 3.1.10, MMA68xx will respond to acceleration data requests with an “Internal Error Present” response until the bits are cleared in the DEVSTAT register. The DEVINIT bit is cleared automatically when device initialization is complete (Reference tOP in Section 2.6). The DEVRES bit is cleared on a read of the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if the DEVINIT or DEVRES bit is set in the DEVSTAT register. The PCM output is disabled if the DEVINIT or DEVRES bit is set. 4.5.5 Internal Error The following errors will result in an internal error, and set the IDE bit in the DEVSTAT register: • OTP CRC Failure • Writable Register CRC Failure • Self-Test Error • Invalid internal logic states 4.5.5.1 CRC Error If the IDE bit is set in the DEVSTAT register due to an OTP Shadow Register or Writable Register CRC failure as described in Section 3.2, MMA68xx will respond to acceleration data requests with an “Internal Error Present” response until the IDE bit is cleared in the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if a CRC Error is detected. The PCM output is not affected by the CRC error. If the CRC error is in the writable register array, and the ENDINIT bit in the DEVCFG register has been set, the error can only be cleared by a device reset. The IDE bit will not be cleared on a read of the DEVSTAT register. If the CRC error is in the OTP shadow register array, the error cannot be cleared. Register operations will be executed as specified in Section 4.4. 4.5.5.2 Self-Test Error If the IDE bit is set in the DEVSTAT register due to a Self-Test activation failure, MMA68xx will respond to acceleration data requests with a “Self-Test Error” response until the IDE bit is cleared in the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if a Self-Test Error is detected. The PCM output is not affected by the Self Test Error. The IDE bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs, even if the internal failure is removed. If the internal error is still present when the DEVSTAT register is read, the IDE bit will remain set. Register operations will be executed as specified in Section 4.4. 4.5.6 Offset Monitor Over Range If an offset monitor over range is present as described in Section 3.8.5, MMA68xx will respond to an acceleration request for the corresponding axis with a “Valid Acceleration Data Request” response, but the Status bits (S[1:0]) will be set to ‘10’. The arming function will be updated on Acceleration Data Request commands even if an Offset Monitor Over Range is detected. Once the over range condition is removed, MMA68xx will respond to acceleration requests with a “Valid Acceleration Data Request” response with the Status bits (S[1:0]) set to ’10’ on the next SPI transfer, and a “Valid Acceleration Data Request” response with normal status on subsequent SPI transfers. The OFFSET_X or OFFSET_Y bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs. The PCM output is not affected by the offset monitor over range condition. Register operations will be executed as specified in Section 4.4. MMA68xx 50 Sensors Freescale Semiconductor, Inc. 4.5.7 ΣΔ Over Range If a ΣΔ Over Range failure is present as described in Section 3.11.2, MMA68xx will respond to acceleration data requests with a "Valid Acceleration Data Request" response, but the Status bits (S[1:0]) will be set to ’10’. The arming function will be updated on Acceleration Data Request commands even if a ΣΔ Over Range is detected. Once the over range condition is removed, MMA68xx will respond to acceleration requests with a "Valid Acceleration Data Request" response with the Status bits (S[1:0]) set to ’10’ on the next SPI transfer, and a "Valid Acceleration Data Request" response with normal status on subsequent SPI transfers. The SDOV bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs. The PCM output is not affected by the ΣΔ over range condition. Register operations will be executed as specified in Section 4.4. 4.6 Initialization SPI Response The first data transmitted by MMA68xx following reset is the SPI Error response shown in Table 30. This ensures that an unexpected reset will always be detectable. MMA68xx will respond to all acceleration data requests with the "Invalid Acceleration Data Request" response until the DEVRES bit in the DEVSTAT register is cleared via a read of the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands until the DEVRES bit in the DEVSTAT register is cleared. 4.7 Acceleration Data Representation Acceleration values are determined from the 10-bit digital output (DV) using the following equations: Acceleration = Sensitivity LSB × DV For Signed Data Acceleration = Sensitivity LSB × ( DV – 512 ) For Unsigned Data The linear range of digital values for signed data is -480 to +480, and for unsigned data is 32 to 992. Resulting ranges and some nominal acceleration values are shown in the following table. Table 34. Nominal Acceleration Data Values Nominal Acceleration Unsigned Digital Value Signed Digital Value 993 - 1023 481 - 511 992 480 19.666 117.19 991 479 19.625 116.94 • • • • • • • • • • • • 514 2 +0.082 +0.488 513 1 +0.041 +0.244 512 0 0 0 511 -1 -0.041 -0.244 510 -2 -0.082 -0.488 • • • • • • • • • • • • 33 -479 -19.625 -116.94 32 -480 -19.666 -117.19 1 - 31 -481 to -511 Unused 0 -512 Fault Trimmed for Maximum Sensitivity (g) Trimmed for Maximum Range (g) Unused MMA68xx Sensors Freescale Semiconductor, Inc. 51 Figure 35 shows the how the possible output data codes are determined from the input data and the error sources. The relevant parameters are specified in Section 2.4. Figure 35. Acceleration Data Output Vs. Acceleration Input MMA68xx 52 Sensors Freescale Semiconductor, Inc. 5 Package 5.1 Case Outline Drawing Reference Freescale Case Outline Drawing # 98ASA00090D http://www.freescale.com/files/shared/doc/package_info/98ASA00090D.pdf 5.2 Recommended Footprint Reference Freescale Application Note AN3111, latest revision: http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf Table 35. Revision History Revision number Revision date 4 12/2011 • Updated ordering table to include MMA6825BKW device options. • Removed “For user register...” comment on page 1 under ordering table. • Electrical Characteristics: Removed “QR2” suffix from device numbers lines 56 through 61. Added 100g (MMA6825) option. • PN Register Value table on pg. 13: Updated values for X and Y axes for Decimal 5, added Decimal 27 and 28. • Updated equation in section 3.6, Self-Test Interface. 5 03/2012 • Added SafeAssure logo, changed first paragraph and disclaimer to include trademark information. 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