TI LMC555CM Lmc555 cmos timer Datasheet

LMC555
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SNAS558J – FEBRUARY 2000 – REVISED MARCH 2013
LMC555 CMOS Timer
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FEATURES
1
•
2
•
•
•
•
•
•
•
•
•
Less than 1 mW Typical Power Dissipation at
5V Supply
3 MHz Astable Frequency Capability
1.5V Supply Operating Voltage Ensured
Output Fully Compatible with TTL and CMOS
Logic at 5V Supply
Tested to −10 mA, +50 mA Output Current
Levels
Reduced Supply Current Spikes During Output
Transitions
Extremely Low Reset, Trigger, and Threshold
Currents
Excellent Temperature Stability
Pin-for-Pin Compatible with 555 Series of
Timers
Available in 8-pin VSSOP Package and 8-Bump
DSBGA package
DESCRIPTION
The LMC555 is a CMOS version of the industry
standard 555 series general purpose timers. In
addition to the standard package (SOIC, VSSSOP,
and PDIP) the LMC555 is also available in a chip
sized package (8 Bump DSBGA) using TI's DSBGA
package technology. The LMC555 offers the same
capability of generating accurate time delays and
frequencies as the LM555 but with much lower power
dissipation and supply current spikes. When operated
as a one-shot, the time delay is precisely controlled
by a single external resistor and capacitor. In the
stable mode the oscillation frequency and duty cycle
are accurately set by two external resistors and one
capacitor. The use of Texas Instruments' LMCMOS
process extends both the frequency range and low
supply capability.
Pulse Width Modulator
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
LMC555
SNAS558J – FEBRUARY 2000 – REVISED MARCH 2013
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Connection Diagram
Figure 1. 8-Pin SOIC, VSSOP, PDIP
Top View
Figure 2. 8-Bump DSBGA
Top View (Bump Side Down)
2
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Table 1. Pin Descriptions
Pin Name
Package Pin Numbers
8-Pin SOIC, VSSOP, and PDIP
8-Bump DSBGA
GND
1
A3
Trigger
2
B3
Output
3
C3
Reset
4
C2
Control Voltage
5
C1
Threshold
6
B1
Discharge
7
A1
8
A2
+
V
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
Supply Voltage, V+
15V
−0.3V to VS + 0.3V
Input Voltages, VTRIG, VRES, VCTRL, VTHRESH
Output Voltages, VO, VDIS
15V
Output Current IO, IDIS
100 mA
−65°C to +150°C
Storage Temperature Range
Soldering specification for PDIP package:
Soldering (10 seconds)
260°C
Soldering specification for all other packages:
see product folder at www.ti.com and http://www.ti.com/lit/SNOA549
(1)
(2)
(3)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
See AN-1112 (SNVA009) for DSBGA considerations.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Operating Ratings (1) (2)
Temperature Range
−40°C to +125°C
LMC555IM
−40°C to +85°C
LMC555CM/MM/N/TP
Thermal Resistance (θJA)
(1)
SOIC, 8-Pin
169°C/W
VSSOP, 8-Pin
225°C/W
PDIP, 8-Pin
111°C/W
8-Bump DSBGA
220°C/W
Maximum Allowable Power Dissipation @25°C
(1)
(2)
PDIP-8
1126 mW
SOIC-8
740 mW
VSSOP-8
555 mW
8-Bump DSBGA
568 mW
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
See AN-1112 (SNVA009) for DSBGA considerations.
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LMC555
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Electrical Characteristics (1)
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(2)
Test Circuit, T = 25°C, all switches open, RESET to VS unless otherwise noted
Parameter
IS
Supply Current
VCTRL
Control Voltage
Test Conditions
Min
VS = 1.5V
VS = 5V
VS = 12V
VS = 1.5V
VS = 5V
VS = 12V
0.8
2.9
7.4
Typ
Max
Units
(Limits)
50
100
150
150
250
400
µA
1.0
3.3
8.0
1.2
3.8
8.6
V
VDIS
Discharge Saturation Voltage
VS = 1.5V, IDIS = 1 mA
VS = 5V, IDIS = 10 mA
75
150
150
300
mV
VOL
Output Voltage (Low)
VS = 1.5V, IO = 1 mA
VS = 5V, IO = 8 mA
VS = 12V, IO = 50 mA
0.2
0.3
1.0
0.4
0.6
2.0
V
Output Voltage
(High)
VS = 1.5V, IO = −0.25 mA
VS = 5V, IO = −2 mA
VS = 12V, IO = −10 mA
1.0
4.4
10.5
1.25
4.7
11.3
VTRIG
Trigger Voltage
VS = 1.5V
VS = 12V
0.4
3.7
0.5
4.0
ITRIG
Trigger Current
VS = 5V
VRES
Reset Voltage
VS = 1.5V
VS = 12V
0.4
0.4
0.7
0.75
IRES
Reset Current
VS = 5V
10
pA
ITHRESH
Threshold Current
VS = 5V
10
pA
IDIS
Discharge Leakage
VS = 12V
1.0
100
t
Timing Accuracy
SW 2, 4 Closed
VS = 1.5V
VS = 5V
VS = 12V
1.1
1.1
1.1
1.25
1.20
1.25
VOH
V
0.6
4.3
10
(3)
0.9
1.0
1.0
V
pA
1.0
1.1
V
nA
ms
Δt/ΔVS
Timing Shift with Supply
VS = 5V ± 1V
0.3
%/V
Δt/ΔT
Timing Shift with Temperature
VS = 5V
75
ppm/°C
fA
Astable Frequency
SW 1, 3 Closed, VS = 12V
fMAX
Maximum Frequency
Max. Freq. Test Circuit, VS = 5V
3.0
MHz
tR, tF
Output Rise and
Fall Times
Max. Freq. Test Circuit
VS = 5V, CL = 10 pF
15
ns
tPD
Trigger Propagation Delay
VS = 5V, Measure Delay
from Trigger to Output
100
ns
(1)
(2)
(3)
4
4.0
4.8
5.6
kHz
All voltages are measured with respect to the ground pin, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
If the RESET pin is to be used at temperatures of −20°C and below VS is required to be 2.0V or greater.
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For device pinout, please see Table 1.
Figure 3. Test Circuit
For device pinout, please see Table 1.
Figure 4. Maximum Frequency Test Circuit
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APPLICATION INFORMATION
MONOSTABLE OPERATION
In this mode of operation, the timer functions as a one-shot (Figure 5). The external capacitor is initially held
discharged by internal circuitry. Upon application of a negative trigger pulse of less than 1/3 VS to the Trigger
terminal, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high.
Figure 5. Monostable (One-Shot)
The voltage across the capacitor then increases exponentially for a period of tH = 1.1 RAC, which is also the time
that the output stays high, at the end of which time the voltage equals 2/3 VS. The comparator then resets the
flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 6 shows the
waveforms generated in this mode of operation. Since the charge and the threshold level of the comparator are
both directly proportional to supply voltage, the timing internal is independent of supply.
VCC = 5V
TIME = 0.1 ms/Div.
RA = 9.1 kΩ
C = 0.01 µF
Top Trace: Input 5 V/Div.
Middle Trace: Output 5 V/Div.
Bottom Trace: Capacitor Voltage 2 V/Div.
Figure 6. Monostable Waveforms
Reset overrides Trigger, which can override threshold. Therefore the trigger pulse must be shorter than the
desired tH. The minimum pulse width for the Trigger is 20ns, and it is 400ns for the Reset. During the timing cycle
when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger
input is returned high at least 10µs before the end of the timing interval. However the circuit can be reset during
this time by the application of a negative pulse to the reset terminal. The output will then remain in the low state
until a trigger pulse is again applied.
When the reset function is not use, it is recommended that it be connected to V+ to avoid any possibility of false
triggering. Figure 7 is a nomograph for easy determination of RC values for various time delays.
NOTE
In monstable operation, the trigger should be driven high before the end of timing cycle.
6
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Figure 7. Time Delay
ASTABLE OPERATION
If the circuit is connected as shown in Figure 8 (Trigger and Threshold terminals connected together) it will
trigger itself and free run as a multivibrator. The external capacitor charges through RA + RB and discharges
through RB. Thus the duty cycle may be precisely set by the ratio of these two resistors.
Figure 8. Astable (Variable Duty Cycle Oscillator)
In this mode of operation, the capacitor charges and discharges between 1/3 VS and 2/3 VS. As in the triggered
mode, the charge and discharge times, and therefore the frequency are independent of the supply voltage.
Figure 9 shows the waveform generated in this mode of operation.
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VCC = 5V
TIME = 20 µs/Div.
RA = 3.9 kΩ
RB = 9 kΩ
C = 0.01 µF
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Top Trace: Output 5 V/Div.
Bottom Trace: Capacitor Voltage 1 V/Div.
Figure 9. Astable Waveforms
The charge time (output high) is given by
t1 = 0.693 (RA + RB)C
(1)
And the discharge time (output low) by:
t2 = 0.693 (RB)C
(2)
Thus the total period is:
T = t1 + t2 = 0.693 (RA + 2RB)C
(3)
The frequency of oscillation is:
(4)
Figure 10 may be used for quick determination of these RC Values. The duty cycle, as a fraction of total period
that the output is low, is:
(5)
Figure 10. Free Running Frequency
8
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FREQUENCY DIVIDER
The monostable circuit of Figure 5 can be used as a frequency divider by adjusting the length of the timing cycle.
Figure 11 shows the waveforms generated in a divide by three circuit.
VCC = 5V
TIME = 20 µs/Div.
RA = 9.1 kΩ
C = 0.01 µF
Top Trace: Input 4 V/Div.
Middle Trace: Output 2 V/Div.
Bottom Trace: Capacitor 2 V/Div.
Figure 11. Frequency Divider Waveforms
PULSE WIDTH MODULATOR
When the timer is connected in the monostable mode and triggered with a continuous pulse train, the output
pulse width can be modulated by a signal applied to the Control Voltage Terminal. Figure 12 shows the circuit,
and in Figure 13 are some waveform examples.
Figure 12. Pulse Width Modulator
VCC = 5V
Top Trace: Modulation 1 V/Div.
TIME = 0.2 ms/Div. Bottom Trace: Output Voltage 2 V/Div.
RA = 9.1 kΩ
C = 0.01 µF
Figure 13. Pulse Width Modulator Waveforms
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PULSE POSITION MODULATOR
This application uses the timer connected for astable operation, as in Figure 14, with a modulating signal again
applied to the control voltage terminal. The pulse position varies with the modulating signal, since the threshold
voltage and hence the time delay is varied. Figure 15 shows the waveforms generated for a triangle wave
modulation signal.
Figure 14. Pulse Position Modulator
VCC = 5V
TIME = 0.1 ms/Div.
RA = 3.9 kΩ
RB = 3 kΩ
C = 0.01 µF
Top Trace: Modulation Input 1 V/Div.
Bottom Trace: Output Voltage 2 V/Div.
Figure 15. Pulse Position Modulator Waveforms
50% DUTY CYCLE OSCILLATOR
The frequency of oscillation is
f = 1/(1.4 RCC)
Figure 16. 50% Duty Cycle Oscillator
10
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REVISION HISTORY
Changes from Revision I (March 2013) to Revision J
•
12
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
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15-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMC555CM
ACTIVE
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 85
LMC
555CM
LMC555CM/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC
555CM
LMC555CMM
ACTIVE
VSSOP
DGK
8
1000
TBD
Call TI
Call TI
-40 to 85
ZC5
LMC555CMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
ZC5
LMC555CMMX
ACTIVE
VSSOP
DGK
8
3500
TBD
Call TI
Call TI
-40 to 85
ZC5
LMC555CMMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
ZC5
LMC555CMX
ACTIVE
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 85
LMC
555CM
LMC555CMX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC
555CM
LMC555CN
ACTIVE
PDIP
P
8
40
TBD
Call TI
Call TI
-40 to 85
LMC
555CN
LMC555CN/NOPB
ACTIVE
PDIP
P
8
40
Green (RoHS
& no Sb/Br)
Call TI
Level-1-NA-UNLIM
-40 to 85
LMC
555CN
LMC555CTP/NOPB
ACTIVE
DSBGA
YPB
8
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
F
02
LMC555CTPX/NOPB
ACTIVE
DSBGA
YPB
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
F
02
LMC555IM/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMC
555IM
LMC555IMX/NOPB
ACTIVE
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 85
LMC
555IM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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15-May-2013
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMC555CMM
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMC555CMM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMC555CMMX
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMC555CMMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMC555CMX
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMC555CMX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LMC555CTP/NOPB
DSBGA
YPB
8
250
178.0
8.4
1.5
1.5
0.66
4.0
8.0
Q1
LMC555CTPX/NOPB
DSBGA
YPB
8
3000
178.0
8.4
1.5
1.5
0.66
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMC555CMM
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMC555CMM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMC555CMMX
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMC555CMMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMC555CMX
SOIC
D
8
2500
367.0
367.0
35.0
LMC555CMX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMC555CTP/NOPB
DSBGA
YPB
8
250
210.0
185.0
35.0
LMC555CTPX/NOPB
DSBGA
YPB
8
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YPB0008
D
0.5±0.045
E
TPA08XXX (Rev A)
D: Max = 1.464 mm, Min =1.403 mm
E: Max = 1.438 mm, Min =1.377 mm
4215100/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
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12/12
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