Infineon HYS72D64320GBR-7-B 184 - pin registered double data rate sdram module Datasheet

D a t a S h e e t , R e v . 1 . 1 , A p r . 2 00 4
HYS72D32300GBR–[5/ 6/7]–B
HYS72D643[ 00/ 20] GBR–[ 5/6/7] –B
HYS72D128320GBR–[5/6/ 7]–B
184 - Pi n Regist ered Doubl e Data Rat e SDRAM
Modules
Reg DIMM
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2004-04
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a S h e e t , R e v . 1 . 1 , A p r . 2 00 4
HYS72D32300GBR–[5/6/7]–B
HYS72D643[00/20]GBR–[5/6/7]–B
HYS72D128320GBR–[5/6/7]–B
184 - Pi n Regist ered Doubl e Data Rat e SDRAM
Modules
Reg DIMM
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
HYS72D32300GBR–[5/6/7]–B HYS72D643[00/20]GBR–[5/6/7]–B HYS72D128320GBR–[5/6/7]–B
HYS72D643[00/20]GBR–[5/6/7]–B HYS72D128320GBR–[5/6/7]–B
Revision History:
Rev. 1.1
2004-04
Previous Version:
Rev. 1.0
2003-12
Page
Subjects (major changes since last revision)
21,22
Registerd and PLL current added
We Listen to Your Comments
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Template: mp_a4_v2.2_2003-10-07.fm
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6
Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Sheet
5
Rev. 1.1, 2004-04
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Overview
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
184-Pin Registered 8-Byte Dual-In-Line
DDR SDRAM Module for “1U” PC, Workstation and Server main memory applications
One rank 32M × 72, 64M × 72 and two ranks 64M × 72, 128M × 72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V (± 0.2 V) power
supply and a single + 2.6 V (± 0.1 V) power supply for DDR400
Built with 256-Mbit DDR-I SDRAMs in P-TFBGA-60-1 packages
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Re-drive for all input signals using register and PLL devices.
Serial Presence Detect with E2PROM
Low Profile Modules form factor:
128.95 mm × 28.58 mm × 4.00 mm
133.35 mm × 30.48 mm (1.2”) × 4.00 mm (6.80 mm with stacked components)
JEDEC standard reference layout for one rank 256MB and 512MB, two ranks 512MB and 1GByte:
PC2700 Registered DIMM Raw Cards A,B,C,D
Gold plated contacts
Table 1
Performance
Part Number Speed Code
-5
–6
-7
Unit
Speed Grade Component
DDR400B
DDR333B
DDR266A
—
PC3200-3033
PC2700–2533
PC2100-2033
—
200
166
–
MHz
166
166
143
MHz
133
133
133
MHz
Module
max. Clock
Frequency
@CL3
@CL2.5
@CL2
1.2
fCK3
fCK2.5
fCK2
Description
The HYS72D[32/64/128]3[00/20]GBR are low profile versions of the standard Registered DIMM modules with
less/equal 1.2” inch (30.48 mm) height for 1U Server Applications. The Low Profile DIMM versions are available
as 32M × 72 (256MB), 64M × 72 (512MB) and 128M × 72 (1 GB).
The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors
are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using
the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer.
Data Sheet
6
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Overview
Table 2
Ordering Information
Type
Compliance Code
Description
SDRAM Technology
PC3200 (CL = 3, tRP = tRCD = 3 at tCK = 5ns)
HYS72D32300GBR–5–B
PC3200R-30330-A
one rank 256 MB Registered
DIMM
256 Mbit (×8)
HYS72D64300GBR–5–B
PC3200R-30330-C
one rank 512 MB Registered
DIMM
256 Mbit (×4)
HYS72D64320GBR–5–B
PC3200R-30330-B
two ranks 512 MB Registered 256 Mbit (×8)
DIMM
HYS72D128320GBR–5–B PC3200R-30331-D
two ranks 1 GB Registered
DIMM
256 Mbit (×4)
PC2700 (CL = 2.5, tRP = tRCD = 3 at tCK = 6ns)
HYS72D32300GBR–6–B
PC2700R-25330-A
one rank 256 MB Registered
DIMM
256 Mbit (×8)
HYS72D64300GBR–6–B
PC2700R-25330-C
one rank 512 MB Registered
DIMM
256 Mbit (×4)
HYS72D64320GBR–6–B
PC2700R-25330-B
two ranks 512 MB Registered 256 Mbit (×8)
DIMM
HYS72D128320GBR–6–B PC2700R-25330-D
two ranks 1 GB Registered
DIMM
256 Mbit (×4)
PC2100 (CL = 2, tRP = tRCD = 3 at tCK = 7.5ns)
HYS72D32300GBR–7–B
PC2100R-20330-A
one rank 256 MB Registered
DIMM
256 Mbit (×8)
HYS72D64300GBR–7–B
PC2100R-20330-C
one rank 512 MB Registered
DIMM
256 Mbit (×4)
HYS72D64320GBR–7–B
PC2100R-20330-B
two ranks 512 MB Registered 256 Mbit (×8)
DIMM
HYS72D128320GBR–7–B PC2100R-20330-D
two ranks 1 GB Registered
DIMM
256 Mbit (×4)
Note: All “product type” end with a place code designating the silicon-die revision. Reference information available
on request. Example: HYS72D64300GR-5-B, indicating rev. C dies are used for SDRAM components. The
“compliance code” is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD1) latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 3
The pin configuration of the Registered DDR SDRAM
DIMM is listed by function in Table 3 (184 pins). The
abbreviations used in columns Pin and Buffer Type are
explained in Table 4 and Table 5 respectively. The pin
numbering is depicted in Figure 1.
Table 3
Pin# Name
Pin Configuration of RDIMM (cont’d)
Pin
Buffer Function
Type Type
125
A6
I
SSTL
29
A7
I
SSTL
Pin Configuration of RDIMM
122
A8
I
SSTL
Pin
Buffer Function
Type Type
27
A9
I
SSTL
141
A10
I
SSTL
AP
I
SSTL
Pin# Name
Clock Signals
137
CK0
I
SSTL
Clock Signal
118
A11
I
SSTL
138
CK0
I
SSTL
Complement Clock
115
A12
I
SSTL
21
CKE0
I
SSTL
Clock Enable Rank 0
111
CKE1
I
SSTL
Clock Enable Rank 1
NC
SSTL
Note: 1-rank module
Control Signals
157
S0
I
SSTL
Chip Select of Rank 0
158
S1
I
SSTL
Chip Select of Rank 1
167
NC
–
Note: 1-rank module
154
RAS
I
SSTL
Row Address Strobe
65
CAS
I
SSTL
Column Address
Strobe
63
WE
I
SSTL
Write Enable
10
RESET I
NC
NC
–
Note: 128 Mbit based
module
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based
module
Note: 2-ranks module
NC
Address Signal 12
Note: Module based on
256 Mbit or larger
dies
Note: 2-rank module
NC
Address Bus 11:0
NC
NC
–
Note: Module based on
512 Mbit or
smaller dies
LVRegister Reset
CMOS Forces registered
inputs low
Note: For detailed
description of the
Power Up and
Power
Management see
the Application
Note at the end of
data sheet
Address Signals
59
BA0
I
SSTL
52
BA1
I
SSTL
Bank Address Bus
1:0
48
A0
I
SSTL
Address Bus 11:0
43
A1
I
SSTL
41
A2
I
SSTL
130
A3
I
SSTL
37
A4
I
SSTL
32
A5
I
SSTL
Data Sheet
Address Bus 11:0
8
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
Table 3
Table 3
Pin Configuration of RDIMM (cont’d)
Pin# Name
Pin
Buffer Function
Type Type
Data Signals
Pin# Name
Pin
Buffer Function
Type Type
150
DQ38
I/O
SSTL
151
DQ39
I/O
SSTL
Data Bus 63:0
2
DQ0
I/O
SSTL
4
DQ1
I/O
SSTL
61
DQ40
I/O
SSTL
6
DQ2
I/O
SSTL
64
DQ41
I/O
SSTL
8
DQ3
I/O
SSTL
68
DQ42
I/O
SSTL
94
DQ4
I/O
SSTL
69
DQ43
I/O
SSTL
95
DQ5
I/O
SSTL
153
DQ44
I/O
SSTL
98
DQ6
I/O
SSTL
155
DQ45
I/O
SSTL
99
DQ7
I/O
SSTL
161
DQ46
I/O
SSTL
12
DQ8
I/O
SSTL
162
DQ47
I/O
SSTL
13
DQ9
I/O
SSTL
72
DQ48
I/O
SSTL
19
DQ10
I/O
SSTL
73
DQ49
I/O
SSTL
20
DQ11
I/O
SSTL
79
DQ50
I/O
SSTL
105
DQ12
I/O
SSTL
80
DQ51
I/O
SSTL
106
DQ13
I/O
SSTL
165
DQ52
I/O
SSTL
109
DQ14
I/O
SSTL
166
DQ53
I/O
SSTL
110
DQ15
I/O
SSTL
170
DQ54
I/O
SSTL
23
DQ16
I/O
SSTL
171
DQ55
I/O
SSTL
24
DQ17
I/O
SSTL
83
DQ56
I/O
SSTL
28
DQ18
I/O
SSTL
84
DQ57
I/O
SSTL
31
DQ19
I/O
SSTL
87
DQ58
I/O
SSTL
114
DQ20
I/O
SSTL
88
DQ59
I/O
SSTL
117
DQ21
I/O
SSTL
174
DQ60
I/O
SSTL
121
DQ22
I/O
SSTL
175
DQ61
I/O
SSTL
123
DQ23
I/O
SSTL
178
DQ62
I/O
SSTL
33
DQ24
I/O
SSTL
179
DQ63
I/O
SSTL
35
DQ25
I/O
SSTL
44
CB0
I/O
SSTL
39
DQ26
I/O
SSTL
45
CB1
I/O
SSTL
40
DQ27
I/O
SSTL
49
CB2
I/O
SSTL
126
DQ28
I/O
SSTL
51
CB3
I/O
SSTL
127
DQ29
I/O
SSTL
134
CB4
I/O
SSTL
131
DQ30
I/O
SSTL
135
CB5
I/O
SSTL
133
DQ31
I/O
SSTL
142
CB6
I/O
SSTL
53
DQ32
I/O
SSTL
144
CB7
I/O
SSTL
55
DQ33
I/O
SSTL
5
DQS0
I/O
SSTL
Data Strobes 8:0
57
DQ34
I/O
SSTL
14
DQS1
I/O
SSTL
60
DQ35
I/O
SSTL
25
DQS2
I/O
SSTL
146
DQ36
I/O
SSTL
36
DQS3
I/O
SSTL
Note: See block
diagram for
corresponding
DQ signals
147
DQ37
I/O
SSTL
56
DQS4
I/O
SSTL
67
DQS5
I/O
SSTL
Data Sheet
Data Bus 63:0
Pin Configuration of RDIMM (cont’d)
9
Check Bits 7:0
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
Table 3
Pin Configuration of RDIMM (cont’d)
Table 3
Pin Configuration of RDIMM (cont’d)
Pin# Name
Pin
Buffer Function
Type Type
Pin# Name
78
DQS6
I/O
SSTL
EEPROM
86
DQS7
I/O
SSTL
92
SCL
I
CMOS Serial Bus Clock
47
DQS8
I/O
SSTL
91
SDA
I/O
OD
97
DM0
I
SSTL
Data Mask 0
181
SA0
I
Note: ×8 based module
182
SA1
I
CMOS Slave Address Select
CMOS Bus 2:0
Data Strobe 9
183
SA2
I
CMOS
Note: ×4 based module
Power Supplies
Data Mask 1
1
Note: ×8 based module
184
DQS9
107
DM1
I/O
I
DQS10 I/O
SSTL
SSTL
SSTL
Data Strobes 8:0
DM2
I
SSTL
Data Mask 2
Note: ×8 based module
DQS11 I/O
SSTL
Data Strobe 11
DM3
SSTL
Data Mask 3
Note: ×4 based module
129
I
Note: ×8 based module
DQS12 I/O
SSTL
Data Strobe 12
Note: ×4 based module
149
DM4
I
SSTL
Data Mask 4
Note: ×8 based module
DQS13 I/O
SSTL
Data Strobe 13
Note: ×4 based module
159
DM5
I
SSTL
Data Mask 5
Note: ×8 based module
DQS14 I/O
SSTL
Data Strobe 14
Note: ×4 based module
169
DM6
I
SSTL
Data Mask 6
Note: ×8 based module
DQS15 I/O
SSTL
VREF
AI
–
VDDSPD PWR –
Data Strobe 10
Note: ×4 based module
119
Pin
Buffer Function
Type Type
Data Strobe 15
Serial Bus Data
I/O Reference Voltage
EEPROM Power
Supply
15, VDDQ
22,
30,
54,
62,
77,
96,
104,
112,
128,
136,
143,
156,
164,
172,
180
PWR –
I/O Driver Power
Supply
7,
VDD
38,
46,
70,
85,
108,
120,
148,
168
PWR –
Power Supply
Note: ×4 based module
177
DM7
I
SSTL
Data Mask 7
Note: ×8 based module
DQS16 I/O
SSTL
Data Strobe 16
Note: ×4 based module
140
DM8
I
SSTL
Data Mask 8
Note: ×8 based module
DQS17 I/O
SSTL
Data Strobe 17
Note: ×4 based module
Data Sheet
10
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
Table 3
Pin Configuration of RDIMM (cont’d)
Pin# Name
Pin
Buffer Function
Type Type
VSS
3,
11,
18,
26,
34,
42,
50,
58,
66,
74,
81,
89,
93,
100,
116,
124,
132,
139,
145,
152,
160,
176
GND
–
Table 4
Abbreviations for Pin Type
Abbreviation Description
Ground Plane
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NU
Not Usable (JEDEC Standard)
NC
Not Connected (JEDEC Standard)
Table 5
Abbreviations for Buffer Type
Abbreviation Description
SSTL
Serial Stub Terminalted Logic (SSTL2)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
Other Pins
82
VDDID
O
OD
VDD Identification
Note: Pin in tristate,
indicating VDD
and VDDQ nets
connected on
PCB
NC
9,
16,
17,
71,
75,
76,
90,
101,
102,
103,
113,
163,
173
Data Sheet
NC
–
Not connected
Pins not connected on
Infineon RDIMM’s
11
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
Front View
Standard Height
PIN 1
PIN 52
PIN 53
PIN 92
Back View
PIN 93
Front View
PIN 144
PIN 145
PIN 184
1U Height
PIN 1
PIN 52
PIN 53
PIN 92
Back View
PIN 93
Figure 1
Data Sheet
PIN 144
PIN 145
PIN 184
PCB with Pin Connector
12
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
Table 6
Address Format
Organization
Memory
Ranks
SDRAMs
# of
SDRAMs
# of
row/bank/
columns
bits
Refresh Period Interval
256 MB
32M x 72
1
32M ×8
9
13 / 2 / 10
8K
64 ms
7.8 µs
512 MB
64M × 72
1
64M ×4
18
13 / 2 / 11
8K
64 ms
7.8 µs
512 MB
64M × 72
2
32M ×8
18
13 / 2 / 10
8K
64 ms
7.8 µs
1 GB
128M × 72
2
64M ×4
36
13 / 2 / 11
8K
64 ms
7.8 µs
Density
Data Sheet
13
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
RS0
DQS0
DM0/DQS9
DQS4
DM4/DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D2
DQS8
DM8/DQS17
CS0
R
E
G
I
S
T
E
R
A0-A12
RAS
CAS
CKE0
WE
PCK
PCK
Figure 2
Data Sheet
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
CS DQS
D5
CS
DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D3
CS DQS
D7
VDDSPD
EEPROM
VDD, V DDQ
D0 - D8
VREF
D0 - D8
Serial PD
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
BA0-BA1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
CS
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D0 - D8
DQS
SDA
D8
SCL
A0
A1
A2
SA0 SA1 SA2
RS0 -> CS : SDRAMs D0-D8
V DDID
D0 - D8
Strap: see Note 4
Notes:
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
RA0-RA12 -> A0-A12: SDRAMs D0 - D8
RRAS -> RAS : SDRAMs D0 - D8
RCAS -> CAS : SDRAMs D0 - D8
RCKE0 -> CKE: SDRAMs D0 - D8
RWE -> WE : SDRAMs D0 - D8
RESET
V SS
CK0, CK 0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
5. SDRAM placement alternates between the back
and front of the DIMM.
Block Diagram: One Rank 32M × 72 DDR SDRAM DIMM Module (32M×8 components)
HYS72D32300GBR on Raw Card A
14
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
RS1
RS0
DQS0
DM0/DQS9
DQS4
DM4/DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D9
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
CS
D4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D13
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D10
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DQS8
DM8/DQS17
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D11
CS
DQS
D6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
D3
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D12
CS DQS
D7
Serial PD
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS DQS
D14
CS
DQS
D15
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D5
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D8
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS
D16
VDDSPD
DQS
EEPROM
SDA
SCL
D17
A0
A1
A2
SA0 SA1 SA2
V DD, V DDQ
D0 - D17
VREF
D0 - D17
V SS
V DDID
D0 - D17
Strap: see Note 4
CK0, CK 0 --------- PLL*
CS0
CS1
BA0-BA1
A0-A12
RAS
CAS
CKE0
CKE1
WE
R
E
G
I
S
T
E
R
PCK
PCK
Figure 3
Data Sheet
* Wire per Clock Loading Table/Wiring Diagrams
RS0 -> CS : SDRAM D0-D8
RS1 -> CS : SDRAM D9-D17
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
RA0-RA12 -> A0-A12: SDRAMs D0 - D17
RRAS -> RAS : SDRAMs D0 - D17
RCAS -> CAS : SDRAMs D0 - D17
RCKE0 -> CKE: SDRAMs D0 - D8
RCKE1 -> CKE: SDRAMs D9 - D17
RWE -> WE : SDRAMs D0 - D17
RESET
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
Block Diagram: Two Ranks 64M × 72 DDR-I SDRAM DIMM Module (32M×8 components)
HYS 72D64320GBR on Raw Card B
15
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
VSS
RS0B
RS0A
DQS0
DM0/DQS9
DQS
CS
DQ0
DQ1
DQ2
DQ3
I/O 0
I/O 1
I/O 2
I/O 3
DQ8
DQ9
DQ10
DQ11
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ16
DQ17
DQ18
DQ19
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ24
DQ25
DQ26
DQ27
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ32
DQ33
DQ34
DQ35
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ40
DQ41
DQ42
DQ43
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQ4
DQ5
DQ6
DQ7
D0
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D9
DM1/DQS10
DQS1
CS
DM
DQ12
DQ13
DQ14
DQ15
D1
DQS2
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D10
DM2/DQS11
DQS3
DM
DQ20
DQ21
DQ22
DQ23
D2
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D11
DM3/DQS12
DM
DQ28
DQ29
DQ30
DQ31
D3
DQS4
DM
DQ36
DQ37
DQ38
DQ39
D4
DQS5
DQS6
DQ48
DQ49
DQ50
DQ51
DM
DM5/DQS14
DQ44
DQ45
DQ46
DQ47
D5
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
CS
DM
DM6/DQS15
DQ52
DQ53
DQ54
DQ55
D6
DQS7
DQS8
DM4/DQS13
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D12
DQS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ56
DQ57
DQ58
DQ59
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
I/O 0
I/O 1
I/O 2
I/O 3
D7
DQS
CS0
BA0-BA1
A0-A11,A12
RAS
CAS
CKE0
WE
PCK
PCK
Figure 4
Data Sheet
R
E
G
I
S
T
E
R
DQ60
DQ61
DQ62
DQ63
CS
DM
DM8/DQS17
D8
CB4
CB5
CB6
CB7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
V DDSPD
EEPROM
VDD, VDDQ
D0 - D17
VREF
D0 - D17
V SS
CS
DM
D0 - D17
V DDID
Strap: see Note 4
D14
Serial PD
CS
DQS
I/O 0
I/O 1
D15
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
D13
DM7/DQS16
DM
DM
CS
DM
D17
A0
A1
A2
SA0 SA1 SA2
DM
Notes:
D16
CS
SDA
SCL
DM
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDDQ
5. SDRAM placement alternates between the back
and front of the DIMM.
RS 0 -> CS : SDRAMs D0-D17
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
RA0-RA11,RA12 -> A0-A11,A12: SDRAMs D0 - D17
RRAS -> RAS : SDRAMs D0 - D17
RCAS -> CAS : SDRAMs D0 - D17
RCKE0A -> CKE: SDRAMs D0 - D8
RCKEB -> CKE: SDRAMs D9 - D17
CK0, CK 0 --------- PLL*
RWE -> WE : SDRAMs D0 - D17
*
Wire
per
Clock
Loading Table/Wiring Diagrams
RESET
Block Diagram: One Rank 64M × 72 DDR-I SDRAM DIMM Modules (64M×4 components)
HYS72D64300GBR on Raw Card C
16
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Pin Configuration
VSS
RS1
RS0
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ8
DQ9
DQ10
DQ11
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ16
DQ17
DQ18
DQ19
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ24
DQ25
DQ26
DQ27
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ32
DQ33
DQ34
DQ35
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ40
DQ41
DQ42
DQ43
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQ48
DQ49
DQ50
DQ51
CS
DQ56
DQ57
DQ58
DQ59
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
CB0
CB1
CB2
CB3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
D0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ4
DQ5
DQ6
DQ7
D18
CS
DM
D9
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D27
DM1/DQS10
DQS1
CS
DM
D1
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
DQ12
DQ13
DQ14
DQ15
D19
DQS2
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D10
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D28
DM2/DQS11
DQS3
DM
D2
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
DQ20
DQ21
DQ22
DQ23
D20
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D11
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D29
DM3/DQS12
DM
D3
DM
DQ28
DQ29
DQ30
DQ31
D21
DQS4
DM4/DQS13
DM
D4
DQ36
DQ37
DQ38
DQ39
DQS5
DQS6
DM
D5
DM
D6
DM5/DQS14
DM
D23
DM6/DQS15
DM
DQ52
DQ53
DQ54
DQ55
D24
DQS7
D7
DM
DQ60
DQ61
DQ62
DQ63
D25
D8
DM
WE
PCK
PCK
Figure 5
Data Sheet
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
SCL
RSO -> CS : SDRAMs D0-D17
RS1 -> CS: SDRAMs D18-D35
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35
RA0-RA12 -> A0-A12: SDRAMs D0- D35
RRAS -> RAS: SDRAMs D0-D35
RCAS -> CAS: SDRAMs D0-D35
RCKE0 -> CKE: SDRAMs D0-D17
RCKE1 -> CKE: SDRAMs D18-D35
RWE -> WE: SDRAMs D0-D35
RESET
WP A0
A1
CS
D17
A2
SA0 SA1 SA2
VDDQ
SDA VDD
VREF
VSS
VDDID
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
D16
VDDSPD
Serial PD
DM
D15
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D14
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
D26
CK0, CK0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
R
E
G
I
S
T
E
R
I/O 0
I/O 1
I/O 2
I/O 3
DM8/DQS17
DM
DM
D13
DM7/DQS16
DM
DQS8
S0
S1
BA0-BA1
A0-A12
RAS
CAS
CKE0
CKE1
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
DQ44
DQ45
DQ46
DQ47
DM
D12
DQS
DM
D22
CS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CS
DM
D30
CS
DM
D31
CS
DM
D32
CS
DM
D33
CS
DM
D34
CS
DM
D35
Serial PD
D0-D35
D0-D35
D0-D35
D0-D35
Strap: see Note 4
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ.
5. Address and control resistors should be 22 Ohms.
6. Each Chip Select and CKE pair alternate between decks for thermal enhancement.
Block Diagram: Two Ranks 128M × 72 DDR SDRAM DIMM Modules (64M×4 components)
HYS72D128320GBR on Raw Card D
17
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 7
Absolute Maximum Ratings
Parameter
Symbol
Voltage on I/O pins relative to VSS
VIN, VOUT
Values
min.
typ.
max.
Unit Note/ Test
Condition
–0.5
–
VDDQ +
V
–
0.5
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
–0.5
–
+3.6
V
–
–0.5
–
+3.6
V
–
–0.5
–
+3.6
V
–
0
–
+70
°C
–
-55
–
+150
°C
–
–
2.0
–
W
–
–
50
–
mA
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 8
Electrical Characteristics and DC Operating Conditions
Parameter
Device Supply Voltage
Symbol
VDD
VDD
Output Supply Voltage
VDDQ
Output Supply Voltage
VDDQ
EEPROM supply voltage
VDDSPD
Supply Voltage, I/O Supply VSS,
Voltage
VSSQ
Input Reference Voltage
VREF
I/O Termination Voltage
VTT
Device Supply Voltage
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
fCK ≤ 166 MHz
fCK > 166 MHz 2)
fCK ≤ 166 MHz 3)
fCK > 166 MHz 2)3)
2.3
2.5
3.6
V
—
0
V
—
0
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V
4)
VREF – 0.04
VREF + 0.04 V
5)
Input High (Logic1) Voltage VIH(DC)
VREF + 0.15
8)
Input Low (Logic0) Voltage VIL(DC)
–0.3
Input Voltage Level,
CK and CK Inputs
VIN(DC)
–0.3
VDDQ + 0.3 V
VREF – 0.15 V
VDDQ + 0.3 V
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
VDDQ + 0.6
V
8)6)
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
1.4
—
7)
(System)
Data Sheet
18
8)
8)
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 8
Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter
Symbol
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
Input Leakage Current
II
–2
2
µA
Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 8)9)
Output Leakage Current
IOZ
–5
5
µA
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ
Output High Current,
Normal Strength Driver
IOH
—
–16.2
mA
VOUT = 1.95 V
Output Low
Current, Normal Strength
Driver
IOL
16.2
—
mA
VOUT = 0.35 V
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD.
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Data Sheet
19
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
HYS72D64300GBR-5-B
HYS72D64320GBR-5-B
HYS72D128320GBR-5-B
IDD Specifications
HYS72D32300GBR-5-B
Product Type & Organisation
Table 9
256 MB
×72
1 Rank
–5
512 MB
×72
1 Rank
–5
512 MB
×72
2 Ranks
–5
1 GByte
×72
2 Ranks
–5
Unit
Note/ Test
Conditions5)
typ.
max.
typ.
max.
typ.
max.
typ.
max.
1690
1960
2500
3040
2284
2599
3688
4318
mA
1)4)
1825
2005
2770
3130
2419
2644
3958
4408
mA
1)3)4)
698
725
752
806
752
806
860
968
mA
2)4)
1076
1139
1508
1634
1508
1634
2372
2624
mA
2)4)
878
932
1112
1220
1112
1220
1580
1796
mA
2)4)
815
869
986
1094
986
1094
1328
1544
mA
2)4)
1238
1319
1832
1994
1832
1994
3020
3344
mA
2)4)
2005
2185
3130
3490
2599
2824
4318
4768
mA
1)3)4)
2005
2194
3130
3508
2599
2833
4318
4786
mA
1)4)
2320
2635
3760
4390
2914
3274
4948
5668
mA
1)4)
656.6
671
669.2
698
669.2
698
694.4
752
mA
2)4)
3040
3310
5200
5740
3634
3949
6388
7018
mA
1)3)4)5)
1) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
n * IDD×[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
2 * n * IDD×[component] for single two bank modules (n: number of components per module bank)
3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
4) Module IDD is calculated on the basis of component IDD and includes Register and PLL
5) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
Data Sheet
20
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
IDD Specifications
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
HYS72D32300GBR-6-B
HYS72D64300GBR-6-B
HYS72D64320GBR-6-B
HYS72D128320GBR-6-B
Product Type & Organisation
Table 10
256 MB
×72
1 Rank
–6
512 MB
×72
1Ranks
–6
512 MB
×72
2 Ranks
–6
1 GB
×72
2 Ranks
–6
Unit
Note/ Test
Conditions5)
typ.
max.
typ.
max.
typ.
max.
typ.
max.
1495
1720
2260
2710
2035
2305
3340
3880
mA
1)4)
1630
1810
2530
2890
2170
2395
3610
4060
mA
1)3)4)
484
511
538
592
538
592
646
754
mA
2)4)
835
925
1240
1420
1240
1420
2050
2410
mA
2)4)
652
682
875
934
875
934
1319
1438
mA
2)4)
592
619
754
808
754
808
1078
1186
mA
2)4)
970
1015
1510
1600
1510
1600
2590
2770
mA
2)4)
1720
1990
2710
3250
2260
2575
3790
4420
mA
1)3)4)
1855
2035
2980
3340
2395
2620
4060
4510
mA
1)4)
2022
2440
3313
4150
2562
3025
4393
5320
mA
1)4)
444
453
457
475
457
475
484
520
mA
2)4)
2600
3160
4470
5590
3140
3745
5550
6760
mA
1)3)4)5)
1) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
n * IDD×[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
2 * n * IDD×[component] for single two bank modules (n: number of components per module bank)
3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
4) Module IDD is calculated on the basis of component IDD and includes Register and PLL
5) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
Data Sheet
21
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
IDD Specifications
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
HYS72D32300GBR-7-B
HYS72D64300GBR-7-B
HYS72D64320GBR-7-B
HYS72D128320GBR-7-B
Product Type & Organisation
Table 11
256 MB
×72
1 Rank
–7
512 MB
×72
1 Rank
–7
512 MB
×72
2 Ranks
–7
1 GB
×72
2 Ranks
–7
Unit
Note/ Test
Conditions5)
typ.
max.
typ.
max.
typ.
max.
typ.
max.
1263
1488
1938
2388
1713
1983
2838
3378
mA
1)4)
1398
1578
2208
2568
1848
2073
3108
3558
mA
1)3)4)
426
448
475
520
475
520
574
664
mA
2)4)
691
736
1006
1096
1006
1096
1636
1816
mA
2)4)
556
601
736
826
736
826
1096
1276
mA
2)4)
511
538
646
700
646
700
916
1024
mA
2)4)
826
871
1276
1366
1276
1366
2176
2356
mA
2)4)
1443
1623
2298
2658
1893
2118
3198
3648
mA
1)3)4)
1533
1713
2478
2838
1983
2208
3378
3828
mA
1)4)
1803
2208
3018
3828
2253
2703
3918
4818
mA
1)4)
390
399
403
421
403
421
430
466
mA
2)4)
2128
2613
3668
4638
2578
3108
4568
5628
mA
1)3)4)5)
1) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
n * IDD×[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
2 * n * IDD×[component] for single two bank modules (n: number of components per module bank)
3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
4) Module IDD is calculated on the basis of component IDD and includes Register and PLL
5) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
Data Sheet
22
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
3.2
AC Characteristics
Table 12
AC Timing - Absolute Specifications –5/–6/–7
Parameter
DQ output access time from
CK/CK
Symbol
tAC
DQS output access time from tDQSCK
CK/CK
CK high-level width
CK low-level width
Clock Half Period
tCH
tCL
tHP
tCK
–5
–6
–7
DDR400B
DDR333
DDR266A
Unit Note/ Test
Condition 1)
Min.
Max.
Min.
Max.
Min.
–0.7
+0.7
–0.7
+0.7
–0.75 +0.75
ns
2)3)4)5)
–0.6
+0.6
–0.6
+0.6
–0.75 +0.75
ns
2)3)4)5)
0.45
0.55
0.45
0.55
0.45
0.55
2)3)4)5)
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCK
min. (tCL, tCH) ns
2)3)4)5)
min. (tCL, tCH)
min. (tCL, tCH)
Max.
2)3)4)5)
5
8
—
—
—
—
ns
CL = 3.0 2)3)4)5)
6
12
6
12
7.5
12
ns
CL = 2.5 2)3)4)5)
7.5
12
7.5
12
7.5
12
ns
CL = 2.0 2)3)4)5)
0.4
—
0.45
—
0.5
—
ns
2)3)4)5)
0.4
—
0.45
—
0.5
—
ns
2)3)4)5)
2.2
—
2.2
—
2.2
—
ns
2)3)4)5)6)
DQ and DM input pulse width tDIPW
(each input)
1.75
—
1.75
—
1.75
—
ns
2)3)4)5)6)
Data-out high-impedance time tHZ
from CK/CK
—
+0.7
—
+0.7
—
+0.75
ns
2)3)4)5)7)
Data-out low-impedance time tLZ
from CK/CK
–0.7
+0.7
–0.7
+0.7
–0.75 +0.75
ns
2)3)4)5)7)
Write command to 1st DQS
latching transition
tDQSS
0.72
1.25
0.75
1.25
0.75
1.25
tCK
2)3)4)5)
DQS-DQ skew (DQS and
associated DQ signals)
tDQSQ
—
+0.4
—
+0.4
—
+0.5
ns
TFBGA 2)3)4)5)
Data hold skew factor
tQHS
tQH
—
+0.5
—
+0.55
+0.75 ns
TFBGA 2)3)4)5)
tHP –
tQHS
—
tHP –
tQHS
—
tHP –
tQHS
—
ns
2)3)4)5)
tDQSL,H
0.35
—
0.35
—
0.35
—
tCK
2)3)4)5)
DQS falling edge to CK setup tDSS
time (write cycle)
0.2
—
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge hold time
from CK (write cycle)
tDSH
0.2
—
0.2
—
0.2
—
tCK
2)3)4)5)
Mode register set command
cycle time
tMRD
2
—
2
—
2
—
tCK
2)3)4)5)
Write preamble setup time
tWPRES
tWPST
tWPRE
0
—
0
—
0
—
ns
2)3)4)5)8)
0.4
0.6
0.4
0.6
0.4
0.6
2)3)4)5)9)
0.25
—
0.25
—
0.25
—
tCK
tCK
Clock cycle time
tDH
DQ and DM input setup time tDS
Control and Addr. input pulse tIPW
DQ and DM input hold time
width (each input)
DQ/DQS output hold time
DQS input low (high) pulse
width (write cycle)
Write postamble
Write preamble
Data Sheet
23
2)3)4)5)
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Table 12
AC Timing - Absolute Specifications –5/–6/–7 (cont’d)
Parameter
Address and control input
setup time
Symbol
tIS
–5
–6
–7
DDR400B
DDR333
DDR266A
Min.
Max.
Min.
Max.
Min.
Max.
0.6
—
0.75
—
0.9
—
Unit Note/ Test
Condition 1)
ns
fast slew rate
3)4)5)6)10)
0.7
—
0.8
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Address and control input hold tIH
time
0.6
0.75
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
0.7
0.8
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
tRPRE
Read postamble
tRPST
Active to Precharge command tRAS
Active to Active/Auto-refresh tRC
Read preamble
tCK
tCK
2)3)4)5)
70E+3 45
70E+3 ns
2)3)4)5)
60
—
65
—
ns
2)3)4)5)
72
—
75
—
ns
2)3)4)5)
—
18
—
20
—
ns
2)3)4)5)
—
18
—
20
—
ns
2)3)4)5)
tRCD or —
tRASmin
ns
2)3)4)5)
—
15
—
ns
2)3)4)5)
—
15
—
ns
2)3)4)5)
tCK
2)3)4)5)11)
0.9
1.1
0.9
1.1
0.90
1.1
0.4
0.6
0.4
0.6
0.4
0.6
40
70E+3 42
55
tRFC
65
tRCD
Precharge command period
tRP
Active to Autoprecharge delay tRAP
15
15
Active bank A to Active bank B tRRD
command
10
—
12
tWR
Auto precharge write recovery tDAL
15
—
15
2)3)4)5)
command period
Auto-refresh to Active/Autorefresh command period
Active to Read or Write delay
Write recovery time
tRCD or
tRASmin
tRCD or
tRASmin
—
—
—
+ precharge time
Internal write to read
command delay
tWTR
2
—
1
—
1
—
tCK
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
75
—
75
—
75
—
ns
2)3)4)5)
Exit self-refresh to read
command
tXSRD
200
—
200
—
200
—
tCK
2)3)4)5)
Average Periodic Refresh
Interval
tREFI
—
7.8
—
7.8
—
7.8
µs
2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Data Sheet
24
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac).
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
25
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D32300GBR–5–B
HYS72D64320GBR–5–B
SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5
HYS72D64300GBR–5–B
Table 13
HYS72D128320GBR–5–B
SPD Contents
Product Type & Organization
4
1 GByte
512 MB
512 MB
256 MB
×72
×72
×72
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
PC3200R–30331
PC3200R–30330
PC3200R–30330 PC3200R–30330
Jedec SPD Revision Rev 1.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
0
Programmed SPD
Bytes in E2PROM
80
80
80
80
1
Total number of Bytes 08
in E2PROM
08
08
08
2
Memory Type (DDR = 07
07h)
07
07
07
3
Number of Row
Addresses
0D
0D
0D
0D
4
Number of Column
Addresses
0B
0B
0A
0A
5
Number of DIMM
Ranks
02
01
02
01
6
Data Width (LSB)
48
48
48
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage
Levels
04
04
04
04
9
tCK @ CLmax (Byte
18) [ns]
50
50
50
50
10
tAC SDRAM @
CLmax (Byte 18) [ns]
50
50
50
50
11
Error Correction
Support
02
02
02
02
12
Refresh Rate
82
82
82
82
13
Primary SDRAM
Width
04
04
08
08
14
Error Checking
SDRAM Width
04
04
08
08
15
tCCD [cycles]
01
01
01
01
Label Code
Data Sheet
26
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D64320GBR–5–B
HYS72D32300GBR–5–B
1 GByte
512 MB
512 MB
256 MB
×72
×72
×72
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
PC3200R–30331
PC3200R–30330
PC3200R–30330 PC3200R–30330
Jedec SPD Revision Rev 1.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
16
Burst Length
Supported
0E
0E
0E
0E
17
Number of Banks on
SDRAM Device
04
04
04
04
18
CAS Latency
1C
1C
1C
1C
19
CS Latency
01
01
01
01
20
Write Latency
02
02
02
02
21
DIMM Attributes
26
26
26
26
22
Component Attributes C0
C1
C1
C1
23
tCK @ CLmax -0.5
(Byte 18) [ns]
60
60
60
60
24
tAC SDRAM @
CLmax -0.5 [ns]
50
50
50
50
25
tCK @ CLmax -1 (Byte 75
18) [ns]
75
75
75
26
tAC SDRAM @
CLmax -1 [ns]
50
50
50
50
27
tRPmin [ns]
3C
3C
3C
3C
28
tRRDmin [ns]
28
28
28
28
29
tRCDmin [ns]
3C
3C
3C
3C
30
tRASmin [ns]
28
28
28
28
31
Module Density per
Rank
80
80
40
40
32
tAS, tCS [ns]
60
60
60
60
33
tAH, TCH [ns]
60
60
60
60
34
tDS [ns]
40
40
40
40
35
tDH [ns]
40
40
40
40
36 - 40
not used
00
00
00
00
41
tRCmin [ns]
37
37
37
37
Product Type & Organization
HYS72D64300GBR–5–B
SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5
HYS72D128320GBR–5–B
Table 13
Label Code
Data Sheet
27
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D64320GBR–5–B
HYS72D32300GBR–5–B
1 GByte
512 MB
512 MB
256 MB
×72
×72
×72
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
PC3200R–30331
PC3200R–30330
PC3200R–30330 PC3200R–30330
Jedec SPD Revision Rev 1.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
42
tRFCmin [ns]
41
41
41
41
43
tCKmax [ns]
28
28
28
28
44
tDQSQmax [ns]
28
28
28
28
45
tQHSmax [ns]
50
50
50
50
46
not used
00
00
00
00
47
DIMM PCB Height
01
00
00
00
48 - 61
not used
00
00
00
00
62
SPD Revision
10
00
00
00
63
Checksum of Byte 062
5F
4E
16
15
64
JEDEC ID Code of
Infineon (1)
C1
C1
C1
C1
65
JEDEC ID Code of
Infineon (2)
49
49
49
49
66
JEDEC ID Code of
Infineon (3)
4E
4E
4E
4E
67
JEDEC ID Code of
Infineon (4)
46
46
46
46
68
JEDEC ID Code of
Infineon (5)
49
49
49
49
69
JEDEC ID Code of
Infineon (6)
4E
4E
4E
4E
70
JEDEC ID Code of
Infineon (7)
45
45
45
45
71
JEDEC ID Code of
Infineon (8)
4F
4F
4F
4F
72
Module Manufacturer
Location
xx
xx
xx
xx
73
Part Number, Char 1
37
37
37
37
74
Part Number, Char 2
32
32
32
32
Product Type & Organization
HYS72D64300GBR–5–B
SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5
HYS72D128320GBR–5–B
Table 13
Label Code
Data Sheet
28
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D64320GBR–5–B
HYS72D32300GBR–5–B
1 GByte
512 MB
512 MB
256 MB
×72
×72
×72
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
PC3200R–30331
PC3200R–30330
PC3200R–30330 PC3200R–30330
Jedec SPD Revision Rev 1.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
75
Part Number, Char 3
44
44
44
44
76
Part Number, Char 4
31
36
36
33
77
Part Number, Char 5
32
34
34
32
78
Part Number, Char 6
38
33
33
33
79
Part Number, Char 7
33
30
32
30
80
Part Number, Char 8
32
30
30
30
81
Part Number, Char 9
30
47
47
47
82
Part Number, Char 10 47
42
42
42
83
Part Number, Char 11 42
52
52
52
84
Part Number, Char 12 52
35
35
35
85
Part Number, Char 13 37
42
42
42
86
Part Number, Char 14 42
20
20
20
87
Part Number, Char 15 20
20
20
20
88
Part Number, Char 16 20
20
20
20
89
Part Number, Char 17 20
20
20
20
90
Part Number, Char 18 20
20
20
20
91
Module Revision Code xx
xx
xx
xx
92
Test Program
Revision Code
xx
xx
xx
xx
93
Module Manufacturing xx
Date Year
xx
xx
xx
94
Module Manufacturing xx
Date Week
xx
xx
xx
95
Module Serial Number xx
(1)
xx
xx
xx
96
Module Serial Number xx
(2)
xx
xx
xx
97
Module Serial Number xx
(3)
xx
xx
xx
Product Type & Organization
HYS72D64300GBR–5–B
SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5
HYS72D128320GBR–5–B
Table 13
Label Code
Data Sheet
29
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D64320GBR–5–B
HYS72D32300GBR–5–B
1 GByte
512 MB
512 MB
256 MB
×72
×72
×72
×72
2 Ranks
1 Rank
2 Ranks
1 Rank
PC3200R–30331
PC3200R–30330
PC3200R–30330 PC3200R–30330
Jedec SPD Revision Rev 1.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
98
Module Serial Number xx
(4)
xx
xx
xx
00
00
00
Product Type & Organization
HYS72D64300GBR–5–B
SPD Codes for HYS72D128320GBR–5, HYS72D643[00/20]GBR–5 and HYS72D32300GBR–5
HYS72D128320GBR–5–B
Table 13
Label Code
HEX
99 - 127 not used
HYS72D32300GBR–6–B
HYS72D64320GBR–6–B
HYS72D64300GBR–7–B
HYS72D64300GBR–6–B
HYS72D128320GBR–6–B
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
Product Type & Organization
Table 14
00
1 GByte
512 MB
512 MB
512 MB
256 MB
×72
×72
×72
×72
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD 80
Bytes in E2PROM
80
80
80
80
1
Total number of
08
Bytes in E2PROM
08
08
08
08
2
Memory Type
(DDR = 07h)
07
07
07
07
Data Sheet
07
30
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D64300GBR–7–B
HYS72D64320GBR–6–B
HYS72D32300GBR–6–B
1 GByte
512 MB
512 MB
512 MB
256 MB
×72
×72
×72
×72
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
3
Number of Row
Addresses
0D
0D
0D
0D
0D
4
Number of
Column
Addresses
0B
0B
0B
0A
0A
5
Number of DIMM
Ranks
02
01
01
02
01
6
Data Width (LSB) 48
48
48
48
48
7
Data Width (MSB) 00
00
00
00
00
8
Interface Voltage
Levels
04
04
04
04
04
9
tCK @ CLmax
(Byte 18) [ns]
60
60
70
60
60
10
tAC SDRAM @
CLmax (Byte 18)
[ns]
70
70
75
70
70
11
Error Correction
Support
02
02
02
02
02
12
Refresh Rate
82
82
82
82
82
13
Primary SDRAM
Width
04
04
04
08
08
14
Error Checking
SDRAM Width
04
04
04
08
08
15
tCCD [cycles]
01
01
01
01
01
16
Burst Length
Supported
0E
0E
0E
0E
0E
17
Number of Banks 04
on SDRAM
Device
04
04
04
04
Product Type & Organization
HYS72D64300GBR–6–B
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
HYS72D128320GBR–6–B
Table 14
Data Sheet
31
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D64300GBR–7–B
HYS72D64320GBR–6–B
HYS72D32300GBR–6–B
1 GByte
512 MB
512 MB
512 MB
256 MB
×72
×72
×72
×72
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
18
CAS Latency
0C
0C
0C
0C
0C
19
CS Latency
01
01
01
01
01
20
Write Latency
02
02
02
02
02
21
DIMM Attributes
26
26
26
26
26
22
Component
Attributes
C0
C0
C0
C0
C0
23
tCK @ CLmax 0.5 (Byte 18) [ns]
75
75
75
75
75
24
tAC SDRAM @
CLmax -0.5 [ns]
70
70
75
70
70
25
tCK @ CLmax -1
(Byte 18) [ns]
00
00
00
00
00
26
tAC SDRAM @
CLmax -1 [ns]
00
00
00
00
00
27
tRPmin [ns]
48
48
50
48
48
28
tRRDmin [ns]
30
30
3C
30
30
29
tRCDmin [ns]
48
48
50
48
48
30
tRASmin [ns]
2A
2A
2D
2A
2A
31
Module Density
per Rank
80
80
80
40
40
32
tAS, tCS [ns]
75
75
90
75
75
33
tAH, TCH [ns]
75
75
90
75
75
34
tDS [ns]
45
45
50
45
45
35
tDH [ns]
45
45
50
45
45
36 - 40
not used
00
00
00
00
00
41
tRCmin [ns]
3C
3C
41
3C
3C
42
tRFCmin [ns]
48
48
4B
48
48
Product Type & Organization
HYS72D64300GBR–6–B
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
HYS72D128320GBR–6–B
Table 14
Data Sheet
32
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D64300GBR–7–B
HYS72D64320GBR–6–B
HYS72D32300GBR–6–B
1 GByte
512 MB
512 MB
512 MB
256 MB
×72
×72
×72
×72
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
43
tCKmax [ns]
30
30
30
30
30
44
tDQSQmax [ns]
28
28
32
28
28
45
tQHSmax [ns]
50
50
75
50
50
46
not used
00
00
00
00
00
47
DIMM PCB Height 00
00
00
00
00
48 - 61
not used
00
00
00
00
00
62
SPD Revision
00
00
00
00
00
63
Checksum of Byte 48
0-62
47
03
0F
0E
64
JEDEC ID Code
of Infineon (1)
C1
C1
C1
C1
C1
65
JEDEC ID Code
of Infineon (2)
49
49
49
49
49
66
JEDEC ID Code
of Infineon (3)
4E
4E
4E
4E
4E
67
JEDEC ID Code
of Infineon (4)
46
46
46
46
46
68
JEDEC ID Code
of Infineon (5)
49
49
49
49
49
69
JEDEC ID Code
of Infineon (6)
4E
4E
4E
4E
4E
70
JEDEC ID Code
of Infineon (7)
45
45
45
45
45
71
JEDEC ID Code
of Infineon (8)
4F
4F
4F
4F
4F
72
Module
Manufacturer
Location
xx
xx
xx
xx
xx
Product Type & Organization
HYS72D64300GBR–6–B
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
HYS72D128320GBR–6–B
Table 14
Data Sheet
33
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D64300GBR–7–B
HYS72D64320GBR–6–B
HYS72D32300GBR–6–B
1 GByte
512 MB
512 MB
512 MB
256 MB
×72
×72
×72
×72
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
73
Part Number,
Char 1
37
37
37
37
37
74
Part Number,
Char 2
32
32
32
32
32
75
Part Number,
Char 3
44
44
44
44
44
76
Part Number,
Char 4
31
36
36
36
33
77
Part Number,
Char 5
32
34
34
34
32
78
Part Number,
Char 6
38
33
33
33
33
79
Part Number,
Char 7
33
30
30
32
30
80
Part Number,
Char 8
32
30
30
30
30
81
Part Number,
Char 9
30
47
47
47
47
82
Part Number,
Char 10
47
42
42
42
42
83
Part Number,
Char 11
42
52
52
52
52
84
Part Number,
Char 12
52
36
37
36
36
85
Part Number,
Char 13
36
42
42
42
42
86
Part Number,
Char 14
42
20
20
20
20
Product Type & Organization
HYS72D64300GBR–6–B
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
HYS72D128320GBR–6–B
Table 14
Data Sheet
34
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D64300GBR–7–B
HYS72D64320GBR–6–B
HYS72D32300GBR–6–B
1 GByte
512 MB
512 MB
512 MB
256 MB
×72
×72
×72
×72
×72
2 Ranks
1 Rank
1 Rank
2 Ranks
1 Rank
Label Code
PC2700R–
25330
PC2700R–
25330
PC2100R–
20330
PC2700R–
25330
PC2700R–
25330
Jedec SPD
Revision
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
HEX
HEX
87
Part Number,
Char 15
20
20
20
20
20
88
Part Number,
Char 16
20
20
20
20
20
89
Part Number,
Char 17
20
20
20
20
20
90
Part Number,
Char 18
20
20
20
20
20
91
Module Revision
Code
xx
xx
xx
xx
xx
92
Test Program
Revision Code
xx
xx
xx
xx
xx
93
Module
Manufacturing
Date Year
xx
xx
xx
xx
xx
94
Module
Manufacturing
Date Week
xx
xx
xx
xx
xx
95
Module Serial
Number (1)
xx
xx
xx
xx
xx
96
Module Serial
Number (2)
xx
xx
xx
xx
xx
97
Module Serial
Number (3)
xx
xx
xx
xx
xx
98
Module Serial
Number (4)
xx
xx
xx
xx
xx
00
00
00
00
00
Product Type & Organization
HYS72D64300GBR–6–B
SPD Codes for HYS72D128320GBR–6–B, HYS72D64300GBR–[6/7]–B, HYS72D64320GBR–6–B
and HYS72D32300GBR–6–B
HYS72D128320GBR–6–B
Table 14
99 - 127 not used
Data Sheet
35
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D32300GBR–7–B
1 GByte
512 MB
256 MB
×72
×72
×72
2 Ranks
2 Ranks
1 Rank
Label Code
PC2100R–
20330
PC2100R–
20330
PC2100R–
20330
Jedec SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
Product Type & Organization
HYS72D64320GBR–7–B
SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B
HYS72D128320GBR–7–B
Table 15
2
Memory Type (DDR = 07h)
07
07
07
3
Number of Row Addresses
0D
0D
0D
4
Number of Column Addresses
0B
0A
0A
5
Number of DIMM Ranks
02
02
01
6
Data Width (LSB)
48
48
48
7
Data Width (MSB)
00
00
00
8
Interface Voltage Levels
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
70
70
70
10
tAC SDRAM @ CLmax (Byte 18) [ns]
75
75
75
11
Error Correction Support
02
02
02
12
Refresh Rate
82
82
82
13
Primary SDRAM Width
04
08
08
14
Error Checking SDRAM Width
04
08
08
15
tCCD [cycles]
01
01
01
16
Burst Length Supported
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
18
CAS Latency
0C
0C
0C
19
CS Latency
01
01
01
20
Write Latency
02
02
02
21
DIMM Attributes
26
26
26
22
Component Attributes
C0
C0
C0
23
tCK @ CLmax -0.5 (Byte 18) [ns]
75
75
75
24
tAC SDRAM @ CLmax -0.5 [ns]
75
75
75
25
tCK @ CLmax -1 (Byte 18) [ns]
00
00
00
Data Sheet
36
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D32300GBR–7–B
1 GByte
512 MB
256 MB
×72
×72
×72
2 Ranks
2 Ranks
1 Rank
Label Code
PC2100R–
20330
PC2100R–
20330
PC2100R–
20330
Jedec SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
26
tAC SDRAM @ CLmax -1 [ns]
00
00
00
27
tRPmin [ns]
50
50
50
28
tRRDmin [ns]
3C
3C
3C
29
tRCDmin [ns]
50
50
50
30
tRASmin [ns]
2D
2D
2D
31
Module Density per Rank
80
40
40
32
tAS, tCS [ns]
90
90
90
33
tAH, TCH [ns]
90
90
90
34
tDS [ns]
50
50
50
35
tDH [ns]
50
50
50
36 - 40
not used
00
00
00
41
tRCmin [ns]
41
41
41
42
tRFCmin [ns]
4B
4B
4B
43
tCKmax [ns]
30
30
30
44
tDQSQmax [ns]
32
32
32
45
tQHSmax [ns]
75
75
75
46
not used
00
00
00
47
DIMM PCB Height
00
00
00
48 - 61
not used
00
00
00
62
SPD Revision
00
00
00
63
Checksum of Byte 0-62
04
CB
CA
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
65
JEDEC ID Code of Infineon (2)
49
49
49
66
JEDEC ID Code of Infineon (3)
4E
4E
4E
67
JEDEC ID Code of Infineon (4)
46
46
46
68
JEDEC ID Code of Infineon (5)
49
49
49
69
JEDEC ID Code of Infineon (6)
4E
4E
4E
Product Type & Organization
HYS72D64320GBR–7–B
SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B
HYS72D128320GBR–7–B
Table 15
Data Sheet
37
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D32300GBR–7–B
1 GByte
512 MB
256 MB
×72
×72
×72
2 Ranks
2 Ranks
1 Rank
Label Code
PC2100R–
20330
PC2100R–
20330
PC2100R–
20330
Jedec SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
70
JEDEC ID Code of Infineon (7)
45
45
45
71
JEDEC ID Code of Infineon (8)
4F
4F
4F
72
Module Manufacturer Location
xx
xx
xx
73
Part Number, Char 1
37
37
37
74
Part Number, Char 2
32
32
32
75
Part Number, Char 3
44
44
44
76
Part Number, Char 4
31
36
33
77
Part Number, Char 5
32
34
32
78
Part Number, Char 6
38
33
33
79
Part Number, Char 7
33
32
30
80
Part Number, Char 8
32
30
30
81
Part Number, Char 9
30
47
47
82
Part Number, Char 10
47
42
42
83
Part Number, Char 11
42
52
52
84
Part Number, Char 12
52
37
37
85
Part Number, Char 13
37
42
42
86
Part Number, Char 14
42
20
20
87
Part Number, Char 15
20
20
20
88
Part Number, Char 16
20
20
20
89
Part Number, Char 17
20
20
20
90
Part Number, Char 18
20
20
20
91
Module Revision Code
xx
xx
xx
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95
Module Serial Number (1)
xx
xx
xx
96
Module Serial Number (2)
xx
xx
xx
Product Type & Organization
HYS72D64320GBR–7–B
SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B
HYS72D128320GBR–7–B
Table 15
Data Sheet
38
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
SPD Contents
HYS72D32300GBR–7–B
1 GByte
512 MB
256 MB
×72
×72
×72
2 Ranks
2 Ranks
1 Rank
Label Code
PC2100R–
20330
PC2100R–
20330
PC2100R–
20330
Jedec SPD Revision
Rev 0.0
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
HEX
97
Module Serial Number (3)
xx
xx
xx
98
Module Serial Number (4)
xx
xx
xx
00
00
00
Product Type & Organization
HYS72D64320GBR–7–B
SPD Codes for HYS72D[64/128]320GBR–7–B and HYS72D32300GBR–7–B
HYS72D128320GBR–7–B
Table 15
99 - 127 not used
Data Sheet
39
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Package Outlines
Package Outlines
0.1 A B C
5
133.35
0.15 A B C
128.95
2.64 MAX.
28.58 ±0.13
4 ±0.1
A
1
2.5 ±0.1
ø0.1 A B C
92
6.62
B
2.175
0.4
6.35
64.77
C
1.27 ±0.1
49.53
1.8 ±0.1
0.1 A B C
184
17.8
93
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
Figure 6
Data Sheet
Package Outlines Raw Card A L-DIM 184-21
40
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
0.1 A B C
Package Outlines
133.35
0.15 A B C
128.95
4 MAX.
28.58 ±0.13
4 ±0.1
A
1
2.5 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
1.8 ±0.1
0.1 A B C
184
17.8
93
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
Figure 7
Data Sheet
Package Outlines Raw Card B L-DIM 184-23
41
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
0.1 A B C
Package Outlines
133.35
0.15 A B C
128.95
4 MAX.
28.58 ±0.13
4 ±0.1
A
1
2.5 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
1.8 ±0.1
0.1 A B C
184
17.8
93
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
Figure 8
Data Sheet
Package Outline Raw Card C L-DIM 184-22
42
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
30.48 ±0.13
4 ±0.1
A
1
2.5 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
Burr max. 0.4 allowed
Figure 9
Data Sheet
Package Outline Raw card D L-DIM 184-24
43
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Application Note
6
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item
1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and
to minimize power consumption during low power mode. One feature is externally controlled via a systemgenerated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations
and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked
Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM
inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the
register outputs are forced to a low level, and all differential register input receivers are powered down, resulting
in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as
an asynchronous signal according to the attached details. Using this function also permits the system and DIMM
clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh
mode.
Table 16
RESET Truth Table
Register Inputs
Register
Outputs
RESET
CK
CK
Data in (D)
Data out (Q)
H
Rising
Falling
H
H
H
Rising
Falling
L
L
H
L or H
L or H
X
Qo
H
High Z
High Z
X
Illegal input
conditions
L
X or Hi-Z
X or Hi-Z
X or Hi-Z
L
X: Don’t care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until
activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz
or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating
frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual
detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made
High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less than
1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied
inactive on the DIMM.
This application note describes the required and optional system sequences associated with the DDR Registered
DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control
CKE to one physical DIMM bank through the use of the RESET pin.
Data Sheet
44
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Application Note
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level.
This is the preferred default state during power-up. This input condition forces all register outputs to a low state
independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level
at the DDR SDRAMs.
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a
stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 µsec prior to
SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would
be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
5. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs
must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows their clock receivers, data input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDECpproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
1. 1. The system applies Self Refresh entry command.
(CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→ High)
Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the registerm
inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level
at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a
specific clock edge is not required.
3. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
Data Sheet
45
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Application Note
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the
register (t (INACT). The deactivate time defines the time in which the clocks and the control and address
signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b.The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which
the clocks and the control and the address signals must maintain valid levels after RESET low has been
applied. It is highly recommended that CKE continue to remain low during this operation.
4. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) — Optional
1. Stabilization of Clocks to the SDRAM.
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this
would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs, to
be consistent with the state of the register outputs.
3. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
RESET timing relationship to a specific clock edge is not required (during this period, register inputs must
remain stable).
4. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this
is an alternate operating mode for these DIMMs.
1. 1. System enters Self Refresh entry command.
(CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)
Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares — with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the data and clock
register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.
3. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes
the time in which the clocks and the control and the address signals must maintain valid levels after RESET
low has been applied. It is highly recommended that CKE continue to remain low during the operation.
4. The DIMM is in a low power, Self Refresh mode.
Data Sheet
46
Rev. 1.1, 2004-04
10102003-01E2-HPA8
HYS72D[32/64/128]3[00/20]GBR
Registered Double Data Rate SDRAM Modules
Application Note
Self Refresh Exit (RESET low, clocks running) — Optional
1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector). CKE must be maintained low and all other inputs should be driven to a known state. In general
these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’
command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this
would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
2. The system switches RESET to a logic 'high' level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain
stable).
3. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE
outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation
time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept
an input signal, is t (ACT ) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the
system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the
sequence defined in this application note. In the case where RESET remains high and the clocks are powered off,
the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM
state will result.
Data Sheet
47
Rev. 1.1, 2004-04
10102003-01E2-HPA8
www.infineon.com
Published by Infineon Technologies AG