AVAGO HCPL-J456 Intelligent power module and gate drive interface optocoupler Datasheet

HCPL-4506/J456/0466, HCNW4506
Intelligent Power Module and Gate Drive Interface Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The HCPL-4506 and HCPL-0466 contain a GaAsP LED while
the HCPL-J456 and the HCNW4506 con­tain an AlGaAs LED.
The LED is optically coupled to an inte­grated high gain
photo detector. Minimized propagation delay difference
between devices makes these optocouplers excellent solutions for improving inverter efficiency through reduced
switching dead time.
• Performance specified for bommon IPM applications
over industrial temperature range: -40°C to 100°C
An on chip 20 kΩ output pull-up resistor can be enabled by
shorting output pins 6 and 7, thus eliminating the need for
an external pull-up resistor in common IPM applications.
Specifications and performance plots are given for typical
IPM applications.
• 15 kV/µs minimum common mode transient immunity
at VCM = 1500 V
Functional Diagram
NC
1
8
VCC
20 kΩ
ANODE
2
7
VL
CATHODE
3
6
VO
NC
4
5
GND
Truth Table
LED
SHIELD
• Minimized Pulse Width Distortion
PWD = 450 ns
• CTR > 44% at IF = 10 mA
• Safety approval:
UL Recognized
-3750 V rms / 1 min. for HCPL-4506/0466/J456
-5000 V rms / 1 min. for HCPL-4506 Option 020
and HCNW4506
CSA Approved
IEC/EN/DIN EN 60747-5-2 Approved
-VIORM = 560 Vpeak for HCPL-0466 Option 060
-VIORM = 630 Vpeak for HCPL-4506 Option 060
-VIORM = 891 Vpeak for HCPL-J456
-VIORM = 1414 Vpeak for HCNW4506
Applications
VO
ON
L
HCPL-4506
Functional Diagram
OFF
• Fast maximum propagation delays
tPHL = 480 ns
tPLH = 550 ns
H
The connection of a 0.1 µF bypass capacitor
between pins 5 and 8 is recommended.
• IPM isolation
• Isolated IGBT/MOSFET gate drive
• AC and brushless DC motor drives
• Industrial inverters
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide Package
Type
Standard
8-Pin DIP
(300 Mil)
White Mold
8-Pin DIP
(300 Mil)
Small Outline
SO8
Widebody
(400 Mil)
Part
HCPL-4506
HCPL-J456
HCPL-0466
HCNW4506
Number
IEC/EN/DIN
EN 607475-2
Approval
VIORM = 630 Vpeak
VIORM = 891 Vpeak
(Option 060)
*Technical data for these products are on separate Avago publications.
VIORM = 560 Vpeak
(Option 060)
VIORM = 1414 Vpeak
Hermetic*
HCPL-5300
HCPL-5301
—
Ordering Information
HCPL-0466, HCPL-4506 and HCPL-J456 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
HCNW4506 is UL Recognized with 5000 Vrms for 1 minute per UL1577. HCPL-0466, HCPL-4506, HCPL-J456 and
HCNW4506 are approved under CSA Component Acceptance Notice #5, File CA 88324.
Part
Number
HCPL-4506
HCPL-J456
HCPL-0466
Option
RoHS
Compliant
non RoHS
Compliant Package
Surface
Mount
Gull
Wing
Tape
& Reel
UL 5000 Vrms/
1 Minute rating
IEC/EN/DIN
EN 60747-5-2
-000E
no option
-300E
#300
X
X
50 per tube
-500E
#500
X
X
1000 per reel
-020E
#020
300 mil DIP-8
X
X
Quantity
50 per tube
50 per tube
-320E
#320
X
X
X
50 per tube
-520E
#520
X
X
X
1000 per reel
-060E
#060
X
50 per tube
-360E
#360
X
X
X
50 per tube
-560E
#560
X
X
X
X
1000 per reel
-000E
no option
300 mil DIP-8
X
50 per tube
-300E
#300
X
X
X
50 per tube
-500E
#500
X
X
X
1000 per reel
-000E
no option
X
100 per tube
-500E
#500
X
1500 per reel
-060E
#060
X
X
100 per tube
-560E
#560
X
X
1500 per reel
-000E
no option
X
42 per tube
SO-8
X
X
X
X
400 mil
X
HCNW4506 -300E
#300
Widebody
X
X
X
X
42 per tube
-500E
#500
DIP-8
X
X
X
X
750 per reel
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-4506-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with
IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant.
Example 2:
HCPL-4506 to order product of 300 mil DIP package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’
Package Outline Drawings
HCPL-4506 Outline Drawing
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
TYPE NUMBER
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
OPTION CODE*
DATE CODE
A XXXXZ
YYWW RU
1
2
3
4
UL
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
5° TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
HCPL-4506 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
10.9 (0.430)
4
1.27 (0.050)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
2.0 (0.080)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12° NOM.
Package Outline Drawings
HCPL-J456 Outline Drawing
7.62 ± 0.25
(0.300 ± 0.010)
9.80 ± 0.25
(0.386 ± 0.010)
8
TYPE NUMBER
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
OPTION CODE*
DATE CODE
A XXXXZ
YYWW RU
1
2
3
4
UL
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
5° TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
HCPL-J456 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
9.80 ± 0.25
(0.386 ± 0.010)
8
7
6
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
10.9 (0.430)
4
1.27 (0.050)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
2.0 (0.080)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12° NOM.
HCPL-0466 Outline Drawing (8-Pin Small Outline Package)
LAND PATTERN RECOMMENDATION
8
7
6
5
5.994 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
7.49 (0.295)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
PIN ONE 1
2
3
1.9 (0.075)
4
0.406 ± 0.076
(0.016 ± 0.003)
0.64 (0.025)
1.270 BSC
(0.050)
* 5.080 ± 0.127
(0.200 ± 0.005)
7°
3.175 ± 0.127
(0.125 ± 0.005)
45° X
0.432
(0.017)
0 ~ 7°
1.524
(0.060)
0.228 ± 0.025
(0.009 ± 0.001)
0.203 ± 0.102
(0.008 ± 0.004)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
0.305 MIN.
(0.012)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
HCNW4506 Outline Drawing (8-Pin Widebody Package)
11.00 MAX.
(0.433)
11.15 ± 0.15
(0.442 ± 0.006)
8
7
6
5
TYPE NUMBER
A
HCNWXXXX
9.00 ± 0.15
(0.354 ± 0.006)
DATE CODE
YYWW
1
2
3
4
10.16 (0.400)
TYP.
1.55
(0.061)
MAX.
7° TYP.
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
5.10 MAX.
(0.201)
3.10 (0.122)
3.90 (0.154)
0.51 (0.021) MIN.
2.54 (0.100)
TYP.
1.78 ± 0.15
(0.070 ± 0.006)
0.40 (0.016)
0.56 (0.022)
DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
HCNW4506 Gull Wing Surface Mount Option 300 Outline Drawing
11.15 ± 0.15
(0.442 ± 0.006)
8
7
6
LAND PATTERN RECOMMENDATION
5
9.00 ± 0.15
(0.354 ± 0.006)
1
2
3
13.56
(0.534)
4
1.3
(0.051)
2.29
(0.09)
12.30 ± 0.30
(0.484 ± 0.012)
1.55
(0.061)
MAX.
11.00 MAX.
(0.433)
4.00 MAX.
(0.158)
1.78 ± 0.15
(0.070 ± 0.006)
2.54
(0.100)
BSC
0.75 ± 0.25
(0.030 ± 0.010)
1.00 ± 0.15
(0.039 ± 0.006)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
7° NOM.
Solder Reflow Temperature Profile
300
PREHEATING RATE 3 °C + 1 °C/–0.5 °C/SEC.
REFLOW HEATING RATE 2.5 °C ± 0.5 °C/SEC.
200
PEAK
TEMP.
245 °C
PEAK
TEMP.
240 °C
TEMPERATURE (°C)
2.5 C ± 0.5 °C/SEC.
30
SEC.
160 °C
150 °C
140 °C
PEAK
TEMP.
230 °C
SOLDERING
TIME
200 °C
30
SEC.
3 °C + 1 °C/–0.5 °C
100
PREHEATING TIME
150 °C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
TIME (SECONDS)
NOTE: NON-HALIDE FLUX SHOULD BE USED.
Recommended Pb-Free IR Profile
tp
Tp
TEMPERATURE
TL
Tsmax
* 260 +0/-5 °C
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
15 SEC.
217 °C
150 - 200 °C
RAMP-UP
3 °C/SEC. MAX.
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
25
tL
60 to 150 SEC.
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
NOTE: NON-HALIDE FLUX SHOULD BE USED.
* RECOMMENDED PEAK TEMPERATURE FOR WIDEBODY 400mils PACKAGE IS 245 °C
200
250
Regulatory Information
The devices contained in this data sheet have been approved by the following agencies:
Agency/Standard
Underwriters Laboratories (UL)
HCPL-4506
HCPL-J456
HCPL-0466
HCNW4506
•
•
•
•
•
•
•
•
•
•
•
UL 1577
Recognized under UL 1577, Component
Recognized Program, Category FPQU2,
File E55361
Canadian Standards
Association (CSA)
Component
Acceptance
Notice #5
File CA88324
Verband Deutscher
Electrotechniker (VDE)
DIN VDE 0884
(June 1992)
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
•
•
•
•
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
Insulation and Safety Related Specifications
Value
Parameter
Symbol
HCPL-4506
HCPL-J456
HCPL-0466
HCNW4506
Units
Conditions
Minimum External
L(101)
7.1
7.4
4.9
9.6
mm
Air Gap (External
Clearance)
Measured from input
terminals to output
terminals, shortest
distance through air.
Minimum External
L(102)
7.4
8.0
4.8
10.0
mm
Tracking (External
Creepage)
Measured from input
terminals to output
terminals, shortest
distance path along body.
Minimum Internal
0.08
0.5
0.08
1.0
mm
Plastic Gap
(Internal Clearance)
Through insulation
distance, conductor to
conductor, usually the
direct distance between
the photoemitter and
photodetector inside the
optocoupler cavity.
Minimum Internal
NA
NA
NA
4.0
mm
Tracking (Internal
Creepage)
Measured from input
terminals to output
terminals, along internal
cavity.
Tracking Resistance
CTI
≥175
≥175
≥175
≥200
Volts
(Comparative
Tracing Index)
Isolation Group
IIIa
IIIa
IIIa
IIIa
DIN IEC 112/VDE 0303
Part 1
Material Group (DIN
VDE 0110, 1/89, Table 1)
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation
require­ments. However, once mounted on a printed
circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment
standards. For creepage, the shortest distance path along
the surface of a printed circuit board between the solder
fillets of the input and output leads must be considered.
There are recom­mend­ed tech­niques such as grooves
and ribs which may be used on a printed circuit board to
achieve desired creepage and clear­ances. Creepage and
clearance distances will also change depending on factors such as pollution degree and insulation level.
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
Description
Symbol
HCPL-0466
Option 060
HCPL-4506
Option 060
HCPL-J456
HCNW4506
Unit
Installation classification per
DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms
I-IV
I-IV
I-IV
I-IV
for rated mains voltage ≤300 V rms
I-III
I-IV
I-IV
I-IV
for rated mains voltage ≤450 V rms
I-III
I-III
I-IV
for rated mains voltage ≤600 V rms
I-III
I-IV
for rated mains voltage ≤1000 V rms
I-III
Climatic Classification
55/100/21
55/100/21
55/100/21
55/100/21
Pollution Degree
(DIN VDE 0110/1.89)
2
2
2
2
560
630
891
1414
Maximum Working
Insulation Voltage
VIORM
Input to Output Test Voltage,
Method b* VIORM x 1.875 = VPR,
100% Production Test with tm =
VPR
1050
1181
1670
2652
1 sec, Partial Discharge < 5pC
Input to Output Test Voltage,
Method a* VIORM x 1.5 = VPR,
Type and Sample Test, tm = 60 sec,
VPR
840
945
1336
2121
Partial Discharge < 5pC
Highest Allowable Overvoltage*
VIOTM
4000
6000
6000
8000
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values – maximum
values allowed in the event of a fail-
ure, also see Thermal Derating curve.
Case Temperature
TS
150
175
175
150
Input Current
IS INPUT
150
230
400
400
Output Power
PS OUTPUT
600
600
600
700
Insulation Resistance at TS ,
RS
≥ 109
≥109
≥109
≥109
VIO = 500 V
Vpeak
Vpeak
Vpeak
Vpeak
°C
mA
mW
Ω
*Refer to the optocoupler section of the Designer's Catalog, under regulatory information (IEC/EN/DIN EN 60747-5-2) for a detailed description of
Method a and Method b partial discharge test profiles.
Notes:
These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data shall be ensured by
means of protective circuits.
Insulation Characteristics are per IEC/EN/DIN EN 60747-5-2.
Surface mount classification is Class A in accordance with CECC 00802.
10
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
100
°C
Average Input Current[1]
IF(avg)
25
mA
Peak Input Current[2] (50% duty cycle, ≤1 ms pulse width)
IF(peak)
50
mA
Peak Transient Input Current (<1 µs pulse width, 300 pps)
IF(tran)
1.0
A
VR
5
Volts
HCPL-J456, HCNW4506
3
Reverse Input Voltage (Pin 3-2)
HCPL-4506, HCPL-0466
Average Output Current (Pin 6)
IO(avg)
15
mA
Resistor Voltage (Pin 7)
V7
-0.5
VCC
Volts
Output Voltage (Pin 6-5)
VO
-0.5
30
Volts
Supply Voltage (Pin 8-5)
VCC
-0.5
30
Volts
Output Power Dissipation[3]
PO
100
mW
Total Power Dissipation[4]
PT
145
mW
Lead Solder Temperature (HCPL-4506, HCPL-J456)
260°C for 10 s, 1.6 mm below seating plane
Lead Solder Temperature (HCNW4506) Infrared and Vapor Phase Reflow Temperature (HCPL-0466 and Option 300)
See Package Outline Drawings Section
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Power Supply Voltage
VCC
4.5
30
Volts
Output Voltage
VO
0
30
Volts
Input Current (ON)
IF(on)
10
20
mA
Input Voltage (OFF)
VF(off )*
-5
0.8
V
TA
-40
100
°C
Operating Temperature
*Recommended VF(OFF) = -3 V to 0.8 V for HCPL-J456, HCNW4506.
11
260°C for 10 s
(up to seating plane)
Electrical Specifications
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off ) = -5 V to 0.8 V†
Parameter
Symbol
Device
Min.
Typ.*
Max.
Units Test Conditions
Fig.
Current Transfer Ratio
CTR
44
90
%
IF = 10 mA,
VO = 0.6 V
Low Level Output Current
IOL
4.4
9.0
mA
IF = 10 mA,
1, 2
VO = 0.6 V
Low Level Output Voltage
VOL
0.3
0.6
V
HCPL-4506
1.5
5
mA VO = 0.8 V,
1
HCPL-0466
IO = 0.75 mA
HCNW4506
HCPL-J456
IOH
5
IO = 2.4 mA
Input Threshold Current
ITH
High Level Output Current
Note
16
0.6
5
50
µA
VF = 0.8 V
3
High Level Supply Current
ICCH
0.6
1.3
mA
VF = 0.8 V,
VO = Open
16
Low Level Supply Current
ICCL
0.6
1.3
mA
IF = 10 mA,
VO = Open
16
Input Forward Voltage
VF
HCPL-4506
1.5
1.8
V
IF = 10 mA
4
HCPL-0466
HCPL-J456
HCNW4506
Temperature Coefficient
∆VF/∆TA
of Forward Voltage
Input Reverse Breakdown
BVR
Voltage
1.2
1.6
1.95
5
1.6
1.85
HCPL-4506
-1.6
mV/°C IF = 10 mA
HCPL-0466
HCPL-J456
HCNW4506
-1.3
HCPL-4506
5
V
IR = 10 µA
HCPL-0466
HCPL-J456
3
HCNW4506
IR = 100 µA
Input Capacitance
CIN
HCPL-4506
60
pF
HCPL-0466
f = 1 MHz,
VF = 0 V
HCPL-J456
72
HCNW4506
Internal Pull-up Resistor
Internal Pull-up Resistor
Temperature Coefficient
RL
∆RL/∆TA
*All typical values at 25°C, VCC = 15 V.
†VF(off ) = -3 V to 0.8 V for HCPL-J456, HCNW4506.
12
14
20
25
0.014
kΩ
TA = 25°C
kΩ/°C
12, 13
Switching Specifications (RL= 20 kΩ External)
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off ) = -5 V to 0.8 V†
Parameter
Symbol
Min.
Typ.*
Max. Units Test Conditions
Propagation Delay
TPHL
30
200
400
ns
CL = 100 pF
Time to Logic HCPL-J456
480
Low at Output
100
CL = 10 pF
IF(on) = 10 mA,
VF(off ) = 0.8 V,
VCC = 15.0 V,
Fig.
Note
6, 8,
1013
11,
14,
16
Propagation Delay
TPLH
270 400
550
ns
CL = 100 pF
V THLH = 2.0 V,
Time to High
V THHL = 1.5 V
Output Level
130
CL = 10 pF
Pulse Width
Distortion
PWD
200
450
ns
CL = 100 pF
20
Propagation Delay
tPLH-tPHL -150 200
450
ns
17
Difference Between
Any 2 Parts
Output High Level
|CMH|
15
30
kV/µs IF = 0 mA,
Common Mode
VO > 3.0 V
Transient Immunity
VCC = 15.0 V,
7
CL = 100 pF,
VCM = 1500 Vp-p
18
Output Low Level
|CML|
15
30
kV/µs IF = 10 mA
TA = 25°C
Common Mode
VO < 1.0 V
Transient Immunity
19
Switching Specifications (RL= Internal Pull-up)
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off ) = -5 V to 0.8 V†
Parameter
Symbol
Min.
Typ.*
Max.
Units Propagation Delay
tPHL
20
200
400
ns
Time to Logic HCPL-J456
485
Low at Output
Propagation Delay Time
to High Output Level
tPLH
Pulse Width
Distortion
PWD
Propagation Delay
Difference Between
Any 2 Parts
tPLH-tPHL
220
-150
Test Conditions
Fig.
IF(on) = 10 mA, VF(off ) = 0.8 V,
6, 9
VCC = 15.0 V, CL = 100 pF,
V THLH = 2.0 V, V THHL = 1.5 V
Note
11-14,
16
450
650
ns
250
500
ns
20
250
500
ns
17
Output High Level
|CMH|
30
kV/µs IF = 0 mA,
Common Mode
VO > 3.0 V
Transient Immunity
VCC = 15.0 V,
CL = 100 pF,
VCM = 1500 Vp-p,
7
18
Output Low Level
|CML|
30
kV/µs IF = 16 mA,
Common Mode
VO < 1.0 V
Transient Immunity
TA = 25°C
19
Square Wave, tRISE, tFALL
> 5 ns, no bypass capacitors
16
Power Supply
PSR
1.0
Vp-p
Rejection
*All typical values at 25°C, VCC = 15 V.
†VF(off ) = -3 V to 0.8 V for HCPL-J456, HCNW4506.
13
Package Characteristics
Over recommended temperature (TA = -40°C to 100°C) unless otherwise specified.
Parameter
Sym.
Input-Output Momentary
VISO
Withstand Voltage†
Device
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
HCPL-4506
3750
V rms
HCPL-0466
RH < 50%
t = 1 min.
6,7,10
HCPL-J456
TA = 25°C
6,8,10
HCPL-4506
5000
Option020
HCNW4506
Resistance
RI-O
(Input-Output)
HCPL-4506
1012
HCPL-J456
Ω
HCPL-0466
HCNW4506
Capacitance
CI-O
(Input-Output)
3750
5000
1012
6,9,
15
6,9,10
VI-O = 500 Vdc
6
f = 1 MHz
6
1013
HCPL-4506
HCPL-0466
0.6
HCPL-J456
0.8
HCNW4506
0.5
pF
*All typical values at 25°C, VCC = 15 V.
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Table (if applicable), your
equipment level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.
Notes:
1. Derate linearly above 90°C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 90°C free-air temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 90°C free-air temperature at a rate of 3.0 mW/°C.
4. Derate linearly above 90°C free-air temperature at a rate of 4.2 mW/°C.
5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO) to the forward LED input current (IF) times 100.
6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7. In accordance with UL 1577, each optocoupler is proof tested by apply­ing an insulation test voltage ≥4500 V rms for 1 second (leakage
detection current limit, II-O ≤5 µA).
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (leakage
detection current limit, Ii-o ≤ 5 µA).
9. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
10. This test is performed before the 100% Production test shown in the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Table, if applicable.
11. Pulse: f = 20 kHz, Duty Cycle = 10%.
12. The internal 20 kΩ resistor can be used by shorting pins 6 and 7 together.
13. Due to tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved
by using an external 20 kΩ 1% load resistor. For more information on how propagation delay varies with load resistance, see Figure 8.
14. The RL = 20 kΩ, CL = 100 pF load represents a typical IPM (Intelligent Power Module) load.
15. See Option 020 data sheet for more information.
16. Use of a 0.1 µF bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise.
17. The difference between tPLH and tPHL between any two devices under the same test condition. (See IPM Dead Time and Propagation Delay
Specifications section.)
18. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that
the output will remain in a Logic High state (i.e., VO > 3.0 V).
19. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that
the output will remain in a Logic Low state (i.e., VO < 1.0 V).
20. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given device.
14
NORMALIZED OUTPUT CURRENT
IO – OUTPUT CURRENT – mA
8
6
4
VO = 0.6 V
2
0
100 °C
25 °C
-40 °C
0
5
10
15
1.00
0.95
0.90
IF = 10 mA
VO = 0.6 V
0.85
0.80
-40
20
-20
20
0
40
60
80
100
TA – TEMPERATURE – °C
IF – FORWARD LED CURRENT – mA
IOH – HIGH LEVEL OUTPUT CURRENT – µA
1.05
10
20.0
VF = 0.8 V
VCC = VO = 4.5 V OR 30 V
15.0
4.5 V
30 V
10.0
5.0
0
-40
-20
0
20
40
60
80
TA – TEMPERATURE – °C
Figure 2. Normalized output current vs. temperature.
Figure 1. Typical transfer characteristics.
Figure 3. High level output current vs.
temperature.
HCPL-4506 fig 6
HCPL-4506 fig 5
HCPL-4506 fig 7
IF – FORWARD CURRENT – mA
IF – INPUT FORWARD CURRENT – mA
HCPL-4506/0466
1000
TA = 25°C
100
IF
+
10
VF
–
1.0
0.1
0.01
0.001
1.10
1.20
1.30
1.40
1.50
1.60
TA = 25 °C
10
IF
0.1
0.01
0.001
0.8
–
1.0
1.2
1.4
1.6
1.8
2.0
Figure 5. HCPL-J456 and HCNW4506 input current vs. forward voltage.
HCPL-4506 fig 9
HCPL-4506 fig 8
+
VF
–
VF – INPUT FORWARD VOLTAGE – V
Figure 4. HCPL-4506 and HCPL-0466 input current vs. forward voltage.
IF(ON) =10 mA
+
1
VF – FORWARD VOLTAGE – VOLTS
1
HCPL-J456/HCNW4506
100
8
2
20 kΩ
0.1 µF
20 kΩ
+
–
7
If
VCC = 15 V
5V
3
6
tf
VO
VOUT
C L*
4
SHIELD
15
90%
90%
10%
10%
VTHHL
5
*TOTAL LOAD CAPACITANCE
Figure 6. Propagation delay test circuit.
tr
HCPL-4506 fig 10
tPHL
tPLH
VTHLH
100
1
IF
VCM
8
0.1 µF
20 kΩ
2
δV = VCM
δt
∆t
20 kΩ
7
+
–
A
B
3
6
OV
VCC = 15 V
∆t
VOUT
100 pF*
4
+
VFF
VO
5
SHIELD
*100 pF TOTAL
CAPACITANCE
–
VCC
SWITCH AT A: IF = 0 mA
VO
VOL
SWITCH AT B: IF = 10 mA
–
+
VCM = 1500 V
Figure 7. CMR test circuit. Typical CMR waveform.
400
IF = 10 mA
VCC = 15 V
CL = 100 pF
RL = 20 kΩ (EXTERNAL)
200
100
-40
-20
0
20
40
60
80
IF = 10 mA
VCC = 15 V
CL = 100 pF
RL = 20 kΩ
500
(INTERNAL)
tPLH
tPHL
400
300
200
100
-40
100
TA – TEMPERATURE – °C
HCPL-4506 fig 12
800
200
100
200
300
400
500
CL – LOAD CAPACITANCE – pF
Figure 11. Propagation delay vs. load capacitance.
HCPL-4506 fig 15
16
80
400
tPLH
tPHL
200
0
100
20
10
800
400
200
5
10
15
20
25
30
VCC – SUPPLY VOLTAGE – V
Figure 12. Propagation delay vs. supply voltage.
HCPL-4506 fig 16
40
50
Figure 10. Propagation delay vs. load resistance.
HCPL-4506 fig 14
500
600
0
30
RL – LOAD RESISTANCE – kΩ
IF = 10 mA
CL = 100 pF
RL = 20 kΩ
TA = 25°C
tPLH
tPHL
1000
400
0
60
600
HCPL-4506 fig 13
1200
600
0
40
Figure 9. Propagation delay with internal 20 kΩ
RL vs. temperature.
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns
1000
20
1400
IF = 10 mA
VCC = 15 V
RL = 20 kΩ
TA = 25°C
tPLH
tPHL
1200
0
IF = 10 mA
VCC = 15 V
CL = 100 pF
TA = 25 °C
TA – TEMPERATURE – °C
Figure 8. Propagation delay with external 20 kΩ
RL vs. temperature.
1400
-20
tP – PROPAGATION DELAY – ns
300
800
tP – PROPAGATION DELAY – ns
tPLH
tPHL
600
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns
HCPL-4506 fig 11b
HCPL-4506 fig 11a
500
tPLH
tPHL
400
VCC = 15 V
CL = 100 pF
RL = 20 kΩ
TA = 25°C
300
200
100
0
5
10
15
20
IF – FORWARD LED CURRENT – mA
Figure 13. Propagation delay vs. input current.
HCPL-4506 fig 17
PS (mW)
IS (mA) FOR HCPL-4506
OPTION 060
IS (mA) FOR HCPL-J456
700
600
500
400
300
(230)
200
100
0
0
25
50
75 100 125 150 175 200
OUTPUT POWER – PS, INPUT CURRENT – IS
OUTPUT POWER – PS, INPUT CURRENT – IS
HCPL-4506 OPTION 060/HCPL-J456
800
HCPL-0466 OPTION 060/HCNW4506
1000
PS (mW) FOR HCNW4506
IS (mA) FOR HCNW4506
PS (mW) FOR HCPL-0466
OPTION 060
IS (mA) FOR HCPL-0466
OPTION 060
900
800
700
600
500
400
300
200
(150)
100
0
0
25
50
75
100 125 150 175
TS – CASE TEMPERATURE – °C
TS – CASE TEMPERATURE – °C
Figure 14. Thermal derating curve, dependence of safety limiting value with case temperature per
IEC/EN/DIN EN 60747-5-2.
HCPL-4504 fig 18b
HCPL-4506 fig 18a
1
8
0.1 µF
20 kΩ
+5 V
310 Ω
2
+
– VCC = 15 V
7
3
1
20 kΩ
6
2
VOUT
CMOS
3
100 pF
4
SHIELD
4
*100 pF TOTAL
CAPACITANCE
2
CLEDP
7
CLED01
3
4
CLEDN
SHIELD
310 Ω
6
1
5
7
6
CLEDN
5
SHIELD
8
0.1 µF
20 kΩ
2
7
3
6
4
5
CMOS
Figure 17. Optocoupler input to output capaciHCPL-4506 fig 21-new
tance model
for shielded optocouplers.
17
+5 V
20 kΩ
CLED02
20 kΩ
Figure 16. Optocoupler input to output capacitance
20-new
model forHCPL-4506
unshieldedfig
optocouplers.
HCPL-4506 fig 19-new
8
CLEDP
5
Figure 15. Recommended LED drive circuit.
1
8
20 kΩ
+
– VCC = 15 V
VOUT
100 pF
SHIELD
*100 pF TOTAL
CAPACITANCE
HCPL-4506
fig 22-new
Figure 18. LED drive circuit with resistor
connected
to LED anode (not recommended).
1
1
ITOTAL*
310 Ω
8
ICLEDP
2
3
IF
20
kΩ
CLED02
CLEDP
7
CLEDN
4
+ VR** –
100 pF
5
SHIELD
CLED02
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
3
CLEDN
4
6
5
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
PERFORMANCE. VR < VF (OFF) DURING +dVCM/dt.
+
–
–
VCM
VCM
Figure 19. AC equivalent circuit for Figure 18 during common mode
transients.
HCPL-4506 fig 23-new
HCPL-4506 fig 24-new
Figure 20. AC equivalent circuit for Figure 15 during common mode
transients.
1
2
1
8
+5 V
20 kΩ
2
3
6
5
CLED02
20 kΩ
7
CLEDN
6
VOUT
100 pF
SHIELD
5
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dVCM/dt TRANSIENTS.
+
–
SHIELD
CLEDP
ICLEDN*
7
3
8
20
kΩ
CLED01
Q1
4
4
VOUT
100 pF
SHIELD
+
Q1
20 kΩ
7
ICLEDN*
VOUT
6
CLEDP
CLED01
310 Ω
CLED01
ICLED01
2
20 kΩ
8
20
kΩ
VCM
Figure 21. Not recommended open collector LED
drive circuit.
HCPL-4506 fig 25-new
1
8
+5 V
20 kΩ
2
7
3
6
4
SHIELD
Figure 23. Recommended LED drive circuit for
ultra high CMR.
HCPL-4506 fig 27
18
5
Figure 22. AC Equivalent circuit for Figure 21 during common mode
transients.
HCPL-4506 fig 26-new
HCPL-4506
1
I
+5 V
LED1
310 Ω
8
20 kΩ
2
VCC1
0.1 µF
3
6
4
5
IPM
20 kΩ
7
+HV
VOUT1
CMOS
Q1
SHIELD
Q2
HCPL-4506
1
I
+5 V
LED2
310 Ω
M
8
20 kΩ
2
VCC2
0.1 µF
3
6
4
5
-HV
HCPL-4506
20 kΩ
7
HCPL-4506
VOUT2
CMOS
HCPL-4506
HCPL-4506
HCPL-4506
SHIELD
Figure 24. Typical application circuit.
HCPL-4506 fig 28
ILED1
VOUT1
VOUT2
ILED1
VOUT1
VOUT2
ILED2
Q1 ON
Q2 OFF
Q2 ON
tPLH
MIN.
Q2 ON
PDD*
MAX.
tPLH
MAX.
tPHL
MIN.
tPHL
MAX.
MAX.
DEAD TIME
tPLH MAX.
tPHL
MIN.
PDD* MAX. =
(tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
HCPL-4506 fig 29
Figure 25. Minimum LED skew for zero dead time.
19
Q2 OFF
Q1 OFF
ILED2
Q1 OFF
Q1 ON
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
= (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.)
= (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.)
= PDD* MAX. - PDD* MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
HCPL-4506 fig 30
Figure 26. Waveforms for dead time calculation.
LED Drive Circuit Considerations for Ultra High CMR Performance
Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupl­-ing from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 16. The HCPL-4506
series improve CMR performance by using a detector
IC with an optically transparent Faraday shield, which
diverts the capaci­tively coupled current away from the
sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and the
opto­coupler output pins and output ground as shown in
Figure 17. This capacitive coupling causes perturbations
in the LED current during common mode transients and
becomes the major source of CMR failures for a shielded
opto­coupler. The main design objective of a high CMR
LED drive circuit becomes keeping the LED in the proper
state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 15),
can achieve 15 kV/µs CMR while minimizing component
com­plexity. Note that a CMOS gate is recommended in
Figure 15 to keep the LED off when the gate is in the high
state.
Another cause of CMR failure for a shielded optocoupler
is direct coupling to the optocoupler output pins through
CLEDO1 and CLEDO2 in Figure 17. Many factors influence
the effect and magni­tude of the direct coupling including: the use of an internal or external output pull-up resistor, the position of the LED current setting resistor, the
connection of the unused input package pins, and the
value of the capacitor at the optocoupler output (CL).
Techniques to keep the LED in the proper state and minimize the effect of the direct coupling are discussed in the
next two sections.
CMR with the LED On (CMRL )
A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so
that it is not pulled below the threshold during a transient. The recommended minimum LED current of 10 mA
provides adequate margin over the maximum ITH of
5.0 mA (see Figure 1) to achieve 15 kV/µs CMR. Capacitive
coupling is higher when the internal load resistor is used
(due to CLEDO2) and an IF = 16 mA is required to obtain
10 kV/µs CMR.
The placement of the LED current setting resistor effects
the ability of the drive circuit to keep the LED on during transients and interacts with the direct coupling to
the optocoupler output. For example, the LED resistor in
Figure 18 is connected to the anode. Figure 19 shows the
AC equivalent circuit for Figure 18 during common mode
transients. During a +dVcm/dt in Figure 19, the current
available at the LED anode (Itotal) is limited by the series
resistor. The LED current (IF) is reduced from its DC value
by an amount equal to the current that flows through
20
CLEDP and CLEDO1. The situation is made worse because
the current through CLEDO1 has the effect of trying to pull
the output high (toward a CMR failure) at the same time
the LED current is being reduced. For this reason, the
recommended LED drive circuit (Figure 15) places the
current setting resistor in series with the LED cathode.
Figure 20 is the AC equivalent circuit for Figure 15 during
common mode transients. In this case, the LED current
is not reduced during a +dVcm/dt transient because the
current flowing through the package capacitance is supplied by the power supply. During a ‑dVcm/dt transient,
however, the LED current is reduced by the amount of
current flowing through CLEDN. But, better CMR performance is achieved since the current flowing in CLEDO1
during a negative transient acts to keep the output low.
Coupling to the LED and output pins is also affected by
the con­nec­tion of pins 1 and 4. If CMR is limited by perturbations in the LED on current, as it is for the recommended drive circuit (Figure 15), pins 1 and 4 should be
connected to the input circuit common. However, if CMR
performance is limited by direct coupling to the output
when the LED is off, pins 1 and 4 should be left unconnected.
CMR with the LED Off (CMRH)
A high CMR LED drive circuit must keep the LED off
(VF ≤ VF(OFF)) during common mode transients. For example, during a +dVcm/dt transient in Figure 20, the
current flowing through CLEDN is supplied by the parallel
combination of the LED and series resistor. As long as the
voltage developed across the resistor is less than VF(OFF)
the LED will remain off and no common mode failure will
occur. Even if the LED momentarily turns on, the 100 pF
capacitor from pins 6-5 will keep the output from dipping below the threshold. The recommended LED drive
circuit (Figure 15) provides about 10 V of margin between
the lowest optocoupler output voltage and a 3 V IPM
threshold during a 15 kV/µs transient with VCM = 1500 V.
Additional margin can be obtained by adding a diode
in parallel with the resistor, as shown by the dashed line
con­nec­tion in Figure 20, to clamp the voltage across the
LED below VF(OFF).
Since the open collector drive circuit, shown
in Figure 21, cannot keep the LED off during
a +dVcm/dt transient, it is not desirable for applications
requiring ultra high CMRH performance. Figure 22 is the
AC equivalent circuit for Figure 21 during common mode
transients. Essentially all the current flowing through
CLEDN during a +dVcm/dt transient must be supplied by
the LED. CMRH failures can occur at dV/dt rates where
the current through the LED and CLEDN exceeds the input
threshold. Figure 23 is an alternative drive circuit which
does achieve ultra high CMR performance by shunting
the LED in the off state.
IPM Dead Time and Propagation Delay Specifications
The HCPL-4506 series include a Propa­gation Delay Difference specifica­tion intended to help designers minimize
“dead time” in their power inverter designs. Dead time is
the time period during which both the high and low side
power transistors (Q1 and Q2 in Figure 24) are off. Any
overlap in Q1 and Q2 conduc­tion will result in large currents flow­ing through the power devices between the
high and low voltage motor rails.
To minimize dead time the designer must consider the
propa­ga­tion delay characteristics of the optocoupler
as well as the charac­teristics of the IPM IGBT gate drive
circuit. Considering only the delay characteristics of the
opto­coupler (the characteristics of the IPM IGBT gate
drive circuit can be analyzed in the same way) it is important to know the mini­mum and maximum turn-on (tPHL)
and turn-off (tPLH) propagation delay specifications, preferably over the desired operating temperature range.
The limiting case of zero dead time occurs when the input to Q1 turns off at the same time that the input to
Q2 turns on. This case determines the minimum delay between LED1 turn-off and LED2 turn-on, which
is related to the worst case optocoupler propaga­tion
delay waveforms, as shown in Figure 25. A minimum
dead time of zero is achieved in Figure 25 when the
signal to turn on LED2 is delayed by (tPLH max - tPHL
min) from the LED1 turn off. Note that the propagation
For product information and a complete list of distributors, please go to our website:
delays used to calculate PDD are taken at equal temperatures since the opto­couplers under consideration
are typically mounted in close proximity to each other.
(Specifically, tPLH max and tPHL min in the previous equation are not the same as the tPLH max and tPHL min, over the
full operating temperature range, specified in the data
sheet.) This delay is the maximum value for the propaga­
tion delay differ­ence specification which is specified at
450 ns for the HCPL-4506 series over an operating temperature range of ‑40°C
to 100°C.
­
Delaying the LED signal by the maximum propagation
delay dif­ference ensures that the mini­mum dead time
is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time occurs in the highly unlikely case where one opto­coupler
with the fastest tPLH and another with the slowest tPHL
are in the same inverter leg. The maximum dead
time in this case becomes the sum of the spread
in the tPLH and tPHL propagation delays as shown in Figure 26.
The maximum dead time is also equivalent to the difference between the maximum and mini­mum propagation
delay difference specifications. The maximum dead time
(due to the optocoup­lers) for the HCPL-4506 series is
600 ns (= 450 ns - (-150 ns) ) over an operating temperature range of ‑40°C to 100°C.
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Data subject to change. Copyright © 2005-2008 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0551EN
AV02-1360EN - June 20, 2008
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