H Dual Channel, High CMR, High Speed, TTL Compatible Optocouplers 8 Pin DIP and SOIC-8 HCPL-2630 HCPL-0630 HCPL-2631 HCPL-0631 HCPL-4661 HCPL-0661 Technical Data Features • Available in 8 Pin DIP and SOIC-8 • Internal Shield for High Common Mode Rejection (CMR) HCPL-2631/0631: 10,000 V/ µs @ VCM = 50 V HCPL-4661/0661: 15,000 V/ µs @ VCM = 1000 V • High Density Packaging • Low Input Current Capability: 5 mA • High Speed: 10 MBd • LSTTL and TTL Compatible • Guaranteed AC and DC Performance Over Temperature: -40°C to 85°C • Recognized Under the Component Program of UL1577 (File No. E55361) for Dielectric Withstand Proof Test Voltages of 2500 Vrms, 1 Minute • 5000 Vrms, 1 Minute (Option 020) (HCPL-2630/ 2631/4661) • CSA Approved Under Component Acceptance Notice No. 5 (File No. CA 88324) (HCPL-2630/2631/ 4661) • Hermetic Equivalent Device Available (HCPL5630/31) • Surface Mount Gull Wing Option Available for 8 Pin DIP (Option 300) Outline Drawing - 8 Pin DIP 9.40 (0.370) 9.90 (0.390) 8 7 6 5 TYPE NUMBER HP 7.36 (0.290) 7.88 (0.310) YYWW PIN ONE 1.19 (0.047) MAX. 1 2 3 0.18 (0.007) 0.33 (0.013) 6.10 (0.240) 6.60 (0.260) DATE CODE XXXX 5° TYP. 4 1.78 (0.070) MAX. 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. V CC ANODE 1 1 CATHODE 1 2 7 V O1 CATHODE 2 3 6 VO2 ANODE 2 4 GND 8 5 0.65 (0.025) MAX. 2.28 (0.090) 2.80 (0.110) DIMENSIONS IN MILLIMETERS AND (INCHES). 0.76 (0.030) 1.40 (0.055) CAUTION: The small junction sizes inherent to the design of this bipolar component increase the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 2 Outline Drawing - SO-8 8 7 0.381 ± 0.076 (0.016 ± 0.003) 5 5.842 ± 0.203 (0.236 ± 0.008) XXX YWW 3.937 ± 0.127 (0.155 ± 0.005) PIN 1 ONE 6 TYPE NUMBER (LAST 3 DIGITS) 2 3 DATE CODE 4 1.270 (0.050) BSG 5.080 ± 0.005 (0.200 ± 0.005) 7° 3.175 ± 0.127 (0.125 ± 0.005) 0.432 45° X (0.017) 1.524 (0.060) 0.228 ± 0.025 (0.009 ± 0.001) LEAD COPLANARITY ± 0.051 (0.002) 0.152 ± 0.051 (0.006 ± 0.002) 0.406 MIN (0.016) "HP" IS MARKED ON THE UNDERSIDE OF THE PACKAGE DIMENSIONS IN MILLIMETERS AND (INCHES). Outline Drawing - Option 300 PIN LOCATION (FOR REFERENCE ONLY) 9.65 ± 0.25 (0.380 ± 0.010) 8 7 6 0.040 (0.0016) 0.047 (0.0019) 5 0.190 (0.0076) TYP. 6.350 ± 0.25 (0.250 ± 0.010) 0.380 ± 0.010 (0.0152 ± 0.0004) MOLDED 1 2 3 4 0.015 (0.0006) 0.025 (0.001) 0.047 (0.0019) 0.070 (0.0028) 1.780 (0.070) MAX. 1.19 (0.047) MAX. 9.65 ± 0.25 (0.380 ± 0.010) 7.62 ± 0.25 (0.300 ± 0.010) 0.255 ± 0.075 (0.010 ± 0.003) 4.19 MAX. (0.165) 1.080 ± 0.320 (0.043 ± 0.013) 0.51 ± 0.130 (0.020 ± 0.005) 0.635 ± 0.25 (0.025 ± 0.010) 12° NOM. 2.540 (0.100) BSC DIMENSIONS IN mm (IN.) TOLERANCES: xx.xx = 0.01 xx.xxx = 0.005 (unless otherwise specified) [2] [5] LEAD COPLANARITY MAXIMUM: 0.102 (0.004) 3 Description These dual channel devices are optically coupled logic gates that combine GaAsP light emitting diodes and integrated high gain photodetectors. The photons are collected in the detector by a photodiode and the current is amplified by a high gain linear amplifier that drives a Schottky clamped open collector output transistor. Each circuit is temperature, current and voltage compensated. The internal shield provides a guaranteed common mode transient immunity specification of 5000 V/µs for the HCPL2631/0631, and 10,000 V/ µs for the HCPL-4661/0661. These dual channel optocouplers are available in an 8 Pin DIP and in an industry standard SOIC-8 package. The following is a cross reference table listing the 8 Pin DIP part number and the electrically equivalent SOIC-8 part number. 8 Pin DIP HCPL-2630 HCPL-2631 HCPL-4661 SOIC-8 Package HCPL-0630 HCPL-0631 HCPL-0661 +85°C. The dual channel design minimizes PCB space. These devices are recommended for high speed logic interfacing, input/output buffering, and for use as line receivers in environments that conventional line receivers cannot tolerate. They can be used for the digital programming of machine control systems, motors and floating power supplies. The internal shield makes the HCPL-2631/0631/4661/0661 ideal for use in extremely high ground or induced noise environments. Applications • Isolation of High Speed Logic Systems • Microprocessor System Interfaces • Isolated Line Receiver • Computer-Peripheral Interfaces • Ground Loop Elimination • Digital Isolation for A/D, D/A Conversion • Power Transistor Isolation in Motor Drives Schematic ICC 1 IF1 + 8 VCC I O1 7 VF 1 VO1 – 2 3 IF2 I O2 – 6 VO2 VF 2 + 4 The SOIC-8 does not require “through holes” in a PCB. This package occupies approximately one-third the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. The unique design provides maximum ac and dc circuit isolation while achieving LSTTL and TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40°C to GND 5 HCPL-2631/0631/4661/0661 SHIELD USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 1). 4 Recommended Operation Conditions Parameter Symbol Min. Max. Units Input Current, Low Level Each Channel IFL* 0 250 µA Input Current, High Level Each Channel IFH 5 15 mA Supply Voltage, Output VCC 4.5 5.5 V Fan Out (@ RL = 1 kΩ) Each Channel N 5 TTL Loads Output Pull-up Resistor RL 330 4k Ω Operating Temperature TA -40 85 °C *The off condition can also be guaranteed by ensuring that VFL ≤ 0.8 volts. Absolute Maximum Ratings (No Derating Required up to 85°C) Storage Temperature ................................................. -55°C to +125°C Operating Temperature ............................................... -40°C to +85°C Lead Solder Temperature (8 Pin DIP) .......................... 260°C for 10 s (1.6 mm below seating plane) Average Forward Input Current (each channel, See note 2) ...................................................... 15 mA Reverse Input Voltage (each channel) .......................................... 5 V Supply Voltage – VCC (1 Minute Maximum) ................................ 7 V Output Collector Current – IO (each channel) .......................... 50 mA Output Collector Voltage – VO (each channel)** ........................... 7 V Output Collector Power Dissipation (each channel) ........... 60 mW[17] Infrared and Vapor Phase Reflow Temperature (SOIC-8 & Option #300) ............ See Thermal Profile **Selection for higher output voltages up to 20 V is available. Thermal Profile 260 240 ∆T = 145°C, 1°C/SEC 220 ∆T = 115°C, 0.3°C/SEC 200 TEMPERATURE – °C 180 160 140 120 100 80 ∆T = 100°C, 1.5°C/SEC 60 40 20 0 0 1 2 3 4 5 6 7 8 9 10 11 12 TIME – MINUTES Maximum Solder Reflow Thermal Profile. (Note: Use of non-chlorine activated fluxes is highly recommended.) 5 Electrical Characteristics Over recommended temperature (TA = -40°C to +85°C) unless otherwise specified. (See note 1.) Parameter Sym. Min. Typ.* Max. Units Test Conditions Fig. Note Input Threshold Current ITH 2.5 5.0 mA VCC = 5.5 V, IO ≥ 13 mA, VO = 0.6 V 5, 15 High Level Output Current IOH 5.5 100 µA VCC = 5.5 V, VO = 5.5 V, IF = 250 µA 2 3 0.35 0.6 V VCC = 5.5 V, IF = 5 mA, IOL (Sinking) = 13 mA 3, 5, 6, 15 3 VOL High Level Supply Current ICCH 10 15 mA VCC = 5.5 V, IF = 0 mA (Both Channels) Low Level Supply Current ICCL 13 21 mA VCC = 5.5 V, IF = 10 mA (Both Channels) 1.5 1.75 4 3 Low Level Output Voltage Input Forward Voltage 1.4 VF 1.3 BVR Input Capacitance CIN 60 Input Diode Temperature Coefficient ∆VF –––– ∆TA -1.6 Input-Output Insulation VISO 2500 VISO 5000 Input-Input Leakage Current IF = 10 mA 1.80 Input Reverse Breakdown Voltage Opt. 020** TA = 25°C V 5 V IR = 10 µA, 3 pF VF = 0, f = 1 MHz 3 mV/°C IF = 10 mA VRMS RH ≤ 50%, t = 1 min TA = 25°C 13 4, 12 4, 15 µA II-I 0.005 Resistance (Input-Input) RI-I 1011 Ω Capacitance (Input-Input) CI-I 0.03** pF RH ≤ 45% t = 5 s, VI-I = 500 V 5 5 f = 1 MHz 5 0.25*** Resistance (Input-Output) RI-O 1012 Ω RH ≤ 45% VI-O = 500 V, t = 5 s Capacitance (Input-Output) CI-O 0.6 pF f = 1 MHz *All typical values are at VCC = 5 V, TA = 25°C. **For HCPL-2630/2631/4661 only. ***For HCPL-0630/0631/0661 only. 3, 16 6 Switching Specifications Over recommended temperature (TA = -40°C to +85°C), VCC = 5 V, IF = 7.5 mA, unless otherwise specified. Parameter Symbol Device Min. Propagation Delay Time to High Output Level tPLH 20 Propagation Delay Time to Low Output Level tPHL 25 Pulse Width Distortion |tPHL-tPLH| Typ.* Max. Units 75 ns 100 ns 75 ns 100 ns 35 ns 40 ns 48 50 3.5 Test Conditions TA = 25°C TA = 25°C RL = 350 Ω CL = 15 pF Fig. Note 7, 8, 9 3, 6 7, 8, 9 3, 7 10 13 Propagation Delay Skew tPSK Output Rise Time (10-90%) tr 24 ns 11 3 Output Fall Time (90-10%) tf 10 ns 11 3 12 3, 8, 10 12 3, 9, 10 Common Mode Transient Immunity at High Output Level Common Mode Transient Immunity at Low Output Level |CMH| |CML| HCPL-2630/0630 10,000 HCPL-2631/0631 5,000 10,000 13,14 VCM = 10 V V/µs VCM = 50 V HCPL-4661/0661 10,000 15,000 VCM = 1000 V HCPL-2630/0630 10,000 VCM = 10 V HCPL-2631/0631 5,000 10,000 HCPL-4661/0661 10,000 15,000 V/µs VCM = 50 V VCM = 1000 V VO(MIN) = 2 V, RL = 350 Ω, IF = 0 mA, TA = 25°C VO(MAX) = 0.8 V, RL = 350 Ω, IF = 7.5 mA TA = 25°C *All typical values are at VCC = 5 V, TA = 25°C. Notes: 1. Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler. Total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. 2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA. 3. Each channel. 4. Measured between pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. 5. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. 6. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 7. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 8. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VOUT > 2.0 V). 9. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT < 0.8 V). 10. For sinusoidal voltages, (|dVCM|/dt)max = πfCMVCM(p-p). 11. As illustrated in Figure 15 the VCC and GND traces can be located between the input and the output leads to provide additional noise immunity at the compromise of insulation capability. 12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 VRMS for 1 second (Leakage detection current limit, II-O ≤ 5 µA). 13. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information. 14. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the operating condition range. 15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 VRMS for 1 second (Leakage detection current limit, II-O ≤ 5 µA). This option is valid for HCPL-2630/2631/4661 only. 16. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. 17. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package. 7 V CC = 5.5 V V O = 5.5 V I F = 250 µA 10 5 1000 0.5 V CC = 5.5 V I F = 5.0 mA 0.4 I O = 12.8 mA I O = 16 mA 0.3 I O = 6.4 mA 0.2 -60 -40 -20 0 20 40 80 60 -60 100 -40 TA – TEMPERATURE – °C 20 IF TA = 25°C + VF _ 10 1.0 0.1 40 60 80 0.001 1.1 100 1.2 TA – TEMPERATURE – °C Figure 2. High Level Output Current vs. Temperature. 1.3 I OL– LOW LEVEL OUTPUT CURRENT – mA 5 4 RL = 350Ω 3 R L = 1KΩ 2 R L = 4KΩ 1 1 0 2 3 4 6 5 V CC = 5.0 V V OL = 0.6 V 60 I F = 10 mA, 15 mA 40 I F = 5.0 mA 20 0 -60 -40 I F – FORWARD INPUT CURRENT – mA -20 0 20 60 40 80 100 TA – TEMPERATURE – °C Figure 5. Output Voltage vs. Forward Input Current. Figure 6. Low Level Output Current vs. Temperature. PULSE GEN. Z O= 50 Ω t r = 5 ns +5 V IF 1 VCC 8 7 RL 2 OUTPUT VO 6 RM 4 GND 5 0.1 µF BYPASS 3 C L* *C L IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. IF = 7.50 mA INPUT IF V CC = 5.0 V I F = 7.5 mA 80 t PLH , R L = 4 KΩ t PHL , R L = 350 Ω 1 KΩ 4 KΩ 60 t PLH , R L = 1 KΩ 40 t PLH , R L = 350 Ω 20 IF = 3.75 mA 0 t PHL OUTPUT VO 100 t P – PROPAGATION DELAY – ns IN -60 t PLH -40 -20 0 20 40 60 80 TA – TEMPERATURE – °C 1.5 V Figure 7. Test Circuit for tPHL and tPLH (See Note 3). 1.5 Figure 4. Input Diode Forward Characteristic. 80 V CC = 5 V TA = 25°C 1.4 V F - FOWARD VOLTAGE - VOLTS Figure 3. Low Level Output Voltage vs. Temperature. 6 V O– OUTPUT VOLTAGE – V 0 -20 100 0.01 I O = 9.6 mA 0.1 0 0 I F - FOWARD CURRENT - mA V OL – LOW LEVEL OUTPUT VOLTAGE – V I OH – HIGH LEVEL OUTPUT CURRENT – µA 15 Figure 8. Propagation Delay vs. Temperature. 100 1.6 8 40 t PLH , R L = 4 KΩ 90 75 60 t PLH , R L = 1 KΩ t PLH , R L = 350 Ω 45 t PHL , R L = 350 Ω 1 KΩ 4 KΩ 30 7 5 9 11 30 V CC = 5.0 V I F = 7.5 mA 20 R L = 350 Ω 10 0 R L = 1 kΩ -60 15 13 V CC = 5.0 V I F = 7.5 mA R L = 4 kΩ t r , t f – RISE, FALL TIME – ns V CC = 5.0 V TA = 25°C PWD – PULSE WIDTH DISTORTION – ns t P – PROPAGATION DELAY – ns 105 -40 0 -20 20 40 60 80 300 290 R L = 4 KΩ 60 R L = 1 KΩ 40 R L = 350 Ω 20 R L = 350 Ω, 1 KΩ, 4 KΩ 0 100 -60 TA – TEMPERATURE – °C I F – PULSE INPUT CURRENT – mA Figure 9. Propagation Delay vs. Pulse Input Current. t FALL t RISE -40 0 -20 20 40 60 80 100 TA – TEMPERATURE – °C Figure 10. Pulse Width Distortion vs. Temperature. Figure 11. Rise and Fall Time vs. Temperature. IF B 1 V CC 8 +5 V 7 A 0.1 µF BYPASS 2 OUTPUT V O MONITORING NODE 6 4 GND -2.4 5 dVF/ dT – FORWARD VOLTAGE TEMPERATURE COEFFICIENT – mV/°C 3 350 Ω VCM _ + PULSE GEN. Z O = 50 Ω V CM (PEAK) V CM 0V 5V VO SWITCH AT A: I F = 0 mA CM H V O (min.) SWITCH AT B: I F = 7.5 mA VO CM L 5V 8 470 VCC2 390Ω IF 1 7 2 5 + *D1 VF – GND 1 0.1 µF BYPASS GND 2 SHIELD 1 -1.6 -1.4 1 10 100 Figure 13. Temperature Coefficient of Forward Voltage vs. Input Current. CHANNEL 1 SHOWN VCC1 -1.8 I F – PULSE INPUT CURRENT – mA Figure 12. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. 5V -2.0 -1.2 0.1 VO (max.) 0.5 V -2.2 2 *DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. Figure 14. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit. 9 I TH – INPUT THRESHOLD CURRENT – mA 6 V CC = 5.0 V V O = 0.6 V 5 ACK) GND BUS (B 4 CC R L = 350 KΩ 3 R L = 1 KΩ V BUS NT) (FRO OUTPUT 1 2 0.1µF OUTPUT 2 1 R L = 4 KΩ 0 -60 -40 -20 0 20 40 60 80 100 10 mm MAX (SEE NOTE 1) TA – TEMPERATURE – °C Figure 15. Input Threshold Current vs. Temperature. Figure 16. Recommended Printed Circuit Board Layout. Insulation Related Specifications Symbol DIP Value SOIC-8 Value Units Min. External Air Gap (Clearance) L(IO1) ≥7 ≥4 mm Measured from input terminals to output terminals Min. External Tracking Path (Creepage) L(IO2) ≥7 ≥4 mm Measured from input terminals to output tminals 0.08 0.08 mm Through insulation distance conductor to conductor 200 200 V IIIa IIIa Parameter Min. Internal Plastic Gap (Clearance) Tracking Resistance CTI Isolation Group (per DIN VDE 0110) Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 7). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data appli- Conditions DIN IEC 112/VDE 0303 Part 1 Material group (DIN VDE 0110) cations where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given H group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 17, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPHL or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 18 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 18 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tPSK specified optocouplers offers the advantages of guaranteed specifications for propagation delays, pulse-width distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges. DATA IF INPUTS 50% CLOCK 1.5 V VO IF DATA 50% OUTPUTS VO t PSK CLOCK 1.5 V t PSK Figure 17. Illustration of Propagation Delay Skew - tPSK. t PSK Figure 18. Parallel Data Transmission Example. For more information call: United States: call your local HP sales office listed in your telephone directory. Ask for a Components representative. Canada: (416) 206-4725 Europe: (49) 7031/14-0 Asia Pacific/Australia: (65) 290-6360 Japan: (81 3) 3331-6111 Printed in U.S.A. Data Subject to Change Obsoletes 5954-1031 (1/86), 5954-0960 (12/83) Copyright © 1993 Hewlett-Packard Co. 5091-9125E (12/93)