CY8CLED16P01
Powerline Communication Solution
Features
■
Powerline Communication Solution
❐ Integrated Powerline Modem PHY
❐ Frequency Shift Keying Modulation
❐ Configurable baud rates up to 2400 bps
❐ Powerline Optimized Network Protocol
❐ Integrates Data Link, Transport, and Network Layers
❐ Supports Bidirectional Half Duplex Communication
❐ 8-bit CRC Error Detection to Minimize Data Loss
2
❐ I C enabled Powerline Application Layer
2
❐ Supports I C Frequencies of 50, 100, and 400 kHz
❐ Reference Designs for 110V/240V AC and 12V/24V AC/DC
Powerlines
❐ Reference Designs comply with CENELEC EN
50065-1:2001 and FCC Part 15
■ HB LED Controller
❐ Configurable Dimmers Support up to 16 Independent LED
Channels
❐ 8 to 32 Bits of Resolution per Channel
❐ PrISM™ Modulation technology to reduce radiated EMI and
Low Frequency Blinking
❐ Additional communication interfaces for lighting control such
as DALI, DMX512 etc.
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
®
■ Programmable System Resources (PSoC Blocks)
❐ 12 Rail-to-Rail Analog PSoC Blocks provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
Logic Block Diagram
❐
16 Digital PSoC Blocks provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Up to Four Full Duplex UARTs
• Multiple SPITM Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Flexible On-Chip Memory
❐ 32 KB Flash Program Storage 50,000 Erase or Write Cycles
❐ 2 KB SRAM Data Storage
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Source on all GPIOs
❐ Pull Up, Pull Down, High Z, Strong, or Open-drain Drive
Modes on all GPIOs
❐ Up to 12 Analog Inputs on GPIO
❐ Configurable Interrupt on all GPIO
■
Additional System Resources
2
❐ I C Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■
Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full Featured In-Circuit Emulator (ICE) and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KB Trace Memory
❐ Complex Events
❐ C Compilers, Assembler, and Link
Powerline Communication Solution
Powerline
Network Protocol
Physical Layer
FSK Modem
PLC Core
Programmable
System Resources
Modulation
Technology
Digital and Analog
Peripherals
PrISM, PWM etc.
Additional System
Resources
Additional
Communication
Interface
MAC, Decimator, I2C,
SPI, UART etc.
PSoC Core
DALI, DMX512
CY8CLED16P01
Embedded Application
HB LED
Controller
Powerline Transceiver Packet
AC/DC Powerline Coupling Circuit
(110V/240V AC, 12V/24V AC/DC etc.)
Powerline
Cypress Semiconductor Corporation
Document Number: 001-49263 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600
Revised June 17, 2011
CY8CLED16P01
1. Contents
PLC Functional Overview ................................................ 3
Robust Communication using Cypress’s PLC Solution 3
Powerline Modem PHY ............................................... 3
Network Protocol ......................................................... 4
High Brightness (HB) LED Controller ............................. 8
LED Dimming Modulation ............................................ 8
Color Mixing Algorithm ................................................ 9
LED Temperature Compensation ................................ 9
ColorLock Algorithm .................................................... 9
Digital Communication .............................................. 10
Other Functions ......................................................... 10
PSoC Core ....................................................................... 11
Programmable System Resources ............................ 12
Additional System Resources ................................... 14
Getting Started ................................................................ 14
Application Notes ...................................................... 14
Development Kits ...................................................... 14
Training ..................................................................... 14
CYPros Consultants .................................................. 14
Solutions Library ........................................................ 14
Technical Support ..................................................... 14
Development Tools ........................................................ 15
PSoC Designer Software Subsystems ...................... 15
In-Circuit Emulator (ICE) ........................................... 15
Designing with PSoC Designer ..................................... 16
Select Components ................................................... 16
Configure Components ............................................. 16
Organize and Connect .............................................. 16
Generate, Verify, and Debug ..................................... 16
PLC User Modules .................................................... 17
Intelligent Lighting User Modules .............................. 17
Pin Information ............................................................... 18
28-Pin Part Pinout ..................................................... 18
48-Pin Part Pinout ..................................................... 19
Document Number: 001-49263 Rev. *J
100-Pin Part Pinout (On-Chip Debug) ....................... 20
Register Reference ......................................................... 22
Register Conventions ................................................ 22
Register Mapping Tables .......................................... 22
Electrical Specifications ................................................ 25
Absolute Maximum Ratings ....................................... 25
Operating Temperature ............................................. 25
DC Electrical Characteristics ..................................... 26
AC Electrical Characteristics ..................................... 35
Packaging Information ................................................... 43
Packaging Dimensions .............................................. 43
Thermal Impedances ................................................. 46
Capacitance on Crystal Pins ..................................... 46
Solder Reflow Peak Temperature ............................. 46
Development Tool Selection ......................................... 47
Software .................................................................... 47
Development Kits ...................................................... 47
Evaluation Kits ........................................................... 48
Device Programmers ................................................. 48
Ordering Information ...................................................... 49
Ordering Code Definitions ......................................... 49
Acronyms ........................................................................ 50
Acronyms Used ......................................................... 50
Reference Documents .................................................... 51
Document Conventions ................................................. 51
Glossary .......................................................................... 52
Document History Page ................................................. 57
Sales, Solutions, and Legal Information ...................... 58
Products .................................................................... 58
PSoC Solutions ......................................................... 58
Page 2 of 58
CY8CLED16P01
2. PLC Functional Overview
Figure 2-2. Physical Layer FSK Modem Block Diagram
Network Protocol
The CY8CLED16P01 is an integrated Powerline Communication
(PLC) chip with the Powerline Modem PHY and Network
Protocol Stack running on the same device. Apart from the PLC
core, the CY8CLED16P01 also offers Cypress's revolutionary
PSoC technology that enables system designers to integrate
multiple functions on the same chip.
Integrated Powerline PHY modem with optimized filters and
amplifiers to work with lossy high voltage and low voltage
powerlines.
■
Powerline optimized network protocol that supports bidirectional communication with acknowledgement-based signaling.
In case of data packet loss due to bursty noise on the powerline,
the transmitter has the capability to retransmit data.
Hysteresis
Comparator
Logic ‘1’ or
Logic ‘0’
Low Pass
Filter
External Low
Pass Filter
Modulator
Correlator
Square Wave
at FSK
Frequencies
IF Band
Pass Filter
Local
Oscillator
Mixer
Programmable
Gain Amplifier
Receiver
■
Local
Oscillator
Transmitter
Powerlines are available everywhere in the world and are a
widely available communication medium for PLC technology.
The pervasiveness of powerlines also makes it difficult to predict
the characteristics and operation of PLC products. Because of
the variable quality of powerlines around the world, implementing robust communication has been an engineering
challenge for years. The Cypress PLC solution enables secure
and reliable communications. Cypress PLC features that enable
robust communication over powerlines include:
Powerline Modem PHY
2.1 Robust Communication using Cypress’s PLC
Solution
Digital
Receiver
Digital
Transmitter
HF Band
Pass Filter
RX
Amplifier
Coupling Circuit
■
The Powerline Network Protocol also supports an 8-bit CRC
for error detection and data packet retransmission.
■
A Carrier Sense Multiple Access (CSMA) scheme is built into
the network protocol that minimizes collisions between packet
transmissions on the powerline and supports multiple masters
and reliable communication on a bigger network.
2.2 Powerline Modem PHY
Figure 2-1. Physical Layer FSK Modem
Physical Layer
FSK Modem
PLC Core
Modulation
Technology
Digital and Analog
Peripherals
PrISM, PWM etc.
Additional System
Resources
Additional
Communication
Interface
MAC, Decimator, I2C,
SPI, UART etc.
PSoC Core
DALI, DMX512
CY8CLED16P01
Embedded Application
Programmable
System Resources
HB LED
Controller
Powerline Transceiver Packet
The physical layer of the Cypress PLC solution is implemented
using an FSK modem that enables half duplex communication
on any high voltage and low voltage powerline. This modem
supports raw data rates up to 2400 bps. A block diagram is
shown in Figure 2-2.
Document Number: 001-49263 Rev. *J
Digital data from the network layer is serialized by the digital
transmitter and fed as input to the modulator. The modulator
divides the local oscillator frequency by a definite factor
depending on whether the input data is high level logic ‘1’ or low
level logic ‘0’. It then generates a square wave at 133.3 kHz (logic
‘0’) or 131.8 kHz (logic ‘1’), which is fed to the Programmable
Gain Amplifier to generate FSK modulated signals. This enables
tunable amplification of the signal depending on the noise in the
channel. The logic ‘1’ frequency can also be configured as
130.4 kHz for wider FSK deviation.
2.2.2 Receiver Section
Powerline Communication Solution
Powerline
Network Protocol
2.2.1 Transmitter Section
The incoming FSK signal from the powerline is input to a high
frequency (HF) band pass filter that filters out-of-band frequency
components and outputs a filtered signal within the desired
spectrum of 125 kHz to 140 kHz for further demodulation. The
mixer block multiplies the filtered FSK signals with a locally
generated signal to produce heterodyned frequencies.
The intermediate frequency (IF) band pass filters further remove
out-of-band noise as required for further demodulation. This
signal is fed to the correlator, which produces a DC component
(consisting of logic ‘1’ and ‘0’) and a higher frequency
component.
The output of the correlator is fed to a low pass filter (LPF) that
outputs only the demodulated digital data at 2400 baud and
suppresses all other higher frequency components generated in
the correlation process. The output of the LPF is digitized by the
hysteresis comparator. This eliminates the effects of correlator
delay and false logic triggers due to noise. The digital receiver
deserializes this data and outputs to the network layer for interpretation.
Page 3 of 58
CY8CLED16P01
2.2.3 Coupling Circuit Reference Design
2.3.1 CSMA and Timing Parameters
The coupling circuit couples low voltage signals from the
CY8CLED16P01 to the powerline. The topology of this circuit is
determined by the voltage on the powerline and design
constraints mandated by powerline usage regulations.
■
CSMA – The protocol provides the random selection of a period
between 85 and 115 ms (out of seven possible values in this
range). Within this period, the Band-In-Use (BIU) detector must
indicate that the line is not in use, before attempting a transmission.
■
BIU – A Band-In-Use detector, as defined under CENELEC EN
50065-1, is active whenever a signal that exceeds 86 dBVrms
anywhere in the range 131.5 kHz to 133.5 kHz is present for
at least 4 ms. This threshold can be configured for different
end-system applications not requiring CENELEC
compliance.The modem tries to retransmit after every 85 to
115 ms when the band is in use. The transmitter times out after
1.1 seconds to 3 seconds (depending on the noise on the
Powerline) and generates an interrupt to indicate that the transmitter was unable to acquire the powerline.
Cypress provides reference designs for a range of powerline
voltages including 110V/240V AC and 12V/24V AC/DC. The
CY8CLED16P01 is capable of data communication over other
AC/DC Powerlines as well with the appropriate external coupling
circuit. The 110V AC and 240V AC designs are compliant to the
following powerline usage regulations:
■
FCC Part 15 for North America
■
EN 50065-1:2001 for Europe
2.3 Network Protocol
Cypress’s powerline optimized network protocol performs the
functions of the data link, network, and transport layers in an
ISO/OSI-equivalent model.
Figure 2-3. Powerline Network Protocol
Powerline Communication Solution
Powerline
Network Protocol
Physical Layer
FSK Modem
PLC Core
Programmable
System Resources
Modulation
Technology
Digital and Analog
Peripherals
PrISM, PWM etc.
Additional System
Resources
Additional
Communication
Interface
MAC, Decimator, I2C,
SPI, UART etc.
PSoC Core
DALI, DMX512
CY8CLED16P01
Embedded Application
HB LED
Controller
Powerline Transceiver Packet
2.3.2 Powerline Transceiver Packet
The powerline network protocol defines a Powerline Transceiver
(PLT) packet structure, which is used for data transfers between
nodes across the powerline. Packet formation and data transmission across the powerline network is implemented internally
in the CY8CLED16P01.
A PLT packet is divided into a variable length header (minimum
6 bytes to maximum 20 bytes, depending on address type),
variable length payload (minimum 0 bytes to maximum 31
bytes), and a packet CRC byte.
This packet (preceded by a one byte preamble "0xAB") is then
transmitted by the powerline modem PHY and the external
coupling circuit across the powerline.
The format of the PLT packet is shown in the following table.
Table 2-1. Powerline Transceiver (PLT) Packet Structure
Byte
Offset
Bit Offset
7
The network protocol implemented on the CY8CLED16P01
supports the following features:
0x00
SA
Type
6
5
4
3
2
1
0
DA Type Service RSVD RSVD Response RSVD
Type
0x01
Destination Address
(8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical)
Master-slave or peer-to-peer network topologies
0x02
Source Address
(8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical)
Multiple masters on powerline network
0x03
Command
■
8-bit logical addressing supports up to 256 powerline nodes
0x04
■
16-bit extended logical addressing supports up to 65536
powerline nodes
0x05
■
Bidirectional half duplex communication
■
■
■
64-bit physical addressing supports up to 264 powerline nodes
■
Individual, broadcast or group mode addressing
■
Carrier Sense Multiple Access (CSMA)
■
Full control over transmission parameters
❐ Acknowledged
❐ Unacknowledged
❐ Repeated Transmit
Document Number: 001-49263 Rev. *J
Payload Length
RSVD
Seq Num
Powerline Packet Header CRC
0x06
Payload (0 to 31 Bytes)
Powerline Transceiver Packet CRC
Page 4 of 58
CY8CLED16P01
2.3.3 Packet Header
The packet header contains the first 6 bytes of the packet when
1-byte logical addressing is used. When 8-byte physical
addressing is used, the source and destination addresses each
contain 8 bytes. In this case, the header can consist of a
maximum of 20 bytes. Unused fields marked RSVD are for future
expansion and are transmitted as bit 0. Table 2-2 describes the
PLT packet header fields in detail.
Table 2-2. Powerline Transceiver (PLT) Packet Header
Field
Name
SA Type
No. of
Bits
1
DA Type
2
Service
Type
Response
1
1
Seq Num
4
Header
CRC
4
Tag
Source
Address
Type
Physical addressing: Every CY8CLED16P01 has a unique
64-bit physical address.
■
Group addressing: This is explained in the next section.
2.3.8 Group Membership
Group membership enables the user to multicast messages to
select groups. The CY8CLED16P01 supports two types of group
addressing:
■
Single Group Membership – The network protocol supports up
to 256 different groups on the network in this mode. In this
mode, each PLC node can only be part of a single group. For
example, multiple PLC nodes can be part of Group 131.
■
Multiple Group Membership – The network protocol supports
eight different groups in this mode and each PLC node can be
a part of multiple groups. For example, a single PLC node can
be a part of Group 3, Group 4, and Group 7 at the same time.
Description
0 – Logical Addressing
1 – Physical Addressing
00 – Logical Addressing
Destination
01 – Group Addressing
Address
10 – Physical Addressing
Type
11 – Invalid
0 – Unacknowledged Messaging
1 – Acknowledged Messaging
Response 0 - Not an acknowledgement or
response packet
1 - Acknowledgement or response
packet
4-bit unique identifier for each
Sequence packet between source and destiNumber
nation.
4-bit CRC value. This enables the
receiver to suspend receiving the
rest of the packet if its header is
corrupted
2.3.4 Payload
The packet payload has a length of 0 to 31 bytes. Payload
content is user defined and can be read or written through I2C.
2.3.5 Packet CRC
The last byte of the packet is an 8-bit CRC value used to check
packet data integrity. This CRC calculation includes the header
and payload portions of the packet and is in addition to the
powerline packet header CRC.
2.3.6 Sequence Numbering
The sequence number is increased for every new unique packet
transmitted. If in acknowledged mode and an acknowledgment
is not received for a given packet, that packet will be re-transmitted (if TX_Retry > 0) with the same sequence number. If in
unacknowledged mode, the packet will be transmitted (TX_Retry
+ 1) times with the same sequence number.
If the receiver receives consecutive packets from the same
source address with the same sequence number and packet
CRC, it does not notify the host of the reception of the duplicate
packet. If in acknowledged mode, it still sends an acknowledgment so that the transmitter knows that the packet was
received.
2.3.7 Addressing
The CY8CLED16P01 has three modes of addressing:
■
■
Logical addressing: Every CY8CLED16P01 node can have
either a 8-bit logical address or a 16-bit logical address. The
logical address of the PLC Node is set by the local application
or by a remote node on the Powerline.
Document Number: 001-49263 Rev. *J
Both of these membership modes can also be used together for
group membership. For example, a single PLC node can be a
part of Group 131 and also multiple groups such as Group 3,
Group 4, and Group 7.
The group membership ID for broadcasting messages to all
nodes in the network is 0x00.
The service type is always set to Unacknowledgment Mode in
Group Addressing Mode. This is to avoid acknowledgment
flooding on the powerline during multicast.
2.3.9 Remote Commands
In addition to sending normal data over the Powerline, the
CY8CPLC10 can also send (and request) control information to
(and from) another node on the network. The type of remote
command to transmit is set by the TX_CommandID register and
when received, is stored in the RX_CommandID register.
When a control command (Command ID = 0x01 - 0x08 and 0x0C
- 0x0F) is received, the protocol will automatically process the
packet (if Lock_Configuration is '0'), respond to the initiator, and
notify the host of the successful transmission and reception.
When the send data command (ID 0x09) or request for data
command (ID 0x0A) is received, the protocol will reply with an
acknowledgment packet (if TX_Service_Type = '1'), and notify
the host of the new received data. If the initiator doesn't receive
the acknowledgment packet within 500ms, it will notify the host
of the no acknowledgment received condition.
When a response command (ID 0x0B) is received by the initiator
within 1.5s of sending the request for data command, the
protocol will notify the host of the successful transmission and
reception. If the response command is not received by the
initiator within 1.5s, it will notify the host of the no response
received condition.
The host is notified by updating the appropriate values in the
INT_Status register (including Status_Value_Change).
The command IDs 0x30-0xff can be used for custom commands
that would be processed by the external host (e.g. set an LED
color, get a temperature/voltage reading). The available remote
commands are described in Table 2-3 on page 6 with the
respective Command IDs.
Page 5 of 58
CY8CLED16P01
Table 2-3. Remote Commands
Cmd ID
Command Name
Description
Payload (TX Data)
Response (RX Data)
0x01
SetRemote_TXEnable
Sets the TX Enable bit in the 0 - Disable Remote TX
PLC Mode Register. Rest of the 1 - Enable Remote TX
PLC Mode register is
unaffected
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
0x03
SetRemote_ExtendedAddr
Set the Addressing to
Extended Addressing Mode
0 - Disable Extended
Addressing
1 - Enable Extended
Addressing
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
0x04
SetRemote_LogicalAddr
Assigns the specified logical
address to the remote PLC
node
If Ext Address = 0,
Payload = 8-bit Logical
Address
If Ext Address = 1,
Payload = 16-bit
Logical Address
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
0x05
GetRemote_LogicalAddr
Get the Logical Address of the None
remote PLC node
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
{If Ext Address = 0,
Response = 8-bit Logical
Address
If Ext Address = 1, Response
= 16-bit Logical Address}
0x06
GetRemote_PhysicalAddr
Get the Physical Address of the None
remote PLC node
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
Response = 64-bit Physical
Address
0x07
GetRemote_State
Request PLC_Mode Register
content from a Remote PLC
node
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
Response = Remote PLC
Mode register
0x08
GetRemote_Version
Get the Version Number of the None
Remote Node
If TX Enable = 0, Response =
None
If TX Enable = 1, Response =
Remote Version register
0x09
SendRemote_Data
Transmit data to a Remote
Node.
Payload = Local TX
Data
If Local Service Type = 0,
Response = None
If Local Service Type = 1,
Response = Ack
0x0A
RequestRemote_Data
Request data from a Remote
Node
Payload = Local TX
Data
If Local Service Type = 1,
Response = Ack
Then, the remote node host
must send a
ResponseRemote_Data
command. The response must
be completely transmitted
within 1.5s of receiving the
request. Otherwise, the
requesting node will time out.
0x0B
ResponseRemote_Data
Transmit response data to a
Remote Node.
Payload = Local TX
Data
None
0x0C
SetRemote_BIU
Enables/Disables BIU function- 0 - Enable Remote BIU If Remote Lock Config = 0,
ality at the remote node
1 - Disable Remote BIU Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
Document Number: 001-49263 Rev. *J
None
Page 6 of 58
CY8CLED16P01
Table 2-3. Remote Commands (continued)
Cmd ID
Command Name
Description
Payload (TX Data)
SetRemote_ThresholdValue
0x0E
SetRemote_GroupMembership Sets the Group Membership of Byte0 - Remote SIngle
the Remote node
Group Membership
Address
Byte1- Remote Multiple
Group Membership
Address
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
0x0F
GetRemote_GroupMembership Gets the Group Membership of None
the Remote node
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
Response =
Byte0 - Remote SIngle Group
Membership Address
Byte1- Remote Multiple Group
Membership Address
0x10 0x2F
Reserved
0x30 0xFF
User Defined Command Set
Document Number: 001-49263 Rev. *J
Sets the Threshold Value at the 3-bit Remote
Remote node
Threshold Value
Response (RX Data)
0x0D
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
Page 7 of 58
CY8CLED16P01
3. High Brightness (HB) LED Controller
3.1 LED Dimming Modulation
Figure 3-1. CY8CLED16P01: HB LED Controller
The LED Dimming modulators are an important part of any HB
LED application. All EZ-Color controllers are capable of three
primary types of LED dimming modulations. These are:
Powerline Communication Solution
Programmable
System Resources
Powerline
Network Protocol
Physical Layer
FSK Modem
PLC Core
Modulation
Technology
Digital and Analog
Peripherals
PrISM, PWM etc.
Additional System
Resources
Additional
Communication
Interface
MAC, Decimator, I2C,
SPI, UART etc.
PSoC Core
DALI, DMX512
CY8CLED16P01
Embedded Application
HB LED
Controller
■
Pulse Width Modulation (PWM)
■
Precise Illumination Signal Modulation (PrISM)
■
Delta Sigma Modulated PWM (DSPWM)
PWM is among the most commonly used and conventional
methods of modulation. It is straightforward to use and effective
in practice. There are two additional techniques of modulation
supported by EZ-Color that are superior to using the PWM alone:
■
Powerline Transceiver Packet
PrISM is a modulation technique that is developed and
patented by Cypress. It results in reduced EMI as compared to
the PWM technique while still providing adequate dimming
control for LEDs.
■
The HB LED Controller is based on Cypress's EZ-Color™
technology. EZ-Color offers the ideal control solution for high
brightness (HB) LED applications requiring intelligent dimming
control. EZ-Color devices combine the power and flexibility of
PSoC (Programmable System-on-Chip) with Cypress's PrISM™
(Precise Illumination Signal Modulation) modulation technology
providing lighting designers a fully customizable and integrated
lighting solution platform.
The CY8CLED16P01 supports up to 16 independent LED
channels with up to 32 bits of resolution per channel, giving
lighting designers the flexibility to choose the LED array size and
color quality. PSoC Designer software, with lighting-specific user
modules, significantly cuts development time and simplifies
implementation of fixed color points through temperature and
LED binning compensation. EZ-Color's virtually limitless analog
and digital customization enable simple integration of features in
addition to intelligent lighting, such as battery charging, image
stabilization, and motor control during the development process.
These features, along with Cypress's best-in-class quality and
design support, make EZ-Color the ideal choice for intelligent HB
LED control applications.
The list of functions that EZ-Color devices implement are:
■
LED Dimming Modulation
■
Pulse Density Modulation Techniques
❐ DMX512
❐ DALI
■
Digital Communication for Lighting
■
LED Temperature Compensation
■
3- and 4-Channel Color Mixing
❐ Including LED Binning Compensation
■
Optical Feedback Algorithms
Document Number: 001-49263 Rev. *J
The Delta Sigma Modulated PWM technique provides higher
resolution while using the same hardware resources as a
conventional PWM.
LED dimming modulators use digital block resources. Digital
blocks are configurable 8-bit digital peripherals. There are two
types of digital blocks in the CY8CLED16P01: basic and communication. Usually, there are equal numbers of each. Any communication functions must be implemented using communication
blocks but basic, noncommunication functions are implemented
using either kind of block.
PWM and DSPWM modulators can have a dimming resolution
of up to 16 bits. A PrISM modulator can theoretically have a
dimming resolution of up to 32 bits, but the maximum recommended resolution for these modulators is 13 bits. This is
because the output signal of a PrISM modulator has a frequency
output range that increases with the resolution of the modulator.
This increase in frequency output range is undesirable as it goes
beyond the switching frequency of the current driver. Therefore,
a resolution of 13 bits or lower is recommended for a PrISM
modulator. Refer to application note AN47372, PrISM
Technology for LED Dimming on http://www.cypress.com, for
details.
To determine the number of digital blocks used by one PWM or
PrISM modulator, use Equation 1. Note that a partial digital block
cannot be used, so the result must always be rounded up. In
Equation 1, n is the dimming resolution of the modulator. The
resolution of dimming is determined by the color accuracy
needed for the end application.
DigBlocksPWM ,PRISM
n
8
Equation 1
Page 8 of 58
CY8CLED16P01
Equations 2 and 3 are used to determine how many digital blocks
are needed by a DSPWM. The total dimming resolution of a
DSPWM modulator is the total of the hardware PWM modulation
resolution and extra resolution added by Delta Sigma modulation
in the software. Equation 3 shows that the number of digital
blocks needed is only determined by the hardware resolution.
DigBlocksDSPWM
nHW
8
nTotal nSW nHW
Equation 2
Equation 3
These equations show that more dimming resolution is achieved
with a DSPWM modulator than with a PWM or PrISM modulator.
A DSPWM modulator requires more code space and execution
time to use.
Equations 1, 2, and 3 determine the number of digital blocks
required by one modulator. The total number of blocks for all
modulators is determined by adding up the digital blocks needed
by each modulator used in the device.
If the dimming resolution is increased, the number of digital
blocks needed should be calculated accordingly.
3.3 LED Temperature Compensation
Many HB LED systems need to measure analog signals. One or
more thermistors are often present to measure temperatures of
the system and the LEDs. The CY8CLED16P01 measures an
analog signal with an analog-to-digital converter (ADC). The
device can implement a variety of flexible ADC implementations.
The ADCs cover a wide range of resolutions and techniques and
use varied number of digital and analog block resources. For help
in selecting from this multitude of ADCs, refer to application note
AN2239, Analog – ADC Selection on http://www.cypress.com.
When designing with an EZ-Color device, the number of digital
and analog blocks used by an ADC must be factored into the total
number of digital and analog blocks that are used.
In a typical case, such as the 3-channel color mixing firmware IP
developed by Cypress, the simple 8-bit incremental ADC is used.
This module occupies one digital and one switched capacitor
analog block.
Analog blocks come in two types: continuous time and switched
capacitor blocks. The former enables continuous time functions
such as comparators and programmable gain amplifiers. The
switched capacitor blocks enable functions such as ADCs and
filters.
The CY8CLED16P01 device has a variety of LED dimming
configurations. Because it has 16 digital blocks, it can implement
eight 16-bit PWM modulators, eight 12-bit PrISM modulators, or
sixteen 12-bit DSPWM modulators (assuming the software
resolution is 4 bits). As another example, it can implement four
10-bit PrISM modulators and still have 8 digital blocks left over
to implement other digital functions.
Temperature sensors with an I2C interface can also be used
instead of raw thermistors, thereby eliminating the need for
ADCs and complicated processing.
The CY8CLED16P01 is a one-device solution for powerline
communication and HB LED control. For an application that runs
powerline communication and HB LED control simultaneously,
the CY8CLED16P01 can implement four 16-bit PWM
modulators, four 12-bit PrISM modulators, or eight 12-bit
DSPWM modulators (assuming the software resolution is 4 bits).
ColorLock functionality uses feedback from an optical sensor in
the system to adjust the LED dimming modulators correctly to
“lock on” to a target color. This is similar to the concept of temperature compensation because it compensates for change in color.
Instead of indirectly measuring change in color through temperature, it senses actual change in color and compensates for it.
3.2 Color Mixing Algorithm
The ColorLock algorithm implemented by Cypress requires the
use of 10 digital blocks. Due to a 9-bit PrISM implementation, 6
digital blocks are used for dimming as in Equation 1. A 16-bit
PWM and two 8-bit timers are also used to form the frame
generator, pulse counter, and debounce counter.
Code algorithms to implement color mixing functionality work
well with EZ-Color controllers. Color mixing algorithms convert a
set of color coordinates that specify a color into the appropriate
8-bit dimming values for the LED dimming modulators. This
enables the EZ-Color controller to be communicated on a higher
level and maintain desired color and brightness levels.
3.4 ColorLock Algorithm
The basic 3-channel color mixing firmware performing 8-bit LED
dimming requires three 8-bit dimming blocks. The discussion on
LED dimming modulation implies that it consumes three digital
blocks. The addition of a simple temperature compensation
algorithm using a thermistor consumes an additional digital block
and analog block (for the ADC).
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CY8CLED16P01
3.5 Digital Communication
Most HB LED-based lighting systems require some form of
digital communication to send and receive data to and from the
light fixtures to control them. The CY8CLED16P01 is a
one-device solution for HB LED lighting control and powerline
communication. However, the CY8CLED16P01 supports
several other data communication protocols, apart from
powerline communication. These are listed in Table 3-1. Some
of the hardware is dedicated for a protocol and does not use any
digital blocks. Some protocols use digital blocks to implement the
communication.
A DMX512 protocol receiver can be implemented using two
digital blocks. This is a standard protocol that is common in stage
and concert lighting systems. The receiver has a software
programmable address and programmable number of channels
that it can control. A typical DMX512 receiver implementation
(developed by Cypress) controlling three LED channels
consumes five digital blocks (three for the LED modulators).
Table 3-1. Digital Communication Resource Usage
Digital Blocks
Communication
Digital Blocks
DMX512 (Receiver)
2
1
DALI (Slave)
3
0
I2 C
0
0
Half Duplex UART
1
1
SPI Master or Slave
1
1
Data Protocol
Master or Slave
Apart from these specific lighting communication protocols, the
industry standard communication protocols such as I2C, UART,
and SPI can be implemented in any of the devices in the family.
As examples, SPI can be used to interface to external WUSB
devices, while I2C can be used to interface to external microcontrollers.
Table 3-1 also shows the number of digital block resources that
each type of communication block consumes.
3.6 Other Functions
The CY8CLED16P01 is capable of functions other than those
previously discussed. Most functions that can be implemented
with a standard microcontroller can be also implemented with the
CY8CLED16P01.
Similar to regular PSoC devices, the CY8CLED16P01 also has
dynamic reconfiguration ability. This is a technique that enables
the device’s digital and analog resources to be reused for
different functions that may not be available simultaneously. For
instance, consider the application to remotely control LED
color/intensity (with current feedback) over powerlines using the
CY8CLED16P01 for both PLC and LED color control. The PLC
functionality and the current feedback do not necessarily need to
happen at the same time. Therefore, the digital and analog
blocks that implement the PLC functionality can dynamically
reconfigure into resources that implement current feedback. By
doing this, the CY8CLED16P01 device gets more functionality
out of a fixed number of resources than would otherwise be
possible. The only constraint on this technique is the amount of
Flash and SRAM size required for the code to implement these
functions. For more details on dynamic reconfiguration, refer to
application note AN2104, PSoC Dynamic Reconfiguration.
DALI is another lighting communication protocol that is common
for large commercial buildings. The DALI slave can be implemented in EZ-Color consuming six digital blocks (three for the
DALI slave and three to modulate 3 LED channels). The three
blocks used to implement DALI need not be communication
blocks as the Manchester encoding is performed in the software.
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CY8CLED16P01
4. PSoC Core
The CY8CLED16P01 is based on the Cypress PSoC® 1 architecture. The PSoC platform consists of many Programmable
System-on-chip Controller devices. These devices are designed
to replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
and programmable interconnects. This architecture enables the
user to create customized peripheral configurations that match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable I/Os are included in a range of convenient pinouts
and packages.
The PSoC architecture, as shown in Figure 4-1., consists of four
main areas: PSoC Core, Digital System, Analog System, and
System Resources. Configurable global busing enables all the
device resources to be combined into a complete custom
system. The CY8CLED16P01 family can have up to five I/O ports
that connect to the global digital and analog interconnects,
providing access to 16 digital blocks and 12 analog blocks.
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
Figure 4-1. PSoC Architecture
Port 7 Port 6 Port 5 Port 4 Port 3 Port 2
Port 1 Port 0
Analog
Drivers
SYSTEM BUS
Global Digital Interconnect
SRAM
2K
Memory encompasses 32 KB of Flash for program storage, 2 KB
of SRAM for data storage, and up to 2 KB of EEPROM emulated
using Flash. Program Flash uses four protection levels on blocks
of 64 bytes, enabling customized software IP protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 2.5
percent over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for the digital system use. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. When
operating the Powerline Transceiver (PLT) user module, the
ECO must be selected to ensure accurate protocol timing. The
clocks, together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, enabling great flexibility in external interfacing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
Global Analog Interconnect
SROM
Flash 32K
PSoC CORE
CPU Core (M8C)
Interrupt
Controller
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a 4 MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 25 vectors, to
simplify programming of realtime embedded events. Program
execution is timed and protected using the included Sleep and
Watchdog timers (WDT).
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Digital
Clocks
Two
Multiply
Accums.
Analog
Block
Array
POR and LVD
Decimator
I2 C
System Resets
Analog
Input
Muxing
Internal
Voltage
Ref.
SYSTEM RESOURCES
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CY8CLED16P01
4.1 Programmable System Resources
Figure 4-3. Digital System Block Diagram
Port 7
Figure 4-2. Programmable System Resources
Port 5
Port 6
Port 3
Port 4
Port 1
Port 2
Port 0
Powerline Communication Solution
Additional System
Resources
Additional
Communication
Interface
MAC, Decimator, I2C,
SPI, UART etc.
DALI, DMX512
PSoC Core
PLC Core
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
PrISM, PWM etc.
HB LED
Controller
Powerline Transceiver Packet
Row 0
DBB00
8
8
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to four)
■
SPI master and slave (up to four each)
2
■I C
slave and multi-master (one available as a System
Resource)
■
Row Input
Configuration
Row Input
Configuration
PWMs with Dead Band (8 to 32 bit)
Row Input
Configuration
■
Row 1
DBB10
DBB11
DCB12
8
4
DCB13
4
Row 2
DBB20
DBB21
DCB22
4
DCB23
4
Row 3
DBB30
DBB31
DCB32
4
Row Output
Configuration
PWMs (8 to 32 bit)
DCB03
Row Output
Configuration
■
DCB02
Row Output
Configuration
The digital system contains 16 digital PSoC blocks. Each block
is an 8-bit resource that can be used alone, or combined with
other blocks to form 8-, 16-, 24-, and 32-bit peripherals called
user modules. Digital peripheral configurations include:
DBB01
4
4
8
4.1.1 The Digital System
ToAnalog
System
Row Output
Configuration
Physical Layer
FSK Modem
Modulation
Technology
Digital and Analog
Peripherals
CY8CLED16P01
Programmable
System Resources
Powerline
Network Protocol
To System Bus
Digital Clocks
FromCore
Embedded Application
DCB33
4
Cyclical Redundancy Checker and Generator (8 to 32 bit)
GIE[7:0]
■
IrDA (up to 4)
GIO[7:0]
■
Pseudo Random Sequence Generators (8 to 32 bit)
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also enable signal multiplexing and perform logic operations. This configurability frees your designs from the constraints
of a fixed peripheral controller.
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CY8CLED16P01
The analog system contains 12 configurable blocks, each
containing an opamp circuit, enabling the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:
■
Analog-to-digital converters (up to 4, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2, 4, 6, or 8 pole band pass, low pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■
High current output drivers (4 with 40 mA drive as a Core
Resource)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
Figure 4-4. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
4.1.2 The Analog System
P2[3]
P2[1]
P2[6]
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
Analog blocks are provided in columns of three, which includes
one CT (continuous time) and two SC (switched capacitor)
blocks, as shown in the Figure 4-4. on page 13.
ACB00
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
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CY8CLED16P01
4.2 Additional System Resources
5. Getting Started
Figure 4-5. Additional System Resources
The quickest way to understand Cypress’s Powerline Communication offering is to read this data sheet and then use the PSoC
Designer Integrated Development Environment (IDE). The latest
version of PSoC Designer can be downloaded from
http://www.cypress.com. This data sheet is an overview of the
CY8CLED16P01 integrated circuit and presents specific pin,
register, and electrical specifications.
Powerline Communication Solution
Powerline
Network Protocol
Physical Layer
FSK Modem
PLC Core
Programmable
System Resources
Modulation
Technology
Digital and Analog
Peripherals
PrISM, PWM etc.
Additional System
Resources
Additional
Communication
Interface
MAC, Decimator, I2C,
SPI, UART etc.
DALI, DMX512
PSoC Core
CY8CLED16P01
Embedded Application
HB LED
Controller
For in depth information, along with detailed programming
details, see the PLC Technical Reference Manual.
For up to date ordering, packaging, and electrical specification
information, see the latest PLC device data sheets on the web at
http://www.cypress.com.
Application Notes
Powerline Transceiver Packet
System Resources, some of which have been previously
described, provide additional capability useful to complete
systems. Resources include a multiplier, decimator, low voltage
detection, and power on reset. The following statements
describe the merits of each system resource.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks are
generated using digital PSoC blocks as clock dividers.
■
Multiply accumulate (MAC) provides a fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are
supported.
■
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC
consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Document Number: 001-49263 Rev. *J
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CY8CLED16P01
6. Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
■
Extensive user module catalog
Debugger
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
■
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
makes it possible to change configurations at run time. In
essence, this lets you to use more than 100 percent of PSoC's
resources for an application.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
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CY8CLED16P01
7. Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
1. Select user modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each eight bits of resolution. Using these parameters, you can
establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application.
Enter values directly or by selecting values from drop-down
menus. All of the user modules are documented in datasheets
that may be viewed directly in PSoC Designer or on the Cypress
website. These user module datasheets explain the internal
operation of the user module and provide performance specifications. Each datasheet describes the use of each user module
parameter, and other information that you may need to successfully implement your design.
Document Number: 001-49263 Rev. *J
Organize and Connect
Build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in C, assembly language, or
both.
The last step in the development process takes place inside
PSoC Designer's Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint, and watch-variable
features, the debug interface provides a large trace buffer. It lets
you to define complex breakpoint events that include monitoring
address and data bus values, memory locations, and external
signals.
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CY8CLED16P01
7.1 PLC User Modules
■
Powerline Transceiver (PLT) User Module (UM) enables data
communication over powerlines up to baud rates of 2400 bps.
This UM also exposes all the APIs from the network protocol for
ease of application development. The UM, when instantiated,
provides the user with three implementation modes:
FSK Modem + Network Stack – This mode allows the user to
use the Cypress network protocol for PLC and build any application with the APIs provided by the network protocol.
■
FSK Modem + Network Stack + I2C – This mode allows the
user to interface the CY8CLEDP01 with any other microcontroller or PSoC device. Users can also split the application
between the PLC device and the external microcontroller. If the
external microcontroller is a PSoC device, then the I2C UMs
can be used to interface it with the PLC device.
■
FSK Modem Only – This mode enables the user to use the
raw FSK modem and build any network protocol or application
with the help of the APIs generated by the modem PHY.
Figure 7-1. shows the starting window for the PLT UM with the
three implementation modes from which the user can choose.
Figure 7-1. PLT User Module
Refer to the application note AN55403 - "Estimating
CY8CPLC20/CY8CLED16P01
Power
Consumption"
at
http://www.cypress.com to determine the power consumption
estimate of the CY8CLED16P01 chip with the PLT User Module,
loaded along with the other User Modules.
7.6 Intelligent Lighting User Modules
The CY8CLED16P01 has the intelligent lighting control user
modules along with the PLC user modules. These user modules
enable the user to do the following:
■
Control multiple channels, anywhere between 1 and 16.
■
Enable temperature compensation and color feedback
■
Provide algorithms for high CRI
■
Control color with 1931 or 1976 gamuts and through CCT
■
Provide additional communication interfaces such as DALI and
DMX512
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CY8CLED16P01
8. Pin Information
The CY8CLED16P01 PLC device is available in a variety of packages which are listed and illustrated in the following tables. Every
port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
8.1 28-Pin Part Pinout
Table 8-1. 28-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
Type
Digital Analog
I/O
I
Reserved
O
I/O
I
O
Pin Name
Description
P0[7]
RSVD
FSK_OUT
P0[1]
TX_SHUT
DOWN
Analog Column Mux Input
Reserved
Analog FSK Output
Analog Column Mux Input
Output to disable PLC transmit
circuitry in receive mode
Logic ‘0’ - When the Modem is transmitting
Logic ‘1’ - When the Modem is not
transmitting
6
7
8
9
10
11
12
I/O
I/O
I
I/O
I
Reserved
I/O
I/O
I/O
P2[5]
P2[3]
P2[1]
RSVD
P1[7]
P1[5]
P1[3]
13
I/O
P1[1]
14
15
I/O
Vss
P1[0]
16
17
I/O
I/O
P1[2]
P1[4]
18
19
I/O
Power
O
21
I
22
Analog Ground
23
24
25
I/O
Reserved
I/O
I/O
26
I/O
I/O
I
Power
A, I , P0[7]
RSVD
FSK_OUT
A, I , P0[1]
TX_ SHUTDOWN
P2[5]
A, I , P2[3]
A , I,P2[1]
RSVD
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
FSK_IN
P0[4] , A , IO
P0[2],A,IO
RSVD
P2[6] , External VREF
AGND
RXCOMP_IN
RXCOMP_OUT
XRES
P1[6]
P1[4] , EXTCLK
P1[2]
P1[0] , XTALout, I2C SDA
Optional External Clock Input
(EXTCLK)[2]
P1[6]
XRES
Input
20
27
28
Direct switched capacitor block input
Direct switched capacitor block input
Reserved
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
XTAL_STABILITY. Connect a 0.1 µF
capacitor between the pin and Vss.
Crystal (XTALin)[2], ISSP-SCLK[1],
I2C SCL
Ground connection.
Crystal (XTALout)[2], ISSP-SDATA[1],
I2C SDA
Figure 8-1. CY8CLED16P01 28-Pin PLC Device
Active high external reset with
internal pull down
RXCOMP_ Analog Output to external Low Pass
OUT
Filter Circuitry
RXCOMP_ Analog Input from the external Low
IN
Pass Filter Circuitry
AGND
Analog Ground. Connect a 1.0 µF
capacitor between the pin and Vss.
P2[6]
External Voltage Reference (VREF)
RSVD
Reserved
P0[2]
Analog column mux input and column
output
P0[4]
Analog column mux input and column
output
FSK_IN
Analog FSK Input
Vdd
Supply Voltage
LEGEND: A = Analog, I = Input, O = Output, and RSVD = Reserved (should be left unconnected).
Notes
1. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Technical Reference Manual for details.
2. When using the PLT user module, the external crystal is always required for protocol timing. For the FSK modem, either the PLL Mode should be enabled or the
external 24MHz on P1[4] should be selected. The IMO should not be used.
Document Number: 001-49263 Rev. *J
Page 18 of 58
CY8CLED16P01
8.2 48-Pin Part Pinout
Table 8-2. 48-Pin Part Pinout (QFN )[3]
17
18
19
I/O
Vss
P1[0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
30
31
32
33
34
I/O
I/O
I/O
I/O
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
Input
O
35
I
36
Analog Ground
37
38
39
I/O
40
41
42
43
44
45
46
47
P4[0]
P4[2]
P4[4]
P4[6]
RXCOMP_
OUT
RXCOMP_
IN
AGND
P2[6]
RSVD
Reserved
Reserved
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
XTAL_STABILITY. Connect a 1.0 µF
capacitor between the pin and Vss.
Crystal (XTALin)[2], I2C Serial Clock (SCL),
ISSP-SCLK[1]
Ground connection.
Crystal (XTALout)[2], I2C Serial Data (SDA),
ISSP-SDATA[1]
I/O
I/O
I
P0[4]
FSK_IN
Vdd
P0[7]
RSVD
FSK_OUT]
P0[1]
TX_SHUT
DOWN
Analog column mux input and column output
Analog FSK Input
Supply Voltage
Analog column mux input
Reserved
Analog FSK Output
Analog column mux input
Output to disable transmit circuitry in receive
mode
Logic ‘0’ - When the Modem is transmitting
Logic ‘1’ - When the Modem is not transmitting
I/O
O
O
I
AGND
RXCOMP_IN
RXCOMP_ OUT
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
Analog Output to external Low Pass Filter
Circuitry
Analog Input from external Low Pass Filter
Circuitry
Analog Ground. Connect a 1.0 µF capacitor
between the pin and Vss.
External Voltage Reference (VREF)
Reserved
Analog column mux input and column
output
I
QFN
( Top View)
36
35
34
33
32
31
30
29
28
27
26
25
Active high external reset with internal pull
down
P0[2]
Reserved
A , I , P2[3] 1
A , I , P2[1] 2
P4[7] 3
P4[5] 4
P4[3] 5
P4[1] 6
RSVD 7
P3[7] 8
P3[5] 9
P3[3] 10
P3[1] 11
P5[3] 12
Optional External Clock Input (EXTCLK)[2]
I/O
Power
P2[5]
TX_SHUTDOWN
P0[1], A, I
FSK_OUT
RSVD
P0[7], A, I
Direct switched capacitor block input
Direct switched capacitor block input
I/O
I/O
Figure 8-2. CY8CLED16P01 48-Pin PLC Device
Vdd
FSK_IN
P0[4], A, IO
P0[2], A, IO
RSVD
P2[6], External VREF
Description
48
47
46
45
44
43
42
41
40
39
38
37
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
RSVD
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Power
20
21
22
23
24
25
26
27
28
29
Pin Name
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
Digital
Analog
I/O
I
I/O
I
I/O
I/O
I/O
I/O
Reserved
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
P5[0]
P5[2]
Pin No.
48
I/O
P2[5]
LEGEND: A = Analog, I = Input, O = Output, and RSVD = Reserved (should be left unconnected).
Note
3. The QFN package has a center pad that must be connected to ground (Vss).
Document Number: 001-49263 Rev. *J
Page 19 of 58
CY8CLED16P01
8.3 100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8CLED16P01-OCD On-Chip Debug PLC device. Note that the OCD parts are only used for
in-circuit debugging. OCD parts are not available for production.
I/O
O
I
NC
NC
P0[1]
TX_SHUTD
OWN
No Connection
No Connection
Analog Column Mux Input
Output to disable transmit circuitry in receive
mode
Logic ‘0’ - When the Modem is transmitting
Logic ‘1’ - When the Modem is not transmitting
Pin
No.
51
52
53
54
Name
NC
P5[0]
P5[2]
P5[4]
I/O
I/O
I/O
19
I/O
P3[1]
69
I
20
I/O
P5[7]
70
Ground
21
22
23
24
25
26
27
I/O
I/O
I/O
I/O
P5[5]
P5[3]
P5[1]
P1[7]
NC
NC
NC
71
72
73
74
75
76
77
I/O
I/O
P0[2]
Analog column mux input and column
output
28
29
I/O
I/O
P1[5]
P1[3]
78
79
I/O
I/O
NC
P0[4]
30
I/O
P1[1]
No Connection
Analog column mux input and column output,
VREF
No Connection
45
46
47
48
49
50
Power
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
Vdd
NC
Vss
NC
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
NC
NC
NC
OCD even data I/O
OCD odd data output
Reserved
Ground Connection
I2C Serial Clock (SCL)
No Connection
No Connection
No Connection
I2C Serial Data (SDA)
XTAL_STABILITY. Connect a 0.1 uF capacitor
between the pin and VSS.
Crystal (XTALin)[2], I2C Serial Clock (SCL),
TC SCLK
No Connection
Supply Voltage
No Connection
Ground Connection
No Connection
Crystal (XTALout)[2], I2C Serial Data (SDA),
TC SDATA
Optional External Clock Input (EXTCLK)[2]
No Connection
No Connection
No Connection
Input
I/O
I/O
Power
I/O
I/O
O
I/O
Reserved
80
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
HCLK
CCLK
XRES
P4[0]
P4[2]
Vss
P4[4]
P4[6]
RXCOMP_OUT
No Connection
Reserved
Power
I/O
I/O
I/O
Direct switched capacitor block input
Direct switched capacitor block input
I/O
I/O
I/O
I/O
I/O
Description
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
OCDE
OCDO
RSVD
Vss
P3[7]
P3[5]
P3[3]
I
I
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Analog
Description
Digital
Name
5
6
7
8
9
10
11
12
13
14
15
16
17
18
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Analog
Pin
No.
1
2
3
4
Digital
Table 8-3. 100-Pin OCD Part Pinout (TQFP)
RXCOMP_IN
AGND
NC
P2[6]
NC
RSVD
NC
NC
NC
81
82
83
84
85
86
87
88
89
90
91
92
93
94
I
Power
Power
Power
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
95
96
97
98
99
100
I/O
I
Reserved
O
OCD high speed clock output
OCD CPU clock output
Active high pin reset with internal pull down
Ground Connection
Analog Output to external Low Pass Filter
Circuitry
Analog Input from external Low Pass Filter
Circuitry
Analog Ground. Connect a 1.0 µF capacitor
between the pin and Vss.
No Connection
External Voltage Reference (VREF) input
No Connection
Reserved
No Connection
No Connection
FSK_IN
Vdd
Vdd
Vss
Vss
P6[0]
P6[1]
P6[2]
P6[3]
P6[4]
P6[5]
P6[6]
P6[7]
NC
Analog FSK Input
Supply Voltage
Supply Voltage
Ground Connection
Ground Connection
P0[7]
NC
RSVD
NC
FSK_OUT
NC
Analog Column Mux Input
No Connection
Reserved
No Connection
Analog FSK Output
No Connection
No Connection
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, TC/TM: Test, TC/TM: Test, RSVD = Reserved (should be left unconnected).
Document Number: 001-49263 Rev. *J
Page 20 of 58
CY8CLED16P01
90 P6[4]
89 P6[3]
88 P6[2]
87 P6[1]
86 P6[0]
85 Vss
84 Vss
83 Vdd
82 Vdd
81 FSK_IN
80 NC
79 P0[4], A, IO
78 NC
77 P0[2], A, IO
76 NC
75
74
OCD TQFP
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
NC
RSVD
NC
P2[6] , External VREF
NC
AGND
RXCOMP_IN
RXCOMP_ OUT
P4[6]
P4[4]
Vss
P4[2]
P4[0]
XRES
CCLK
HCLK
P3[6]
P3[4]
P3[2]
P3[0]
P5[6]
P5[4]
P5[2]
P5[0]
NC
NC
NC
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
XTALout, I2C SDA, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
NC
54
53
52
51
26
27
28
29
30
31
32
33
34
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
I2C SDA, P1[5]
P1[3]
XTALin, I2C SCL, P1[1]
NC
Vdd
NC
Vss
NC
NC
NC
AI , P0[1]
TX_ SHUTDOWN
P2[5]
AI , P2[3]
AI , P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
OCDE
OCDO
RSVD
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
I2 C SCL, P1[7]
NC
100 NC
99 FSK_OUT
98 NC
97 RSVD
96 NC
95 P0[7], AI
94 NC
93 P6[7]
92 P6[6]
91 P6[5]
Figure 8-3. CY8CLED16P01-OCD
Not for Production
Document Number: 001-49263 Rev. *J
Page 21 of 58
CY8CLED16P01
9. Register Reference
This section lists the registers of the CY8CLED16P01 PLC
device. For detailed register information, refer to the PLC
Technical Reference Manual.
9.1 Register Conventions
The register conventions specific to this section are listed in the
following table.
Convention
R
9.2 Register Mapping Tables
The CY8CLEDP01 device has a total register address space of
512 bytes. The register space is referred to as I/O space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Description
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-49263 Rev. *J
Page 22 of 58
CY8CLED16P01
Table 9-1. Register Map Bank 0 Table: User Space
Name
Addr (0,Hex) Access Name
PRT0DR
00
RW
DBB20DR0
PRT0IE
01
RW
DBB20DR1
PRT0GS
02
RW
DBB20DR2
PRT0DM2
03
RW
DBB20CR0
PRT1DR
04
RW
DBB21DR0
PRT1IE
05
RW
DBB21DR1
PRT1GS
06
RW
DBB21DR2
PRT1DM2
07
RW
DBB21CR0
PRT2DR
08
RW
DCB22DR0
PRT2IE
09
RW
DCB22DR1
PRT2GS
0A
RW
DCB22DR2
PRT2DM2
0B
RW
DCB22CR0
PRT3DR
0C
RW
DCB23DR0
PRT3IE
0D
RW
DCB23DR1
PRT3GS
0E
RW
DCB23DR2
PRT3DM2
0F
RW
DCB23CR0
PRT4DR
10
RW
DBB30DR0
PRT4IE
11
RW
DBB30DR1
PRT4GS
12
RW
DBB30DR2
PRT4DM2
13
RW
DBB30CR0
PRT5DR
14
RW
DBB31DR0
PRT5IE
15
RW
DBB31DR1
PRT5GS
16
RW
DBB31DR2
PRT5DM2
17
RW
DBB31CR0
PRT6DR
18
RW
DCB32DR0
PRT6IE
19
RW
DCB32DR1
PRT6GS
1A
RW
DCB32DR2
PRT6DM2
1B
RW
DCB32CR0
PRT7DR
1C
RW
DCB33DR0
PRT7IE
1D
RW
DCB33DR1
PRT7GS
1E
RW
DCB33DR2
PRT7DM2
1F
RW
DCB33CR0
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
DBB00DR2
22
RW
DBB00CR0
23
#
ARF_CR
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
ASY_CR
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
DCB02DR0
28
#
DCB02DR1
29
W
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
DBB10DR0
30
#
ACB00CR3
DBB10DR1
31
W
ACB00CR0
DBB10DR2
32
RW
ACB00CR1
DBB10CR0
33
#
ACB00CR2
DBB11DR0
34
#
ACB01CR3
DBB11DR1
35
W
ACB01CR0
DBB11DR2
36
RW
ACB01CR1
DBB11CR0
37
#
ACB01CR2
DCB12DR0
38
#
ACB02CR3
DCB12DR1
39
W
ACB02CR0
DCB12DR2
3A
RW
ACB02CR1
DCB12CR0
3B
#
ACB02CR2
DCB13DR0
3C
#
ACB03CR3
DCB13DR1
3D
W
ACB03CR0
DCB13DR2
3E
RW
ACB03CR1
DCB13CR0
3F
#
ACB03CR2
Blank fields are Reserved and should not be accessed.
Document Number: 001-49263 Rev. *J
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
RW
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
MUL1_X
A8
MUL1_Y
A9
MUL1_DH
AA
MUL1_DL
AB
ACC1_DR1
AC
ACC1_DR0
AD
ACC1_DR3
AE
ACC1_DR2
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
RDI3RI
RDI3SYN
RDI3IS
RDI3LT0
RDI3LT1
RDI3RO0
RDI3RO1
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
Page 23 of 58
CY8CLED16P01
Table 9-2. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
PRT6DM0
PRT6DM1
PRT6IC0
PRT6IC1
PRT7DM0
PRT7DM1
Addr (1,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
DBB20FN
DBB20IN
DBB20OU
DBB21FN
DBB21IN
DBB21OU
DCB22FN
DCB22IN
DCB22OU
DCB23FN
DCB23IN
DCB23OU
DBB30FN
DBB30IN
DBB30OU
DBB31FN
DBB31IN
DBB31OU
DCB32FN
DCB32IN
DCB32OU
DCB33FN
DCB33IN
PRT7IC0
PRT7IC1
DBB00FN
DBB00IN
DBB00OU
1E
RW
DCB33OU
1F
RW
20
RW
CLK_CR0
21
RW
CLK_CR1
22
RW
ABF_CR0
23
AMD_CR0
DBB01FN
24
RW
DBB01IN
25
RW
DBB01OU
26
RW
AMD_CR1
27
ALT_CR0
DCB02FN
28
RW
ALT_CR1
DCB02IN
29
RW
CLK_CR2
DCB02OU
2A
RW
2B
DCB03FN
2C
RW
TMP_DR0
DCB03IN
2D
RW
TMP_DR1
DCB03OU
2E
RW
TMP_DR2
2F
TMP_DR3
DBB10FN
30
RW
ACB00CR3
DBB10IN
31
RW
ACB00CR0
DBB10OU
32
RW
ACB00CR1
33
ACB00CR2
DBB11FN
34
RW
ACB01CR3
DBB11IN
35
RW
ACB01CR0
DBB11OU
36
RW
ACB01CR1
37
ACB01CR2
DCB12FN
38
RW
ACB02CR3
DCB12IN
39
RW
ACB02CR0
DCB12OU
3A
RW
ACB02CR1
3B
ACB02CR2
DCB13FN
3C
RW
ACB03CR3
DCB13IN
3D
RW
ACB03CR0
DCB13OU
3E
RW
ACB03CR1
3F
ACB03CR2
Blank fields are Reserved and should not be accessed.
Document Number: 001-49263 Rev. *J
Addr (1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
Access
Name
RW
ASC10CR0
RW
ASC10CR1
RW
ASC10CR2
ASC10CR3
RW
ASD11CR0
RW
ASD11CR1
RW
ASD11CR2
ASD11CR3
RW
ASC12CR0
RW
ASC12CR1
RW
ASC12CR2
ASC12CR3
RW
ASD13CR0
RW
ASD13CR1
RW
ASD13CR2
ASD13CR3
RW
ASD20CR0
RW
ASD20CR1
RW
ASD20CR2
ASD20CR3
RW
ASC21CR0
RW
ASC21CR1
RW
ASC21CR2
ASC21CR3
RW
ASD22CR0
RW
ASD22CR1
RW
ASD22CR2
ASD22CR3
RW
ASC23CR0
RW
ASC23CR1
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
ASC23CR2
ASC23CR3
Addr (1,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
RDI3RI
RDI3SYN
RDI3IS
RDI3LT0
RDI3LT1
RDI3RO0
RDI3RO1
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
OSC_GO_E
N
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
DEC_CR2
IMO_TR
ILO_TR
BDG_TR
ECO_TR
RW
RW
RW
RW
RW
RW
RW
CPU_F
RW
RW
RW
RW
RW
RW
RW
FLS_PR1
CPU_SCR1
CPU_SCR0
Addr (1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
Access
RW
RW
RW
RW
RW
RW
RW
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
RW
W
RL
RW
#
#
Page 24 of 58
CY8CLED16P01
10. Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CLED16P01 device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com.
Specifications are valid for -40°C TA 85°C and TJ 100°C, except where noted.
10.1 Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 10-1. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage Temperature
TBAKETEMP Bake Temperature
Min
–55
Typ
25
Max
+100
Units
°C
–
125
C
See
package
label
–40
–
See
package
label
72
Hours
–
+85
°C
V
V
mA
mA
TBAKETIME
Bake Time
TA
Vdd
VIO
Ambient Temperature with Power
Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
–0.5
Vss – 0.5
–
–
VIOZ
DC Voltage Applied to Tristate
Vss – 0.5
–
IMIO
IMAIO
Maximum Current into any Port Pin
Maximum Current into any Port Pin
Configured as Analog Driver
Electro Static Discharge Voltage
Latch-up Current
–25
-50
–
–
+6.0
Vdd +
0.5
Vdd +
0.5
+50
+50
2000
–
–
–
–
200
V
mA
Typ
–
–
Max
+85
+100
Units
C
C
ESD
LU
Notes
Higher storage temperatures
reduce data retention time. Recommended storage temperature is
+25°C ± 25°C. Extended duration
storage temperatures above 65°C
degrade reliability.
V
Human Body Model ESD
10.2 Operating Temperature
Table 10-2. Operating Temperature
Symbol
TA
TJ
Description
Ambient Temperature
Junction Temperature
Document Number: 001-49263 Rev. *J
Min
-40
-40
Notes
The temperature rise from ambient to
junction is package specific. See
Thermal Impedances on page
46.The user must limit the power
consumption to comply with this
requirement.
Page 25 of 58
CY8CLED16P01
10.3 DC Electrical Characteristics
10.3.1 DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-3. DC Chip-Level Specifications
Symbol
Description
Vdd
Supply Voltage
IDD
Supply Current
Min
4.75
–
Typ
–
8
Max
5.25
14
Units
V
mA
VREF
1.28
1.3
1.32
V
Reference Voltage (Bandgap)
Notes
Conditions are 5.0V, TA = 25°C,
CPU = 3 MHz, SYSCLK doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 0.366 kHz.
Trimmed for appropriate Vdd.
10.3.2 DC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature range: 4.75V to 5.25V and
-40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-4. DC GPIO Specifications
Symbol
RPU
RPD
VOH
Description
Pull Up Resistor
Pull Down Resistor
High Output Level
Min
4
4
Vdd 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
k
k
V
VOL
Low Output Level
–
–
0.75
V
IOH
High Level Source Current
10
–
–
mA
IOL
Low Level Sink Current
25
–
–
mA
VIL
VIH
VH
IIL
CIN
COUT
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
Capacitive Load on Pins as Output
–
2.1
–
–
–
–
–
–
60
1
3.5
3.5
0.8
V
V
mV
nA
pF
pF
Document Number: 001-49263 Rev. *J
–
–
10
10
Notes
IOH = 10 mA, (8 total loads, 4 on even port
pins (for example, P0[2], P1[4]), 4 on odd
port pins (for example, P0[3], P1[5])). 80
mA maximum combined IOH budget.
IOL = 25 mA, (8 total loads, 4 on even port
pins (for example, P0[2], P1[4]), 4 on odd
port pins (for example, P0[3], P1[5])). 150
mA maximum combined IOL budget.
VOH = Vdd-1.0V. See the limitations of the
total current in the Note for VOH.
VOL = 0.75V. See the limitations of the total
current in the Note for VOL.
Gross tested to 1 A.
Package and pin dependent. Temp = 25°C.
Package and pin dependent. Temp = 25°C.
Page 26 of 58
CY8CLED16P01
10.3.3 DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 10-5. 5-V DC Operational Amplifier Specifications
Symbol
Min
Typ
Max
Unit
Input offset voltage (absolute value)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
–
–
1.6
1.6
1.6
1.6
1.6
1.6
10
10
10
10
10
10
mV
mV
mV
mV
mV
mV
TCVOSOA
Average input offset voltage drift
–
4
23
µV/°C
I
VOSOA
Description
Notes
EBOA
Input leakage current (port 0 analog pins)
–
200
–
pA
Gross tested to 1 µA
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
V
Common mode voltage range (All cases,
except Power = High, Opamp bias = High)
0
–
VDD
V
Common mode voltage range (Power = High,
Opamp bias = High)
0.5
–
VDD – 0.5
V
The common-mode input voltage range
is measured through an analog output
buffer.
The specification includes the
limitations imposed by the
characteristics of the analog output
buffer.
CMRROA
Common mode rejection ratio
60
–
–
dB
GOLOA
Open loop gain
CMOA
80
–
–
dB
VDD – 0.01
–
–
V
–
–
0.1
V
Supply current (including associated
AGND buffer)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = Medium, Opamp bias = Low
Power = Medium, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
µA
µA
µA
µA
µA
µA
Supply voltage rejection ratio
67
80
–
dB
VOHIGHOA High output voltage swing (internal signals)
VOLOWOA Low output voltage swing (internal signals)
ISOA
PSRROA
VSS VIN (VDD – 2.25) or
(VDD – 1.25 V) VIN VDD.
10.3.4 DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-6. DC Low Power Comparator Specifications
Symbol
Description
VREFLPC Low Power Comparator (LPC) Reference
Voltage Range
LPC Supply Current
ISLPC
VOSLPC
LPC Voltage Offset
Document Number: 001-49263 Rev. *J
Min
0.2
Typ
–
Max
Vdd - 1
Units
V
–
–
10
2.5
40
30
A
mV
Notes
Page 27 of 58
CY8CLED16P01
10.3.5 DC Analog Output Buffer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-7. DC Analog Output Buffer Specifications
Symbol
CL
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Description
Load capacitance
Input Offset Voltage (Absolute Value)
Power = Low, Opamp bias = Low
Power = Low, Opamp bias = High
Power = High, Opamp bias = Low
Power = High, Opamp bias = High
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 32 ohms to
Vdd/2)
Power = Low
Power = High
Low Output Voltage Swing (Load = 32 ohms to
Vdd/2)
Power = Low
Power = High
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
Document Number: 001-49263 Rev. *J
Min
–
Typ
–
Max
200
Units
pF
–
–
–
–
–
0.5
3.2
3.2
3.2
3.2
5.5
–
18
18
18
18
26
Vdd - 1.0
mV
mV
mV
mV
V/°C
V
–
–
–
–
1
1
W
W
0.5 × Vdd + 1.3
0.5 × Vdd + 1.3
–
–
–
–
V
V
–
–
–
–
0.5 × Vdd - 1.3
0.5 × Vdd - 1.3
V
V
–
–
40
1.1
2.6
64
2
5
–
mA
mA
dB
Notes
This specification
applies to the
external circuit driven
by the analog output
buffer.
Page 28 of 58
CY8CLED16P01
10.3.6 DC Analog Reference Specifications
Table 10-8 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling
of the digital signal may appear on the AGND.
Table 10-8. 5-V DC Analog Reference Specifications
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
Description
Min
RefPower = High
Opamp bias = High
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.228
VDD/2 + 1.290 VDD/2 + 1.352
VAGND
AGND
VDD/2
VDD/2 – 0.078
VDD/2 – 0.007
VDD/2 + 0.063
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.336
VDD/2 – 1.295
VDD/2 – 1.250
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.224
VDD/2 + 1.293 VDD/2 + 1.356
V
VAGND
AGND
VDD/2
VDD/2 – 0.056
VDD/2 – 0.005
VDD/2 + 0.043
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.338
VDD/2 – 1.298
VDD/2 – 1.255
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.226
VDD/2 + 1.293 VDD/2 + 1.356
V
VAGND
AGND
VDD/2
VDD/2 – 0.057
VDD/2 – 0.006
VDD/2 + 0.044
V
RefPower = High
Opamp bias = Low
0b000
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Typ
Max
Unit
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.337
VDD/2 – 1.298
VDD/2 – 1.256
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.226
VDD/2 + 1.294 VDD/2 + 1.359
V
VAGND
AGND
VDD/2
VDD/2 – 0.047
VDD/2 – 0.004
VDD/2 + 0.035
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.338
VDD/2 – 1.299
VDD/2 – 1.258
V
Document Number: 001-49263 Rev. *J
Page 29 of 58
CY8CLED16P01
Table 10-8. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = High
Opamp bias = High
VREFHI
Ref High
RefPower = High
Opamp bias = Low
0b001
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b010
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Description
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
Min
Typ
Max
Unit
P2[4] + P2[6] –
0.085
P2[4] + P2[6] –
0.016
P2[4] + P2[6]
+ 0.044
V
P2[4]
P2[4]
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.010
0.055
V
VREFHI
Ref High
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] + P2[6] –
0.077
P2[4] + P2[6] –
0.010
P2[4] + P2[6]
+ 0.051
V
P2[4]
P2[4]
P2[4]
P2[4]
–
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.005
0.039
V
VREFHI
Ref High
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] + P2[6] –
0.070
P2[4] + P2[6] –
0.010
P2[4] + P2[6]
+ 0.050
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.005
0.039
V
VREFHI
Ref High
P2[4] + P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
P2[4] + P2[6] –
0.070
P2[4] + P2[6] –
0.007
P2[4] + P2[6]
+ 0.054
V
P2[4]
P2[4]
P2[4]
P2[4]
VAGND
AGND
VREFLO
Ref Low
P2[4] – P2[6]
(P2[4] = VDD/2,
P2[6] = 1.3 V)
VREFHI
Ref High
VDD
VAGND
AGND
P2[4]
VDD/2
P2[4]
P2[4]
P2[4] – P2[6] –
0.022
P2[4] – P2[6] + P2[4] – P2[6] +
0.002
0.032
–
–
V
VDD – 0.037
VDD – 0.009
VDD
V
VDD/2 – 0.061
VDD/2 – 0.006
VDD/2 + 0.047
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.007
VSS + 0.028
V
VREFHI
Ref High
VDD
VDD – 0.039
VDD – 0.006
VDD
V
VAGND
AGND
VDD/2 – 0.049
VDD/2 – 0.005
VDD/2 + 0.036
V
VDD/2
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.019
V
VREFHI
Ref High
VDD
VDD – 0.037
VDD – 0.007
VDD
V
VAGND
AGND
VDD/2 – 0.054
VDD/2 – 0.005
VDD/2 + 0.041
V
VDD/2
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.024
V
VREFHI
Ref High
VDD
VDD – 0.042
VDD – 0.005
VDD
V
VDD/2 – 0.046
VDD/2 – 0.004
VDD/2 + 0.034
V
VSS
VSS + 0.004
VSS + 0.017
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 001-49263 Rev. *J
VDD/2
VSS
Page 30 of 58
CY8CLED16P01
Table 10-8. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = High
Opamp bias = High
VREFHI
Ref High
3 × Bandgap
RefPower = High
Opamp bias = Low
0b011
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b100
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Description
Min
Typ
Max
Unit
3.788
3.891
3.986
V
VAGND
AGND
2 × Bandgap
2.500
2.604
3.699
V
VREFLO
Ref Low
Bandgap
1.257
1.306
1.359
V
VREFHI
Ref High
3 × Bandgap
3.792
3.893
3.982
V
2 × Bandgap
2.518
2.602
2.692
V
Bandgap
1.256
1.302
1.354
V
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
3 × Bandgap
3.795
3.894
3.993
V
VAGND
AGND
2 × Bandgap
2.516
2.603
2.698
V
VREFLO
Ref Low
Bandgap
1.256
1.303
1.353
V
VREFHI
Ref High
3 × Bandgap
3.792
3.895
3.986
V
VAGND
AGND
2 × Bandgap
2.522
2.602
2.685
V
VREFLO
Ref Low
Bandgap
1.255
1.301
1.350
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.495 – P2[6]
2.586 – P2[6]
2.657 – P2[6]
V
VAGND
AGND
2.502
2.604
2.719
V
VREFLO
Ref Low
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
2.531 – P2[6]
2.611 – P2[6]
2.681 – P2[6]
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.500 – P2[6]
2.591 – P2[6]
2.662 – P2[6]
V
2 × Bandgap
VAGND
AGND
2.519
2.602
2.693
V
VREFLO
Ref Low
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
2.530 – P2[6]
2.605 – P2[6]
2.666 – P2[6]
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.503 – P2[6]
2.592 – P2[6]
2.662 – P2[6]
V
2 × Bandgap
VAGND
AGND
2.517
2.603
2.698
V
VREFLO
Ref Low
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
2.529 – P2[6]
2.606 – P2[6]
2.665 – P2[6]
V
VREFHI
Ref High
2 × Bandgap +
P2[6] (P2[6] =
1.3 V)
2.505 – P2[6]
2.594 – P2[6]
2.665 – P2[6]
V
VAGND
AGND
2.525
2.602
2.685
V
VREFLO
Ref Low
2.528 – P2[6]
2.603 – P2[6]
2.661 – P2[6]
V
Document Number: 001-49263 Rev. *J
2 × Bandgap
2 × Bandgap
2 × Bandgap –
P2[6] (P2[6] =
1.3 V)
Page 31 of 58
CY8CLED16P01
Table 10-8. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR[5:3]
Reference Power
Settings
Symbol
Reference
RefPower = High
Opamp bias = High
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
RefPower = High
Opamp bias = Low
0b101
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b110
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
RefPower = High
Opamp bias = High
RefPower = High
Opamp bias = Low
0b111
RefPower = Med
Opamp bias = High
RefPower = Med
Opamp bias = Low
Description
Min
Typ
Max
Unit
P2[4] + 1.222
P2[4] + 1.290
P2[4] + 1.343
V
P2[4]
P2[4]
P2[4]
–
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.331
P2[4] – 1.295
P2[4] – 1.254
V
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.226
P2[4] + 1.293
P2[4] + 1.347
V
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4]
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4]
P2[4] – 1.331
P2[4] – 1.298
P2[4] – 1.259
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.227
P2[4] + 1.294
P2[4] + 1.347
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4]
P2[4] – 1.331
P2[4] – 1.298
P2[4] – 1.259
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.228
P2[4] + 1.295
P2[4] + 1.349
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – 1.332
P2[4] – 1.299
P2[4] – 1.260
V
VREFHI
Ref High
VAGND
AGND
P2[4]
P2[4] – Bandgap
(P2[4] = VDD/2)
2 × Bandgap
2.535
2.598
2.644
V
Bandgap
1.227
1.305
1.398
V
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.009
VSS + 0.038
VREFHI
Ref High
2 × Bandgap
2.530
2.598
2.643
V
VAGND
AGND
Bandgap
1.244
1.303
1.370
V
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.024
VREFHI
Ref High
2 × Bandgap
2.532
2.598
2.644
V
VAGND
AGND
Bandgap
1.239
1.304
1.380
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.026
V
VREFHI
Ref High
2 × Bandgap
2.528
2.598
2.645
V
Bandgap
1.249
1.302
1.362
V
VSS
VSS + 0.004
VSS + 0.018
V
4.155
4.234
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.041
1.6 × Bandgap
1.998
2.083
2.183
V
VSS
VSS + 0.010
VSS + 0.038
V
4.153
4.236
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.047
1.6 × Bandgap
2.012
2.082
2.157
V
VSS
VSS + 0.006
VSS + 0.024
V
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
3.2 × Bandgap
4.049
4.154
4.238
V
VAGND
AGND
1.6 × Bandgap
2.008
2.083
2.165
V
VREFLO
Ref Low
VSS
VSS + 0.006
VSS + 0.026
V
VREFHI
Ref High
3.2 × Bandgap
4.047
4.154
4.238
V
VAGND
AGND
1.6 × Bandgap
2.016
2.081
2.150
V
VREFLO
Ref Low
VSS
VSS + 0.004
VSS + 0.018
V
Document Number: 001-49263 Rev. *J
VSS
VSS
VSS
Page 32 of 58
CY8CLED16P01
10.3.7 DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-9. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switch Cap)
Min
–
–
Typ
12.2
80
Max
–
–
Units
k
fF
Notes
10.3.8 DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C = TA = 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-10. DC POR and LVD Specifications
Symbol
Description
Vdd Value for PPOR Trip (positive ramp)
VPPOR2R PORLEV[1:0] = 10b
Min
Typ
Max
Units
–
4.55
–
V
VPPOR2
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 10b
–
4.55
–
V
VPH2
PPOR Hysteresis
PORLEV[1:0] = 10b
–
0
–
mV
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 110b
VM[2:0] = 111b
4.63
4.72
4.73
4.81
4.82
4.91
V
V
Document Number: 001-49263 Rev. *J
Notes
Page 33 of 58
CY8CLED16P01
10.3.9 DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-11. DC Programming Specifications
Symbol
VDDP
Description
VDD for programming and erase
Min
4.5
Typ
5
Max
5.5
Units
V
VDDLV
Low VDD for verify
4.7
4.8
4.9
V
VDDHV
High VDD for verify
5.1
5.2
5.3
V
VDDIWRITE
Supply voltage for flash write operation
4.75
5,0
5.25
V
IDDP
VILP
10
–
30
0.8
mA
V
–
–
V
–
0.2
mA
–
1.5
mA
–
V
–
Vss +
0.75
Vdd
FlashENPB
Supply Current During Programming or Verify
–
Input Low Voltage During Programming or
–
Verify
Input High Voltage During Programming or
2.2
Verify
Input Current when Applying VILP to P1[0] or
–
P1[1] During Programming or Verify
Input Current when Applying VIHP to P1[0] or
–
P1[1] During Programming or Verify
Output Low Voltage During Programming or
–
Verify
Output High Voltage During Programming or Vdd - 1.0
Verify
Flash Endurance (per block)
50,000
–
–
–
FlashENT
FlashDR
Flash Endurance (total)[5]
Flash Data Retention
–
–
–
–
–
Years
VIHP
IILP
IIHP
VOLV
VOHV
1,800,000
10
Notes
This specification applies
to the functional
requirements of external
programmer tools.
This specification applies
to the functional
requirements of external
programmer tools.
This specification applies
to the functional
requirements of external
programmer tools.
This specification applies
to this device when it is
executing internal flash
writes.
Driving internal pull down
resistor
Driving internal pull down
resistor
V
Erase/write cycles per
block
Erase/write cycles
DC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-12. DC I2C Specifications
Parameter
VILI2C[4]
VIHI2C[4]
Description
Min
Typ
Max
Units
Notes
Input low level
–
–
0.25 × VDD
V
4.75 V VDD 5.25 V
Input high level
0.7 × VDD
–
–
V
4.75 V VDD 5.25 V
Note
4. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO specifications sections.The I2C GPIO pins also meet the mentioned specs.
Document Number: 001-49263 Rev. *J
Page 34 of 58
CY8CLED16P01
10.4 AC Electrical Characteristics
10.4.1 AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Note See the individual user module data sheets for information on maximum frequencies for user modules.
Table 10-13. AC Chip-Level Specifications
Symbol
FIMO24
Description
Internal Main Oscillator Frequency for 24 MHz
Min
23.4
Typ
24
Max
24.6
Units
MHz
FIMO6
Internal Main Oscillator Frequency for 6 MHz
5.5
6
6.5[6]
MHz
FCPU1
F48M
CPU Frequency (5V Nominal)
Digital PSoC Block Frequency
0.0914
0
24
48
24.6[6]
49.2[6, 7]
MHz
MHz
F32K1
F32K2
Internal Low Speed Oscillator Frequency
External Crystal Oscillator
15
–
32
32.768
64
–
kHz
kHz
F32K_U
Internal Low Speed Oscillator (ILO)
Untrimmed Frequency
5
–
100
kHz
FPLL
PLL Frequency
–
23.986
–
MHz
TPLLSLEW
TPLLSLEWLOW
TOS
TOSACC
PLL Lock Time
PLL Lock Time for Low Gain Setting
External Crystal Oscillator Startup to 1%
External Crystal Oscillator Startup to 100 ppm
0.5
0.5
–
–
–
–
250
300
10
50
500
600
ms
ms
ms
ms
TXRST
External Reset Pulse Width
SRPOWER_UP Power Supply Slew Rate
10
–
–
–
–
250
s
V/ms
TPOWERUP
Time from End of POR to CPU Executing Code
–
16
100
ms
DC24M
24 MHz Duty Cycle
40
50
60
%
Notes
Trimmed for 5V operation
using factory trim values.
SLIMO Mode = 0.
Trimmed for 5V operation
using factory trim values.
SLIMO Mode = 1.
SLIMO Mode = 0.
Refer to the AC Digital Block
Specifications below.
Accuracy is capacitor and
crystal dependent. 50% duty
cycle.
After a reset and before the
m8c starts to run, the ILO is
not trimmed. See the System
Resets section of the PSoC
Technical Reference Manual
for details on timing this.
A multiple (x732) of crystal
frequency.
The crystal oscillator
frequency is within 100 ppm
of its final value by the end of
the TOSACC period. Correct
operation assumes a
properly loaded 1 W
maximum drive level 32.768
kHz crystal. -40°C TA
85°C.
Vdd slew rate during power
up.
Power up from 0V. See the
System Resets section of the
PSoC Technical Reference
Manual.
Notes
5. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
6. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
7. See the individual user module data sheets for information on maximum frequencies for user modules.
8. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-49263 Rev. *J
Page 35 of 58
CY8CLED16P01
Table 10-13. AC Chip-Level Specifications (continued)
Symbol
DCILO
Step24M
Fout48M
Description
Internal Low Speed Oscillator Duty Cycle
24 MHz Trim Step Size
48 MHz Output Frequency
FMAX
Maximum frequency of signal on row input or
row output.
24 MHz IMO cycle-to-cycle jitter (RMS)
24 MHz IMO long term N cycle-to-cycle jitter
(RMS)
24 MHz IMO period jitter (RMS)
24 MHz IMO cycle-to-cycle jitter (RMS)
24 MHz IMO long term N cycle-to-cycle jitter
(RMS)
24 MHz IMO period jitter (RMS)
tjit_IMO [8]
tjit_PLL [8]
Min
20
–
46.8
Typ
50
50
48.0
Max
80
–
49.2
Units
%
kHz
MHz
Notes
–
–
12.3
MHz
–
–
200
300
700
900
ps
ps
N = 32
–
–
–
100
200
300
400
800
1200
ps
ps
ps
N = 32
–
100
700
ps
Trimmed using factory trim
values.
Figure 10-1. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 10-2. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 10-3. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Document Number: 001-49263 Rev. *J
Page 36 of 58
CY8CLED16P01
10.4.2 AC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-14. AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12.3
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
10% - 90%
10% - 90%
10% - 90%
10% - 90%
Figure 10-4. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
10.4.3 AC Operational Amplifier Specifications
Table 10-15 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 10-15. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
Description
Rising Settling Time to 0.1% for a 1V Step (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time to 0.1% for a 1V Step (10
pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%) of a 1V Step
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%) of a 1V Step
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Document Number: 001-49263 Rev. *J
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
s
s
s
–
–
–
–
–
–
5.9
0.92
0.72
s
s
s
0.15
1.7
6.5
–
–
–
–
–
–
V/s
V/s
V/s
0.01
0.5
4.0
–
–
–
–
–
–
V/s
V/s
V/s
Notes
Page 37 of 58
CY8CLED16P01
Table 10-15. 5V AC Operational Amplifier Specifications (continued)
Symbol
BWOA
ENOA
Description
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias
= High)
Min
Typ
Max
Units
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Notes
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 10-5. Typical AGND Noise with P2[4] Bypass
nV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 10-6. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
Document Number: 001-49263 Rev. *J
0.1
Freq (kHz)
1
10
100
Page 38 of 58
CY8CLED16P01
10.4.4 AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-16. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
s
Notes
50 mV overdrive comparator
reference set within VREFLPC.
10.4.5 AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-17. AC Digital Block Specifications
Function
Description
All functions
Block input clock frequency
Timer
Input clock frequency
VDD 4.75 V
Max
Unit
–
–
49.2
MHz
No capture, VDD 4.75 V
–
–
49.2
MHz
–
–
24.6
MHz
50[9]
–
–
ns
–
–
49.2
MHz
–
–
24.6
MHz
50[9]
–
–
ns
Notes
Input clock frequency
No enable input, VDD 4.75 V
With enable input
Enable input pulse width
Dead Band
Typ
With capture
Capture pulse width
Counter
Min
Kill pulse width
Asynchronous restart mode
20
–
–
ns
Synchronous restart mode
50[9]
–
–
ns
Disable mode
50[9]
–
–
ns
–
–
49.2
MHz
Input clock frequency
VDD 4.75 V
CRCPRS
(PRS Mode)
Input clock frequency
–
–
49.2
MHz
CRCPRS
(CRC Mode)
Input clock frequency
–
–
24.6
MHz
SPIM
Input clock frequency
–
–
8.2
MHz
The SPI serial clock (SCLK) frequency is equal to the
input clock frequency divided by 2
SPIS
Input clock (SCLK) frequency
–
–
4.1
MHz
The input clock is the SPI SCLK in SPIS mode
–
–
ns
VDD 4.75 V
Width of SS_negated between
transmissions
Transmitter
Receiver
50
[9]
Input clock frequency
VDD 4.75 V, 2 stop bits
–
–
49.2
MHz
VDD 4.75 V, 1 stop bit
–
–
24.6
MHz
Input clock frequency
VDD 4.75 V, 2 stop bits
–
–
49.2
MHz
VDD 4.75 V, 1 stop bit
–
–
24.6
MHz
The baud rate is equal to the input clock frequency
divided by 8
The baud rate is equal to the input clock frequency
divided by 8
Note
9. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-49263 Rev. *J
Page 39 of 58
CY8CLED16P01
10.4.6 AC Analog Output Buffer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-18. 5V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step,
100 pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step,
100 pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mVpp, 3 dB BW,
100 pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1Vpp, 3 dB BW,
100 pF Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
4
4
s
s
–
–
–
–
3.4
3.4
s
s
0.5
0.5
–
–
–
–
V/s
V/s
0.55
0.55
–
–
–
–
V/s
V/s
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Notes
10.4.7 AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-19. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
0.093
–
24.6
MHz
High Period
20.6
–
5300
ns
Low Period
20.6
–
–
ns
Power Up IMO to Switch
150
–
–
µs
FOSCEXT
Frequency
–
–
–
Document Number: 001-49263 Rev. *J
Notes
Page 40 of 58
CY8CLED16P01
10.4.8 AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-20. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TERASEALL
Description
Rise Time of SCLK
Fall Time of SCLK
Data Setup Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Flash Erase Time (Bulk)
TPROGRAM_HOT Flash Block Erase + Flash Block Write Time
TPROGRAM_COLD Flash Block Erase + Flash Block Write Time
Document Number: 001-49263 Rev. *J
Min
1
1
40
40
0
–
–
–
–
Typ
–
–
–
–
–
10
40
–
80
Max
20
20
–
–
8
–
–
45
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ms
–
–
–
–
100[10]
200[10]
ms
ms
Notes
Erase all Blocks and protection
fields at once
0°C <= Tj <= 100°C
-40°C <= Tj <= 0°C
Page 41 of 58
CY8CLED16P01
10.4.9 AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10-21. AC Characteristics of the I2C SDA and SCL Pins
Symbol
FSCLI2C
THDSTAI2C
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Description
SCL Clock Frequency
Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP and START
Condition
Pulse Width of spikes are suppressed by the
input filter
Standard-Mode
Min
Max
0
100
4.0
–
Fast-Mode
Min
Max
0
400
0.6
–
Units
Notes
kHz
s
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
1.3
0.6
0.6
0
100[11]
0.6
1.3
–
–
–
–
–
–
–
s
s
s
s
ns
s
s
–
–
0
50
ns
Figure 10-7. Definition for Timing for Fast-/Standard-Mode on the I2C Bus Packaging Dimensions
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Notes
10. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com for more information.
11. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If this device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-49263 Rev. *J
Page 42 of 58
CY8CLED16P01
11. Packaging Information
This section illustrates the packaging specifications for the CY8CLED16P01 PLC device, along with the thermal impedances for each
package, and the typical package capacitance on crystal pins.
Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation
tools' dimensions, refer to the Emulator Pod Dimension drawings at http://www.cypress.com.
11.1 Packaging Dimensions
Figure 11-1. 28-Pin (210-Mil) SSOP
51-85079 *E
Document Number: 001-49263 Rev. *J
Page 43 of 58
CY8CLED16P01
Figure 11-2. 48-Pin (7 × 7 mm) QFN
SOLDERABLE
EXPOSED
PAD
001-12919 *C
Important Note
For information on the preferred dimensions for mounting QFN packages, refer to Application Note, "Application Notes for Surface
Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com.
Pinned vias for thermal conduction are not required for the low power PSoC devices.
Document Number: 001-49263 Rev. *J
Page 44 of 58
CY8CLED16P01
Figure 11-3. 48-Pin QFN 7x7x 0.90 MM (Sawn Type)
001-13191 *E
Figure 11-4. 100-Pin TQFP
51-85048 *E
Document Number: 001-49263 Rev. *J
Page 45 of 58
CY8CLED16P01
11.1 Thermal Impedances
Table 11-1. Thermal Impedances per Package
Package
Typical JA[12]
Typical JC
28 SSOP
59 °C/W
23 C/W
[13]
15 °C/W
18 C/W
100 TQFP
42 °C/W
15 C/W
48 QFN
11.2 Capacitance on Crystal Pins
Table 11-2. Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
28 SSOP
2.8 pF
48 QFN
1.8 pF
100 TQFP
3.1 pF
11.3 Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 11-3. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Time at Maximum Peak Temperature
28 SSOP
260 °C
20 s
48 QFN
260 °C
20 s
100 TQFP
260 °C
20 s
Notes
12. TJ = TA + POWER × JA
13. To achieve the thermal impedance specified for the QFN package, refer to "Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF)
Packages" available at http://www.amkor.com.
Document Number: 001-49263 Rev. *J
Page 46 of 58
CY8CLED16P01
12. Development Tool Selection
12.1 Software
■
CY8CLED16P01-OCD (100 TQFP)
12.1.1 PSoC Designer™
■
Software CD
At the core of the PSoC development software suite is PSoC
Designer, used to generate firmware applications. PSoC
Designer is available free of charge at http://www.cypress.com.
PSoC Designer comes with a free C compiler.
■
Supporting Literature
■
MiniProg1
12.1.2 PSoC Programmer
The CY3250-PLC Pod Kits are essential for development
purposes as they provide the users a medium to emulate and
debug their designs. The pod kits are available for all the
available footprints. The details are:
PSoC Programmer is a very flexible programming application. It
is used on the bench in development and is also suitable for
factory programming. PSoC Programmer works either in a
standalone configuration or operates directly from PSoC
Designer. PSoC Programmer software is compatible with both
PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC
programmer
is
available
free
of
charge
at
http://www.cypress.com.
12.2.3 CY3250-PLC Pod Kits
■
CY3250-LED16P01NQ – One SSOP Pod
(CY8CLED16P01-OCD), Two 28-SSOP Feet, One 3250-Flex
Cable, One 28-SSOP Foot Mask
■
CY3250-LED16P01QFN – One QFN Pod
(CY8CLED16P01-OCD), Two 48-QFN Feet, One 3250-Flex
Cable
■
CY3250-LED16P01NQ-POD – Two SSOP Pods
(CY8CLED16P01-OCD)
■
CY3250-LED16P01QFN-POD – Two QFN Pods
(CY8CLED16P01-OCD)
12.2 Development Kits
All development kits are sold at the Cypress Online Store.
12.2.1 CY3276-Programmable HV PLC + EZ-Color™ Development Kit
The CY3276 is used for prototyping and development on the
CY8CLED16P01 with PSoC Designer. This kit supports in-circuit
emulation. The software interface enables users to run, halt, and
single-step the processor and view the content of specific
memory locations. PSoC Designer also supports the advanced
emulation features. The hardware contains the high voltage
coupling circuit for 110 VAC to 240 VAC powerline, which is
compliant with the CENELEC/FCC standards. This board also
has an onboard switch mode power supply. The kit includes:
■
12.2.4 CY3215-DK Basic Development Kit
The CY3215-DK is used for prototyping and development with
PSoC Designer. This kit can be used in conjunction with the PLC
kits to support in-circuit emulation. The software interface
enables users to run, halt, and single step the processor and
view the content of specific memory locations. PSoC Designer
also supports the advanced emulation features. The kit includes:
One High Voltage (110 to 230VAC) PLC Board. Cypress recommends that a user purchases two CY3276 kits to set up a
two-node PLC subsystem for evaluation and development.
■
PSoC Designer Software CD
■
ICE-Cube In-Circuit Emulator
■
LED Daughter Card
■
ICE Flex-Pod for CY8C29x66 Family
■
CY8CLED16P01-OCD (100 TQFP)
■
Cat-5 Adapter
■
Software CD
■
Mini-Eval Programming Board
■
Supporting Literature
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
MiniProg1
■
iMAGEcraft C Compiler (Registration Required)
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
12.2.2 CY3277-Programmable LV PLC + EZ-Color Development
Kit
The CY3277-PLC is used for prototyping and development on
the CY8CLED16P01 with PSoC Designer. This kit supports
in-circuit emulation. The software interface enables users to run,
halt, and single-step the processor and view the content of
specific memory locations. PSoC Designer also supports
advanced emulation features. The hardware contains the low
voltage coupling circuit for 12-24V AC/DC powerline. The kit
includes:
■ One Low Voltage (12 to 24V AC/DC) PLC Board. Cypress
recommends that a user purchases two CY3275 kits to set up
a two-node PLC subsystem for evaluation and development
■
LED Daughter Card
Document Number: 001-49263 Rev. *J
Page 47 of 58
CY8CLED16P01
12.3 Evaluation Kits
12.4 Device Programmers
The evaluation kits do not have on-board powerline capability,
but can be used with a PLC kit for evaluation purposes. All evaluation tools are sold at the Cypress Online Store.
All device programmers are sold at the Cypress.
12.3.1 CY3210-MiniProg1
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
12.4.1 CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular Programmer Base
■
MiniProg Programming Unit
■
Three Programming Module Cards
■
MiniEval Socket Programming and Evaluation Board
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
Getting Started Guide
■
PSoC Designer Software CD
■
USB 2.0 Cable
■
Getting Started Guide
12.4.2 CY3207 ISSP In-System Serial Programmer (ISSP)
■
USB 2.0 Cable
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
12.3.2 CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread
boarding space to meet all of your evaluation needs. The kit
includes:
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
Evaluation Board with LCD Module
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
MiniProg Programming Unit
■
USB 2.0 Cable
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
12.3.3 CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special
features of the board include both USB and capacitive sensing
development and debugging support. This evaluation board also
includes an LCD module, potentiometer, LEDs, an enunciator,
and plenty of bread boarding space to meet all of your evaluation
needs. The kit includes:
■
PSoCEvalUSB Board
■
LCD Module
■
MIniProg Programming Unit
■
Mini USB Cable
■
PSoC Designer and Example Projects CD
■
Getting Started Guide
■
Wire Pack
Document Number: 001-49263 Rev. *J
Page 48 of 58
CY8CLED16P01
13. Ordering Information
The following table lists the CY8CLED16P01 PLC device family key package features and ordering codes.
RAM
(Bytes)
Temperature
Range
Digital PSoC
Blocks
Analog PSoC
Blocks
Digital I/O
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
CY8CLED16P01-28PVXI
32 K
2K
–40 °C to +85 °C
16
12
24
12
4
Yes
28-Pin (210-Mil) SSOP
(Tape and Reel)
CY8CLED16P01-28PVXIT
32 K
2K
–40 °C to +85 °C
16
12
24
12
4
Yes
48-Pin QFN[14]
CY8CLED16P01-48LFXI
32 K
2K
–40 °C to +85 °C
16
12
44
12
4
Yes
48-Pin QFN (Sawn)
CY8CLED16P01-48LTXI
32 K
2K
–40 °C to +85 °C
16
12
44
12
4
Yes
48-Pin QFN (Sawn)
(Tape and Reel)
CY8CLED16P01-48LTXIT
32 K
2K
–40 °C to +85 °C
16
12
44
12
4
Yes
100-Pin OCD TQFP[15]
CY8CLED16P01-OCD
32 K
2K
–40 °C to +85 °C
16
12
64
12
4
Yes
Ordering
Code
28-Pin (210-Mil) SSOP
Package
Flash
(Bytes)
Table 13-1. CY8CLED16P01 PLC Device Key Features and Ordering Information
13.1 Ordering Code Definitions
CY 8 C LED 16 P01- PC xxx
Package Type:
PVX = SSOP Pb-Free
LFX/LTX = QFN Pb-Free
Pin Count: 28/48
Powerline Communication capability with Programmability
Family Code: HB LED Controllers with 16 Channels
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Note
14. Not recommended for new designs.
15. This part may be used for in-circuit debugging. It is not available for production.
Document Number: 001-49263 Rev. *J
Page 49 of 58
CY8CLED16P01
14. Acronyms
14.1 Acronyms Used
Table 14-1 lists the acronyms that are used in this document.
Table 14-1. Acronyms Used in this Datasheet
Acronym
Description
Acronym
Description
AC
alternating current
MCU
microcontroller unit
ADC
analog-to-digital converter
MIPS
million instructions per second
API
application programming interface
OCD
on-chip debug
BIU
band-in-use
PCB
printed circuit board
CMOS
complementary metal oxide semiconductor
PDIP
plastic dual-in-line package
CPU
central processing unit
PGA
programmable gain amplifier
CRC
cyclic redundancy check
PLC
powerline communication
CSMA
carrier sense multiple access
PLL
phase-locked loop
CT
continuous time
PLT
powerline transceiver
DAC
digital-to-analog converter
POR
power on reset
DC
direct current
PPOR
precision power on reset
DTMF
dual-tone multi-frequency
PRS
pseudo-random sequence
ECO
external crystal oscillator
PSoC®
Programmable System-on-Chip
EEPROM
electrically erasable programmable read-only
memory
PWM
pulse width modulator
FSK
frequency-shift keying
QFN
quad flat no leads
GPIO
general-purpose I/O
RTC
real time clock
I/O
input/output
SAR
successive approximation
ICE
in-circuit emulator
SC
switched capacitor
IDE
integrated development environment
SLIMO
slow IMO
ILO
internal low speed oscillator
SPITM
serial peripheral interface
IMO
internal main oscillator
SRAM
static random access memory
IrDA
infrared data association
SROM
supervisory read only memory
ISSP
in-system serial programming
SSOP
shrink small-outline package
LCD
liquid crystal display
TQFP
thin quad flat pack
LED
light-emitting diode
UART
universal asynchronous reciever / transmitter
LPC
low power comparator
USB
universal serial bus
LPF
low pass filter
WDT
watchdog timer
LVD
low voltage detect
XRES
external reset
MAC
multiply-accumulate
Document Number: 001-49263 Rev. *J
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CY8CLED16P01
15. Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Estimating CY8CPLC20/CY8CLED16P01 Power Consumption – AN55403 (001-55403)
PSoC Dynamic Reconfiguration – AN2104 (001-36000)
Analog – ADC Selection – AN2239 (001-33719)
PrISM™ Technology for LED Dimming – AN47372 (001-47372)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
16. Document Conventions
Units of Measure
Table 16-1 lists the unit sof measures.
Table 16-1. Units of Measure
Symbol
kB
dB
C
fF
kHz
k
MHz
µA
µF
µs
µV
µW
mA
mm
Unit of Measure
1024 bytes
decibels
degree Celsius
femto farad
kilohertz
kilohm
megahertz
microampere
microfarad
microsecond
microvolts
microwatts
milliampere
millimeter
Symbol
ms
mV
nA
ns
nV
ppm
%
pF
ps
pA
rt-Hz
V
W
Unit of Measure
millisecond
millivolts
nanoampere
nanosecond
nanovolts
parts per million
percent
picofarad
picosecond
pikoampere
root hertz
volts
watt
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimals.
Document Number: 001-49263 Rev. *J
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CY8CLED16P01
17. Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous
time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain
stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs
the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and
lower level services and functions (for example, user modules and libraries). APIs serve as
building blocks for programmers that create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with
the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally)
reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital
PSoC block or an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for IO operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented
using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously
satisfy predetermined amplitude requirements.
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CY8CLED16P01
17. Glossary (continued)
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to
‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear
check (CRC)
feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC
generator, pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave like the first system.
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
blocks to stop and return to a pre-defined state.
Flash
An electrically programmable and erasable, non-volatile technology that provides you the
programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means
that the data is retained when power is OFF.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest
amount of Flash space that may be protected. A Flash block holds 64 bytes.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used
as a simple internal bus system for building control electronics. I2C uses only two bi-directional
pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100
kbits/second in standard mode and 400 kbits/second in fast mode.
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CY8CLED16P01
17. Glossary (continued)
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware
interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
(LVD)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside
a PSoC by interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controlled device is called the
slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition
to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason
for this is to permit the realization of a controller with a minimal quantity of chips, thus
achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts
involve pin numbers as a link between schematic and PCB design (both being computer generated
files) and may also involve pin names.
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CY8CLED16P01
17. Glossary (continued)
port
A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of
hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.
slave device
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
SRAM
An acronym for static random access memory. A memory device where you can store and
retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell,
it remains unchanged until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be
accessed in normal user code, operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next
character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
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CY8CLED16P01
17. Glossary (continued)
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high
level API (Application Programming Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually
5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified
period of time.
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CY8CLED16P01
18. Document History Page
Document Title: CY8CLED16P01 Powerline Communication Solution
Document Number: 001-49263
Revision
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
2575716
GHH/PYRS
10/01/08
New Datasheet
*A
2731927
GHH/HMT/
DSG
07/06/09
Added
- Configurable baud rates and FSK Frequencies
- PLC Pod Kits for development purposes
Modified
- Pin information for all packages
*B
2748537
GHH
See ECN
Added Sections on ‘Getting Started’ and ‘Document Conventions’
Modified the following Electrical Parameters
- FIMO6 Min: Changed from 5.75 MHz to 5.5 MHz
- FIMO6 Max: Changed from 6.35 MHz to 6.5 MHz
- SPIS (Maximum input clock frequency): Changed from 4.1 ns to 4.1 MHz
- TWRITE (Flash Block Write Time): Changed from 40 ms to 10 ms
*C
2752799
GHH
08/17/09
Posting to external web.
*D
2759000
GHH
09/02/2009
Fixed typos in the data sheet.
Updated Figure 2-2. on page 3 and Figure 4-1. on page 11.
*E
2778970
FRE
10/05/2009
Added a table for DC POR and LVD Specifications
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
- Modified FIMO6, TWRITE, and Power Up IMO to Switch specifications
- Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, and
SRPOWER_UP specifications
Added 48-Pin QFN (Sawn) package diagram and CY8CLED16P01-48LTXI and
CY8CLED16P01-48LTXIT part details in the Ordering Information table
Updated section 5 and Tables 10-1, 10-2, and 10-3 to state the requirement to use
the external crystal for PLC protocol timing
Table 10-1 and Figure 10-1: Changed pins 9 and 25 from NC to RSVD
Table 10-2 and Figure 10-2: Changed pins 7 and 39 from NC to RSVD
Table 10-3 and Figure 10-3: Changed pins 14 and 77 from NC to RSVD
Tables 10-1, 10-2, 10-3: Added explanation to Connect a 0.1 uF capacitor between
XTAL_Stability and VSS.
Fixed minor typos
*F
2846686
FRE
01/12/2010
Add Table of Contents.
Update copyright and Sales URLs.
Update 28-Pin SSOP, 48-Pin QFN, 48-Pin QFN (Sawn Type) package diagrams.
Add footnote in Ordering Information table of CY8CPLC20-48LFXI stating, “Not
recommended for new designs.”
Add capacitor description to AGND pin.
*G
2903114
NJF
04/01/2010
Updated Cypress website links
Added TBAKETEMP and TBAKETIME parameters
Updated package diagrams
*H
2938300
CGX
05/27/10
Minor ECN to post to external website
*I
3114960
NJF
12/19/10
Added DC I2C Specifications table.
Added F32K_U max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated DC Analog reference, DC operational amplifier specifications and DC
analog output buffer specifications tables.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table and I2C
Timing Diagram. They were updated for clearer understanding.
Updated Figure 10-5 since the labelling for y-axis was incorrect.
Removed footnote reference for “Solder Reflow Peak Temperature” table.
Added the typical JC parameter to the Thermal Impedances table.
Table 8-1 and Figure 8-1: Changed pin 25 from RSVD to P0[2].
Table 8-2 and Figure 8-2: Changed pin 39 from RSVD to P0[2].
Table 8-3 and Figure 8-3: Changed pin 77 from RSVD to P0[2].
*J
3284094
SHOB
06/17/11
Updated Getting Started, Development Tools, and Designing with PSoC
Designer
Document Number: 001-49263 Rev. *J
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CY8CLED16P01
19. Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
19.1 Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
19.2 PSoC Solutions
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-49263 Rev. *J
Revised June 17, 2011
Page 58 of 58
PSoC® and CapSense® are registered trademarks and PSoC Designer™ and EZ-Color™ are trademarks of Cypress Semiconductor Corp. All products and company names mentioned in this document
may be the trademarks of their respective holders.