AD AD9057PCB 8-bit 40 msps/60 msps/80 msps a/d converter Datasheet

a
8-Bit
40 MSPS/60 MSPS/80 MSPS A/D Converter
AD9057
FEATURES
8-Bit, Low Power ADC: 200 mW Typical
120 MHz Analog Bandwidth
On-Chip +2.5 V Reference and T/H
1 V p-p Analog Input Range
Single +5 V Supply Operation
+5 V or +3 V Logic Interface
Power-Down Mode: < 10 mW
Three Performance Grades (40 MSPS, 60 MSPS, 80 MSPS)
APPLICATIONS
Digital Communications (QAM Demodulators)
RGB & YC/Composite Video Processing
Digital Data Storage Read Channels
Medical Imaging
Digital Instrumentation
PRODUCT DESCRIPTION
The AD9057 is an 8-bit monolithic analog-to-digital converter
optimized for low cost, low power, small size, and ease of use.
With a 40 MSPS, 60 MSPS or 80 MSPS encode rates capability and full-power analog bandwidth of 120 MHz, the component is ideal for applications requiring excellent dynamic
performance.
To minimize system cost and power dissipation, the AD9057
includes an internal +2.5 V reference and a track-and-hold
circuit. The user must provide only a +5 V power supply and an
encode clock. No external reference or driver components are
required for many applications.
The AD9057’s encode input is TTL/CMOS compatible and the
8-bit digital outputs can be operated from +5 V or +3 V supplies.
A power-down function may be exercised to bring total consumption to < 10 mW. In power-down mode the digital outputs
are driven to a high impedance state.
Fabricated on an advanced BiCMOS process, the AD9057 is
available in a space saving 20-lead surface mount plastic package (20 SSOP) and is specified over the industrial (–40°C to
+85°C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
VD
PWRDN
VDD
AD9057
AIN
T/H
ADC
8
D7–D0
1kΩ
BIAS OUT
VREF IN
VREF OUT
+2.5V
GND
ENCODE
Customers desiring multichannel digitization may consider the
AD9059, a dual 8-bit, 60 MSPS monolithic based on the
AD9057 ADC core. The AD9059 is available in a 28-lead surface mount plastic package (28 SSOP) and is specified over the
industrial temperature range.
PIN CONFIGURATION
20 D0 (LSB)
PWRDN 1
VREF OUT 2
19 D1
VREF IN 3
18 D2
GND 4
AD9057
17 D3
VD 5
TOP VIEW 16 GND
(Not to Scale)
BIAS OUT 6
15 VDD
AIN 7
14 D4
VD 8
13 D5
GND 9
12 D6
ENCODE 10
11 D7 (MSB)
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
AD9057–SPECIFICATIONS
Parameter
Temp
Test
Level
(VD = +5 V, VDD = +3 V; external reference)
AD9057BRS-40
Min
Typ
Max
RESOLUTION
DC ACCURACY
Differential Nonlinearity
AD9057BRS-60
Min
Typ
Max
8
8
Bits
0.75
0.75
0.75
LSB
LSB
LSB
LSB
I
VI
I
VI
VI
I
VI
V
+25°C
+25°C
Full
+25°C
+25°C
+25°C
Full
+25°C
V
I
VI
V
V
I
VI
V
BANDGAP REFERENCE
Output Voltage
Temperature Coefficient
Full
Full
VI
V
2.4
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Valid Time (tV)2
Output Propagation Delay (tPD)2
Full
Full
+25°C
+25°C
Full
Full
VI
IV
V
V
IV
IV
40
+25°C
+25°C
V
V
+25°C
+25°C
I
V
42
45.5
44.0
42
45
43.5
+25°C
+25°C
I
V
6.7
7.2
7.0
6.7
+25°C
+25°C
I
V
43
46.5
45.5
+25°C
+25°C
I
V
–50
–46
No Missing Codes
Gain Error1
Gain Tempco1
ANALOG INPUT
Input Voltage Range
(Centered at +2.5 V)
Input Offset Voltage
Input Resistance
Input Capacitance
Input Bias Current
Analog Bandwidth
1.9
2.0
0.75
1.9
2.0
GUARANTEED
–6
–2.5
+6
–8
+8
± 70
–15
–25
1.0
±0
150
2
6
+15
+25
1.9
2.0
0.75
1.9
2.0
GUARANTEED
–6
–2.5
+6
–8
+8
± 70
–15
–25
2.5
± 10
1.0
±0
150
2
6
16
25
120
+15
+25
–15
–25
2.6
2.4
2.5
± 10
1.0
±0
150
2
6
16
25
2.6
2.4
2.5
± 10
4.0
16
25
2.6
80
5
18.0
+15
+25
120
60
2.7
5
6.6
11.5
1.9
2.0
0.75
1.9
2.0
GUARANTEED
–6
–2.5
+6
–8
+8
± 70
120
5
4.0
Units
8
+25°C
Full
+25°C
Full
Full
+25°C
Full
Full
Integral Nonlinearity
AD9057BRS-80
Min
Typ
Max
2.7
5
6.6
9.5
5
4.0
14.2
2.7
5
6.6
8.0
11.3
% FS
% FS
ppm/°C
V p-p
mV
mV
kΩ
pF
µA
µA
MHz
V
ppm/°C
MSPS
MSPS
ns
ps, rms
ns
ns
3
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
fIN = 10.3 MHz
fIN = 76 MHz
Effective Number of Bits
fIN = 10.3 MHz
fIN = 76 MHz
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz
fIN = 76 MHz
2nd Harmonic Distortion
fIN = 10.3 MHz
fIN = 76 MHz
3rd Harmonic Distortion
fIN = 10.3 MHz
fIN = 76 MHz
Two Tone Intermodulation
Distortion (IMD)
Differential Phase
Differential Gain
+25°C
+25°C
I
V
+25°C
+25°C
+25°C
V
V
V
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Encode Pulse Width High (tEH)
Encode Pulse Width Low (tEL)
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
V
IV
IV
9
9
9
9
9
9
ns
ns
41.5
45
43.5
dB
dB
7.2
6.9
6.6
7.2
6.9
Bits
Bits
43
46
45
42.5
46
45
dB
dB
–62
–54
–50
–62
–54
–50
–62
–54
dBc
dBc
–60
–54
–46
–60
–54
–46
–60
–54
dBc
dBc
–52
0.8
1.0
dBc
Degrees
%
–52
0.8
1.0
–52
0.8
1.0
2.0
2.0
2.0
0.8
±1
±1
0.8
±1
±1
4.5
9.0
9.0
4.5
166
166
–2–
0.8
±1
±1
6.7
6.7
4.5
166
166
5.5
5.5
166
166
V
V
µA
µA
pF
ns
ns
REV. B
AD9057
Parameter
Temp
Test
Level
AD9057BRS-40
Min
Typ
Max
AD9057BRS-60
Min
Typ
Max
AD9057BRS-80
Min
Typ
Max
DIGITAL OUTPUTS
Logic “1” Voltage (VDD = +3 V)
Logic “1” Voltage (VDD = +5 V)
Logic “0” Voltage
Offset Binary Code
Full
Full
Full
VI
IV
VI
2.95
4.95
V
V
V
Output Coding
Full
Full
Full
Full
VI
VI
VI
VI
POWER SUPPLY
VD Supply Current (VD = +5 V)
VDD Supply Current (VDD = +3 V)4
Power Dissipation5, 6
Power-Down Dissipation
Power Supply Rejection Ratio
(PSRR)
0.05
36
4.0
192
6
+25°C I
48
6.5
260
10
38
5.5
205
6
15
48
6.5
260
10
15
40
7.4
220
6
Units
51
8.8
281
10
mA
mA
mW
mW
15
mV/V
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).
2
tV and t PD are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed
an ac load of 10 pF or a dc current of ± 40 µA.
3
SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range.
4
Digital supply current based on V DD = +3 V output drive with <10 pF loading under dynamic test conditions.
5
Power dissipation is based on specified encode and 10.3 MHz analog input dynamic test conditions (V D = +5 V ± 5%, VDD = +3 V ± 5%).
6
Typical thermal impedance for the RS style (SSOP) 20-pin package: θJC = 46°C/W, θCA = 80°C/W, θJA = 126°C/W.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
Description
I
II
100% Production Tested
100% Production Tested at +25°C and Sample
Tested at Specified Temperatures
Sample Tested Only
Parameter is Guaranteed by Design and Characterization Testing
Parameter is a Typical Value Only
100% Production Tested at +25°C; Guaranteed by Design and Characterization Testing
for Industrial Temperature Range
III
IV
V
VI
N
N+5
N+3
AIN
N+1
N+4
N+2
tA
ENCODE
tEH
tEL
tV
DIGITAL
OUTPUTS
N–3
N–2
N–1
N
N+1
tPD
MIN
tA
APERTURE DELAY
tEH
PULSE WIDTH HIGH
tEL
PULSE WIDTH LOW
tV
OUTPUT VALID TIME
tPD
OUTPUT PROP DELAY
TYP
166 ns
166 ns
4.0 ns
6.6 ns
9.5 ns
Figure 1. Timing Diagram
REV. B
–3–
MAX
2.7 ns
N+2
AD9057
ABSOLUTE MAXIMUM RATINGS
PIN DESCRIPTIONS
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
VREF Input . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150°C
ORDERING GUIDE
Temperature
Range
Model
Package Option*
AD9057BRS–40, –60, –80 –40°C to +85°C RS-20
AD9057/PCB
+25°C
Evaluation Board
*RS = Shrink Small Outline (SSOP).
Table I. Digital Coding (VREF = +2.5 V)
Analog Input
Voltage Level
Digital Output
3.0 V
2.502 V
2.498 V
2.0
Positive Full Scale
Midscale +1/2 LSB
Midscale –1/2 LSB
Negative Full Scale
1111 1111
1000 0000
0111 1111
0000 0000
Pin No.
Name
Function
1
PWRDN
2
VREF OUT
3
VREF IN
4, 9, 16
5, 8
6
GND
VD
BIAS OUT
7
10
AIN
ENCODE
11–14, 17–20
15
D7–D4, D3–D0
VDD
Power-Down Function Select;
Logic HIGH for Power-Down
Mode (Digital Outputs Go to
High Impedance State).
Internal Reference Output
(+2.5 V typ); Bypass with
0.1 µF to Ground.
Reference Input for ADC (+2.5
V typ, ± 10%).
Ground (Analog/Digital).
Analog +5 V Power Supply.
Bias Pin for AC Coupling
(1 kΩ to REF IN).
Analog Input for ADC.
Encode Clock for ADC (ADC
Samples on Rising Edge of
ENCODE).
Digital Outputs of ADC.
Digital Output Power Supply.
Nominally +3 V to +5 V.
PIN CONFIGURATION
20 D0 (LSB)
PWRDN 1
VREF OUT 2
19 D1
VREF IN 3
18 D2
GND 4
AD9057
17 D3
VD 5
TOP VIEW 16 GND
(Not to Scale)
BIAS OUT 6
15 VDD
AIN 7
14 D4
VD 8
13 D5
GND 9
12 D6
ENCODE 10
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9057 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
11 D7 (MSB)
WARNING!
ESD SENSITIVE DEVICE
REV. B
Typical Performance Characteristics–AD9057
0
–30
ENCODE = 60MSPS
ANALOG IN = 10.3MHz, –0.5dBFS
SINAD = 46.1dB
ENOB = 7.36 BITS
SNR = 46.5dB
–10
–20
ENCODE = 60MSPS
AIN = –0.5dBFS
–35
–40
–30
–45
–40
dB
dB
2ND HARMONIC
–50
–50
–55
–60
3RD HARMONIC
–60
–70
–65
–80
–90
0
–70
30
FREQUENCY – MHz
0
20
40
60
80
100
120
140
160
ANALOG INPUT FREQUENCY – MHz
Figure 2. Spectral Plot 60 MSPS, 10.3 MHz
Figure 5. Harmonic Distortion vs. AIN Frequency
0
0
ENCODE = 60MSPS
–10 ANALOG IN = 76MHz, –0.5dBFS
SINAD = 44.9dB
ENOB = 7.16 BITS
–20 SNR = 45.2dB
ENCODE = 60MSPS
F1 IN = 9.5MHz @ –7.0dBFS
F2 IN = 9.9MHz @ –7.0dBFS
2F1 - F2 = –52.0dBc
2F2 - F1 = –53.0dBc
–10
–20
–30
–40
–40
dB
dB
–30
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
0
30
FREQUENCY – MHz
0
Figure 3. Spectral Plot 60 MSPS, 76 MHz
10
20
FREQUENCY – MHz
30
Figure 6. Two-Tone Intermodulation Distortion
54
48
SNR
46
SNR
48
44
42
SINAD
42
SINAD
36
38
dB
dB
40
ENCODE = 60MSPS
AIN = –0.5dBFS
30
AIN = 10.3MHz, –0.5dBFS
24
36
18
34
12
32
30
0
0
20
40
60
80
100
120
ANALOG INPUT FREQUENCY – MHz
140
5
160
Figure 4. SINAD/SNR vs. AIN Frequency
REV. B
10
20
30
40
50
60
ENCODE RATE – MSPS
70
80
Figure 7. SINAD/SNR vs. Encode Rate
–5–
90
AD9057–Typical Performance Characteristics
350
12
11
300
VDD = +3V
10
VDD = +5V
250
9.5
9.0
tPD – ns
mW
200
VDD = +3V
150
8.5
8.0
VDD = +5V
7.5
100
AIN = 10.3MHz, –0.5dBFS
7.0
50
6.5
0
5
10
20
30
40
50
60
ENCODE RATE – MSPS
70
80
6.0
–45
90
Figure 8. Power Dissipation vs. Encode Rate
0
25
TEMPERATURE – °C
90
Figure 11. tPD vs. Temperature/Supply (VDD = +3 V/+5 V)
46.5
46.5
46.0
SNR
46
45.5
SNR
45.5
45.0
SINAD
44.5
45
44.0
dB
dB
70
43.5
ENCODE = 60MSPS
AIN = 10.3MHz, –0.5dBFS
44.5
44
43.0
SINAD
43.5
42.5
43
42.0
41.5
–45
0
25
TEMPERATURE – °C
70
ENCODE = 60MSPS
AIN = 10.3MHz, –05dBFS
42.5
5.8
90
Figure 9. SINAD/SNR vs. Temperature
6.7
8.35
9.2
7.5
10
ENCODE HIGH PULSE WIDTH – ns
10.9
Figure 12. SINAD/SNR vs. Encode Pulse Width
0
0
–1
–0.2
–2
–0.4
ADC GAIN – dB
GAIN ERROR – %
–3
–0.6
–0.8
–1.0
–1.2
–5
–6
–7
–1.4
–8
–9
–1.6
–1.8
–45
ENCODE = 60MSPS
AIN = –0.5dBFS
–4
–10
0
25
TEMPERATURE – °C
70
1
90
2
5
10
20
50
100
ANALOG FREQUENCY – MHz
200
500
Figure 13. ADC Frequency Response
Figure 10. ADC Gain vs. Temperature (with External
+2.5 V Reference)
–6–
REV. B
AD9057
THEORY OF OPERATION
+5V
The AD9057 combines Analog Devices’ proprietary MagAmp
gray code conversion circuitry with flash converter technology to
provide a high performance, low cost ADC. The design architecture ensures low power, high speed, and 8-bit accuracy. A
single-ended TTL/CMOS compatible ENCODE input controls
ADC timing for sampling the analog input pin and strobing the
digital outputs (D7–D0). An internal voltage reference (VREF
OUT) may be used to control ADC gain and offset or an external reference may be applied.
The analog input signal is buffered at the input of the ADC and
applied to a high speed track-and-hold. The T/H circuit holds
the analog input value during the conversion process (beginning
with the rising edge of the ENCODE command). The T/H’s
output signal passes through the gray code and flash conversion
stages to generate coarse and fine digital representations of the
held analog input level. Decode logic combines the multistage
data and aligns the 8-bit word for strobed outputs on the rising
edge of the ENCODE command. The MagAmp/Flash architecture of the AD9057 results in three pipeline delays for the output data.
USING THE AD9057
Analog Inputs
The AD9057 provides a single-ended analog input impedance of
150 kΩ. The input requires a dc bias current of 6 µA (typical)
centered near +2.5 V (± 10%). The dc bias may be provided by
the user or may be derived from the ADC’s internal voltage
reference. Figure 14 shows a low cost dc bias implementation
allowing the user to capacitively couple ac signals directly into
the ADC without additional active circuitry. For best dynamic
performance, the VREF OUT pin should be decoupled to
ground with a 0.1 µF capacitor (to minimize modulation of
the reference voltage) and the bias resistor should be approximately 1 kΩ. A 1 kΩ bias resistor (± 20%) is included within
the AD9057 and may be used to reduce application board size
and complexity.
+5V
2 REF OUT
0.1µF
3
REF IN
1kΩ
6
BIAS OUT
0.1µF
VIN
(1V p-p)
7 AIN
AD9057
Figure 14. Capacitively Coupled AD9057
Figure 15 shows typical connections for high performance dc
biasing using the ADC’s internal voltage reference. All components may be powered from a single +5 V supply (in the example
analog input signals are referenced to ground).
REV. B
2 REF OUT
10kΩ
10kΩ
AD9057
0.1µF
+5V
3 REF IN
AD8041
7 AIN
1kΩ
VIN
(–0.5V TO +0.5V)
1kΩ
Figure 15. DC Coupled AD9057 (Inverted VIN)
Voltage Reference
A stable and accurate +2.5 V voltage reference is built into the
AD9057 (VREF OUT). The reference output may be used to
set the ADC gain/offset by connecting VREF OUT to VREF IN.
The internal reference is capable of providing 300 µA of drive
current (for dc biasing the analog input or other user circuitry).
Some applications may require greater accuracy, improved
temperature performance, or gain adjustments which cannot be
obtained using the internal reference. An external voltage may
be applied to the VREF IN with VREF OUT disconnected for
gain adjustment of up to ± 10% (the VREF IN pin is internally
tied directly to the ADC circuitry). ADC gain and offset will
vary simultaneously with external reference adjustment with a
1:1 ratio (a 2% or 50 mV adjustment to the +2.5 V reference
varies ADC gain by 2% and ADC input range center offset by
50 mV). Theoretical input voltage range versus reference input
voltage may be calculated from the following equations:
VRANGE (p-p)
= VREF IN/2.5
VMIDSCALE
= VREF IN
VTOP-OF-RANGE
= VREF IN + VRANGE/2
VBOTTOM-OF-RANGE = VREF IN – VRANGE/2
Digital Logic (+5 V/+3 V Systems)
The digital inputs and outputs of the AD9057 can easily be
configured to interface directly with +3 V or +5 V logic systems.
The ENCODE and power-down (PWRDN) inputs are CMOS
stages with TTL thresholds of 1.5 V, making the inputs compatible with TTL, +5 V CMOS, and +3 V CMOS logic families.
As with all high speed data converters, the encode signal should
be clean and jitter free to prevent degradation of ADC dynamic
performance.
The AD9057’s digital outputs will also interface directly with
+5 V or +3 V CMOS logic systems. The voltage supply pin
(VDD) for these CMOS stages is isolated from the analog VD
voltage supply. By varying the voltage on this supply pin the
digital output HIGH level will change for +5 V or +3 V systems.
Optimum SNR is obtained running the outputs at +3 V. Care
should be taken to isolate the VDD supply voltage from the +5 V
analog supply to minimize digital noise coupling into the ADC.
–7–
AD9057
The AD9057 provides high impedance digital output operation
when the ADC is driven into power-down mode (PWRDN,
logic HIGH). A 200 ns (minimum) power-down time should be
provided before a high impedance characteristic is required at
the outputs. A 200 ns power-up period should be provided to
ensure accurate ADC output data after reactivation (valid output
data is available three clock cycles after the 200 ns delay).
full-power analog bandwidth of 2× the maximum sampling
rate, the ADC provides sufficient pixel to pixel transient settling time to ensure accurate 60 MSPS video digitization. Figure 17 shows a typical RGB video digitizer implementation for
the AD9057.
8
RED
AD9057
GREEN
AD9057
BLUE
AD9057
Timing
The AD9057 is guaranteed to operate with conversion rates
from 5 MSPS to 80 MSPS depending on grade. The ADC is
designed to operate with an encode duty cycle of 50%, but performance is insensitive to moderate variations. Pulse width variations of up to ± 10% (allowing the encode signal to meet the
minimum/maximum HIGH/LOW specifications) will cause no
degradation in ADC performance (see Figure 1 timing diagram).
8
8
PIXEL CLOCK
H-SYNC
PLL
Power Dissipation
The power dissipation of the AD9057 is specified to reflect a
typical application setup under the following conditions: analog
input is –0.5 dBFS at 10.3 MHz, VD is +5 V, VDD is +3 V, and
digital outputs are loaded with 7 pF typical (10 pF maximum).
The actual dissipation will vary as these conditions are modified
in user applications. Figure 8 shows typical power consumption
for the AD9057 versus ADC encode frequency and VDD supply
voltage.
Figure 17. RGB Video Encoder
Evaluation Board
A power-down function allows users to reduce power dissipation
when ADC data is not required. A TTL/CMOS HIGH signal
(PWRDN) shuts down portions of the ADC and brings total
power dissipation to less than 10 mW. The internal bandgap
voltage reference remains active during power-down mode to
minimize ADC reactivation time. If the power-down function is
not desired, Pin 1 should be tied to ground.
APPLICATIONS
The wide analog bandwidth of the AD9057 makes it attractive
for a variety of high performance receiver and encoder applications. Figure 16 shows two ADCs in a typical low cost I & Q
demodulator implementation for cable, satellite, or wireless
LAN modem receivers. The excellent dynamic performance of
the ADC at higher analog input frequencies and encode rates
empowers users to employ direct IF sampling techniques (refer
to Figure 3 spectral plot). IF sampling eliminates or simplifies
analog mixer and filter stages to reduce total system cost and
power.
IF IN
BPF
AD9057
BPF
AD9057
For dc coupled analog input applications, amplifier U2 is configured to operate as a unity gain inverter with adjustable offset
for the analog input signal. For full-scale ADC drive the analog
input signal should be 1 V p-p into 50 Ω (R1) referenced to
ground (0 V). The amplifier offsets the analog signal by
+VREF (+2.5 V typical) to center the voltage for proper ADC
input drive. For dc coupled operation, connect E1 to E2 (analog input to R2) and E11 to E12 (amplifier output to analog
input of AD9057) using the board jumper connectors. DC
offset of the analog input signal can be modified by adjusting
potentiometer R10.
For ac coupled analog input applications, amplifier U2 is
removed from the analog signal path. The analog signal is
coupled into the input of the AD9057 through capacitor C2.
The ADC pulls analog input bias current from the VREF IN
voltage through the 1 kΩ resistor internal to the AD9057
(BIAS OUT). The analog input signal to the board should be
1 V p-p into 50 Ω (R1) for full-scale ADC drive. For ac
coupled operation, connect E1 to E3 (analog input A to C2
feedthrough capacitor) and E10 to E12 (C2 to the analog input
and internal bias resistor) using the board jumper connectors.
90°
VCO
The AD9057/PCB evaluation board provides an easy to use
analog/digital interface for the 8-bit, 60 MSPS ADC. The
board includes typical hardware configurations for a variety of
high speed digitization evaluations. On board components
include the AD9057 (in the 20-pin SSOP package), an optional
analog input buffer amplifier, a digital output latch, board
timing drivers, an analog reconstruction digital-to-analog converter, and configurable jumpers for ac coupling, dc coupling,
and power-down function testing. The board is configured at
shipment for dc coupling using the AD9057’s internal voltage
reference.
VCO
The onboard reference voltage may be used to drive the ADC
or an external reference may be applied. To use the internal
voltage reference, connect E6 to E5 (VREF OUT to VREF
IN). To apply an external voltage reference, connect E4 to E5
(external reference from the REF banana jack to VREF IN).
The external voltage reference should be +2.5 V ± 10%.
Figure 16. I & Q Digital Receiver
The high sampling rate and analog bandwidth of the AD9057
are ideal for computer RGB video digitizer applications. With a
–8–
REV. B
AD9057
The power-down function of the AD9057 can be exercised
through a board jumper connection. Connect E7 to E9 (+5 V to
PWRDN) for power-down operation. For normal operation,
connect E8 to E9 (ground to PWRDN).
The encode signal source should be TTL/CMOS compatible
and capable of driving a 50 Ω termination (R7). The digital
outputs of the AD9057 are buffered through latches on the
evaluation board (U3) and are available for the user at connector Pins 30–37. Latch timing is derived from the ADC ENCODE clock and a digital clocking signal is provided for the
board user at connector Pins 2 and 21.
An onboard reconstruction digital-to-analog converter is
available for quick evaluations of ADC performance using an
oscilloscope or spectrum analyzer. The DAC converts the
ADC’s digital outputs to an analog signal for examination at
the DAC OUT connector. The DAC is clocked at the ADC
ENCODE frequency. The AD9760 is a 10-bit/100 MSPS single
+5 V supply DAC. The reconstruction signal facilitates quick
system troubleshooting or confirmation of ADC functionality
without requiring external digital memory, timing, or display
interfaces. The DAC can be used for limited dynamic testing,
but customers should note that test results will be based on the
combined performance of the ADC and DAC (the best ADC
performance will be recognized by evaluating the digital outputs
of the ADC directly).
+VD
+VD
ENCODE
500Ω
VREFIN
AIN
PWRDN
Digital Inputs
Analog Input
+VDD, +3V TO +5V
+VD
1kΩ
VREFIN
D0–D7
BIAS OUT
Bias Output
Digital Outputs
+VD
+VD
3kΩ
VREFIN
VREFOUT
2.5kΩ
VREF Output
VREF Input
Figure 18. Equivalent Circuits
REV. B
–9–
AD9057
E7
+5V
J6, REF
ANALOG IN
BNC
J1
C17
0.1µF
U2
AD8041Q
R2
E2 1kΩ
1
NC
2
3
4
–VS
E1
E3
C37DRPF
P2
E4
DIS
+VS
NC
8
7
6
5
R3
1kΩ
R1
50Ω
GND
PWRDN
E9
E8
E5
E6
R5
2kΩ
C1
0.1µF
R10
500Ω
GND
+5V
R4
2kΩ
R6
10Ω
+5V
GND
E11
E12
1
2
3
4
5
PWRDN
(LSB) D0
REF OUT
D1
REF IN
D2
GND
D3
VD
GND
6
BIAS OUT
VDD
7
AIN
D4
8
VD
D5
9
GND
D6
10
ENC
(MSB) D7
20
19
18
17
16
15
14
13
12
11
D0
D1
D2
D3
GND
VDD
D4
D5
D6
D7
1
2
3
4
5
U3
74ACQ574
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
8D
7D
6D
5D
4D
3D
2D
1D
CK
4
3
2
E10
11
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
12
13
14
15
16
DA7
DA6
DA5
DA4
DA3
17
DA2
18
DA1
19
DA0
6
7
8
9
10
11
12
OE
13
14
1
C2
0.1µF
15
16
17
18
19
20
21
U4
74AC00
BNC
J3
1
3
2
ENCODE
R7
50Ω
U4
74AC00
4
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
GND
GND
6
5
U4
74AC00
12
11
13
U4
74AC00
9
8
10
J7, VDD
ANALOG
RECONSTRUCT
DAC OUT
VDD
C10 +
0.1µF
C11
10µF
1
2
3
4
5
6
7
8
9
10
BNC
J2
CLK
DVDD
(MSB)
DB9
AVDD
DB8
COMP2
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
(LSB)
R8
50Ω
+5V
27
24
+5V
+5V
C18
0.1µF
23
19
C19
0.1µF
COMP1
FSADJ
REFIO
18
17
16
R9
2kΩ
REFLO
SLEEP
IOUT
A
B
22
22
23
24
25
26
DAC
AD9760AR
28
21
15
C13
0.1µF
27
28
29
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
30
31
32
33
34
35
36
37
PWRDN
R11
50Ω
J4, GND
C7
0.1µF
C8
0.1µF
C14
0.1µF
J5, +5V
C3
0.1µF
C4
0.1µF
C5
0.1µF
+
C9
0.1µF
C12
10µF
DECOUPLING CAPS
Figure 19. Evaluation Board Schematic
–10–
REV. B
AD9057
Figure 20. Evaluation Board Layout
REV. B
–11–
AD9057
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C2156b–2–4/97
20-Lead SSOP
(RS-20)
0.295 (7.50)
0.271 (6.90)
11
1
10
0.311 (7.9)
0.301 (7.64)
0.212 (5.38)
0.205 (5.21)
20
0.07 (1.78)
0.066 (1.67)
0.008 (0.203)
0.002 (0.050)
0.0256
(0.65)
BSC
SEATING 0.009 (0.229)
PLANE
0.005 (0.127)
8°
0°
0.037 (0.94)
0.022 (0.559)
PRINTED IN U.S.A.
0.078 (1.98) PIN 1
0.068 (1.73)
–12–
REV. B