Sample & Buy Product Folder Support & Community Tools & Software Technical Documents BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 BQ32002 Real-Time Clock (RTC) 1 Features 3 Description • • The BQ32002 device is a compatible replacement for industry standard real-time clocks. 1 • • • • Automatic Switchover to Backup Supply I2C Interface Supports Serial Clock up to 400 kHz Uses 32.768-kHz Crystal With –63-ppm to +126-ppm Adjustment Integrated Oscillator-Fail Detection 8-Pin SOIC Package –40°C to +85°C Ambient Operating Temperature 2 Applications General Consumer Electronics The BQ32002 features an automatic backup supply that can be implemented using a capacitor or nonrechargeable battery. The BQ32002 has a programmable calibration adjustment from –63 ppm to +126 ppm. The BQ32002 registers include an OF (oscillator fail) flag indicating the status of the RTC oscillator, as well as a STOP bit that allows the host processor to disable the oscillator. The time registers are normally updated once per second, and all the registers are updated at the same time to prevent a timekeeping glitch. The BQ32002 includes automatic leap-year compensation. Device Information(1) PART NUMBER BQ32002 PACKAGE SOIC (8) BODY SIZE (NOM) 4.90 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Application Circuit Simplified Schematic VCC Place supply-decoupling capacitor near supply pin 3.0 to 3.6 V 1 µF BQ32002 VCC VBACK Automatic Backup Switch VCORE Interrupt Generator OSCI OSCO 4.7 kW 32-kHz Oscillator I2C Register Interface With Undervoltage Lockout 4.7 kW 4.7 kW IRQ SCL Controller VCC SCL SDA ____ IRQ Real-Time Clock Copyright © 2016, Texas Instruments Incorporated SDA Registers GND Copyright © 2016, Texas Instruments Incorporated NOTE: All pullup resistors should be connected to VCC such that no pullup is applied during backup supply operation. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 6 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Detailed Description .............................................. 7 7.1 Overview ................................................................... 7 7.2 Functional Block Diagram ......................................... 7 7.3 Feature Description................................................... 7 7.4 Device Functional Modes........................................ 10 7.5 Programming........................................................... 10 7.6 Register Maps ......................................................... 12 8 Application and Implementation ........................ 19 8.1 Application Information............................................ 19 8.2 Typical Application .................................................. 19 9 Power Supply Recommendations...................... 21 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 10.2 Layout Example .................................................... 21 11 Device and Documentation Support ................. 22 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History Changes from Revision A (December 2010) to Revision B Page • Added Pin Configuration and Functions section, ESD Ratings section, Thermal Information section, Detailed Description section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................ 1 • Deleted Trickle Charge Pump from Functional Block Diagram/Application Circuit ............................................................... 1 • Changed Crystal series resistance maximum from 40 kΩ to 70 kΩ in Recommended Operating Conditions ...................... 4 • Added Recommended Operating Conditions table note (1) Crystal load capacitance ±10% is allowed. ............................. 4 2 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 BQ32002 www.ti.com SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 5 Pin Configuration and Functions D Package 8-Pin SOIC Top View OSCI 1 8 VCC OSCO 2 7 IRQ VBACK 3 6 SCL GND 4 5 SDA Pin Functions PIN NAME NO. TYPE DESCRIPTION POWER AND GROUND VCC 8 — Main device power GND 4 — Ground VBACK 3 — Backup device power SERIAL INTERFACE I2C serial interface clock SCL 6 I SDA 5 I/O I2C serial data 7 O Configurable interrupt output. Open-drain output. OSCI 1 — Oscillator input OSCO 2 — Oscillator output INTERRUPT IRQ OSCILLATOR Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 3 BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC to GND –0.3 4 UNIT All other pins to GND –0.3 VCC + 0.3 VIN Input voltage TJ Operating junction temperature –40 150 °C Tstg Storage temperature after reflow –60 150 °C (1) V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN VCC Supply voltage, VCC to GND TA Operating free-air temperature fo Crystal resonant frequency RS Crystal series resistance CL Crystal load capacitance (1) (1) NOM MAX UNIT 3 3.6 V –40 85 °C 32.768 kHz 70 12 kΩ pF Crystal load capacitance ±10% is allowed. 6.4 Thermal Information BQ32002 THERMAL METRIC (1) D (SOIC) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 114.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 59.1 °C/W RθJB Junction-to-board thermal resistance 55.5 °C/W ψJT Junction-to-top characterization parameter 11.9 °C/W ψJB Junction-to-board characterization parameter 55 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 BQ32002 www.ti.com SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT 200 μA POWER SUPPLY ICC VCC supply current VBACK Backup supply voltage IBACK Backup supply current VSO Switchover voltage 65 Operating Switchover 1.4 VCC 2 VCC 0.9 (1) VCC = 0 V, VBAT = 3 V, Oscillator on, TA = 25°C Operating → Backup 1.8 Backup → Operating 2.4 1.5 V μA V LOGIC LEVEL INPUTS VIL Input low voltage VIH Input high voltage IIN Input current 0.3 × VCC 0.7 × VCC 0 V ≤ VIN ≤ VCC V V –1 1 μA LOGIC LEVEL OUTPUTS VOL Output low voltage IL Leakage current IOL = 3 mA –1 0.4 V 1 μA REAL-TIME CLOCK CHARACTERISTICS Pre-calibration accuracy (1) (2) VCC = 3.3 V, VBAT = 3 V, Oscillator on, TA = 25°C ±35 (2) ppm The backup supply current is measured only after an initial power up. The device behavior is not ensured before the first power up. Typical accuracy is measured using reference board design and KDS DMX-26S surface-mount 32.768-kHz crystal. Variation in board design and crystal section results in different typical accuracy. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 5 BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 www.ti.com 6.6 Timing Requirements STANDARD MODE PARAMETER MIN fscl I2C clock frequency 0 tsch I2C clock high time 4 2 tscl I C clock low time tsp I2C spike time tsds I2C serial data setup time NOM FAST MODE MAX MIN 100 MAX 0 400 50 0 250 50 100 0 kHz μs 1.3 0 UNIT μs 0.6 4.7 2 NOM ns ns tsdh I C serial data hold time ticr I2C input rise time 1000 20 + 0.1Cb (1) 0 300 ns ticf I2C input fall time 300 20 + 0.1Cb (1) 300 ns 20 + 0.1Cb (1) 300 μs 2 300 ns tocf I C output fall time tbuf I2C bus free time 4.7 1.3 μs tsts I2C Start setup time 4.7 0.6 μs tsth I2C Start hold time 4 0.6 μs 2 I C Stop setup time tvd (data) Valid data time (SCL low to SDA valid) 1 1 μs (ack) Valid data time of ACK (ACK signal from SCL low to SDA low) 1 1 μs tvd (1) 4 μs tsps 0.6 Cb = total capacitance of one bus line in pF 6.7 Typical Characteristics VCC = 2 V Iback (uA) 45 20 100 Icc (uA) 107.5 90 15 80 106 70 40 10 50 35 40 30 30 ICC (uA) 60 Iback (uA) ICC (uA) VCC = 3.3 V 104.5 5 103 Iback (uA) 50 0 20 101.5 10 25 -10 20 0.5 1.0 1.5 2.0 Vbackup (V) 2.5 2.4 -10 2.9 3.4 Vbackup (V) C001 Figure 1. Current Consumption vs Backup Supply Voltage 6 Iback (uA) 100 3.0 -5 Icc (uA) 0 3.9 C002 Figure 2. Current Consumption vs Backup Supply Voltage Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 BQ32002 www.ti.com SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 7 Detailed Description 7.1 Overview The BQ32002 is a real-time clock that features an automatic backup supply with integrated oscillator-fail detection. 7.2 Functional Block Diagram VCC Place supply-decoupling capacitor near supply pin 1 µF VCC Automatic Backup Switch VBACK Use only super-capacitor or battery, not both .22 F VCC VCORE 4.7 NŸ Interrupt Generator IRQ I2C Register Interface With Undervoltage Lockout SCL 4.7 NŸ 4.7 NŸ OSCI 32-kHz Oscillator SDA OSCO Registers GND Copyright © 2016, Texas Instruments Incorporated NOTE: All pullup resistors should be connected to VCC such that no pullup is applied during backup supply operation. 7.3 Feature Description 7.3.1 IRQ Function The IRQ pin of the BQ32002 functions as a general-purpose output or a frequency test output. The function of IRQ is configurable in the device register space by setting the FT, FTF, and OUT bits. On initial power cycles, the OUT bit is set to one, and the FTF and FT bits are set to zero. On subsequent power-ups, with backup supply present, the OUT bit remains unchanged, and the FTF and FT bits are set to zero. When operating on backup supply, the IRQ pin function is unused. IRQ pullup resistor must be tied to VCC to prevent IRQ operation when operating on backup supply. The effect of the calibration logic is not normally observable when IRQ is configured to output 1 Hz. The calibration logic functions by periodically adjusting the width of the 1-Hz clock. The calibration effect is observable only every eight or sixteen minutes, depending on the sign of the calibration. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 7 BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 www.ti.com Feature Description (continued) Figure 3. IRQ Pin Functional Diagram Table 1. IRQ Function 8 FT OUT FTF 1 X 1 1 Hz 1 X 0 512 Hz 0 1 X 1 0 0 X 0 Submit Documentation Feedback IRQ STATE Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 BQ32002 www.ti.com SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 7.3.2 VBACK Switchover The BQ32002 has an internal switchover circuit that causes the device to switch from main power supply to backup power supply when the voltage of the main supply pin VCC drops below a minimum threshold. The VBACK switchover circuit uses an internal reference voltage VREF derived from the on-chip bandgap reference; VREF is approximately 1.8 V. The device switches to the VBACK supply when VCC is less than the lesser of VBACK or VREF. Similarly, the device switches to the VCC supply when VCC is greater than either VBACK or VREF. Some registers are reset to default values when the RTC switches from main power supply to backup power supply. See the register definitions to determine what register bits are effected by a backup switchover (effected bits have their reset value (1/0) shown for Cycle, bits that are unchanged by backup are marked UC). The time-keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. V BACK > VREF V BACK > VREF 3.3V VB AC K VR E F VCC Voltage Voltage VC C –5 V/ms (max) 3.3V VB AC K VR E F T ime On VC C Time On V BAC K On V BAC K V REF > V BACK V REF > V BACK 3.3V 3.3V VR E F VR E F Voltage VB AC K VCC Voltage VB AC K VCC –5 V/ms (max) T ime On VC C On V C C Time On V BAC K On V BAC K On V C C Figure 4. Switchover Diagram Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 9 BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 www.ti.com 7.4 Device Functional Modes When the device switches from the main power supply to backup supply, the time-keeping registers [0- 9] cannot be accessed through the I2C. The access to these registers are only when VCC > VREF. The time-keeping registers can take up to 1 second to update after the device switches from backup power supply to main power supply. 7.5 Programming 7.5.1 I2C Serial Interface The I2C interface allows control and monitoring of the RTC by a microcontroller. I2C is a two-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with off-chip pullup resistors. When the bus is idle, both SDA and SCL lines are pulled high. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. This device operates only as a slave device. I2C communication is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while SCL is held high. After the start condition, the device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W). After receiving a valid address byte, this device responds with an acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. This device responds to the I2C slave address 11010000b for write commands and slave address 11010001b for read commands. This device does not respond to the general call address. A data byte follows the address acknowledge. If the R/W bit is low, the data is written from the master. If the R/W bit is high, the data from this device are the values read from the register previously selected by a write to the subaddress register. The data byte is followed by an acknowledge sent from this device. Data is output only if complete bytes are received and acknowledged. A stop condition, which is a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the master to terminate the transfer. A master device must wait at least 60 μs after the RTC exits backup mode to generate a START condition. 10 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 BQ32002 www.ti.com SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 Programming (continued) ticf SDA ticr tsdh tvd 0.7 VCC 0.3 VCC Start Condition ticf ticr tsds tsch SCL 0.7 VCC 1 0.3 VCC 2 3 4 tscl tsth 1/fscl Stop Condition tvd SDA 0.7 VCC tbuf D7/A 0.3 VCC Start Condition tsds SCL 0.7 VCC 8 0.3 VCC 9 tsps Figure 5. I2C Timing Diagram Slave Address (DN) 0 Sub Address R (DN+1) 0 0 0 Slave Address ACK 0 0 0W ACK START 0 1 S DataN DataN+1 NACK STOP 1 1 (AN) ACK 1 ACK START 1 1 S Figure 6. I2C Read Mode Figure 7. I2C Write Mode Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 11 BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 www.ti.com 7.6 Register Maps Table 2. Normal Registers REGISTER ADDRESS (HEX) REGISTER NAME 0 0x00 SECONDS Clock seconds and STOP bit 1 0x01 MINUTES Clock minutes 2 0x02 CENT_HOURS 3 0x03 DAY Clock day 4 0x04 DATE Clock date 5 0x05 MONTH Clock month 6 0x06 YEARS Clock years 7 0x07 CAL_CFG1 9 0x09 CFG2 DESCRIPTION Clock hours, century, and CENT_EN bit Calibration and configuration Configuration 2 Table 3. Special Function Registers REGISTER ADDRESS (HEX) REGISTER NAME 32 0x20 SF KEY 1 Special function key 1 33 0x21 SF KEY 2 Special function key 2 34 0x22 SFR DESCRIPTION Special function register 7.6.1 I2C Read After Backup Mode The time-keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. An I2C read of the RTC that starts before the update has completed will return the time when the RTC enters backup mode. To ensure that the correct time is read after backup mode, the host should wait longer than 1 second after the main supply is greater than 2.8 V and VBACK. 12 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 BQ32002 www.ti.com SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 7.6.2 Normal Register Descriptions Table 4. SECONDS Register Address Name Initial Value Description D7 STOP r/w 0 UC STOP 10_SECOND 1_SECOND 0x00 SECONDS 0XXXXXXb Clock seconds and STOP bit D6 X UC D5 10_SECOND r/w X UC D4 D3 D2 D1 D0 X UC X UC 1_SECOND r/w X UC X UC X UC BIT(S) Name Read/Write Initial Cycle Oscillator stop. The STOP bit is used to force the oscillator to stop oscillating. STOP is set to 0 on initial application of power, on all subsequent power cycles STOP remains unchanged. On initial power application STOP can be written to 1 and then written to 0 to force start the oscillator. 0 Normal 1 Stop BCD of tens of seconds. The 10_SECOND bits are the BCD representation of the number of tens of seconds on the clock. Valid values are 0 to 5. If invalid data is written to 10_SECOND, the clock will update with invalid data in 10_SECOND until the counter rolls over; thereafter, the data in 10_SECOND is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. BCD of seconds. The 1_SECOND bits are the BCD representation of the number of seconds on the clock. Valid values are 0 to 9. If invalid data is written to 1_SECOND, the clock will update with invalid data in 1_SECOND until the counter rolls over; thereafter, the data in 1_SECOND is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. Table 5. MINUTES Register Address Name Initial Value Description D7 OF r/w 1 0 OF 10_MINUTE 1_MINUTE 0x01 MINUTES 1XXXXXXb Clock minutes D6 X UC D5 10_MINUTE r/w X UC D4 D3 D2 D1 D0 X UC X UC 1_MINUTE r/w X UC X UC X UC BIT(S) Name Read/Write Initial Cycle Oscillator fail flag. The OF bit is a latched flag indicating when the 32.768-kHz oscillator has dropped at least four consecutive pulses. The OF flag is always set on initial power-up, and it can be cleared through the serial interface. When OF is 0, no oscillator failure has been detected. When OF is 1, the oscillator fail detect circuit has detected at least four consecutive dropped pulses. 0 No failure detected 1 Failure detected BCD of tens of minutes. The 10_MINUTE bits are the BCD representation of the number of tens of minutes on the clock. Valid values are 0 to 5. If invalid data is written to 10_MINUTE, the clock will update with invalid data in 10_MINUTE until the counter rolls over; thereafter, the data in 10_MINUTE is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. BCD of minutes. The 1_MINUTE bits are the BCD representation of the number of minutes on the clock. Valid values are 0 to 9. If invalid data is written to 1_MINUTE, the clock will update with invalid data in 1_MINUTE until the counter rolls over; thereafter, the data in 1_MINUTE is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 13 BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 www.ti.com Table 6. CENT_HOURS Register Address Name Initial Value Description D7 CENT_EN r/w X UC CENT_EN CENT 10_HOUR 1_HOUR 0x02 CENT_HOURS XXXXXXXXb Clock hours, century, and CENT_EN bit D6 CENT r/w X UC D5 D4 D3 D2 10_HOUR r/w X UC D1 D0 X UC X UC 1_HOUR r/w X UC X UC X UC BIT(S) Name Read/Write Initial Cycle Century enable. The CENT_EN bit enables the century timekeeping feature. If CENT_EN is set to 1, then the clock tracks the century using the CENT bit. If CENT_EN is set to 0, the clock ignores the CENT bit. 0 Century disabled 1 Century enabled Century. The CENT bit tracks the century when century timekeeping is enabled. The clock toggles the CENT bit when the year count rolls from 99 to 00. Because the clock compliments the CENT bit, the user can define the meaning of CENT (1 for current century and 0 for next century, or 0 for current century and 1 for next century). BCD of tens of hours (24-hour format). The 10_HOUR bits are the BCD representation of the number of tens of hours on the clock, in 24-hour format. Valid values are 0 to 2. If invalid data is written to 10_HOUR, the clock will update with invalid data in 10_HOUR until the counter rolls over; thereafter, the data in 10_HOUR is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. BCD of hours (24-hour format). The 1_HOUR bits are the BCD representation of the number of hours on the clock, in 24hour format. Valid values are 0 to 9. If invalid data is written to 1_HOUR, the clock will update with invalid data in 1_HOUR until the counter rolls over; thereafter, the data in 1_HOUR is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. Table 7. DAY Register Address Name Initial Value Description D7 D6 0 0 0 0 RSVD DAY 14 0x03 DAY 00000XXXb Clock day D5 RSVD r/w 0 0 D4 D3 D2 0 0 0 0 X UC D1 DAY r/w X UC D0 X UC BIT(S) Name Read/Write Initial Cycle Reserved. The RSVD bits should always be written as 0. BCD of the day of the week. The DAY bits are the BCD representation of the day of the week. Valid values are 1 to 7 and represent the days from Sunday to Saturday. DAY updates if set to 0 until the counter rolls over; thereafter, the data in DAY is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. 1 Sunday 2 Monday 3 Tuesday 4 Wednesday 5 Thursday 6 Friday 7 Saturday Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 BQ32002 www.ti.com SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 Table 8. DATE Register Address Name Initial Value Description D7 0x04 DATE 00XXXXXXb Clock date D6 D5 RSVD r/w 0 0 RSVD 10_DATE 1_DATE (1) D4 D3 D2 10_DATE r/w 0 0 X UC D1 D0 X UC X UC 1_DATE r/w X UC X UC X UC BIT(S) Name Read/Write Initial Cycle Reserved. The RSVD bits should always be written as 0. BCD of tens of date. The 10_DATE bits are the BCD representation of the tens of date on the clock. Valid values are 0 to 3 (1). If invalid data is written to 10_DATE, the clock will update with invalid data in 10_DATE until the counter rolls over; thereafter, the data in 10_DATE is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. BCD of date. The 1_DATE bits are the BCD representation of the date on the clock. Valid values are 0 to 9 (1). If invalid data is written to 1_DATE, the clock will update with invalid data in 1_DATE until the counter rolls over; thereafter, the data in 1_DATE is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. 10_DATE and 1_DATE must form a valid date, 01 to 31, dependent on month and year. Table 9. MONTH Register Address Name Initial Value Description D7 0 0 RSVD 10_MONTH 1_MONTH (1) 0x05 MONTH 000XXXXXb Clock month D6 RSVD r/w 0 0 D5 0 0 D4 10_MONTH r/w X UC D3 D2 D1 D0 X UC X UC 1_MONTH r/w X UC X UC BIT(S) Name Read/Write Initial Cycle Reserved. The RSVD bits should always be written as 0. BCD of tens of month. The 10_MONTH bits are the BCD representation of the tens of month on the clock. Valid values are 0 to 1 (1). If invalid data is written to 10_MONTH, the clock will update with invalid data in 10_MONTH until the counter rolls over; thereafter, the data in 10_MONTH is valid. BCD of month. The 1_MONTH bits are the BCD representation of the month on the clock. Valid values are 0 to 9 (1). If invalid data is written to 1_MONTH, the clock will update with invalid data in 1_MONTH until the counter rolls over; thereafter, the data in 1_MONTH is valid. 10_MONTH and 1_MONTH must form a valid date, 01 to 12. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 15 BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 www.ti.com Table 10. YEARS Register Address Name Initial Value Description D7 0x06 YEARS XXXXXXXXb Clock year D6 D5 D4 D3 D2 10_YEAR r/w X UC 10_YEAR 1_YEAR X UC D1 D0 X UC X UC 1_YEAR r/w X UC X UC X UC X UC BIT(S) Name Read/Write Initial Cycle BCD of tens of years. The 10_YEAR bits are the BCD representation of the tens of years on the clock. Valid values are 0 to 9. If invalid data is written to 10_YEAR, the clock will update with invalid data in 10_YEAR until the counter rolls over; thereafter, the data in 10_YEAR is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. BCD of year. The 1_YEAR bits are the BCD representation of the years on the clock. Valid values are 0 to 9. If invalid data is written to 1_YEAR, the clock will update with invalid data in 1_YEAR until the counter rolls over; thereafter, the data in 1_YEAR is valid. Time keeping registers can take up to 1 second to update after the RTC switches from backup power supply to main power supply. Table 11. CAL_CFG1 Register Address Name Initial Value Description D7 OUT r/w 1 UC OUT FT S CAL 0x07 CAL_CFG1 10000000b Calibration and control D6 FT r/w 0 UC D5 S r/w 0 UC D4 D3 0 UC 0 UC D2 CAL r/w 0 UC D1 D0 0 UC 0 UC BIT(S) Name Read/Write Initial Cycle Logic output, when FT = 0. When FT is zero, the logic output of IRQ pin reflects the value of OUT. 0 IRQ is logic 0 1 IRQ is logic 1 Frequency test. The FT bit is used to enable the frequency test signal on the IRQ pin. When FT is 1, a square wave is produced on the IRQ pin. The FTF bit in the SFR register determines the frequency of the test signal. 0 Disable 1 Enable Calibration sign. The S bit determines the polarity of the calibration applied to the oscillator. If S is 0, then the calibration slows the RTC. If S is 1, then the calibration speeds the RTC. 0 Slowing (+) 1 Speeding (–) Calibration. The CAL bits along with S determine the calibration amount as shown in Table 12. Table 12. Calibration 16 CAL (DEC) S=0 S=1 0 +0 ppm –0 ppm 1 +2 ppm –4 ppm N +N / 491520 (per minute) –N / 245760 (per minute) 30 +61 ppm –122 ppm 31 +63 ppm –126 ppm Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 BQ32002 www.ti.com SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 Table 13. CFG2 Register Address Name Initial Value Description D7 RSVD r/w 1 1 RSVD 0x09 CFG2 10101010b Configuration 2 D6 RSVD r/w 0 0 D5 D4 D3 D2 RSVD r/w 1 UC D1 D0 1 1 0 0 RSVD r/w 0 UC 1 1 0 0 BIT(S) Name Read/Write Initial Cycle Reserved. The RSVD bits should always be written as 0. 7.6.3 Special Function Registers Table 14. SF KEY 1 Register Address Name Initial Value Description D7 0x20 SF KEY 1 00000000b Special function key 1 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 SF KEY B1 r/w 0 0 SF KEY B1 0 0 0 0 0 0 BIT(S) Name Read/Write Initial Cycle Special function access key byte 1. Reads as 0x00, and key is 0x5E. The SF KEY 1 and SF KEY 2 registers are used to enable access to the main special function register (SFR). Access to SFR is granted only after the special function keys are written sequentially to SF KEY 1 and SF KEY 2. Each write to the SFR must be preceded by writing the SF keys to the SF key registers, in order, SF KEY 1 then SF KEY 2. Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 17 BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 www.ti.com Table 15. SF KEY 2 Register Address Name Initial Value Description D7 0x21 SF KEY 2 00000000b Special function key 2 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 SF KEY 2 r/w 0 0 SF KEY 2 0 0 0 0 0 0 BIT(S) Name Read/Write Initial Cycle Special function access key byte 2. Reads as 0x00, and key is 0xC7. The SF KEY 1 and SF KEY 2 registers are used to enable access to the main special function register (SFR). Access to SFR is granted only after the special function keys are written sequentially to SF KEY 1 and SF KEY 2. Each write to the SFR must be preceded by writing the SF keys to the SF key registers, in order, SF KEY 1 then SF KEY 2. Table 16. SFR Register Address Name Initial Value Description D7 D6 D5 0 0 0 0 0 0 RSVD FTF 18 0x22 SFR 00000000b Special function register 1 D4 RSVD r/w 0 0 D3 D2 D1 0 0 0 0 0 0 D0 FTF r/w 0 0 BIT(S) Name Read/Write Initial Cycle Reserved. The RSVD bits should always be written as 0. Force calibration to 1 Hz. FTF allows the frequency of the calibration output to be changed from 512 Hz to 1 Hz. By default, FTF is cleared, and the RTC outputs a 512-Hz calibration signal. Setting FTF forces the calibration signal to 1 Hz, and the calibration tracks the internal ppm adjustment. Note: The default 512-Hz calibration signal does not include the effect of the ppm adjustment. 0 Normal 512-Hz calibration 1 1-Hz calibration Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 BQ32002 www.ti.com SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The typical application for the BQ32002 is to provide precise time and date to a system. The backup power supply provides additional reliability by automatically switching over from the main supply when it drops under the voltage threshold. 8.2 Typical Application The following design is a common application of the BQ32002. V CC bq32002 V CC OSCI 32.768 kHz 1 µF 4.7 kΩ OSCO 4.7 kΩ 4.7 kΩ IRQ V BACK SCL SDA GND Copyright © 2016, Texas Instruments Incorporated Figure 8. Typical Application Schematic 8.2.1 Design Requirements Table 17 lists the parameters for this design example. Table 17. Design Parameters DESIGN PARAMETER REFERENCE Supply Voltage VCC EXAMPLE VALUE 3.3 V Backup Supply VBACK BR1225 Crystal Oscillator XT 32.768 kHz Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 19 BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 www.ti.com 8.2.2 Detailed Design Procedure 8.2.2.1 Reading From a Register The report details the read-back of the SECONDS register. Figure 9 depicts the first condition that will be used as a benchmark to compare the values taken from the SECONDS register in the BQ32002, to the internal PC time of the oscilloscope. In this example two modes of operation are demonstrated. Condition 1 The main power supply, VCC, is greater than the backup power supply, VBACK, and the internal reference voltage, VREF. In this mode, the device's internal registers are fully operational with READ and WRITE access. Analyzing Figure 9, the known register values are compared to the system clock; in this case, the PC clock which is shown at the bottom of the screen capture. The BQ32002 during this condition is reading back [101][0010]= [5][2], which corresponds to 52 seconds at PC time of 2:22:43 PM. Condition 2 VCC is now lowered to 2 V (VBACK > VCC). In this mode, the I2C communications are halted. However, the internal time-keeping registers maintain full functional operation and accuracy which will be available to be reliably read by the controller 1 second after the RTC switches from VBACK to VCC supply. Condition 3 During this final test condition, the RTC is restored to operate from the main power supply and I2C communications are now fully functional. Figure 10 demonstrates a read-back value from the SECONDS register of [100][0101]= [4][5], or 45 seconds at PC time of 2:23:36 PM. This proves that the BQ32002 managed to accurately maintain the time-keeping registers functional while the VCC dropped below VBACK. 8.2.2.2 Leap Year Compensation The BQ32002 classifies a leap year as any year that is evenly divisible by 4. Using this rule allows for reliable leap year compensation until 2100. Years that fall outside this rule will need to be compensated for by the external controller. 8.2.2.3 Utilizing the Backup Supply In order for the BQ32002 to achieve a low backup supply current as specified in the Electrical Characteristics, the VCC pin must be initialized after every total power loss situation. Initialization Is achieved by powering on VCC with a voltage between 3 to 3.6 V for at least 1 ms immediately after the backup supply is connected. If the VCC is not powered on while connecting the backup supply, then the expected leakage current from VBACK will be much greater than specified. 8.2.3 Application Curves Figure 9. Master and Slave I2C Communication for the SECONDS Register 20 Figure 10. Master and Slave I2C Communication for the SECONDS Register After Recovering from the Backup Supply Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 BQ32002 www.ti.com SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 9 Power Supply Recommendations The BQ32002 is designed to operate from an input voltage supply, VCC, range between 3 and 3.6 V. The user must place a minimum of 1-µF ceramic bypass capacitor rated for at least the maximum voltage as close as possible to VCC and GND pin. 10 Layout 10.1 Layout Guidelines The VCC pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a minimum recommended value of 1 µF. This capacitor must be placed as close to the VCC and GND pins as possible with thick trace or ground plane connection to the device GND pin. Locate the 32.768-kHz crystal oscillator as close as possible to the OSCI and OSCO pins. This will minimize stray capacitance. 10.2 Layout Example 1 µF ____ IRQ VBACK SCL GND SDA 4.7 kΩ OSCO 4.7 kΩ VCC 4.7 kΩ OSCI 0.22F Figure 11. Recommended PCB Layout Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 21 BQ32002 SLUSA96B – AUGUST 2010 – REVISED APRIL 2016 www.ti.com 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Product Folder Links: BQ32002 PACKAGE OPTION ADDENDUM www.ti.com 21-Aug-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) BQ32002D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM BQ32002DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -40 to 85 32002 32002 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Aug-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device BQ32002DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Aug-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ32002DR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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