STMicroelectronics M50LPW080N5TG 8 mbit 1mb x8, uniform block 3v supply low pin count flash memory Datasheet

M50LPW080
8 Mbit (1M x8, Uniform Block)
3V Supply Low Pin Count Flash Memory
FEATURES SUMMARY
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SUPPLY VOLTAGE
– VCC = 3.0 to 3.6V for Program, Erase and
Read Operations
– VPP = 12V for Fast Program and Fast
Erase (optional)
TWO INTERFACES
– Low Pin Count (LPC) Standard Interface
for embedded operation with PC
Chipsets.
– Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility.
LOW PIN COUNT (LPC) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface
supporting Read and Write Operations
– Hardware Write Protect Pins for Block
Protection
– Register Based Read and Write
Protection
– 5 Additional General Purpose Inputs for
platform design flexibility
– Synchronized with 33MHz PCI clock
PROGRAMMING TIME
– 10µs typical
– Quadruple Byte Programming Option
16 UNIFORM 64 Kbyte MEMORY BLOCKS
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program and Block/Chip
Erase algorithms
– Status Register Bits
PROGRAM and ERASE SUSPEND
– Read other Blocks during Program/Erase
Suspend
– Program other Blocks during Erase
Suspend
FOR USE in PC BIOS APPLICATIONS
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 2Fh
August 2004
Figure 1. Packages
PLCC32 (K)
TSOP40 (N)
10 x 20mm
1/44
M50LPW080
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2.
Figure 3.
Table 1.
Table 2.
Figure 4.
Figure 5.
Table 3.
Logic Diagram (LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Names (LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory Identification Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low Pin Count (LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input/Output Communications (LAD0-LAD3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Input Communication Frame (LFRAME). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Identification Inputs (ID0-ID1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General Purpose Inputs (GPI0-GPI4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Top Block Lock (TBL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Low Pin Count (LPC) Bus Operations . . . . . . . . . . . . . . . .
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2/44
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M50LPW080
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Manufacturer and Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. LPC Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. LPC Bus Read Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. LPC Bus Write Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. LPC Bus Write Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS. . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Low Pin Count Register Configuration Map (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/44
M50LPW080
General Purpose Input Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. General Purpose Input Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. LPC Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. LPC Interface AC Testing Input Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. A/A Mux Interface AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 21. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10.LPC Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 22. LPC Interface Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11.LPC Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 23. LPC Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 24. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13.A/A Mux Interface Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 25. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 14.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 26. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 33
Table 27. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 34
Figure 16.TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline . . . . . . . . . 35
Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data. . 35
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 17.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 38
Figure 19.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 39
Figure 20.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 40
Figure 21.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 22.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 42
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M50LPW080
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 30. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5/44
M50LPW080
SUMMARY DESCRIPTION
The M50LPW080 is a 8 Mbit (1Mb x8) non-volatile
memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For
fast programming and fast erasing in production
lines an optional 12V power supply can be used to
reduce the programming and the erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Program or Erase commands from modifying the
memory. Program and Erase commands are written to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
6/44
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface is the Low Pin
Count (or LPC) Standard Interface. This has been
designed to remove the need for the ISA bus in
current PC Chipsets; the M50LPW080 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in TSOP40 (10 x 20mm)
and PLCC32 packages and it is supplied with all
the bits erased (set to ’1’).
M50LPW080
Figure 2. Logic Diagram (LPC Interface)
VCC VPP
2
4
LAD0LAD3
ID0-ID1
5
GPI0GPI4
WP
LFRAME
TBL
M50LPW080
CLK
IC
Table 1. Signal Names (LPC Interface)
LAD0-LAD3
Input/Output Communications
LFRAME
Input Communication Frame
ID0-ID1
Identification Inputs
GPI0-GPI4
General Purpose Inputs
IC
Interface Configuration
RP
Interface Reset
INIT
CPU Reset
CLK
Clock
TBL
Top Block Lock
WP
Write Protect
RFU
Reserved for Future Use. Leave
disconnected
VCC
Supply Voltage
VPP
Optional Supply Voltage for Fast
Erase Operations
VSS
Ground
NC
Not Connected Internally
RP
INIT
VSS
AI04426
Table 2. Signal Names (A/A Mux Interface)
Figure 3. Logic Diagram (A/A Mux Interface)
VCC VPP
11
8
DQ0-DQ7
A0-A10
RC
IC
M50LPW080
RB
G
W
IC
Interface Configuration
A0-A10
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
G
Output Enable
W
Write Enable
RC
Row/Column Address Select
RB
Ready/Busy Output
RP
Interface Reset
VCC
Supply Voltage
VPP
Optional Supply Voltage for Fast
Program and Fast Erase Operations
VSS
Ground
NC
Not Connected Internally
RP
VSS
AI04427
7/44
M50LPW080
A8
A9
RP
VPP
VCC
RC
A10
Figure 4. PLCC Connections
A/A Mux
GPI2
GPI3
RP
VPP
VCC
CLK
GPI4
A/A Mux
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
GPI1
GPI0
WP
TBL
ID1
ID0
RFU
RFU
LAD0
9
M50LPW080
25
IC (VIL)
NC
NC
VSS
VCC
INIT
LFRAME
RFU
RFU
IC (VIH)
NC
NC
VSS
VCC
G
W
RB
DQ7
A/A Mux
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
LAD1
LAD2
VSS
LAD3
RFU
RFU
RFU
17
A/A Mux
AI05465
8/44
M50LPW080
Figure 5. TSOP Connections
A/A Mux
NC
IC (VIL)
NC
NC
NC
NC
GPI4
NC
CLK
VCC
VPP
RP
NC
NC
GPI3
GPI2
GPI1
GPI0
WP
TBL
1
40
10
31
M50LPW080
11
30
20
21
VSS
VCC
LFRAME
INIT
RFU
RFU
RFU
RFU
RFU
VCC
VSS
VSS
LAD3
LAD2
LAD1
LAD0
RFU
RFU
ID0
ID1
VSS
VCC
W
G
RB
DQ7
DQ6
DQ5
DQ4
VCC
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
A/A Mux
NC
IC (VIH)
NC
NC
NC
NC
A10
NC
RC
VCC
VPP
RP
NC
NC
A9
A8
A7
A6
A5
A4
AI04428
Table 3. Memory Identification Input Configuration
Memory Number
ID1
ID0
A21
A20
1 (Boot)
VIL or floating
VIL or floating
1
1
2
VIL or floating
VIH
1
0
3
VIH
VIL or floating
0
1
4
VIH
VIH
0
0
9/44
M50LPW080
SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Configuration Pin, IC.
The signals for each interface are discussed in the
Low Pin Count (LPC) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply signals are discussed in the Supply Signal Descriptions section below.
Low Pin Count (LPC) Signal Descriptions
For the Low Pin Count (LPC) Interface see Figure
2. and Table 1..
Input/Output Communications (LAD0-LAD3).
All Input and Output Communication with the
memory take place on these pins. Addresses and
Data for Bus Read and Bus Write operations are
encoded on these pins.
Input Communication Frame (LFRAME). The
Input Communication Frame (LFRAME) signals
the start of a bus operation. When Input Communication Frame is Low, VIL, on the rising edge of
the Clock a new bus operation is initiated. If Input
Communication Frame is Low, VIL, during a bus
operation then the operation is aborted. When Input Communication Frame is High, VIH, the current bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID1). The Identification
Inputs (ID0-ID1) allow to address up to 4 memories on a bus. The value on addresses A20-A21 is
compared to the hardware strapping on the ID0ID1 pins to select which memory is being addressed. For an address bit to be ‘1’ the correspondent ID pin can be left floating or driven Low,
VIL; an internal pull-down resistor is included with
a value of R IL. For an address bit to be ‘0’ the correspondent ID pin must be driven High, VIH; there
will be a leakage current of ILI2 through each pin
when pulled to VIH (see Table 21.).
By convention the boot memory must have ID0ID1 pins left floating or driven Low, V IL and a ‘11’
value on A20-A21 and all additional memories
take sequential ID0-ID1 configuration, as shown in
Table 3..
General Purpose Inputs (GPI0-GPI4). The General Purpose Inputs can be used as digital inputs for
the CPU to read. The General Purpose Input Register holds the values on these pins. The pins must
have stable data from before the start of the cycle
that reads the General Purpose Input Register until after the cycle is complete. These pins must not
be left to float, they should be driven Low, V IL, or
High, V IH.
Interface Configuration (IC). The Interface Configuration input selects whether the Low Pin Count
10/44
(LPC) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Low Pin Count (LPC) Interface the
Interface Configuration pin should be left to float or
driven Low, VIL; to select the Address/Address
Multiplexed (A/A Mux) Interface the pin should be
driven High, VIH. An internal pull-down resistor is
included with a value of R IL; there will be a leakage
current of ILI2 through each pin when pulled to VIH;
see Table 21..
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, VIL, the memory is in Reset
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, V IH, the memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, LAD0-LAD3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL). The Top Block Lock input is used to prevent the Top Block (Block 15)
from being changed. When Top Block Lock, TBL,
is set Low, V IL, Program and Block Erase operations in the Top Block have no effect, regardless of
the state of the Lock Register. When Top Block
Lock, TBL, is set High, VIH, the protection of the
Block is determined by the Lock Register. The
state of Top Block Lock, TBL, does not affect the
protection of the Main Blocks (Blocks 0 to 14).
Top Block Lock, TBL, must be set prior to a Program or Block Erase operation is initiated and
must not be changed until the operation completes
or unpredictable results may occur. Care should
be taken to avoid unpredictable behavior by
changing TBL during Program or Erase Suspend.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 14)
from being changed. When Write Protect, WP, is
set Low, V IL, Program and Block Erase operations
in the Main Blocks have no effect, regardless of
the state of the Lock Register. When Write Protect,
WP, is set High, VIH, the protection of the Block is
determined by the Lock Register. The state of
M50LPW080
Write Protect, WP, does not affect the protection of
the Top Block (Block 15).
Write Protect, WP, must be set prior to a Program
or Block Erase operation is initiated and must not
be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing
WP during Program or Erase Suspend.
Reserved for Future Use (RFU). These pins do
not have assigned functions in this revision of the
part. They must be left disconnected.
Table 4. Block Addresses
Size
(Kbytes)
Address Range
Block
Number
Block Type
64
F0000h-FFFFFh
15
Top Block
64
E0000h-EFFFFh
14
Main Block
64
D0000h-DFFFFh
13
Main Block
64
C0000h-CFFFFh
12
Main Block
64
B0000h-BFFFFh
11
Main Block
64
A0000h-AFFFFh
10
Main Block
64
90000h-9FFFFh
9
Main Block
64
80000h-8FFFFh
8
Main Block
64
70000h-7FFFFh
7
Main Block
64
60000h-6FFFFh
6
Main Block
64
50000h-5FFFFh
5
Main Block
64
40000h-4FFFFh
4
Main Block
64
30000h-3FFFFh
3
Main Block
64
20000h-2FFFFh
2
Main Block
64
10000h-1FFFFh
1
Main Block
64
00000h-0FFFFh
0
Main Block
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
For the Address/Address Multiplexed (A/A Mux)
Interface see Figure 3. and Table 2..
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A19). They are
latched during any bus operation by the Row/Column Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read
from the memory. They output the data stored at
the selected address during a Bus Read operation. During Bus Write operations they represent
the commands sent to the Command Interface of
the internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write
operation.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
Row/Column Address Select (RC). The Row/
Column Address Select input selects whether the
Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits
(A11-A19). The Row Address bits are latched on
the falling edge of RC whereas the Column Address bits are latched on the rising edge.
Ready/Busy Output (RB). The Ready/Busy pin
gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, VOL, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase Suspend command. When Ready/Busy is High, VOH,
the memory is ready for any Read, Program or
Erase operation.
Supply Signal Descriptions
The Supply Signals are the same for both interfaces.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the V CC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid. After V CC
becomes valid the Command Interface is reset to
Read mode.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pins and the VSS Ground
pin to decouple the current surges from the power
supply. Both V CC Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents required during program and erase operations.
VPP Optional Supply Voltage. The VPP Optional
Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command
description) and Fast Erase options of the memory
and to protect the memory. When V PP < VPPLK
Program and Erase operations cannot be performed and an error is reported in the Status Register if an attempt to change the memory contents
is made. When V PP = VCC Program and Erase operations take place as normal. When V PP = VPPH
Fast Program (if a Quadruple Byte Program Command is performed) and Fast Erase operations are
11/44
M50LPW080
used. Any other voltage input to VPP will result in
undefined behavior and should not be used.
VPP should not be set to VPPH for more than 80
hours during the life of the memory.
VSS Ground. VSS is the reference for all the voltage measurements.
BUS OPERATIONS
The two interfaces have similar bus operations but
the signals and timings are completely different.
The Low Pin Count (LPC) Interface is the usual interface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/Address Multiplexed (A/A Mux) Interface.
Follow the section Low Pin Count (LPC) Bus Operations below and the section Address/Address
Multiplexed (A/A Mux) Interface Bus Operations
below for a description of the bus operations on
each interface.
Low Pin Count (LPC) Bus Operations
The Low Pin Count (LPC) Interface consists of
four data signals (LAD0-LAD3), one control line
(LFRAME) and a clock (CLK). In addition protection against accidental or malicious data corruption can be achieved using two further signals
(TBL and WP). Finally two reset signals (RP and
INIT) are available to put the memory into a known
state.
The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds
up to 33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Low Pin Count Registers. A valid Bus
Read operation starts when Input Communication
Frame, LFRAME, is Low, VIL, as Clock rises and
the correct Start cycle is on LAD0-LAD3. On the
following clock cycles the Host will send the Cycle
Type + Dir, Address and other control bits on
LAD0-LAD3. The memory responds by outputting
Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7.
See Table 7. and Figure 6. for a description of the
Field definitions for each clock cycle of the transfer. See Table 23. and Figure 11. for details on the
timings of the signals.
Bus Write. Bus Write operations write to the
Command Interface or Low Pin Count Registers. A
valid Bus Write operation starts when Input Communication Frame, LFRAME, is Low, VIL, as Clock
rises and the correct Start cycle is on LAD0-LAD3.
12/44
On the following Clock cycles the Host will send
the Cycle Type + Dir, Address, other control bits,
Data0-Data3 and Data4-Data7 on LAD0-LAD3.
The memory outputs Sync data until the waitstates have elapsed.
See Table 8. and Figure 7. for a description of the
Field definitions for each clock cycle of the transfer. See Table 23. and Figure 11. for details on the
timings of the signals.
Bus Abort. The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when LFRAME is driven Low,
VIL, during the bus operation; the memory will tristate the Input/Output Communication pins,
LAD0-LAD3.
Note that, during a Bus Write operation, the Command Interface starts executing the command as
soon as the data is fully received; a Bus Abort during the final TAR cycles is not guaranteed to abort
the command; the bus, however, will be released
immediately.
Standby. When LFRAME is High, VIH, the memory is put into Standby mode where LAD0-LAD3
are put into a high-impedance state and the Supply Current is reduced to the Standby level, ICC1.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP, or CPU
Reset, INIT, is Low, VIL. RP or INIT must be held
Low, VIL, for tPLPH. The memory resets to Read
mode upon return from Reset mode and the Lock
Registers return to their default states regardless
of their state before Reset (see Table 13.). If RP or
INIT goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory
cells affected no longer contain valid data; the
memory can take up to tPLRH to abort a Program
or Erase operation.
Block Protection. Block Protection can be
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0-
M50LPW080
A10), data signals, (DQ0-DQ7) and three control
signals (RC, G, W). An additional signal, RP, can
be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming
equipment for faster factory programming. Only a
subset of the features available to the Low Pin
Count (LPC) Interface are available; these include
all the Commands but exclude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through
this interface.
Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid
Bus Read operation begins by latching the Row
Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and
the Row/Column Address Select RC. Then Write
Enable (W) and Interface Reset (RP) must be
High, VIH, and Output Enable, G, Low, V IL, in order
to perform a Bus Read operation. The Data Inputs/
Outputs will output the value, see Figure 13. and
Table 25. for details of when the output becomes
valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Interface Reset, RP, must be High, VIH and Write Enable, W, must be Low, VIL. The Data Inputs/
Outputs are latched on the rising edge of Write Enable, W. See Figure 14. and Table 26. for details
of the timing requirements.
Output Disable. The data outputs are high-impedance when the Output Enable, G, is at VIH.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP is Low, VIL. RP must be
held Low, V IL for tPLPH. If RP is goes Low, VIL, during a Program or Erase operation, the operation is
aborted and the memory cells affected no longer
contain valid data; the memory can take up to tPLRH to abort a Program or Erase operation.
Table 5. A/A Mux Bus Operations
G
W
RP
VPP
DQ7-DQ0
Bus Read
VIL
VIH
VIH
Don’t Care
Data Output
Bus Write
VIH
VIL
VIH
VCC or VPPH
Data Input
Output Disable
VIH
VIH
VIH
Don’t Care
Hi-Z
VIL or VIH
VIL or VIH
VIL
Don’t Care
Hi-Z
Operation
Reset
Table 6. Manufacturer and Device Codes
G
W
RP
A19-A1
A0
DQ7-DQ0
Manufacturer Code
VIL
VIH
VIH
VIL
VIL
20h
Device Code
VIL
VIH
VIH
VIL
VIH
2Fh
Operation
13/44
M50LPW080
Table 7. LPC Bus Read Field Definitions
Clock
Cycle
Number
Clock
Cycle
Count
Field
LAD0LAD3
Memory
I/O
Description
1
1
START
0000b
I
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a
LPC cycle.
2
1
CYCTYPE
+ DIR
010Xb
I
Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1
indicates the direction of transfer: 0b for read. Bit 0 is don’t
care (X).
3-10
8
ADDR
XXXX
I
A 32-bit address phase is transferred starting with the most
significant nibble first. A23-A31 must be set to 1. A22 = 1
for Array, A22 = 0 for registers access. For A20-A21
values, see Table 3..
11
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
12
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-LAD3
during this cycle.
13-14
2
WSYNC
0101b
O
The LPC Flash Memory drives LAD0-LAD3 to 0101b
(short wait-sync) for two clock cycles, indicating that the
data is not yet available. Two wait-states are always
included.
15
1
RSYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating that data will be available during the next clock
cycle.
16-17
2
DATA
XXXX
O
Data transfer is two CLK cycles, starting with the least
significant nibble.
18
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to 1111b to
indicate a turnaround cycle.
19
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs, the host takes
control of LAD0-LAD3.
Figure 6. LPC Bus Read Waveforms
CLK
LFRAME
LAD0-LAD3
START
CYCTYPE
+ DIR
ADDR
TAR
SYNC
DATA
TAR
Number of
clock cycles
1
1
8
2
3
2
2
AI04429
14/44
M50LPW080
Table 8. LPC Bus Write Field Definitions
Clock
Cycle
Number
Clock
Cycle
Count
Field
LAD0LAD3
Memory
I/O
Description
1
1
START
0000b
I
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a LPC
cycle.
2
1
CYCTY
PE +
DIR
011Xb
I
Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1
indicates the direction of transfer: 1b for write. Bit 0 is don’t
care (X).
3-10
8
ADDR
XXXX
I
A 32-bit address phase is transferred starting with the most
significant nibble first. A23-A31 must be set to 1. A22 = 1 for
Array, A22 = 0 for registers access. For A20-A21 values, see
Table 3..
11-12
2
DATA
XXXX
I
Data transfer is two cycles, starting with the least significant
nibble.
13
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
14
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-LAD3 during
this cycle.
15
1
SYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating it has received data or a command.
16
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to 1111b,
indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs and the host takes
control of LAD0-LAD3.
Figure 7. LPC Bus Write Waveforms
CLK
LFRAME
LAD0-LAD3
START
CYCTYPE
+ DIR
ADDR
DATA
TAR
SYNC
TAR
Number of
clock cycles
1
1
8
2
2
1
2
AI04430
15/44
M50LPW080
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations.
After power-up or a Reset operation the memory
enters Read mode.
The commands are summarized in Table 10.. The
following text descriptions should be read in conjunction with Table 10..
Read Memory Array Command. The
Read
Memory Array command returns the memory to its
Read mode where it behaves like a ROM or
EPROM. One Bus Write cycle is required to issue
the Read Memory Array command and return the
memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus
Read operations will access the memory array.
While the Program/Erase Controller is executing a
Program or Erase operation the memory will not
accept the Read Memory Array command until the
operation completes.
Read Status Register Command. The
Read
Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the
command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status
Register for details on the definitions of the Status
Register bits.
Read Electronic Signature Command. The Read
Electronic Signature command is used to read the
Manufacturer Code and the Device Code. One
Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is
issued subsequent Bus Read operations read the
Manufacturer Code or the Device Code until another command is issued.
After the Read Electronic Signature Command is
issued the Manufacturer Code and Device Code
can be read using Bus Read operations using the
addresses in Table 9..
Table 9. Read Electronic Signature
Code
Address
Data
Manufacturer Code
00000h
20h
Device Code
00001h
2Fh
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data
16/44
in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the address falls in a protected block then the
Program operation will abort, the data in the memory array will not be changed and the Status Register will output the error.
During the Program operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Program
times are given in Table 15..
Note that the Program command cannot change a
bit set at ‘0’ back to ‘1’ and attempting to do so will
not cause any modification on its value. One of the
Erase commands must be used to set all of the
bits in the block to ‘1’.
See Figure 17. for a suggested flowchart on using
the Program command.
Quadruple Byte Program Command. The Quadruple Byte Program Command can be only used
in A/A Mux mode to program four adjacent bytes
in the memory array at a time. The four bytes must
differ only for the addresses A0 and A10. Programming should not be attempted when V PP is
not at V PPH. The operation can also be executed if
VPP is below V PPH, but result could be uncertain.
Five Bus Write operations are required to issue the
command. The second, the third and the fourth
Bus Write cycle latches respectively the address
and data of the first, the second and the third byte
in the internal state machine. The fifth Bus Write
cycle latches the address and data of the fourth
byte in the internal state machine and starts the
Program/Erase Controller. Once the command is
issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
During the Quadruple Byte Program operation the
memory will only accept the Read Status register
command and the Program/Erase Suspend command. All other commands will be ignored. Typical
Quadruple Byte Program times are given in Table
15..
Note that the Quadruple Byte Program command
cannot change a bit set to ‘0’ back to ‘1’ and attempting to do so will not cause any modification
on its value. One of the Erase commands must be
used to set all of the bits in the block to ‘1’.
See Figure 18. for a suggested flowchart on using
the Quadruple Byte Program command.
M50LPW080
Chip Erase Command. The Chip Erase Command can be only used in A/A Mux mode to erase
the entire chip at a time. Erasing should not be attempted when VPP is not at VPPH. The operation
can also be executed if V PP is below VPPH, but result could be uncertain. Two Bus Write operations
are required to issue the command and start the
Program/Erase Controller. Once the command is
issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits. During the Chip Erase operation the
memory will only accept the Read Status Register
command. All other commands will be ignored.
Typical Chip Erase times are given in Table 15..
The Chip Erase command sets all of the bits in the
memory to ‘1’. See Figure 20. for a suggested
flowchart on using the Chip Erase command.
Block Erase Command. The Block Erase command can be used to erase a block. Two Bus Write
operations are required to issue the command; the
second Bus Write cycle latches the block address
in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the block is protected then the Block Erase operation will abort, the data in the block will not be
changed and the Status Register will output the error.
During the Block Erase operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Block
Erase times are given in Table 15..
The Block Erase command sets all of the bits in
the block to ‘1’. All previous data in the block is
lost.
See Figure 21. for a suggested flowchart on using
the Block Erase command.
Clear Status Register Command. The
Clear
Status Register command can be used to reset
bits 1, 3, 4 and 5 in the Status Register to ‘0’. One
Bus Write is required to issue the Clear Status
Register command. Once the command is issued
the memory returns to its previous mode, subsequent Bus Read operations continue to output the
same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Program
or Erase command is issued. If an error occurs
then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register
command before attempting a new Program or
Erase command.
Program/Erase Suspend Command. The Program/Erase Suspend command can be used to
pause a Program or Block Erase operation. One
Bus Write cycle is required to issue the Program/
Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase
Controller Status bit to find out when the Program/
Erase Controller has paused; no other commands
will be accepted until the Program/Erase Controller has paused. After the Program/Erase Controller has paused, the memory will continue to output
the Status Register until another command is issued.
During the polling period between issuing the Program/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the operation to complete. Once Program/Erase Controller Status bit indicates that the Program/Erase
Controller is no longer active, the Program Suspend Status bit or the Erase Suspend Status bit
can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend
command and the Program/Erase Controller
pausing see Table 15..
During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic
Signature and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was
Block Erase then the Program command will also
be accepted; only the blocks not being erased may
be read or programmed correctly.
See Figure 19. and Figure 22. for suggested flowcharts on using the Program/Erase Suspend command.
Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a
Program/Erase Suspend has paused it. One Bus
Write cycle is required to issue the Program/Erase
Resume command. Once the command is issued
subsequent Bus Read operations read the Status
Register.
17/44
M50LPW080
Command
Cycles
Table 10. Commands
Bus Write Operations
1st
2nd
Addr
Data
3rd
Addr
Data
Read Memory Array
1
X
FFh
Read Status Register
1
X
70h
1
X
90h
1
X
98h
2
X
40h
PA
PD
2
X
10h
PA
PD
Quadruple Byte Program
5
X
30h
A1
PD
Chip Erase
2
X
80h
X
10h
Block Erase
2
X
20h
BA
D0h
Clear Status Register
1
X
50h
Program/Erase Suspend
1
X
B0h
Program/Erase Resume
1
X
D0h
1
X
00h
1
X
01h
1
X
60h
1
X
2Fh
1
X
C0h
Read Electronic Signature
4th
5th
Addr
Data
Addr
Data
Addr
Data
A2
PD
A3
PD
A4
PD
Program
Invalid/Reserved
Note: X Don’t Care, PA Program Address, PD Program Data, A1,2,3,4 Consecutive Addresses, BA Any address in the Block.
Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued.
Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued.
Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another command is issued.
Block Erase, Program. After these commands read the Status Register until the command completes and another command is issued.
Quadruple Byte Program. This command is only valid in A/A Mux mode. Addresses A 1, A2, A3 and A4 must be consecutive addresses
differing only for address bit A0 and A10. After this command read the Status Register until the command completes and another command is issued.
Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes
and another command is issued.
Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.
Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status
Register, Program (during Erase suspend) and Program/Erase resume commands.
Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the
Status Register until the Program/Erase Controller Do not use Invalid or Reserved commands not use Invalid or Reserved commands.
18/44
M50LPW080
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey different information and errors on the operation.
To read the Status Register the Read Status Register command can be issued. The Status Register
is automatically read after Program, Erase and
Program/Erase Resume commands are issued.
The Status Register can be read from any address.
The Status Register bits are summarized in Table
11.. The following text descriptions should be read
in conjunction with Table 11..
Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
‘0’, the Program/Erase Controller is active; when
the bit is ‘1’, the Program/Erase Controller is inactive.
The Program/Erase Controller Status is ‘0’ immediately after a Program/Erase Suspend command
is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the
bit is ‘1’.
During Program and Erase operation the Program/Erase Controller Status bit can be polled to
find the end of the operation. The other bits in the
Status Register should not be tested until the Program/Erase Controller completes the operation
and the bit is ‘1’.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and Block Protection Status bits should be
tested for errors.
Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that a Block Erase operation has been suspended and is waiting to be
resumed. The Erase Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’ the Program/Erase Controller is active or has completed
its operation; when the bit is ‘1’ a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block(s)
and still failed to verify that the block(s) has erased
correctly. The Erase Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Erase Status bit is ‘0’ the memory has
successfully verified that the block(s) has erased
correctly; when the Erase Status bit is ‘1’ the Program/Erase Controller has applied the maximum
number of pulses to the block(s) and still failed to
verify that the block(s) has erased correctly.
Once the Erase Status bit is set to ‘1’ it can only be
reset to ‘0’ by a Clear Status Register command or
a hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is issued, otherwise the new command will appear to
fail.
Program Status (Bit 4). The Program Status bit
can be used to identify if the memory has applied
the maximum number of program pulses to the
byte and still failed to verify that the byte has programmed correctly. The Program Status bit should
be read once the Program/Erase Controller Status
bit is ‘1’ (Program/Erase Controller inactive).
When the Program Status bit is ‘0’ the memory has
successfully verified that the byte has programmed correctly; when the Program Status bit is
‘1’ the Program/Erase Controller has applied the
maximum number of pulses to the byte and still
failed to verify that the byte has programmed correctly.
Once the Program Status bit is set to ‘1’ it can only
be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail.
VPP Status (Bit 3). The VPP Status bit can be
used to identify an invalid voltage on the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can occur if VPP becomes invalid during a Program or
Erase operation.
When the VPP Status bit is ‘0’ the voltage on the
VPP pin was sampled at a valid voltage; when the
VPP Status bit is ‘1’ the V PP pin has a voltage that
is below the V PP Lockout Voltage, VPPLK, the
memory is protected; Program and Erase operation cannot be performed.
Once the VPP Status bit set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a
hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is issued, otherwise the new command will appear to
fail.
19/44
M50LPW080
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Program Suspend Status bit is ‘0’ the
Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Resume command.
When a Program/Erase Resume command is issued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if the Pro-
gram or Block Erase operation has tried to modify
the contents of a protected block. When the Block
Protection Status bit is to ‘0’ no Program or Block
Erase operations have been attempted to protected blocks since the last Clear Status Register
command or hardware reset; when the Block Protection Status bit is ‘1’ a Program or Block Erase
operation has been attempted on a protected
block.
Once it is set to ‘1’ the Block Protection Status bit
can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If it is set to ‘1’ it
should be reset before a new Program or Block
Erase command is issued, otherwise the new
command will appear to fail.
Using the A/A Mux Interface the Block Protection
Status bit is always ‘0’.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
Table 11. Status Register Bits
Operation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Program active
‘0’
X(1)
‘0’
‘0’
‘0’
‘0’
‘0’
Program suspended
‘1
X(1)
‘0’
‘0’
‘0’
‘1’
‘0’
Program completed successfully
‘1’
X(1)
‘0’
‘0’
‘0’
‘0’
‘0’
Program failure due to VPP Error
‘1’
X(1)
‘0’
‘0’
‘1’
‘0’
‘0’
Program failure due to Block Protection (LPC Interface only)
‘1’
X(1)
‘0’
‘0’
‘0’
‘0’
‘1’
Program failure due to cell failure
‘1’
X(1)
‘0’
‘1’
‘0’
‘0’
‘0’
Erase active
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Block Erase suspended
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
Erase completed successfully
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Erase failure due to VPP Error
‘1’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
Block Erase failure due to Block Protection (LPC Interface
only)
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
Erase failure due to failed cell(s)
‘1’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.
20/44
M50LPW080
LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS
When the Low Pin Count Interface is selected several additional registers can be accessed. These
registers control the protection status of the Blocks
and read the General Purpose Input pins. See Ta-
ble 12. for an example of the Register Configuration map, valid for the boot memory, i.e. ID0-ID1
floating or driven L OW, VIL and A20-A21 set to ‘1’.
Table 12. Low Pin Count Register Configuration Map (1)
Memory
Address
Default
Value
Access
Top Block Lock Register (Block 15)
FFBF0002h
01h
R/W
T_MINUS01_LK
Top Block [-1] Lock Register (Block 14)
FFBE0002h
01h
R/W
T_MINUS02_LK
Top Block [-2] Lock Register (Block 13)
FFBD0002h
01h
R/W
T_MINUS03_LK
Top Block [-3] Lock Register (Block 12)
FFBC0002h
01h
R/W
T_MINUS04_LK
Top Block [-4] Lock Register (Block 11)
FFBB0002h
01h
R/W
T_MINUS05_LK
Top Block [-5] Lock Register (Block 10)
FFBA0002h
01h
R/W
T_MINUS06_LK
Top Block [-6] Lock Register (Block 9)
FFB90002h
01h
R/W
T_MINUS07_LK
Top Block [-7] Lock Register (Block 8)
FFB80002h
01h
R/W
T_MINUS08_LK
Top Block [-8] Lock Register (Block 7)
FFB70002h
01h
R/W
T_MINUS09_LK
Top Block [-9] Lock Register (Block 6)
FFB60002h
01h
R/W
T_MINUS10_LK
Top Block [-10] Lock Register (Block 5)
FFB50002h
01h
R/W
T_MINUS11_LK
Top Block [-11] Lock Register (Block 4)
FFB40002h
01h
R/W
T_MINUS12_LK
Top Block [-12] Lock Register (Block 3)
FFB30002h
01h
R/W
T_MINUS13_LK
Top Block [-13] Lock Register (Block 2)
FFB20002h
01h
R/W
T_MINUS14_LK
Top Block [-14] Lock Register (Block 1)
FFB10002h
01h
R/W
T_MINUS15_LK
Top Block [-15] Lock Register (Block 0)
FFB00002h
01h
R/W
General Purpose Input Register
FFBC0100h
N/A
R
Mnemonic
T_BLOCK_LK
GPI_REG
Register Name
Note: 1. This map is referred to the boot memory (ID0-ID1 floating or driven, LOW, VIL and A20-A21 set to ‘1’).
Lock Registers
The Lock Registers control the protection status of
the Blocks. Each Block has its own Lock Register.
Three bits within each Lock Register control the
protection of each block, the Write Lock Bit, the
Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written,
though care should be taken when writing as, once
the Lock Down Bit is set, ‘1’, further modifications
to the Lock Register cannot be made until cleared,
to ‘0’, by a reset or power-up.
See Table 13. for details on the bit definitions of
the Lock Registers.
Write Lock. The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Block Erase Command).
When the Write Lock Bit is set, ‘1’, the block is
write protected; any operations that attempt to
change the data in the block will fail and the Status
Register will report the error. When the Write Lock
Bit is reset, ‘0’, the block is not write protected
through the Lock Register and may be modified
unless write protected through some other means.
When V PP is less than VPPLK all blocks are protected and cannot be modified, regardless of the
state of the Write Lock Bit. If Top Block Lock, TBL,
is Low, V IL, then the Top Block (Block 15) is write
protected and cannot be modified. Similarly, if
Write Protect, WP, is Low, VIL, then the Main
Blocks (Blocks 0 to 14) are write protected and
cannot be modified.
After power-up or reset the Write Lock Bit is always set to ‘1’ (write protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read
(from Read mode). When the Read Lock Bit is set,
‘1’, the block is read protected; any operation that
attempts to read the contents of the block will read
00h instead. When the Read Lock Bit is reset, ‘0’,
read operations in the Block return the data programmed into the block as expected.
After power-up or reset the Read Lock Bit is always reset to ‘0’ (not read protected).
21/44
M50LPW080
Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from simple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset or power-up is required before changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
General Purpose Input Register
The General Purpose Input Register holds the
state of the General Purpose Input pins, GPI0GPI4. When this register is read, the state of these
pins is returned. This register is read-only and writing to it has no effect.
The signals on the General Purpose Input pins
should remain constant throughout the whole Bus
Read cycle in order to guarantee that the correct
data is read.
Table 13. Lock Register Bit Definitions
Bit
Bit Name
Value
7-3
2
1
0
Function
Reserved
‘1’
Bus Read operations in this Block always return 00h.
‘0’
Bus read operations in this Block return the Memory Array contents. (Default
value).
‘1’
Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a
‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset
to ‘0’ following a Reset (using RP or INIT) or after power-up.
‘0’
Read-Lock and Write-Lock can be changed by writing new values to them. (Default
value).
‘1’
Program and Block Erase operations in this Block will set an error in the Status
Register. The memory contents will not be changed. (Default value).
‘0’
Program and Block Erase operations in this Block are executed and will modify the
Block contents.
Read-Lock
Lock-Down
Write-Lock
Note: Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-15] Lock Register (T_MINUS15_LK).
Table 14. General Purpose Input Register Definition
Bit
Bit Name
Value
7-5
4
3
2
1
0
Function
Reserved
‘1’
Input Pin GPI4 is at VIH
‘0’
Input Pin GPI4 is at VIL
‘1’
Input Pin GPI3 is at VIH
‘0’
Input Pin GPI3 is at VIL
‘1’
Input Pin GPI2 is at VIH
‘0’
Input Pin GPI2 is at VIL
‘1’
Input Pin GPI1 is at VIH
‘0’
Input Pin GPI1 is at VIL
‘1’
Input Pin GPI0 is at VIH
‘0’
Input Pin GPI0 is at VIL
GPI4
GPI3
GPI2
GPI1
GPI0
Note: Applies to the General Purpose Input Register (GPI_REG).
22/44
M50LPW080
PROGRAM AND ERASE TIMES
The Program and Erase times are shown in Table
15..
Table 15. Program and Erase Times
Parameter
Interface
Test Condition
Byte Program
Min
Typ (1)
Max
Unit
10
200
µs
200
µs
Quadruple Byte Program
A/A Mux
VPP = 12V ± 5%
10
Chip Erase
A/A Mux
VPP = 12V ± 5%
9
A/A Mux
VPP = 12V ± 5%
Block Program
0.1
(2)
sec
5
sec
VPP = VCC
0.4
5
sec
VPP = 12V ± 5%
0.75
8
sec
VPP = VCC
1
10
sec
Program/Erase Suspend to Program pause (3)
5
µs
Program/Erase Suspend to Block Erase pause (3)
30
µs
Block Erase
Note: 1. TA = 25°C, VCC = 3.3V
2. This time is obtained executing the Quadruple Byte Program Command.
3. Sampled only, not 100% tested.
23/44
M50LPW080
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 16. Absolute Maximum Ratings
Symbol
Parameter
TSTG
Storage Temperature
TLEAD
Lead Temperature during Soldering
Min.
Max.
Unit
–65
150
°C
See note 1
°C
VIO
Input or Output range 2
–0.60
VCC + 0.6
V
VCC
Supply Voltage
–0.60
4
V
VPP
Program Voltage
–0.6
13
V
VESD
Electrostatic Discharge Voltage (Human Body model) 3
–2000
2000
V
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to VCC + 2V for
less than 20ns during transitions.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
24/44
M50LPW080
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 17., Table 18.
and Table 19. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 17. Operating Conditions
Symbol
VCC
TA
Parameter
Min
Max
Unit
3.0
3.6
V
Ambient Operating Temperature (Device Grade 1)
0
70
°C
Ambient Operating Temperature (Device Grade 5)
–20
85
°C
Supply Voltage
Table 18. LPC Interface AC Measurement Conditions
Parameter
Value
Unit
10
pF
≤ 1.4
ns
0.2 VCC and 0.6 VCC
V
0.4 VCC
V
Value
Unit
30
pF
≤ 10
ns
0 to 3
V
1.5
V
Load Capacitance (CL)
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Table 19. A/A Mux Interface AC Measurement Conditions
Parameter
Load Capacitance (CL)
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 8. LPC Interface AC Testing Input Output Waveforms
0.6 VCC
0.4 VCC
0.2 VCC
Input and Output AC Testing Waveform
IO < ILO
IO > ILO
IO < ILO
Output AC Tri-state Testing Waveform
AI03404
25/44
M50LPW080
Figure 9. A/A Mux Interface AC Testing Input Output Waveform
3V
1.5V
0V
AI01417
Table 20. Impedance
Symbol
Parameter
Test Condition(3)
CIN(1)
Input Capacitance
VIN = 0V
CCLK(1)
Clock Capacitance
VIN = 0V
LPIN(2)
Recommended Pin
Inductance
Note: 1. Sampled only, not 100% tested.
2. See PCI Specification.
3. TA = 25°C, f = 1MHz.
26/44
Min
3
Max
Unit
13
pF
12
pF
20
nH
M50LPW080
Table 21. DC Characteristics
Symbol
VIH
VIL
Parameter
Input High Voltage
Input Low Voltage
Interface
Test Condition
Min
Max
Unit
LPC
0.5 VCC
VCC + 0.5
V
A/A Mux
0.7 VCC
VCC + 0.3
V
LPC
–0.5
0.3 VCC
V
A/A Mux
-0.5
0.8
V
VIH(INIT)
INIT Input High Voltage
LPC
1.35
VCC + 0.5
V
VIL(INIT)
INIT Input Low Voltage
LPC
–0.5
0.2 VCC
V
ILI(2)
Input Leakage Current
0V ≤ VIN ≤ VCC
±10
µA
ILI2
IC, IDx Input Leakage
Current
IC, ID0, ID1 = VCC
200
µA
RIL
IC, IDx Input Pull Low
Resistor
100
kΩ
VOH
Output High Voltage
VOL
ILO
20
LPC
IOH = –500µA
0.9 VCC
V
A/A Mux
IOH = –100µA
VCC – 0.4
V
LPC
IOL = 1.5mA
0.1 VCC
V
A/A Mux
IOL = 1.8mA
0.45
V
0V ≤ VOUT ≤ VCC
±10
µA
3
3.6
V
12.6
V
Output Low Voltage
Output Leakage Current
VPP1
VPP Voltage
VPPH
VPP Voltage (Fast
Program/Fast Erase)
11.4
VPPLK(1)
VPP Lockout Voltage
1.5
VLKO(1)
VCC Lockout Voltage
1.8
V
2.3
V
ICC1
Supply Current (Standby)
LPC
LFRAME = 0.9 VCC, VPP = VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6V, f(CLK) = 33MHz
100
µA
ICC2
Supply Current (Standby)
LPC
LFRAME = 0.1 VCC, VPP = VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6V, f(CLK) = 33MHz
10
mA
ICC3
Supply Current
(Any internal operation
active)
LPC
VCC = VCC max, VPP = VCC
f(CLK) = 33MHz
IOUT = 0mA
60
mA
ICC4
Supply Current (Read)
A/A Mux
G = VIH, f = 6MHz
20
mA
Supply Current
(Program/Erase)
A/A Mux
Program/Erase Controller Active
20
mA
VPP Supply Current
(Read/Standby)
VPP > VCC
400
µA
VPP Supply Current
(Program/Erase active)
VPP = VCC
40
mA
VPP = 12V ± 5%
15
mA
ICC5(1)
IPP
IPP1(1)
Note: 1. Sampled only, not 100% tested.
2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.
27/44
M50LPW080
Figure 10. LPC Interface Clock Waveform
tCYC
tHIGH
tLOW
0.6 VCC
0.5 VCC
0.4 VCC, p-to-p
0.4 VCC
(minimum)
0.3 VCC
0.2 VCC
AI03403
Table 22. LPC Interface Clock Characteristics
Symbol
Parameter
Test Condition
Value
Unit
tCYC
CLK Cycle Time(1)
Min
30
ns
tHIGH
CLK High Time
Min
11
ns
tLOW
CLK Low Time
Min
11
ns
Min
1
V/ns
Max
4
V/ns
CLK Slew Rate
peak to peak
Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed
by design rather than tested. Refer to PCI Specification.
28/44
M50LPW080
Figure 11. LPC Interface AC Signal Timing Waveforms
CLK
tCHQV
tCHQZ
tDVCH
tCHQX
tCHDX
LAD0-LAD3
VALID
VALID OUTPUT DATA
FLOAT OUTPUT DATA
VALID INPUT DATA
AI04431
Table 23. LPC Interface AC Signal Timing Characteristics
Symbol
PCI
Symbol
tCHQV
tval
CLK to Data Out
tCHQX(1)
ton
tCHQZ
Parameter
Test Condition
Value
Unit
Min
2
ns
Max
11
ns
CLK to Active
(Float to Active Delay)
Min
2
ns
toff
CLK to Inactive
(Active to Float Delay)
Max
28
ns
tAVCH
tDVCH
tsu
Input Set-up Time(2)
Min
7
ns
tCHAX
tCHDX
th
Input Hold Time(2)
Min
0
ns
Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current specification.
2. Applies to all inputs except CLK.
29/44
M50LPW080
Figure 12. Reset AC Waveforms
RP, INIT
tPLPH
W, G, LFRAME
tPHWL, tPHGL, tPHFL
tPLRH
RB
AI04432
Table 24. Reset AC Characteristics
Symbol
Parameter
tPLPH
RP or INIT Reset Pulse Width
tPLRH
RP or INIT Low to Reset
RP or INIT Slew Rate(1)
Test Condition
Value
Unit
Min
100
ns
Program/Erase Inactive
Max
100
ns
Program/Erase Active
Max
30
µs
Rising edge only
Min
50
mV/ns
tPHFL
RP or INIT High to LFRAME Low
LPC Interface only
Min
30
µs
tPHWL
tPHGL
RP High to Write Enable or Output
Enable Low
A/A Mux Interface only
Min
50
µs
Note: 1. See Chapter 4 of the PCI Specification.
30/44
M50LPW080
Figure 13. A/A Mux Interface Read AC Waveforms
tAVAV
ROW ADDR VALID
A0-A10
NEXT ADDR VALID
COLUMN ADDR VALID
tAVCL
tAVCH
tCLAX
tCHAX
RC
tCHQV
G
tGLQV
tGHQZ
tGLQX
tGHQX
VALID
DQ0-DQ7
W
tPHAV
RP
AI03406
Table 25. A/A Mux Interface Read AC Characteristics
Symbol
Parameter
Test Condition
Value
Unit
tAVAV
Read Cycle Time
Min
250
ns
tAVCL
Row Address Valid to RC Low
Min
50
ns
tCLAX
RC Low to Row Address Transition
Min
50
ns
tAVCH
Column Address Valid to RC high
Min
50
ns
tCHAX
RC High to Column Address Transition
Min
50
ns
tCHQV(1)
RC High to Output Valid
Max
150
ns
tGLQV(1)
Output Enable Low to Output Valid
Max
50
ns
tPHAV
RP High to Row Address Valid
Min
1
µs
tGLQX
Output Enable Low to Output Transition
Min
0
ns
tGHQZ
Output Enable High to Output Hi-Z
Max
50
ns
tGHQX
Output Hold from Output Enable High
Min
0
ns
Note: 1. G may be delayed up to tCHQV – t GLQV after the rising edge of RC without impact on tCHQV.
31/44
M50LPW080
Figure 14. A/A Mux Interface Write AC Waveforms
Write erase or
program setup
A0-A10
R1
Write erase confirm or
valid address and data
C1
R2
tCLAX
tAVCH
tAVCL
Automated erase
or program delay
Read Status
Register Data
Ready to write
another command
C2
tCHAX
RC
tWHWL
tWLWH
tCHWH
W
tVPHWH
tWHGL
G
tWHRL
RB
tQVVPL
VPP
tDVWH
DQ0-DQ7
DIN1
tWHDX
DIN2
VALID SRD
AI04194
Table 26. A/A Mux Interface Write AC Characteristics
Symbol
Parameter
Test Condition
Value
Unit
tWLWH
Write Enable Low to Write Enable High
Min
100
ns
tDVWH
Data Valid to Write Enable High
Min
50
ns
tWHDX
Write Enable High to Data Transition
Min
5
ns
tAVCL
Row Address Valid to RC Low
Min
50
ns
tCLAX
RC Low to Row Address Transition
Min
50
ns
tAVCH
Column Address Valid to RC High
Min
50
ns
tCHAX
RC High to Column Address Transition
Min
50
ns
tWHWL
Write Enable High to Write Enable Low
Min
100
ns
tCHWH
RC High to Write Enable High
Min
50
ns
tVPHWH(1)
VPP High to Write Enable High
Min
100
ns
tWHGL
Write Enable High to Output Enable Low
Min
30
ns
tWHRL
Write Enable High to RB Low
Min
0
ns
Output Valid, RB High to VPP Low
Min
0
ns
tQVVPL(1,2)
Note: 1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (V PP < 3.6V).
32/44
M50LPW080
PACKAGE MECHANICAL
Figure 15. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline
D
D1
A1
A2
1 N
B1
E2
E3
e
E1 E
F
B
0.51 (.020)
E2
1.14 (.045)
A
D3
R
D2
CP
D2
PLCC-A
Note: Drawing is not to scale.
33/44
M50LPW080
Table 27. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
A
3.18
A1
Min
Max
3.56
0.125
0.140
1.53
2.41
0.060
0.095
A2
0.38
–
0.015
–
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
CP
0.10
0.004
D
12.32
12.57
0.485
0.495
D1
11.35
11.51
0.447
0.453
D2
4.78
5.66
0.188
0.223
–
–
–
–
E
14.86
15.11
0.585
0.595
E1
13.89
14.05
0.547
0.553
E2
6.05
6.93
0.238
0.273
D3
7.62
0.300
E3
10.16
–
–
0.400
–
–
e
1.27
–
–
0.050
–
–
0.00
0.13
0.000
0.005
–
–
–
–
F
R
N
34/44
Typ
0.89
32
0.035
32
M50LPW080
Figure 16. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline
A2
N
1
e
E
B
N/2
A
D1
CP
D
DIE
C
A1
TSOP-a
α
L
Note: Drawing is not to scale.
Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
Max
0.0472
A1
0.050
0.150
0.0020
0.0059
A2
0.950
1.050
0.0374
0.0413
B
0.170
0.270
0.0067
0.0106
C
0.100
0.210
0.0039
0.0083
CP
0.100
0.0039
D
19.800
20.200
0.7795
0.7953
D1
18.300
18.500
0.7205
0.7283
–
–
–
–
E
9.900
10.100
0.3898
0.3976
L
0.500
0.700
0.0197
0.0276
α
0°
5°
0°
5°
N
40
e
0.500
0.0197
40
35/44
M50LPW080
PART NUMBERING
Table 29. Ordering Information Scheme
Example:
M50LPW080
K
1
T
G
Device Type
M50 =
Architecture
LP = Low Pin Count Interface
Operating Voltage
W = 3.0 to 3.6V
Device Function
080 = 8 Mbit (1Mx8), Uniform Block
Package
K = PLCC32
N = TSOP40: 10 x 20 mm
Device Grade
5 = Temperature range –20 to 85 °C.
Device tested with standard test flow
1 = Temperature range 0 to 70 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact your nearest ST Sales Office.
36/44
M50LPW080
FLOWCHARTS AND PSEUDO CODES
Figure 17. Program Flowchart and Pseudo Code
Start
Program command:
– write 40h or 10h
– write Address & Data
(memory enters read status state after
the Program command)
Write 40h or 10h
Write Address
& Data
do:
–read Status Register if Program/Erase
Suspend command given execute
suspend program loop
NO
Read Status
Register
Suspend
b7 = 1
NO
YES
Suspend
Loop
while b7 = 1
YES
b3 = 0
NO
VPP Invalid
Error (1, 2)
If b3 = 1, VPP invalid error:
– error handler
NO
Program
Error (1, 2)
If b4 = 1, Program error:
– error handler
NO
Program to Protected
Block Error (1, 2)
YES
b4 = 0
YES
LPC
Interface
Only
b1 = 0
If b1 = 1, Program to protected block error:
– error handler
YES
End
AI04433
Note: 1. A Status check of b1 (Protected Block), b3 (V PP invalid) and b4 (Program Error) can be made after each Program operation by
following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
37/44
M50LPW080
Figure 18. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)
Start
Write 30h
Write Address 1
& Data 1 (3)
Quadruple Byte Program command:
– write 30h
– write Address 1 & Data 1 (3)
– write Address 2 & Data 2 (3)
– write Address 3 & Data 3 (3)
– write Address 4 & Data 4 (3)
Write Address 2
& Data 2 (3)
(memory enters read status state after
the Quadruple Byte Program command)
Write Address 3
& Data 3 (3)
Write Address 4
& Data 4 (3)
do:
– read Status Register if Program/Erase
Suspend command given execute
suspend program loop
NO
Read Status
Register
Suspend
b7 = 1
NO
YES
Suspend
Loop
while b7 = 1
YES
b3 = 0
NO
VPP Invalid
Error (1, 2)
If b3 = 1, VPP invalid error:
– error handler
NO
Program
Error (1, 2)
If b4 = 1, Program error:
– error handler
YES
b4 = 0
YES
End
AI03982
Note: 1. A Status check of b3 (VPP invalid) and b4 (Program Error) can be made after each Program operation by following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Address 1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A10.
38/44
M50LPW080
Figure 19. Program Suspend and Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend command:
– write B0h
– write 70h
Write 70h
do:
– read Status Register
Read Status
Register
b7 = 1
NO
while b7 = 1
YES
b2 = 1
NO
Program Complete
If b2 = 0 Program completed
YES
Write a read
Command
Read data from
another address
Write D0h
Write FFh
Program Continues
Read Data
Program/Erase Resume command:
– write D0h to resume the program
– if the Program operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
AI03408
39/44
M50LPW080
Figure 20. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)
Start
Chip Erase command:
– write 80h
– write 10h
(memory enters read Status Register after
the Chip Erase command)
Write 80h
Write 10h
do:
– read Status Register
Read Status
Register
b7 = 1
NO
while b7 = 1
YES
b3 = 0
NO
VPP Invalid
Error (1)
NO
Command
Sequence Error (1)
If b3 = 1, VPP invalid error:
– error handler
YES
b4, b5 = 0
If b4, b5 = 1, Command sequence error:
– error handler
YES
b5 = 0
NO
Erase Error (1)
If b5 = 1, Erase error:
– error handler
YES
End
AI04195
Note: If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
40/44
M50LPW080
Figure 21. Block Erase Flowchart and Pseudo Code
Start
Block Erase command:
– write 20h
– write Block Address & D0h
(memory enters read Status Register after
the Block Erase command)
Write 20h
Write Block Address
& D0h
Suspend
b7 = 1
do:
– read Status Register
– if Program/Erase Suspend command
given execute suspend erase loop
NO
Read Status
Register
NO
YES
Suspend
Loop
while b7 = 1
YES
b3 = 0
NO
VPP Invalid
Error (1)
NO
Command
Sequence Error (1)
If b3 = 1, VPP invalid error:
– error handler
YES
b4, b5 = 0
If b4, b5 = 1, Command sequence error:
– error handler
YES
b5 = 0
NO
Erase Error (1)
If b5 = 1, Erase error:
– error handler
YES
LPC
Interface
Only
b1 = 0
NO
Erase to Protected
Block Error (1)
If b1 = 1, Erase to protected block error:
– error handler
YES
End
AI04434
Note: If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
41/44
M50LPW080
Figure 22. Erase Suspend and Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend command:
– write B0h
– write 70h
Write 70h
do:
– read Status Register
Read Status
Register
b7 = 1
NO
while b7 = 1
YES
b6 = 1
NO
Erase Complete
If b6 = 0, Erase completed
YES
Read data from
another block
or
Program
Write D0h
Write FFh
Erase Continues
Read Data
Program/Erase Resume command:
– write D0h to resume erase
– if the Erase operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
AI03410
42/44
M50LPW080
REVISION HISTORY
Table 30. Revision History
Date
Version
April 2001
-01
First Issue
22-June-2001
-02
Clock Cycle Number 2 changed (Table 7. and Table 8.)
Low Pin Count Register Configuration Map (Table 12.) clarification
03-Sep-2001
-03
PLCC32 package added
Note 2 changed under Table 4.
24-Oct-2001
-04
Document Status changed from Product Preview to Preliminary Data
VPP Optional Supply Voltage section clarified
12-Mar-2002
-05
RFU pins must be left disconnected
Specification of PLCC32 package mechanical data revised
8.0
Revision numbering modified. Document reformatted.
Temperature Range ordering information replaced by Device Grade, Standard
packing option added and Plating Technology added. TLEAD parameter added to
Absolute Maximum Ratings and TBIAS parameter removed.
Inch values corrected in TSOP40 package mechanical data.
02-Aug-2004
Revision Details
43/44
M50LPW080
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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44/44