Numonyx M58LR256KC785 128 or 256 mbit (x16, mux i/o, multiple bank, multilevel interface, burst) 1.8 v supply flash memory Datasheet

M58LR128KC, M58LR128KD
M58LR256KC, M58LR256KD
128 or 256 Mbit (x16, mux I/O, multiple bank,
multilevel interface, burst) 1.8 V supply Flash memories
Target Specification
Features
■
Supply voltage
– VDD = 1.7 V to 2.0 V for program, erase and
read
– VDDQ = 1.7 V to 2.0 V for I/O buffers
– VPP = 9 V for fast program
■
Multiplexed address/data
■
Synchronous/asynchronous read
– Synchronous burst read mode:
66 MHz, 86 MHz
– Random access: 70 ns
■
Synchronous burst read suspend
■
Programming time
– 2.5 µs typical word program time using
Buffer Enhanced Factory Program
command
■
Memory organization
– Multiple bank memory array:
8 Mbit banks for the M58LR128KC/D
16 Mbit banks for the M58LR256KC/D
– Parameter blocks (top or bottom location)
■
Dual operations
– Program/erase in one bank while read in
others
– No delay between read and write
operations
■
Common Flash interface (CFI)
■
100 000 program/erase cycles per block
Wafer
■
Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for block lock-down
– Absolute write protection with VPP = VSS
■
Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■
Electronic signature
– Manufacturer code: 20h
– Top device codes:
M58LR128KC: 882Eh
M58LR256KC: 881Ch
– Bottom device codes
M58LR128KD: 882Fh
M58LR256KD: 881Dh
The M58LRxxxKC/D memories are only available as part of a multichip package.
March 2008
Rev 3
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1/108
www.numonyx.com
1
Contents
M58LRxxxKC, M58LRxxxKD
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
4
2/108
2.1
Address inputs (ADQ0-ADQ15 and A16-Amax) . . . . . . . . . . . . . . . . . . . . 13
2.2
Data input/output (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7
Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.8
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.9
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.11
VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.12
VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.13
VPP program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.14
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.15
VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
Bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3
Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
M58LRxxxKC, M58LRxxxKD
5
6
Contents
4.5
Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7
Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.9
Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.10
Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 23
4.10.1
Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.10.2
Program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.10.3
Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.11
Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.12
Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.13
Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.14
Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.15
Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.16
Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.17
Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1
Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2
Erase suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3
Erase/blank check status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4
Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5
VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.6
Program suspend status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.7
Block protection status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.8
Bank write/multiple word program status bit (SR0) . . . . . . . . . . . . . . . . . 35
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1
Read select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2
X latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3
Wait polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.4
Data output configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5
Wait configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.6
Burst type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Contents
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M58LRxxxKC, M58LRxxxKD
6.7
Valid clock edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.8
Wrap burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.9
Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.1
Asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2
Synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.1
7.3
Synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8
Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 47
9
Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.1
Reading a block’s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.2
Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.3
Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.4
Lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.5
Locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 50
10
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 52
11
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13
Part ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Appendix B Common Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Appendix C Flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14
4/108
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
M58LRxxxKC, M58LRxxxKD
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
M58LR128KC/D bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
M58LR256KC/D bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Factory commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
X latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Program/erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Asynchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Synchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Write AC characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Write AC characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Reset and power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
M58LR128KC - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
M58LR128KC - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
M58LR128KC - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
M58LR256KC - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
M58LR256KC - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
M58LR256KC - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
M58LR128KD - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
M58LR128KD - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
M58LR128KD - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
M58LR256KD - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
M58LR256KD - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
M58LR256KD - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5/108
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
6/108
M58LRxxxKC, M58LRxxxKD
Bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Command interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 101
Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 105
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
M58LRxxxKC, M58LRxxxKD
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
M58LR128KC/D memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
M58LR256KC/D memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
X latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Asynchronous random access read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Synchronous burst read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Single synchronous read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Synchronous burst read suspend AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Write AC waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Write AC waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Reset and power-up AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Blank check flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Buffer program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Program suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . 92
Block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Erase suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Locking operations flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Protection Register program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Buffer enhanced factory program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . 97
7/108
Description
1
M58LRxxxKC, M58LRxxxKD
Description
The M58LR128KC/D and M58LR256KC/D are 128 Mbit (8 Mbit ×16) and 256 Mbit
(16 Mbit ×16) non-volatile Flash memories, respectively. They may be erased electrically at
block level and programmed in-system on a word-by-word basis using a 1.7 V to 2.0 V VDD
supply for the circuitry and a 1.7 V to 2.0 V VDDQ supply for the input/output pins. An
optional 9 V VPP power supply is provided to speed up factory programming. In the rest of
the document they are collectively referred to as the M58LRxxxKC/D unless otherwise
specified.
The first sixteen address lines are multiplexed with the data input/output signals on the
multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-Amax are
the most significant bit addresses.
The devices feature an asymmetrical block architecture:
●
The M58LR128KC/D has an array of 131 blocks, and are divided into 8 Mbit banks.
There are 15 banks each containing 8 main blocks of 64 KWords, and one parameter
bank containing 4 parameter blocks of 16 KWords and 7 main blocks of 64 KWords.
●
The M58LR256KC/D has an array of 259 blocks, and is divided into 16 Mbit banks.
There are 15 banks each containing 16 main blocks of 64 KWords, and one parameter
bank containing 4 parameter blocks of 16 KWords and 15 main blocks of 64 KWords.
The multiple bank architecture allows dual operations; while programming or erasing in one
bank, read operations are possible in other banks. Only one bank at a time is allowed to be
in program or erase mode. It is possible to perform burst reads that cross bank boundaries.
The bank architectures are summarized in Table 2 and Table 3 and the memory maps are
shown in Figure 2 and Figure 3. The parameter blocks are located at the top of the memory
address space for the M58LR128KC and M58LR256KC, and at the bottom for the
M58LR128KD and M58LR256KD.
Each block can be erased separately. Erase can be suspended to perform a program or
read operation in any other block, and then resumed. Program can be suspended to read
data at any memory location except for the one being programmed, and then resumed.
Each block can be programmed and erased over 100 000 cycles using the supply voltage
VDD. There is a Buffer Enhanced Factory Programming command available to speed up
programming.
Program and erase commands are written to the command interface of the memory. An
internal Program/Erase Controller manages the timings necessary for program and erase
operations. The end of a program or erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The device supports synchronous burst read and asynchronous read from all blocks of the
memory array; at power-up the device is configured for asynchronous read. In synchronous
burst read mode, data is output on each clock cycle at frequencies of up to 86 MHz. The
synchronous burst read operation can be suspended and resumed.
The device features an automatic standby mode. When the bus is inactive during
asynchronous read operations, the device automatically switches to the automatic standby
mode. In this condition the power consumption is reduced to the standby value and the
outputs are still driven.
8/108
M58LRxxxKC, M58LRxxxKD
Description
The M58LRxxxKC/D features an instant, individual block locking scheme that allows any
block to be locked or unlocked with no latency, enabling instant code and data protection. All
blocks have three levels of protection. They can be locked and locked-down individually
preventing any accidental programming or erasure. There is an additional hardware
protection against program and erase. When VPP ≤VPPLK all blocks are protected against
program or erase. All blocks are locked at power-up.
The device includes 17 Protection Registers and 2 Protection Register locks, one for the first
Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection
Registers of 128 bits each. The first Protection Register is divided into two segments: a 64
bit segment containing a unique device number written by Numonyx, and a 64 bit segment
that is OTP by the user. The user programmable segment can be permanently protected.
Figure 4, shows the Protection Register memory map.
The devices are supplied with all the bits erased (set to ’1’)
Note:
The M58LRxxxKC/D is only available as part of a multichip package.
9/108
Description
M58LRxxxKC, M58LRxxxKD
Figure 1.
Logic diagram
VDD VDDQ VPP
16
A16-Amax(1)
ADQ0-ADQ15
W
E
G
RP
M58LR128KC
M58LR128KD
M58LR256KC
M58LR256KD
WAIT
WP
L
K
VSS
VSSQ
AI13453c
1. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D.
Table 1.
Signal names
Name
Function
A16-Amax(1)
Address inputs
ADQ0-ADQ15
Data input/outputs or address inputs, command inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset
WP
Write Protect
K
Clock
L
Latch Enable
WAIT
Wait
VDD
Supply voltage
VDDQ
Supply voltage for input/output buffers
VPP
Optional supply voltage for fast program and erase
VSS
Ground
VSSQ
Ground input/output supply
1. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D.
10/108
M58LRxxxKC, M58LRxxxKD
Table 2.
Description
M58LR128KC/D bank architecture
Parameter bank
8 Mbits
4 blocks of 16 KWords
7 blocks of 64 KWords
Bank 1
8 Mbits
-
8 blocks of 64 KWords
Bank 2
8 Mbits
-
8 blocks of 64 KWords
Bank 3
8 Mbits
-
8 blocks of 64 KWords
----
Main blocks
----
Parameter blocks
----
Bank size
----
Number
Bank 14
8 Mbits
-
8 blocks of 64 KWords
Bank 15
8 Mbits
-
8 blocks of 64 KWords
Figure 2.
M58LR128KC/D memory map
M58LR128KC - Top Boot Block
Address lines A22-A16 and ADQ15-ADQ0
M58LR128KD - Bottom Boot Block
Address lines A22-A16 and ADQ15-ADQ0
000000h
00FFFFh
64 KWord
000000h
003FFFh
070000h
07FFFFh
64 KWord
8 Main
Blocks
Bank 15
600000h
60FFFFh
8 Main
Blocks
6F0000h
6FFFFFh
700000h
70FFFFh
Parameter
Bank
7E0000h
7EFFFFh
7F0000h
7F3FFFh
7FC000h
7FFFFFh
170000h
17FFFFh
180000h
18FFFFh
64 KWord
8 Main
Blocks
16 KWord
64 KWord
7 Main
Blocks
64 KWord
64 KWord
8 Main
Blocks
64 KWord
64 KWord
8 Main
Blocks
Bank 2
64 KWord
Bank 1
770000h
77FFFFh
780000h
78FFFFh
0F0000h
0FFFFFh
100000h
10FFFFh
64 KWord
Bank 2
4 Parameter
Blocks
Bank 1
64 KWord
8 Main
Blocks
00C000h
00FFFFh
010000h
01FFFFh
070000h
07FFFFh
080000h
08FFFFh
64 KWord
Bank 3
670000h
67FFFFh
680000h
68FFFFh
Parameter
Bank
16 KWord
64 KWord
64 KWord
8 Main
Blocks
Bank 3
64 KWord
1F0000h
1FFFFFh
64 KWord
780000h
78FFFFh
64 KWord
7F0000h
7FFFFFh
64 KWord
64 KWord
7 Main
Blocks
64 KWord
16 KWord
4 Parameter
Blocks
Bank 15
16 KWord
8 Main
Blocks
AI13454b
11/108
Description
Table 3.
M58LRxxxKC, M58LRxxxKD
M58LR256KC/D bank architecture
Parameter bank
16 Mbits
4 blocks of 16 KWords
15 blocks of 64 KWords
Bank 1
16 Mbits
-
16 blocks of 64 KWords
Bank 2
16 Mbits
-
16 blocks of 64 KWords
Bank 3
16 Mbits
-
16 blocks of 64 KWords
----
Main blocks
----
Parameter blocks
----
Bank size
----
Number
Bank 14
16 Mbits
-
16 blocks of 64 KWords
Bank 15
16 Mbits
-
16 blocks of 64 KWords
Figure 3.
M58LR256KC/D memory map
M58LR256KD- Bottom Boot Block
Address lines A23-A16 and ADQ15-ADQ0
M58LR256KC - Top Boot Block
Address lines A23-A16 and ADQ15-ADQ0
000000h
00FFFFh
64 KWord
0F0000h
0FFFFFh
64 KWord
Bank 15
C00000h
C0FFFFh
16 Main
Blocks
EF0000h
EFFFFFh
F00000h
F0FFFFh
Parameter
Bank
FE0000h
FEFFFFh
FF0000h
FF3FFFh
FFC000h
FFFFFFh
1F0000h
1FFFFFh
200000h
20FFFFh
2F0000h
2FFFFFh
300000h
30FFFFh
64 KWord
16 Main
Blocks
4 Parameter
Blocks
16 KWord
64 KWord
15 Main
Blocks
64 KWord
64 KWord
16 Main
Blocks
64 KWord
64 KWord
16 Main
Blocks
Bank 2
64 KWord
Bank 1
16 KWord
Bank 1
64 KWord
16 Main
Blocks
00C000h
00FFFFh
010000h
01FFFFh
0F0000h
0FFFFFh
100000h
10FFFFh
64 KWord
Bank 2
DF0000h
DFFFFFh
E00000h
E0FFFFh
Parameter
Bank
64 KWord
Bank 3
CF0000h
CFFFFFh
D00000h
D0FFFFh
000000h
003FFFh
16 Main
Blocks
64 KWord
64 KWord
16 Main
Blocks
Bank 3
64 KWord
3F0000h
3FFFFFh
64 KWord
F00000h
F0FFFFh
64 KWord
FF0000h
FFFFFFh
64 KWord
64 KWord
15 Main
Blocks
64 KWord
16 KWord
4 Parameter
Blocks
16 KWord
16 Main
Blocks
Bank 15
AI13786b
12/108
M58LRxxxKC, M58LRxxxKD
2
Signal descriptions
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals
connected to this device.
2.1
Address inputs (ADQ0-ADQ15 and A16-Amax)
Amax is the highest order address input. It is equal to A22 in the M58LR128KC/D and to
A23 in the M58LR256KC/D. The address inputs select the cells in the memory array to
access during bus read operations. During bus write operations they control the commands
sent to the command interface of the Program/Erase Controller.
2.2
Data input/output (ADQ0-ADQ15)
The data I/O output the data stored at the selected address during a bus read operation or
input a command or the data to be programmed during a bus write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is deselected, the outputs are high
impedance and the power consumption is reduced to the standby level.
2.4
Output Enable (G)
The Output Enable input controls data outputs during the bus read operation of the memory.
2.5
Write Enable (W)
The Write Enable input controls the bus write operation of the memory’s command interface.
The data and address inputs are latched on the rising edge of Chip Enable or Write Enable,
whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at VIL, the lock-down is enabled and the protection status of the lockeddown blocks cannot be changed. When Write Protect is at VIH, the lock-down is disabled
and the locked-down blocks can be locked or unlocked. (Refer to Table 17: Lock status).
13/108
Signal descriptions
2.7
M58LRxxxKC, M58LRxxxKD
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the reset supply current IDD2. Refer to Table 22: DC characteristics - currents, for
the value of IDD2. After Reset all blocks are in the locked state and the Configuration
Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset
mode the device enters asynchronous read mode, but a negative transition of Chip Enable
or Latch Enable is required to ensure valid data outputs.
2.8
Latch Enable (L)
Latch Enable latches the ADQ0-ADQ15 and A16-Amax address bits on its rising edge. The
address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch
Enable is at VIH.
2.9
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous
read and in write operations.
2.10
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is
at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance.
The WAIT signal is forced deasserted when Output Enable is at VIH.
2.11
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (read, program and erase).
2.12
VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all outputs to be powered
independently from VDD. VDDQ can be tied to VDD or can use a separate supply.
14/108
M58LRxxxKC, M58LRxxxKD
2.13
Signal descriptions
VPP program supply voltage
VPP is both a control input and a power supply pin. The two functions are selected by the
voltage range applied to the pin.
If VPP is kept in a low voltage range (0 V to VDDQ) VPP is seen as a control input. In this case
a voltage lower than VPPLK gives absolute protection against program or erase, while VPP in
the VPP1 range enables these functions (see Tables 22 and 23, DC Characteristics, for the
relevant values). VPP is only sampled at the beginning of a program or erase; a change in its
value after the operation has started does not have any effect and program or erase
operations continue.
If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be
stable until the program/erase algorithm is completed.
2.14
VSS ground
VSS ground is the reference for the core supply. It must be connected to the system ground.
2.15
VSSQ ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be
connected to VSS
Note:
Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1 µF ceramic
capacitor close to the pin (high-frequency, inherently-low inductance capacitors should be
as close as possible to the package). See Figure 8: AC measurement load circuit. The PCB
track widths should be sufficient to carry the required VPP program and erase currents.
15/108
Bus operations
3
M58LRxxxKC, M58LRxxxKD
Bus operations
There are six standard bus operations that control the device. These are bus read, bus
write, address latch, output disable, standby and reset. See Table 4: Bus operations, for a
summary.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus write operations.
3.1
Bus read
Bus read operations output the contents of the memory array, the electronic signature, the
Status Register and the common Flash interface. Both Chip Enable and Output Enable must
be at VIL to perform a read operation. The Chip Enable input should be used to enable the
device, and Output Enable should be used to gate data onto the output. The data read
depends on the previous command written to the memory (see Section 4: Command
interface). See Figures 9, 10 and 11 Read AC Waveforms, and Tables 24 and 25 Read AC
Characteristics, for details of when the output becomes valid.
3.2
Bus write
Bus write operations write commands to the memory or latch Input Data to be programmed.
A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output
Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of
Write Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to
the write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch Enable
must be tied to VIH during the bus write operation.
See Figures 14 and 15, Write AC Waveforms, and Tables 26 and 27, Write AC
Characteristics, for details of the timing requirements.
3.3
Address Latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be
at VIL during address latch operations. The addresses are latched on the rising edge of
Latch Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at VIH.
16/108
M58LRxxxKC, M58LRxxxKD
3.5
Bus operations
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power
consumption is reduced to the standby level IDD3 and the outputs are set to high impedance,
independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH
during a program or erase operation, the device enters standby mode when finished.
3.6
Reset
During reset mode the memory is deselected and the outputs are high impedance. The
memory is in reset mode when Reset is at VIL. The power consumption is reduced to the
reset level, independently from the Chip Enable, Output Enable, or Write Enable inputs. If
Reset is pulled to VSS during a program or erase, this operation is aborted and the memory
content is no longer valid.
Table 4.
Bus operations(1)
Operation
WAIT(2)
E
G
W
L
RP
Bus Read
VIL
VIL
VIH
VIH
VIH
Data Output
Bus write
VIL
VIH
VIL
VIH
VIH
Data Input
Address Latch
VIL
VIH
X
VIL
VIH
Address Input
Output Disable
VIL
VIH
VIH
VIH
VIH
Hi-Z
Standby
VIH
X
X
X
VIH
Hi-Z
Hi-Z
X
X
X
X
VIL
Hi-Z
Hi-Z
Reset
ADQ15-ADQ0
1. X = ‘don't care’
2. WAIT signal polarity is configured using the Set Configuration Register command.
17/108
Command interface
4
M58LRxxxKC, M58LRxxxKD
Command interface
All bus write operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential bus write operations. An internal
Program/Erase Controller manages all timings and verifies the correct execution of the
program and erase commands. The Program/Erase Controller provides a Status Register,
whose output may be read at any time to monitor the progress or the result of the operation.
The command interface is reset to read mode when power is first applied, when exiting from
reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly.
Any invalid combinations of commands are ignored.
Refer to Table 5: Command codes, Table 6: Standard commands, Table 7: Factory
commands, and Appendix D: Command interface state tables for a summary of the
command interface.
Table 5.
Command codes
Hex Code
18/108
Command
01h
Block Lock Confirm
03h
Set Configuration Register Confirm
10h
Alternative Program Setup
20h
Block Erase Setup
2Fh
Block Lock-Down Confirm
40h
Program Setup
50h
Clear Status Register
60h
Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set
Configuration Register Setup
70h
Read Status Register
80h
Buffer Enhanced Factory Program Setup
90h
Read Electronic Signature
98h
Read CFI Query
B0h
Program/Erase Suspend
BCh
Blank Check Setup
C0h
Protection Register Program
CBh
Blank Check Confirm
D0h
Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm, Buffer
Program or Buffer Enhanced Factory Program Confirm
E8h
Buffer Program
FFh
Read Array
M58LRxxxKC, M58LRxxxKD
4.1
Command interface
Read Array command
The Read Array command returns the addressed bank to read array mode.
One bus write cycle is required to issue the Read Array command. Once a bank is in read
array mode, subsequent read operations output the data from the memory array.
A Read Array command can be issued to any banks while programming or erasing in
another bank.
If the Read Array command is issued to a bank currently executing a program or erase
operation, the bank returns to read array mode but the program or erase operation
continues. However, the data output from the bank is not guaranteed until the program or
erase operation has finished. The read modes of other banks are not affected.
4.2
Read Status Register command
The device contains a Status Register that monitors program or erase operations.
The Read Status Register command reads the contents of the Status Register for the
addressed bank.
One bus write cycle is required to issue the Read Status Register command. Once a bank is
in read Status Register mode, subsequent read operations output the contents of the Status
Register.
The Status Register data is latched on the falling edge of the Chip Enable or Output Enable
signals. Either Chip Enable or Output Enable must be toggled to update the Status Register
data.
The Read Status Register command can be issued at any time, even during program or
erase operations. The Read Status Register command only changes the read mode of the
addressed bank. The read modes of other banks are not affected. Only asynchronous read
and single synchronous read operations should be used to read the Status Register. A Read
Array command is required to return the bank to read array mode.
See Table 10 for the description of the Status Register bits.
4.3
Read Electronic Signature command
The Read Electronic Signature command reads the manufacturer and device codes, the
lock status of the addressed bank, the Protection Register, and the Configuration Register.
One bus write cycle is required to issue the Read Electronic Signature command. Once a
bank is in read electronic signature mode, subsequent read operations in the same bank
output the manufacturer code, the device code, the lock status of the addressed bank, the
Protection Register, or the Configuration Register (see Table 8).
The Read Electronic Signature command can be issued at any time, even during program or
erase operations, except during Protection Register program operations. Dual operations
between the parameter bank and the electronic signature location are not allowed (see
Table 16: Dual operation limitations for details).
19/108
Command interface
M58LRxxxKC, M58LRxxxKD
If a Read Electronic Signature command is issued to a bank that is executing a program or
erase operation, the bank goes into read electronic signature mode. Subsequent bus read
cycles output the electronic signature data and the Program/Erase Controller continues to
program or erase in the background.
The Read Electronic Signature command only changes the read mode of the addressed
bank. The read modes of other banks are not affected. Only asynchronous read and single
synchronous read operations should be used to read the electronic signature. A Read Array
command is required to return the bank to read array mode.
4.4
Read CFI Query command
The Read CFI Query command reads data from the common Flash interface (CFI).
One bus write cycle is required to issue the Read CFI Query command. Once a bank is in
read CFI query mode, subsequent bus read operations in the same bank read from the
common Flash interface.
The Read CFI Query command can be issued at any time, even during program or erase
operations.
If a Read CFI Query command is issued to a bank that is executing a program or erase
operation, the bank goes into read CFI query mode. Subsequent bus read cycles output the
CFI data and the Program/Erase Controller continues to program or erase in the
background.
The Read CFI Query command only changes the read mode of the addressed bank; the
read modes of other banks are not affected. Only asynchronous read and single
synchronous read operations should be used to read from the CFI. A Read Array command
is required to return the bank to read array mode. Dual operations between the parameter
bank and the CFI memory space are not allowed (see Table 16: Dual operation limitations
for details).
See Appendix B: Common Flash interface and Tables 42, 43, 44, 45, 46, 47, 48, 49, 50 and
51 for details on the information contained in the common Flash interface memory area.
4.5
Clear Status Register command
The Clear Status Register command resets (set to ‘0’) all error bits (SR1, 3, 4 and 5) in the
Status Register.
One bus write cycle is required to issue the Clear Status Register command. The Clear
Status Register command does not affect the read mode of the bank.
The error bits in the Status Register do not automatically return to ‘0’ when a new command
is issued. The error bits in the Status Register should be cleared before attempting a new
program or erase command.
20/108
M58LRxxxKC, M58LRxxxKD
4.6
Command interface
Block Erase command
The Block Erase command erases a block. It sets all the bits within the selected block to ’1,
and all previous data in the block is lost.
If the block is protected then the erase operation aborts, the data in the block does not
change, and the Status Register outputs the error.
Two bus write cycles are required to issue the command:
●
The first bus cycle sets up the Block Erase command.
●
The second latches the block address and starts the Program/Erase Controller.
If the second bus cycle is not the block erase confirm code, Status Register bits SR4 and
SR5 are set and the command is aborted.
Once the command is issued the bank enters read Status Register mode and any read
operation within the addressed bank outputs the contents of the Status Register. A Read
Array command is required to return the bank to read array mode.
During block erase operations the bank containing the block being erased only accepts the
Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and the
Program/Erase Suspend commands; all other commands are ignored.
The block erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be
guaranteed when the block erase operation is aborted, the block must be erased again.
Refer to Section 8 for detailed information about simultaneous operations allowed in banks
not being erased.
Typical Erase times are given in Table 18: Program/erase times and endurance cycles.
See Appendix C, Figure 21: Block erase flowchart and pseudocode for a suggested
flowchart for using the Block Erase command.
4.7
Blank Check command
The Blank Check command checks whether a main array block has been completely
erased. Only one block at a time can be checked. To use the Blank Check command VPP
must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the command and no
error is shown in the Status Register.
Two bus cycles are required to issue the Blank Check command:
●
The first bus cycle writes the Blank Check command (BCh) to any address in the block
to be checked.
●
The second bus cycle writes the Blank Check Confirm command (CBh) to any address
in the block to be checked and starts the blank check operation.
If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are
set to '1' and the command aborts.
Once the command is issued, the addressed bank automatically enters Status Register
mode and further reads within the bank output the Status Register contents.
The only operation permitted during blank check is read Status Register. Dual operations
are not supported while a blank check operation is in progress. Blank check operations
cannot be suspended and are not allowed while the device is in Program/Erase Suspend.
21/108
Command interface
M58LRxxxKC, M58LRxxxKD
The SR7 Status Register bit indicates the status of the blank check operation in progress.
SR7 = '0' means that the blank check operation is still ongoing, and SR7 = '1' means that the
operation is complete.
The SR5 Status Register bit goes High (SR5 = '1') to indicate that the blank check operation
has failed.
At the end of the operation the bank remains in the read Status Register mode until another
command is written to the command interface.
See Appendix C, Figure 18: Blank check flowchart and pseudocode for a suggested
flowchart for using the Blank Check command.
Typical blank check times are given in Table 18: Program/erase times and endurance
cycles.
4.8
Program command
The program command programs a single word to the memory array.
If the block being programmed is protected, then the program operation will abort, the data
in the block does not change and the Status Register outputs the error.
Two bus write cycles are required to issue the Program command.
●
The first bus cycle sets up the Program command.
●
The second latches the address and data to be programmed and starts the
Program/Erase Controller.
Once the programming has started, read operations in the bank being programmed output
the Status Register content.
During a program operation, the bank containing the word being programmed only accepts
the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and the
Program/Erase Suspend commands; all other commands are ignored. A Read Array
command is required to return the bank to read array mode.
Refer to Section 8 for detailed information about simultaneous operations allowed in banks
not being programmed.
Typical program times are given in Table 18: Program/erase times and endurance cycles.
The program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be
guaranteed when the program operation is aborted, the word must be reprogrammed.
See Appendix C, Figure 17: Program flowchart and pseudocode for the flowchart for using
the Program command.
22/108
M58LRxxxKC, M58LRxxxKD
4.9
Command interface
Buffer Program command
The Buffer Program command uses the device’s 32-word write buffer to speed up
programming. Up to 32 words can be loaded into the write buffer. The Buffer Program
command dramatically reduces in-system programming time compared to the standard nonbuffered Program command.
Four successive steps are required to issue the Buffer Program command:
1.
The first bus write cycle sets up the Buffer Program command. The setup code can be
addressed to any location within the targeted block.
After the first bus write cycle, read operations in the bank output the contents of the
Status Register. Status Register bit SR7 should be read to check that the buffer is
available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program
command to update the Status Register contents.
2.
The second bus write cycle sets up the number of words to be programmed. Value n is
written to the same block address, where n+1 is the number of words to be
programmed.
3.
Use n+1 bus write cycles to load the address and data for each word into the write
buffer. Addresses must lie within the range from the start address to the start
address + n, where the start address is the location of the first data to be programmed.
Optimum performance is obtained when the start address corresponds to a 32-word
boundary.
4.
The final bus write cycle confirms the Buffer Program command and starts the program
operation.
All the addresses used in the buffer program operation must be within the same block.
Address combinations that are invalid or that do not follow the correct bus write cycle
sequence set an error in the Status Register and abort the operation without affecting the
data in the memory array.
If the block being programmed is protected an error is set in the Status Register and the
operation aborts without affecting the data in the memory array.
During buffer program operations the bank being programmed only accepts the Read Array,
Read Status Register, Read Electronic Signature, Read CFI Query, and Program/Erase
Suspend commands; all other commands are ignored.
Refer to Section 8 for detailed information about simultaneous operations allowed in banks
not being programmed.
See Appendix C, Figure 19: Buffer program flowchart and pseudocode for a suggested
flowchart on using the Buffer Program command.
4.10
Buffer Enhanced Factory Program command
The Buffer Enhanced Factory Program command has been specially developed to speed up
programming in manufacturing environments where the programming time is critical.
It is used to program one or more write buffer(s) of 32 words to a block. Once the device
enters buffer enhanced factory program mode, the write buffer can be reloaded any number
of times as long as the address remains within the same block. Only one block can be
programmed at a time.
23/108
Command interface
M58LRxxxKC, M58LRxxxKD
If the block being programmed is protected, then the program operation aborts, the data in
the block does not change, and the Status Register outputs the error.
The use of the Buffer Enhanced Factory Program command requires certain operating
conditions:
●
VPP must be set to VPPH
●
VDD must be within operating range
●
Ambient temperature TA must be 30°C ± 10°C
●
The targeted block must be unlocked
●
The start address must be aligned with the start of a 32-word buffer boundary
●
The address must remain the start address throughout programming.
Dual operations are not supported during the Buffer Enhanced Factory program operation
and the command cannot be suspended.
The Buffer Enhanced Factory Program Command consists of three phases: the setup
phase, the program and verify phase, and the exit phase. Refer to Table 7: Factory
commands for detailed information.
4.10.1
Setup phase
The Buffer Enhanced Factory Program command requires two bus write cycles to initiate the
command:
●
The first bus write cycle sets up the Buffer Enhanced Factory Program command.
●
The second bus write cycle confirms the command.
After the confirm command is issued, read operations output the contents of the Status
Register. The Read Status Register command must not be issued or it is interpreted as data
to program.
The Status Register P/EC Bit SR7 should be read to check that the P/EC is ready to
proceed to the next phase.
If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory program
operation is terminated. See Section 5: Status Register for details on the error.
4.10.2
Program and verify phase
The program and verify phase requires 32 cycles to program the 32 words to the write
buffer. The data is stored sequentially, starting at the first address of the write buffer, until the
write buffer is full (32 words). To program less than 32 words, the remaining words should be
programmed with FFFFh.
Three successive steps are required to issue and execute the program and verify phase of
the command:
1.
24/108
Use one bus write operation to latch the start address and the first word to be
programmed. The Status Register bank write status bit SR0 should be read to check
that the P/EC is ready for the next word.
M58LRxxxKC, M58LRxxxKD
Command interface
2.
Each subsequent word to be programmed is latched with a new bus write operation.
The address must remain the start address as the P/EC increments the address
location.If any address is given that is not in the same block as the start address, the
program and verify phase terminates. Status Register bit SR0 should be read between
each bus write cycle to check that the P/EC is ready for the next word.
3.
Once the write buffer is full, the data is programmed sequentially to the memory array.
After the program operation the device automatically verifies the data and reprograms if
necessary.
The program and verify phase can be repeated, without re-issuing the command, to
program additional 32-word locations as long as the address remains in the same block.
4.
Finally, after all words, or the entire block, have been programmed, write one bus write
operation to any address outside the block containing the start address, to terminate
program and verify phase.
Status Register bit SR0 must be checked to determine whether the program operation is
finished. The Status Register may be checked for errors at any time but it must be checked
after the entire block has been programmed.
4.10.3
Exit phase
Status Register P/EC bit SR7 set to ‘1’ indicates that the device has exited the buffer
enhanced factory program operation and returned to read Status Register mode. A full
Status Register check should be done to ensure that the block has been successfully
programmed. See tSection 5: Status Register for more details.
For optimum performance the Buffer Enhanced Factory Program command should be
limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the
internal algorithm continues to work properly but some degradation in performance is
possible. Typical program times are given in Table 18.
See Appendix C, Figure 25: Buffer enhanced factory program flowchart and pseudocode for
a suggested flowchart on using the Buffer Enhanced Factory Program command.
4.11
Program/Erase Suspend command
The Program/Erase Suspend command pauses a program or block erase operation. The
command can be addressed to any bank.
The Program/Erase Resume command is required to restart the suspended operation.
One bus write cycle is required to issue the Program/Erase Suspend command. Once the
Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register is
set to ‘1’.
The following commands are accepted during program/erase suspend:
–
Program/Erase Resume
–
Read Array (data from erase-suspended block or program-suspended word is not
valid)
–
Read Status Register
–
Read Electronic Signature
–
Read CFI Query
–
Clear Status Register
25/108
Command interface
M58LRxxxKC, M58LRxxxKD
In addition, if the suspended operation was a block erase then the following commands are
also accepted:
–
Set Configuration Register
–
Program (except in erase-suspended block)
–
Buffer Program (except in erase suspended blocks)
–
Block Lock
–
Block Lock-Down
–
Block Unlock.
During an erase suspend the block being erased can be protected by issuing the Block Lock
or Block Lock-Down commands. When the Program/Erase Resume command is issued the
operation completes.
It is possible to accumulate multiple suspend operations. For example, it is possible to
suspend an erase operation, start a program operation, suspend the program operation,
and then read the array.
If a Program command is issued during a block erase suspend, the erase operation cannot
be resumed until the program operation has completed.
The Program/Erase Suspend command does not change the read mode of the banks. If the
suspended bank was in read Status Register, read electronic signature or read CFI query
mode the bank remains in that mode and outputs the corresponding data.
Refer to Section 8 for detailed information about simultaneous operations allowed during
program/erase suspend.
During a program/erase suspend, the device can be placed in standby mode by taking Chip
Enable to VIH. Program/erase is aborted if Reset, RP, goes to VIL.
See Appendix C, Figure 20: Program suspend and resume flowchart and pseudocode, and
Figure 22: Erase suspend and resume flowchart and pseudocode for flowcharts for using
the Program/Erase Suspend command.
4.12
Program/Erase Resume command
The Program/Erase Resume command restarts the program or erase operation suspended
by the Program/Erase Suspend command. One bus write cycle is required to issue the
command. The command can be issued to any address.
The Program/Erase Resume command does not change the read mode of the banks. If the
suspended bank was in read Status Register, read electronic signature or read CFI query
mode the bank remains in that mode and outputs the corresponding data.
If a Program command is issued during a block erase suspend, then the erase cannot be
resumed until the program operation has completed.
See Appendix C, Figure 20: Program suspend and resume flowchart and pseudocode, and
Figure 22: Erase suspend and resume flowchart and pseudocode for flowcharts for using
the Program/Erase Resume command.
26/108
M58LRxxxKC, M58LRxxxKD
4.13
Command interface
Protection Register Program command
The Protection Register Program command programs the user one-time-programmable
(OTP) segments of the Protection Register and the two Protection Register Locks.
The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as
shown in Figure 4: Protection Register memory map.
The segments are programmed one word at a time. When shipped, all bits in the segment
are set to ‘1’. The user can only program the bits to ‘0’.
Two bus write cycles are required to issue the Protection Register Program command:
●
The first bus cycle sets up the Protection Register Program command.
●
The second latches the address and data to be programmed to the Protection Register
and starts the Program/Erase Controller.
Read operations to the bank being programmed output the Status Register content after the
program operation has started.
Attempting to program a previously protected Protection Register results in a Status
Register error.
The Protection Register Program cannot be suspended. Dual operations between the
parameter bank and the Protection Register memory space are not allowed (see Table 16:
Dual operation limitations for details).
The two Protection Register Locks protect the OTP segments from further modification. The
protection of the OTP segments is not reversible. Refer to Figure 4: Protection Register
memory map and Table 9: Protection Register locks for details on the lock bits.
See Appendix C, Figure 24: Protection Register program flowchart and pseudocode for a
flowchart for using the Protection Register Program command.
4.14
Set Configuration Register command
The Set Configuration Register command rewrites a new value to the Configuration
Register.
Two bus write cycles are required to issue the Set Configuration Register command:
●
The first cycle sets up the Set Configuration Register command and the address
corresponding to the Configuration Register content.
●
The second cycle writes the Configuration Register data and the confirm command.
The Configuration Register data must be written as an address during the bus write cycles,
that is ADQ0 = CR0, ADQ1 = CR1, …, ADQ15 = CR15. Addresses A16-Amax are ignored.
Read operations output the array content after the Set Configuration Register command is
issued.
The Read Electronic Signature command is required to read the updated contents of the
Configuration Register.
27/108
Command interface
4.15
M58LRxxxKC, M58LRxxxKD
Block Lock command
The Block Lock command locks a block and prevents program or erase operations from
changing the data in it. All blocks are locked after power-up or reset.
Two bus write cycles are required to issue the Block Lock command:
●
The first bus cycle sets up the Block Lock command.
●
The second bus write cycle latches the block address and locks the block.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 17 shows the lock status after issuing a Block Lock command.
Once set, the block lock bits remain set even after a hardware reset or power-down/powerup. They are cleared by a Block Unlock command.
Refer to Section 9: Block locking, for a detailed explanation. See Appendix C, Figure 23:
Locking operations flowchart and pseudocode for a flowchart for using the Lock command.
4.16
Block Unlock command
The Block Unlock command unlocks a block, allowing the block to be programmed or
erased.
Two bus write cycles are required to issue the Block Unlock command.
●
The first bus cycle sets up the Block Unlock command.
●
The second bus write cycle latches the block address and unlocks the block.
The lock status can be monitored for each block using the Read Electronic Signature
command. Table 17 shows the protection status after issuing a Block Unlock command.
Refer to Section 9: Block locking for a detailed explanation and Appendix C, Figure 23:
Locking operations flowchart and pseudocode for a flowchart for using the Block Unlock
command.
4.17
Block Lock-Down command
The Block Lock-Down command locks down a locked or unlocked block.
A locked-down block cannot be programmed or erased. The lock status of a locked-down
block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function
is disabled and the locked blocks can be individually unlocked by the Block Unlock
command.
Two bus write cycles are required to issue the Block Lock-Down command:
●
The first bus cycle sets up the Block Lock-Down command.
●
The second bus write cycle latches the block address and locks-down the block.
The lock status can be monitored for each block using the Read Electronic Signature
command.
Locked-down blocks revert to the locked (and not locked-down) state when the device is
reset on power-down. Table 17 shows the lock status after issuing a Block Lock-Down
command.
28/108
M58LRxxxKC, M58LRxxxKD
Command interface
Refer to Section 9: Block locking for a detailed explanation and Appendix C, Figure 23:
Locking operations flowchart and pseudocode for a flowchart for using the Lock-Down
command.
Standard commands(1)
Table 6.
Commands
Read Array
Read Status Register
Cycles
Bus operations
1+
1+
1st cycle
2nd cycle
Op.
Add
Data
Op.
Add
Data
Write
BKA
FFh
Read
WA
RD
Read
BKA(2)
SRD
(2)
ESD
Write
BKA
70h
Read Electronic Signature
1+
Write
BKA
90h
Read
BKA
Read CFI Query
1+
Write
BKA
98h
Read
BKA(2)
QD
Clear Status Register
1
Write
X
50h
Block Erase
2
Write
BKA or
BA(3)
20h
Write
BA
D0h
Program
2
Write
BKA or
WA(3)
40h or
10h
Write
WA
PD
Write
BA
E8h
Write
BA
n
Write
PA1
PD1
Write
PA2
PD2
Write
PAn+1
PDn+1
Write
X
D0h
Buffer
Program(4)
n+4
Program/Erase Suspend
1
Write
X
B0h
Program/Erase Resume
1
Write
X
D0h
Protection Register Program
2
Write
PRA
C0h
Write
PRA
PRD
Set Configuration Register
2
Write
CRD
60h
Write
CRD
03h
Block Lock
2
Write
BKA or
BA(3)
60h
Write
BA
01h
Block Unlock
2
Write
BKA or
BA(3)
60h
Write
BA
D0h
Block Lock-Down
2
Write
BKA or
BA(3)
60h
Write
BA
2Fh
1. X = ‘don't care’, WA = Word Address in targeted bank, RD = Read Data, SRD = Status Register Data,
ESD = Electronic Signature Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PD =
Program Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration
Register Data.
2. Must be same bank as in the first cycle. The signature addresses are listed in Table 8.
3. Any address within the bank can be used.
4. n+1 is the number of words to be programmed.
29/108
Command interface
Table 7.
M58LRxxxKC, M58LRxxxKD
Factory commands
Command
Cycles
Bus write operations(1)
Phase
Blank
Check
Setup
1st
2nd
3rd
Add
Data Add Data Add Data
2
BA
BCh
BA
CBh
2
BKA or
WA(2)
80h
WA1
D0h
WA1
PD1
WA1
PD2 WA1 PD3
NOT
BA1(4)
X
Buffer
Enhanced Program/
≥32
Factory
Verify(3)
Program
Exit
1
Final -1
Add
Final
Data
Add
Data
WA1 PD31 WA1 PD32
1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address, X =
’don’t care’.
2. Any address within the bank can be used.
3. The program/verify phase can be executed any number of times as long as the data is to be programmed
to the same block.
4. WA1 is the start address, NOT BA1 = not block address of WA1.
Table 8.
Electronic signature codes
Code
Manufacturer code
Address (h)
Data (h)
Bank address + 00
0020
Top
Bank address + 01
882Eh (M58LR128KC)
881Ch (M58LR256KC)
Bottom
Bank address + 01
882Fh (M58LR128KD)
881Dh (M58LR256KD)
Device code
Locked
0001
Unlocked
Block protection
Locked and locked-down
0003
Unlocked and locked-down
0002
Configuration Register
Protection
Register PR0 lock
0000
Block address + 02
Bank address + 05
Numonyx factory default
CR(1)
0002
Bank address + 80
OTP area permanently locked
0000
Bank address + 81
Bank address + 84
Unique device number
Bank address + 85
Bank address + 88
OTP area
Protection Register PR1 through PR16 lock
Bank address + 89
PRLD(1)
Protection Registers PR1-PR16
Bank address + 8A
Bank address + 109
OTP area
Protection Register PR0
1. CR = Configuration Register, PRLD = Protection Register Lock Data
30/108
M58LRxxxKC, M58LRxxxKD
Figure 4.
Command interface
Protection Register memory map
PROTECTION REGISTERS
109h
PR16
User Programmable OTP
102h
91h
PR1
User Programmable OTP
8Ah
Protection Register Lock 89h
88h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR0
User Programmable OTP
85h
84h
Unique device number
81h
80h
Protection Register Lock
1 0
AI07563
31/108
Command interface
Table 9.
M58LRxxxKC, M58LRxxxKD
Protection Register locks
Lock
Description
Number
Lock 1
Address
80h
Bits
Bit 0
Preprogrammed to protect unique device number, address
81h to 84h in PR0
Bit 1
Protects 64 bits of OTP segment, address 85h to 88h in PR0
Bits 2 to 15 Reserved
32/108
Bit 1
Protects 128 bits of OTP segment PR2
Bit 2
Protects 128 bits of OTP segment PR3
----
89h
Protects 128 bits of OTP segment PR1
----
Lock 2
Bit 0
Bit 13
Protects 128 bits of OTP segment PR14
Bit 14
Protects 128 bits of OTP segment PR15
Bit 15
Protects 128 bits of OTP segment PR16
M58LRxxxKC, M58LRxxxKD
5
Status Register
Status Register
The Status Register provides information on the current or previous program or erase
operations. Issue a Read Status Register command to read the contents of the Status
Register (refer to Section 4.2: Read Status Register command for more details). To output
the contents, the Status Register is latched and updated on the falling edge of the Chip
Enable or Output Enable signals and can be read until Chip Enable or Output Enable
returns to VIH. The Status Register can only be read using single asynchronous or single
synchronous reads. Bus read operations from any address within the bank always read the
Status Register during program and erase operations.
The various bits convey information about the status and any errors of the operation. Bits
SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset
by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the
device but must be reset by issuing a Clear Status Register command or a hardware reset.
If an error bit is set to ‘1’ the Status Register should be reset before issuing another
command.
The bits in the Status Register are summarized in Table 10: Status Register bits. Refer to
Table 10 in conjunction with the descriptions in the following sections.
5.1
Program/Erase Controller status bit (SR7)
The Program/Erase Controller status bit indicates whether the Program/Erase Controller is
active or inactive in any bank.
When the Program/Erase Controller status bit is Low (set to ‘0’), the Program/Erase
Controller is active. When the bit is High (set to ‘1’), the Program/Erase Controller is inactive,
and the device is ready to process a new command.
The Program/Erase Controller status bit is Low immediately after a Program/Erase Suspend
command is issued until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses the bit is High.
5.2
Erase suspend status bit (SR6)
The erase suspend status bit indicates that an erase operation has been suspended in the
addressed block. When the erase suspend status bit is High (set to ‘1’), a Program/Erase
Suspend command has been issued and the memory is waiting for a Program/Erase
Resume command.
The erase suspend status bit should only be considered valid when the Program/Erase
Controller status bit is High (Program/Erase Controller inactive). SR6 is set within the erase
suspend latency time of the Program/Erase Suspend command being issued, therefore, the
memory may still complete the operation rather than entering the suspend mode.
When a Program/Erase Resume command is issued the erase suspend status bit returns
Low.
33/108
Status Register
5.3
M58LRxxxKC, M58LRxxxKD
Erase/blank check status bit (SR5)
The erase/blank check status bit identifies if there was an error during a block erase
operation. When the erase/blank check status bit is High (set to ‘1’), the Program/Erase
Controller has applied the maximum number of pulses to the block and still failed to verify
that it has erased correctly.
The erase/blank check status bit should be read once the Program/Erase Controller Status
bit is High (Program/Erase Controller inactive).
The erase/blank check status bit also indicates whether an error occurred during the blank
check operation. If the data at one or more locations in the block where the blank check
command has been issued is different from FFFFh, SR5 is set to '1'.
Once set High, the erase/blank check status bit must be set Low by a Clear Status Register
command or a hardware reset before a new erase command is issued, otherwise the new
command appears to fail.
5.4
Program status bit (SR4)
The program status bit identifies if there was an error during a program operation.
The program status bit should be read once the Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).
When the program status bit is High (set to ‘1’), the Program/Erase Controller has applied
the maximum number of pulses to the word and still failed to verify that it has programmed
correctly.
Attempting to program a '1' to an already programmed bit while VPP = VPPH also sets the
Program Status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0') and the
attempt is not shown.
Once set High, the program status bit must be set Low by a Clear Status Register command
or a hardware reset before a new program command is issued, otherwise the new command
appears to fail.
5.5
VPP status bit (SR3)
The VPP status bit identifies an invalid voltage on the VPP pin during program and erase
operations. The VPP pin is only sampled at the beginning of a program or erase operation.
Program and erase operations are not guaranteed if VPP becomes invalid during an
operation
When the VPP status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid
voltage.
When the VPP status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP
lockout voltage, VPPLK, the memory is protected and program and erase operations cannot
be performed.
Once set High, the VPP status bit must be set Low by a Clear Status Register command or a
hardware reset before a new program or erase command is issued, otherwise the new
command appears to fail.
34/108
M58LRxxxKC, M58LRxxxKD
5.6
Status Register
Program suspend status bit (SR2)
The program suspend status bit indicates that a program operation has been suspended in
the addressed block. The program suspend status bit should only be considered valid when
the Program/Erase Controller status bit is High (Program/Erase Controller inactive).
When the program suspend status bit is High (set to ‘1’), a Program/Erase Suspend
command has been issued and the memory is waiting for a Program/Erase Resume
command.
SR2 is set within the program suspend latency time of the Program/Erase Suspend
command being issued, therefore, the memory may still complete the operation rather than
entering the suspend mode.
When a Program/Erase Resume command is issued, the program suspend status bit
returns Low.
5.7
Block protection status bit (SR1)
The block protection status bit identifies if a program or block erase operation has tried to
modify the contents of a locked or locked-down block.
When the block protection status bit is High (set to ‘1’), a program or erase operation has
been attempted on a locked or locked-down block
Once set High, the block protection status bit must be set Low by a Clear Status Register
command or a hardware reset before a new program or erase command is issued,
otherwise the new command appears to fail.
5.8
Bank write/multiple word program status bit (SR0)
The bank write status bit indicates whether the addressed bank is programming or erasing.
In buffer enhanced factory program mode the multiple word program bit shows if the device
is ready to accept a new word to be programmed to the memory array.
The bank write status bit should only be considered valid when the Program/Erase
Controller status bit SR7 is Low (set to ‘0’).
When both the Program/Erase Controller status bit and the bank write status bit are Low (set
to ‘0’), the addressed bank is executing a program or erase operation. When the
Program/Erase Controller status bit is Low (set to ‘0’) and the bank write status bit is High
(set to ‘1’), a program or erase operation is being executed in a bank other than the one
being addressed.
In buffer enhanced factory program mode if the multiple word program status bit is Low (set
to ‘0’), the device is ready for the next word. If the multiple word program status bit is High
(set to ‘1’) the device is not ready for the next word.
For further details on how to use the Status Register, see the flowcharts and pseudocodes
provided in Appendix C.
35/108
Status Register
M58LRxxxKC, M58LRxxxKD
Table 10.
Bit
Status Register bits
Name
SR7 P/EC status
Type
Logic
Level(1)
Definition
'1'
Ready
'0'
Busy
'1'
Erase suspended
'0'
Erase In progress or completed
'1'
Erase/blank check error
'0'
Erase/blank check success
'1'
Program error
'0'
Program success
'1'
VPP invalid, abort
'0'
VPP OK
'1'
Program suspended
'0'
Program in progress or completed
'1'
Program/erase on protected block, abort
'0'
No operation to protected blocks
Status
SR6 Erase suspend status Status
SR5
Erase/blank check
status
SR4 Program status
SR3 VPP status
SR2
SR1
Error
Error
Error
Program suspend
status
Status
Block protection
status
Error
SR7 = ‘1’ Not allowed
'1'
Bank write status
SR7 = ‘0’
Program or erase operation in a bank
other than the addressed bank
SR7 = ‘1’
No program or erase operation in the
device
SR7 = ‘0’
Program or erase operation in
addressed bank
Status
'0'
SR0
SR7 = ‘1’ Not allowed
'1'
Multiple word
program status (buffer
enhanced factory
program mode)
The device is not ready for the next
SR7 = ‘0’ buffer loading or is going to exit the
BEFP mode.
Status
SR7 = ‘1’
The device has exited the BEFP
mode.
SR7 = ‘0’
The device is ready for the next buffer
loading.
'0'
1. Logic level '1' is High, '0' is Low.
36/108
M58LRxxxKC, M58LRxxxKD
6
Configuration Register
Configuration Register
The Configuration Register configures the type of bus access that the memory performs.
Refer to Section 7: Read modes for details on read operations.
The Configuration Register is set through the command interface using the Set
Configuration Register command. After a reset or power-up the device is configured for
asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 12
They specify the selection of the burst length, burst type, burst X latency and the read
operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations.
6.1
Read select bit (CR15)
The read select bit, CR15, switches between asynchronous and synchronous read
operations.
When the read select bit is set to ’1’, read operations are asynchronous, and when the read
select bit is set to ’0’, read operations are synchronous.
Synchronous burst read is supported in both parameter and main blocks and can be
performed across banks.
On reset or power-up the read select bit is set to ’1’ for asynchronous access.
6.2
X latency bits (CR13-CR11)
The X latency bits are used during synchronous read operations to set the number of clock
cycles between the address being latched and the first data becoming available. Refer to
Figure 5: X latency and data output configuration example.
For correct operation the X latency bits can only assume the values in Table 12:
Configuration Register.
Table 11 shows how to set the X latency parameter, taking into account the speed class of
the device and the frequency used to read the Flash memory in synchronous mode.
Table 11.
X latency settings
fmax
tKmin
X latency min
30 MHz
33 ns
2
40 MHz
25 ns
3
54 MHz
19 ns
4
66 MHz
15 ns
4
86 MHz
12 ns
6
37/108
Configuration Register
6.3
M58LRxxxKC, M58LRxxxKD
Wait polarity bit (CR10)
The wait polarity bit sets the polarity of the Wait signal used in synchronous burst read
mode. During synchronous burst read mode the Wait signal indicates whether the data
output are valid or a WAIT state must be inserted.
When the wait polarity bit is set to ‘0’ the Wait signal is active Low. When the wait polarity bit
is set to ‘1’ the Wait signal is active High.
6.4
Data output configuration bit (CR9)
The data output configuration bit configures the output to remain valid for either one or two
clock cycles during synchronous mode.
When the data output configuration bit is ’0’ the output data is valid for one clock cycle, and
when the data output configuration bit is ’1’ the output data is valid for two clock cycles.
The data output configuration bit must be configured using the following condition:
●
tK > tKQV + tQVK_CPU
where
●
tK is the clock period
●
tQVK_CPU is the data setup time required by the system CPU
●
tKQV is the clock to data valid time.
If this condition is not satisfied, the data output configuration bit should be set to ‘1’ (two
clock cycles). Refer to Figure 5: X latency and data output configuration example.
6.5
Wait configuration bit (CR8)
The wait configuration bit controls the timing of the Wait output pin, WAIT, in synchronous
burst read mode.
When WAIT is asserted, data is not valid and when WAIT is deasserted, data is valid.
When the wait configuration bit is Low (set to ’0’) the Wait output pin is asserted during the
WAIT state. When the wait configuration bit is High (set to ’1’), the Wait output pin is
asserted one data cycle before the WAIT state.
6.6
Burst type bit (CR7)
The burst type bit determines the sequence of addresses read during synchronous burst
reads. It is High (set to ’1’), as the memory outputs from sequential addresses only.
See Table 13: Burst type definition for the sequence of addresses output from a given
starting address in sequential mode.
38/108
M58LRxxxKC, M58LRxxxKD
6.7
Configuration Register
Valid clock edge bit (CR6)
The valid clock edge bit, CR6, configures the active edge of the Clock, K, during
synchronous read operations. When the valid clock edge bit is Low (set to ’0’) the falling
edge of the Clock is the active edge. When the valid clock edge bit is High (set to ’1’) the
rising edge of the Clock is the active edge.
6.8
Wrap burst bit (CR3)
The wrap burst bit, CR3, selects between wrap and no wrap. Synchronous burst reads can
be confined inside the 4, 8 or 16-word boundary (wrap) or overcome the boundary (no
wrap).
When the wrap burst bit is Low (set to ‘0’) the burst read wraps. When it is High (set to ‘1’)
the burst read does not wrap.
6.9
Burst length bits (CR2-CR0)
The burst length bits set the number of words to be output during a synchronous burst read
operation as result of a single address latch cycle.
They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are
read sequentially. In continuous burst mode the burst sequence can cross bank boundaries.
In continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address,
the device asserts the WAIT signal to indicate that a delay is necessary before the data is
output.
If the starting address is shifted by 1, 2 or 3 positions from the four-word boundary, WAIT is
asserted for 1, 2 or 3 clock cycles, respectively, when the burst sequence crosses the first
16-word boundary, to indicate that the device needs an internal delay to read the successive
words in the array. WAIT will be asserted only once during a continuous burst access. See
also Table 13: Burst type definition.
CR14, CR5 and CR4 are reserved for future use.
39/108
Configuration Register
Table 12.
Bit
CR15
CR14
CR13-CR11
M58LRxxxKC, M58LRxxxKD
Configuration Register
Description
Value
Description
0
Synchronous read
1
Asynchronous read (default at power-on)
010
2 clock latency(1)
011
3 clock latency
100
4 clock latency
101
5 clock latency
110
6 clock latency
111
7 clock latency (default)
Read select
Reserved
X latency
Other configurations reserved
CR10
CR9
CR8
CR7
CR6
WAIT is active Low (default)
1
WAIT is active High
0
Data held for one clock cycle
1
Data held for two clock cycles (default)(1)
0
WAIT is active during WAIT state (default)
1
WAIT is active one data cycle before WAIT
state(1)
0
Reserved
1
Sequential (default)
0
Falling Clock edge
1
Rising Clock edge (default)
0
Wrap
1
No wrap (default)
001
4 words
010
8 words
011
16 words
111
Continuous (default)
Data output configuration
Wait configuration
Burst type
Valid clock edge
CR5-CR4
Reserved
CR3
Wrap burst
CR2-CR0
0
Wait polarity
Burst length
1. The combination X latency=2, data held for two clock cycles and Wait active one data cycle before the
WAIT state is not supported.
40/108
M58LRxxxKC, M58LRxxxKD
Wrap
Mode
Table 13.
Configuration Register
Burst type definition
4 words
8 words
16 words
Sequential
Sequential
Sequential
0
0-1-2-3
0-1-2-3-4-5-67
0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15
0-1-2-3-4-5-6...
1
1-2-3-0
1-2-3-4-5-6-70
1-2-3-4-5-6-7-8-9-1011-12-13-14-15-0
1-2-3-4-5-6-7-...15-WAIT-16-1718...
2
2-3-0-1
2-3-4-5-6-7-01
2-3-4-5-6-7-8-9-10-1112-13-14-15-0-1
2-3-4-5-6-7...15-WAIT-WAIT-1617-18...
3
3-0-1-2
3-4-5-6-7-0-1- 3-4-5-6-7-8-9-10-11-122
13-14-15-0-1-2
7-4-5-6
7-0-1-2-3-4-56
Start
Add
Continuous burst
3-4-5-6-7...15-WAIT-WAITWAIT-16-17-18...
...
7
7-8-9-10-11-12-13-1415-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-WAITWAIT-WAIT-16-17...
...
12
12-13-14-15-16-17-18...
13
13-14-15-WAIT-16-17-18...
14
14-15-WAIT-WAIT-16-17-18....
15
15-WAIT-WAIT-WAIT-16-17-18...
41/108
Configuration Register
Mode
Table 13.
M58LRxxxKC, M58LRxxxKD
Burst type definition (continued)
4 words
8 words
16 words
Sequential
Sequential
Sequential
0
0-1-2-3
0-1-2-3-4-5-67
0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15
1
1-2-3-4
1-2-3-4-5-6-78
1-2-3-4-5-6-7-8-9-1011-12-13-14-15-WAIT16
2
2-3-4-5
2-3-4-5-6-7-89...
2-3-4-5-6-7-8-9-10-1112-13-14-15-WAITWAIT-16-17
3
3-4-5-6
3-4-5-6-7-8-910
3-4-5-6-7-8-9-10-11-1213-14-15-WAIT-WAITWAIT-16-17-18
7-8-9-10
7-8-9-10-1112-13-14
7-8-9-10-11-12-13-1415-WAIT-WAIT-WAIT16-17-18-19-20-21-22
12
12-13-1415
12-13-14-1516-17-18-19
12-13-14-15-16-17-1819-20-21-22-23-24-2526-27
13
13-14-15WAIT-16
13-14-15WAIT-16-1718-19-20
13-14-15-WAIT-16-1718-19-20-21-22-23-2425-26-27-28
14
14-15WAITWAIT-1617
14-15-WAITWAIT-16-1718-19-20-21
14-15-WAIT-WAIT-1617-18-19-20-21-22-2324-25-26-27-28-29
15
15-WAITWAITWAIT-1617-18
15-WAITWAIT-WAIT16-17-18-1920-21-22
15-WAIT-WAIT-WAIT16-17-18-19-20-21-2223-24-25-26-27-28-2930
Start
Add
Continuous burst
No-wrap
...
42/108
7
...
Same as for wrap
(wrap /no wrap has no effect on
continuous burst)
M58LRxxxKC, M58LRxxxKD
Figure 5.
Configuration Register
X latency and data output configuration example
X-latency
1st cycle
2nd cycle
3rd cycle
4th cycle
K
E
L
Amax-A16(1)
VALID ADDRESS
tQVK_CPU
tK
tKQV
ADQ15-ADQ0
VALID ADDRESS
VALID DATA VALID DATA
AI12321b
1. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D.
2. The settings shown are X-latency = 4, data output held for one clock cycle.
43/108
Configuration Register
Figure 6.
M58LRxxxKC, M58LRxxxKD
Wait configuration example
E
K
L
G
Amax-A16(1)
VALID ADDRESS
ADQ15-ADQ0
VALID ADDRESS
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT
CR8 = '0'
CR10 = '0'
WAIT
CR8 = '1'
CR10 = '0'
WAIT
CR8 = '0'
CR10 = '1'
WAIT
CR8 = '1'
CR10 = '1'
AI12322b
1. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D.
44/108
M58LRxxxKC, M58LRxxxKD
7
Read modes
Read modes
Read operations can be performed in two different ways depending on the settings in the
Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read
operation is asynchronous. If the data output is synchronized with clock, the read operation
is synchronous.
The read mode and format of the data output are determined by the Configuration Register
(see Section 6: Configuration Register for details). All banks support both asynchronous
and synchronous read operations.
7.1
Asynchronous read mode
In asynchronous read operations the clock signal is ‘don’t care’. The device outputs the data
corresponding to the address latched, that is the memory array, Status Register, common
Flash interface or electronic signature depending on the command issued. CR15 in the
Configuration Register must be set to ‘1’ for asynchronous operations.
The device features an automatic standby mode. During asynchronous read operations,
after a bus inactivity of 150 ns, the device automatically switches to the automatic standby
mode. In this condition the power consumption is reduced to the standby value and the
outputs are still driven.
In asynchronous read mode, the WAIT signal is always de-asserted.
See Table 24: Asynchronous read AC characteristics and Figure 9: Asynchronous random
access read AC waveforms for details.
7.2
Synchronous burst read mode
In synchronous burst read mode the data is output in bursts synchronized with the clock. It is
possible to perform burst reads across bank boundaries.
Synchronous burst read mode can only be used to read the memory array. For other read
operations, such as read Status Register, read CFI and read electronic signature, single
synchronous read or asynchronous random access read must be used.
In synchronous burst read mode the flow of the data output depends on parameters that are
configured in the Configuration Register.
A burst sequence starts at the first clock edge (rising or falling depending on valid clock
edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip
Enable, whichever occurs last. Addresses are internally incremented and data is output on
each data cycle after a delay which depends on the X latency bits CR13-CR11 of the
Configuration Register.
The number of words to be output during a synchronous burst read operation can be
configured as 4 words, 8 words, 16 words or continuous (burst length bits CR2-CR0). The
data can be configured to remain valid for one or two clock cycles (data output configuration
bit CR9).
The order of the data output can be modified through the wrap burst bit in the Configuration
Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 word
boundary (wrap) or overcome the boundary (no wrap).
45/108
Read modes
M58LRxxxKC, M58LRxxxKD
The WAIT signal may be asserted to indicate to the system that an output delay occurs. This
delay depends on the starting address of the burst sequence and on the burst configuration.
WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16-word
burst. It is only deasserted when output data are valid or when G is at VIH. In continuous
burst read mode a WAIT state occurs when crossing the first 16-word boundary. If the
starting address is aligned to the burst length (4, 8 or 16 words) the wrapped configuration
has no impact on the output sequence.
The WAIT signal can be configured to be active Low or active High by setting CR10 in the
Configuration Register.
See Table 25: Synchronous read AC characteristics and Figure 10: Synchronous burst read
AC waveforms for details.
7.2.1
Synchronous burst read suspend
A synchronous burst read operation can be suspended, freeing the data bus for other higher
priority devices. It can be suspended during the initial access latency time (before data is
output) or after the device has output data. When the synchronous burst read operation is
suspended, internal array sensing continues and any previously latched internal data is
retained. A burst sequence can be suspended and resumed as often as required as long as
the operating conditions of the device are met.
A synchronous burst read operation is suspended when Chip Enable, E, is Low and the
current address has been latched (on a Latch Enable rising edge or on a valid clock edge).
The Clock signal is then halted at VIH or at VIL, and Output Enable, G, goes High.
When Output Enable, G, becomes Low again and the Clock signal restarts, the
synchronous burst read operation is resumed exactly where it stopped.
WAIT, being gated by E, becomes deasserted and does not revert to high impedance when
G goes High. Therefore, if two or more devices are connected to the system’s READY
signal, to prevent bus contention the WAIT signal of the M58LRxxxKC/D should not be
directly connected to the system’s READY signal.
WAIT will revert to high-impedance when Chip Enable, E, goes High.
See Table 25: Synchronous read AC characteristics and Figure 12: Synchronous burst read
suspend AC waveforms for details.
7.3
Single synchronous read mode
Single synchronous read operations are similar to synchronous burst read operations
except that the memory outputs the same data to the end of the operation.
Synchronous single reads are used to read the electronic signature, Status Register, CFI,
block protection status, Configuration Register Status or Protection Register. When the
addressed bank is in read CFI, read Status Register or read electronic signature mode, the
WAIT signal is deasserted when Output Enable, G, is at VIH or for the one clock cycle during
which output data is valid. Otherwise, it is asserted.
See Table 25: Synchronous read AC characteristics and Figure 11: Single synchronous
read AC waveforms for details.
46/108
M58LRxxxKC, M58LRxxxKD
8
Dual operations and multiple bank architecture
Dual operations and multiple bank architecture
The multiple bank architecture of the M58LRxxxKC/D gives greater flexibility for software
developers to split the code and data spaces within the memory array. The dual operations
feature simplifies the software management of the device by allowing code to be executed
from one bank while another bank is being programmed or erased.
The dual operations feature means that while programming or erasing in one bank, read
operations are possible in another bank with zero latency (only one bank at a time is allowed
to be in program or erase mode).
If a read operation is required in a bank, which is programming or erasing, the program or
erase operation can be suspended.
Also, if the suspended operation is erase then a program command can be issued to
another block, so the device can have one block in erase suspend mode, one programming,
and other banks in read mode.
Bus read operations are allowed in another bank between setup and confirm cycles of
program or erase operations.
By using a combination of these features, read operations are possible at any moment in the
M58LRxxxKC/D device.
Dual operations between the parameter bank and either of the CFI, the OTP or the
electronic signature memory space are not allowed. Table 16 shows which dual operations
are allowed or not between the CFI, the OTP, the electronic signature locations and the
memory array.
Tables 14 and 15 show the dual operations possible in other banks and in the same bank.
Table 14.
Dual operations allowed in other banks
Commands allowed in another bank
Status of bank
Read
Array
Read
Read
Read
Status
CFI Electronic
Register Query Signature
Program,
Buffer
Program
Block
Erase
Program Program
/Erase
/Erase
Suspend Resume
Idle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Programming
Yes
Yes
Yes
Yes
–
–
Yes
–
Erasing
Yes
Yes
Yes
Yes
–
–
Yes
–
Program
suspended
Yes
Yes
Yes
Yes
–
–
–
Yes
Erase
suspended
Yes
Yes
Yes
Yes
Yes
–
–
Yes
47/108
Dual operations and multiple bank architecture
Table 15.
M58LRxxxKC, M58LRxxxKD
Dual operations allowed in same bank
Commands allowed in same bank
Status of
bank
Read
Array
Idle
Programming
Erasing
Read
Read
Status
CFI
Register Query
Read
Electronic
Signature
Program,
Buffer
Program
Block
Erase
Program Program
/Erase
/Erase
Suspend Resume
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(1)
Yes
Yes
Yes
–
–
Yes
–
(1)
Yes
Yes
Yes
–
–
Yes
–
–
–
Program
suspended
Yes(2)
Yes
Yes
Yes
–
–
–
Yes
Erase
suspended
Yes(2)
Yes
Yes
Yes
Yes(2)
–
–
Yes
1. The Read Array command is accepted but the data output is not guaranteed until the program or erase has
completed.
2. Not allowed in the block that is being erased or in the word that is being programmed.
Table 16.
Dual operation limitations
Commands allowed
Read main blocks
Current status
Programming/erasing
parameter blocks
Located in
parameter
bank
Programming /
erasing main
Not located in
blocks
parameter
bank
Programming OTP
48/108
Read CFI/OTP/
electronic
signature
Read
parameter
blocks
No
Located in
parameter
bank
Not located in
parameter
bank
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
In different
bank only
No
No
No
No
M58LRxxxKC, M58LRxxxKD
9
Block locking
Block locking
The M58LRxxxKC/D features an instant, individual block locking scheme that allows any
block to be locked or unlocked with no latency. This locking scheme has three levels of
protection.
●
Lock/unlock - this first level allows software only control of block locking.
●
Lock-down - this second level requires hardware interaction before locking can be
changed.
●
VPP ≤VPPLK - the third level offers complete hardware protection against program and
erase on all blocks.
The protection status of each block can be set to locked, unlocked, and locked-down.
Table 17 defines all of the possible protection states (WP, ADQ1, ADQ0), and Appendix C
Figure 23 shows a flowchart for the locking operations.
9.1
Reading a block’s lock status
The lock status of every block can be read in the read electronic signature mode of the
device. To enter this mode issue the Read Electronic Signature command. Subsequent
reads at the address specified in Table 8 output the protection status of that block.
The lock status is represented by ADQ0 and ADQ1. ADQ0 indicates the block lock/unlock
status and is set by the Lock command and cleared by the Unlock command. ADQ0 is
automatically set when entering lock-down. ADQ1 indicates the lock-down status and is set
by the Lock-Down command. ADQ1 cannot be cleared by software, only by a hardware
reset or power-down.
The following sections explain the operation of the locking system.
9.2
Locked state
The default status of all blocks on power-up or after a hardware reset is locked (states
(0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any
program or erase operations attempted on a locked block return an error in the Status
Register. The status of a locked block can be changed to unlocked or locked-down using the
appropriate software commands. An unlocked block can be locked by issuing the Lock
command.
9.3
Unlocked state
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)) can be programmed or erased. All unlocked
blocks return to the locked state after a hardware reset or when the device is powered-down.
The status of an unlocked block can be changed to locked or locked-down using the
appropriate software commands. A locked block can be unlocked by issuing the Unlock
command.
49/108
Block locking
9.4
M58LRxxxKC, M58LRxxxKD
Lock-down state
Blocks that are locked-down (state (0,1,x)) are protected from program and erase operations
(as for locked blocks) but their protection status cannot be changed using software
commands alone. A locked or unlocked block can be locked down by issuing the Lock-Down
command. Locked-down blocks revert to the locked state when the device is reset or
powered-down.
The lock-down function is dependent on the Write Protect, WP, input pin.
When WP=0 (VIL), the blocks in the lock-down state (0,1,x) are protected from program,
erase and protection status changes.
When WP=1 (VIH) the lock-down function is disabled (1,1,x) and locked-down blocks can be
individually unlocked to the (1,1,0) state by issuing the software command, where they can
be erased and programmed.
When the lock-down function is disabled (WP=1) blocks can be locked (1,1,1) and unlocked
(1,1,0) as desired. When WP=0 blocks that were previously locked-down return to the lockdown state (0,1,x) regardless of any changes that were made while WP=1.
Device reset or power-down resets all blocks, including those in lock-down, to the locked
state.
9.5
Locking operations during erase suspend
Changes to the block lock status can be performed during an erase suspend by using the
standard locking command sequences to unlock, lock or lock-down a block. This is useful in
the case when another block needs to be updated while an erase operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command,
then check the Status Register until it indicates that the erase operation has been
suspended. Next, write the desired lock command sequence to a block and the lock status is
changed. After completing any desired lock, read, or program operations, resume the erase
operation with the Erase Resume command.
If a block is locked or locked down during an erase suspend of the same block, the locking
status bits change immediately. But when the erase is resumed, the erase operation
completes. Locking operations cannot be performed during a program suspend.
50/108
M58LRxxxKC, M58LRxxxKD
Table 17.
Block locking
Lock status
Current protection status(1)
Next protection status(1)
(WP, ADQ1, ADQ0)
(WP, ADQ1, ADQ0)
Current
state
Program/erase
allowed
After Block
Lock
command
After Block
Unlock
command
After Block
Lock-Down
command
After WP
transition
1,0,0
yes
1,0,1
1,0,0
1,1,1
0,0,0
no
1,0,1
1,0,0
1,1,1
0,0,1
1,1,0
yes
1,1,1
1,1,0
1,1,1
0,1,1
1,1,1
no
1,1,1
1,1,0
1,1,1
0,1,1
0,0,0
yes
0,0,1
0,0,0
0,1,1
1,0,0
no
0,0,1
0,0,0
0,1,1
1,0,1
no
0,1,1
0,1,1
0,1,1
1,1,1 or 1,1,0(3)
(2)
1,0,1
(2)
0,0,1
0,1,1
1. The lock status is defined by the write protect pin and by ADQ1 (‘1’ for a locked-down block) and ADQ0 (‘1’
for a locked block) as read in the Read Electronic Signature command with ADQ1 = VIH and ADQ0 = VIL.
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.
3. A WP transition to VIH on a locked block restores the previous ADQ0 value, giving a 111 or 110.
51/108
Program and erase times and endurance cycles
10
M58LRxxxKC, M58LRxxxKD
Program and erase times and endurance cycles
The program and erase times and the number of program/erase cycles per block are shown
in Table 18. Exact erase times may change depending on the memory array condition. The
best case is when all the bits in the block are at ‘0’ (pre-programmed). The worst case is
when all the bits in the block are at ‘1’ (not preprogrammed). Usually, the system overhead is
negligible with respect to the erase time. In the M58LRxxxKC/D the maximum number of
program/erase cycles depends on the VPP voltage supply used.
Table 18.
Program/erase times and endurance cycles(1) (2)
Typ
Typical after
100 kW/E
cycles
Max
Unit
0.4
1
2.5
s
Preprogrammed
1.2
3
4
s
Not preprogrammed
1.5
4
s
Word program
12
180
µs
Buffer program
12
180
µs
Buffer (32 words) (buffer program)
384
µs
Main block (64 KWord)
768
ms
Program
20
25
µs
Erase
20
25
µs
Parameter
Condition
Min
Parameter block (16 KWord)
Erase
Main block (64
KWord)
VPP = VDD
Single word
Program(3)
Suspend latency
Program/erase
cycles (per block)
52/108
Main blocks
100 000
cycles
Parameter blocks
100 000
cycles
M58LRxxxKC, M58LRxxxKD
Table 18.
Program and erase times and endurance cycles
Program/erase times and endurance cycles(1) (2) (continued)
Parameter
Condition
Typ
Typical after
100 kW/E
cycles
Max
Unit
0.4
2.5
s
1
4
s
Word program
10
170
µs
Buffer enhanced
factory program(4)
2.5
µs
Buffer program
80
µs
Buffer enhanced
factory program
80
µs
Buffer program
160
ms
Buffer enhanced
factory program
160
ms
Buffer program
1.28
s
Buffer enhanced
factory program
1.28
s
Parameter block (16 KWord)
Min
Erase
Main block (64 KWord)
Single word
VPP = VPPH
Buffer
(32 words)
Program
(3)
Main block
(64 KWords)
Bank (8 Mbits)
Program/erase
cycles (per block)
Main blocks
1000
cycles
Parameter blocks
2500
cycles
Main blocks
16
ms
Parameter blocks
4
ms
Blank check
1. TA = –25 to 85°C; VDD = 1.7 V to 2 V; VDDQ = 1.7 V to 2 V.
2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling
execution).
3. Excludes the time needed to execute the command sequence.
4. This is an average value on the entire device.
53/108
Maximum ratings
11
M58LRxxxKC, M58LRxxxKD
Maximum ratings
Stressing the device above the rating listed in Table 19 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to Absolute maximum rating conditions for extended periods may affect device
reliability. Refer to the Numonyx SURE program and other relevant quality documents.
Table 19.
Absolute maximum ratings
Value
Symbol
Unit
Min
Max
Ambient operating temperature
–25
85
°C
TBIAS
Temperature under bias
–25
85
°C
TSTG
Storage temperature
–65
125
°C
VIO
Input or output voltage
–0.5
VDDQ + 0.6
V
VDD
Supply voltage
–0.2
2.45
V
Input/output supply voltage
–0.2
2.45
V
Program voltage
–0.2
10
V
Output short circuit current
100
mA
Time for VPP at VPPH
100
hours
TA
VDDQ
VPP
IO
tVPPH
54/108
Parameter
M58LRxxxKC, M58LRxxxKD
12
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables in this
section are derived from tests performed under the measurement conditions summarized in
Table 20: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 20.
Operating and AC measurement conditions
Parameter
Min
Max
Units
VDD supply voltage
1.7
2.0
V
VDDQ supply voltage
1.7
2.0
V
VPP supply voltage (factory environment)
8.5
9.5
V
VPP supply voltage (application environment)
–0.4
VDDQ+0.4
V
Ambient operating temperature
–25
85
°C
Load capacitance (CL)
30
Input rise and fall times
5
Input pulse voltages
Input and output timing ref. voltages
Figure 7.
pF
ns
0 to VDDQ
V
VDDQ/2
V
AC measurement I/O waveform
VDDQ
VDDQ/2
0V
AI06161
55/108
DC and AC parameters
Figure 8.
M58LRxxxKC, M58LRxxxKD
AC measurement load circuit
VDDQ
VDDQ
VDD
16.7kΩ
DEVICE
UNDER
TEST
CL
0.1µF
16.7kΩ
0.1µF
CL includes JIG capacitance
Table 21.
Symbol
CIN
COUT
Capacitance(1)
Parameter
Input capacitance
Output capacitance
1. Sampled only, not 100% tested.
56/108
AI06162
Test condition
Min
Max
Unit
VIN = 0 V
6
8
pF
VOUT = 0 V
8
12
pF
M58LRxxxKC, M58LRxxxKD
Table 22.
DC characteristics - currents
Symbol
Parameter
DC and AC parameters
Test condition
Typ
Max
Unit
0V ≤VIN ≤VDDQ
±1
µA
±1
µA
ILI
Input leakage current
ILO
Output leakage current
0V ≤VOUT ≤VDDQ
Supply current
asynchronous read (f = 5 MHz)
E = VIL, G = VIH
13
15
mA
4 word
18
20
mA
8 word
20
22
mA
16 word
22
24
mA
Continuous
24
26
mA
4 word
22
25
mA
8 word
25
27
mA
16 word
30
32
mA
Continuous
33
35
mA
M58LR128KC/D
22
70
M58LR256KC/D
50
70
M58LR128KC/D
22
70
M58LR256KC/D
50
70
M58LR128KC/D
22
70
M58LR256KC/D
50
70
VPP = VPPH
10
30
mA
VPP = VDD
20
34
mA
VPP = VPPH
10
30
mA
VPP = VDD
20
34
mA
Program/erase in one bank,
asynchronous read in another bank
33
49
mA
Program/erase in one bank,
synchronous read (continuous f = 66
MHz) in another bank
44
60
mA
M58LR128KC/D
22
50
M58LR256KC/D
50
70
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP supply current (read)
VPP ≤VDD
0.2
5
µA
VPP supply current (standby)
VPP ≤VDD
0.2
5
µA
Supply current
synchronous read (f = 66 MHz)
IDD1
Supply current
synchronous read (f = 86 MHz)
IDD2
Supply current (reset)
IDD3
Supply current (standby)
IDD4
Supply current (automatic standby)
Supply current (program)
IDD5(1)
Supply current (erase)
Supply current
IDD6(1),(2)
(dual operations)
IDD7(1)
Supply current program/ erase
suspended (standby)
VPP supply current (program)
IPP1(1)
VPP supply current (erase)
IPP2
IPP3(1)
RP = VSS ± 0.2 V
E = VDD ± 0.2 V
K = VSS
E = VIL, G = VIH
E = VDD± 0.2 V
K = VSS
µA
µA
µA
µA
1. Sampled only, not 100% tested.
2. VDD dual operation current is the sum of read and program or erase currents.
57/108
DC and AC parameters
Table 23.
Symbol
M58LRxxxKC, M58LRxxxKD
DC characteristics - voltages
Parameter
Test condition
Min
Typ
Max
Unit
VIL
Input low voltage
0
0.4
V
VIH
Input high voltage
VDDQ –0.4
VDDQ + 0.4
V
VOL
Output low voltage
IOL = 100 µA
0.1
V
VOH
Output high voltage
IOH = –100 µA
VDDQ –0.1
VPP1
VPP program voltage-logic
Program, erase
1.3
1.8
3.3
V
VPPH
VPP program voltage factory
Program, erase
8.5
9.0
9.5
V
VPPLK
Program or erase lockout
0.4
V
VLKO
VDD lock voltage
1
V
58/108
V
Hi-Z
tELTV
tELQV
tLLQV
Valid Address Latch
tELLH
tLLLH
tGLQV
Outputs Enabled
tGLQX
tLHGL
tLHAX
Data Valid
tAVAV
Notes:
1. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D
2. Write Enable, W, is High, WAIT is active Low.
WAIT(2)
G
E
L
VALID ADDRESS
A16-Amax(1)
VALID DATA
tEHTZ
tGHQZ
tGHQX
tEHQX
tEHQZ
Standby
AI13798b
VALID
Hi-Z
Figure 9.
tAVLH
VALID ADDRESS
ADQ0-ADQ15
tAVQV
M58LRxxxKC, M58LRxxxKD
DC and AC parameters
Asynchronous random access read AC waveforms
59/108
DC and AC parameters
Table 24.
M58LRxxxKC, M58LRxxxKD
Asynchronous read AC characteristics
Symbol
Alt
tAVAV
tRC
Address Valid to Next Address Valid
Min
70
70
ns
tAVQV
tACC
Address Valid to Output Valid (Random)
Max
70
70
ns
Chip Enable Low to Wait Valid
Max
9
11
ns
Chip Enable Low to Output Valid
Max
70
70
ns
Chip Enable High to Wait Hi-Z
Max
11
14
ns
tELTV
Read Timings
tELQV(2)
tEHTZ
86 MHz 66 MHz Unit
tEHQX(1)
tOH
Chip Enable High to Output Transition
Min
0
0
ns
(1)
tHZ
Chip Enable High to Output Hi-Z
Max
11
14
ns
tGLQV(2)
tOE
Output Enable Low to Output Valid
Max
20
20
ns
tGLQX(1)
tOLZ
Output Enable Low to Output Transition
Min
0
0
ns
(1)
tOH
Output Enable High to Output Transition
Min
0
0
ns
tGHQZ(1)
tDF
Output Enable High to Output Hi-Z
Max
11
14
ns
tAVLH
tAVADVH
Address Valid to Latch Enable High
Min
4
7
ns
tELLH
tELADVH
Chip Enable Low to Latch Enable High
Min
9
10
ns
tLHAX
tADVHAX
Latch Enable High to Address Transition
Min
4
5
ns
Min
7
7
ns
tEHQZ
tGHQX
Latch Timings
tCE
Parameter
tLLLH
tADVLADVH Latch Enable Pulse Width
tLLQV
tADVLQV
Latch Enable Low to Output Valid
(Random)
Max
70
70
ns
tLHGL
tADVHGL
Latch Enable High to Output Enable Low
Min
4
5
ns
1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
60/108
Hi-Z
tELKH
tLLLH
Address
Latch
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
VALID ADDRESS
X Latency
tGLTV
tGLQX
tGLQV
Note 2
Note 1
tKHQV
VALID
Valid Data Flow
VALID
Note 2
tKHQX
VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
3. Address latched and data output on the rising clock edge.
4. Amax is equal to A22 in the M58LR128KC/D and to A23 in the M58LR256KC/D.
WAIT
G
E
K
L
A16-Amax(4)
ADQ0-ADQ15
Boundary
Crossing
Note 2
tKHTX
tKHTV
NOT VALID
tGHQZ
tGHQX
tEHQZ
tEHQX
AI13799b
Standby
tEHTZ
tEHEL
VALID
M58LRxxxKC, M58LRxxxKD
DC and AC parameters
Figure 10. Synchronous burst read AC waveforms
61/108
62/108
Hi-Z
tELKH
tELTV
tKHAX
tAVKH
tLLKH
tLLLH
tAVLH
VALID ADDRESS
VALID ADDRESS
tGLTV
tGLQV
tGLQX
Note 1
tKHTV
tKHQV
VALID
NOT VALID
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
3. Address latched and data output on the rising clock edge.
4. Amax is equal to A22 in the M58LR128KC/D and, to A23 in the M58LR256KC/D.
WAIT(2)
G
E
K(3)
L
A16-Amax(4)
ADQ0-ADQ15
NOT VALID
NOT VALID
tGHTV
tGHQZ
tGHQX
tEHEL
tEHQZ
AI13800b
tEHTZ
NOT VALID
tEHQX
NOT VALID
DC and AC parameters
M58LRxxxKC, M58LRxxxKD
Figure 11. Single synchronous read AC waveforms
Hi-Z
tELKH
tLLLH
tELTV
tKHAX
tAVKH
tLLKH
tAVLH
VALID ADDRESS
VALID ADDRESS
tGLTV
tGLQV
tGLQX
Note 1
tKHQV
VALID
VALID
Note 3
tGHQZ
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
3. The CLOCK signal can be held high or low
4. Address latched and data output on the rising clock edge.
5. Amax is equal to A22 in the M58LR128KC/D and to A23 in the M58LR256KC/D.
WAIT(2)
G
E
K(4)
L
A16-Amax(5)
ADQ0-ADQ15
tGLQV
VALID
tGHQZ
tGHQX
tEHEL
tEHQZ
tEHQX
VALID
AI13801b
tEHTZ
M58LRxxxKC, M58LRxxxKD
DC and AC parameters
Figure 12. Synchronous burst read suspend AC waveforms
63/108
DC and AC parameters
M58LRxxxKC, M58LRxxxKD
Figure 13. Clock input AC waveform
tKHKL
tKHKH
tr
tf
tKLKH
AI06981
Table 25.
Synchronous Read Timings
Symbol
Alt
Parameter
86 MHz
66 MHz
Unit
tAVKH
tAVCLKH
Address Valid to Clock High
Min
4
5
ns
tELKH
tELCLKH
Chip Enable Low to Clock High
Min
4
5
ns
tELTV
Chip Enable Low to Wait Valid
Max
9
11
ns
tEHEL
Chip Enable Pulse Width
(subsequent synchronous reads)
Min
11
14
ns
tEHTZ
Chip Enable High to Wait Hi-Z
Max
11
14
ns
tGHTV
Output Enable High to Wait Valid
Min
11
11
ns
tGLTV
Output Enable Low to Wait Valid
Max
11
11
ns
tKHAX
tCLKHAX
Clock High to Address Transition
Min
6
7
ns
tKHQV
tKHTV
tCLKHQV
Clock High to Output Valid
Clock High to WAIT Valid
Max
9
11
ns
tKHQX
tKHTX
tCLKHQX
Clock High to Output Transition
Clock High to WAIT Transition
Min
2
3
ns
Min
4
5
ns
tLLKH
Clock Specifications
Synchronous read AC characteristics(1) (2)
tKHKH(3)
tADVLCLKH Latch Enable Low to Clock High
tCLK
Clock Period (f = 66 MHz)
15
Min
ns
Clock Period (f = 86 MHz)
12
tKHKL
tKLKH
Clock High to Clock Low
Clock Low to Clock High
Min
3.5
3.5
ns
tf
tr
Clock Fall or Rise Time
Max
3
3
ns
1. Sampled only, not 100% tested.
2. For other timings please refer to Table 24: Asynchronous read AC characteristics.
3. The device can support jitters of +/-5% on clock frequency.
64/108
tELLH
tLLLH
SET-UP
COMMAND
tGHLL
COMMAND
tWLWH
CONFIRM
COMMAND
tVPHWH
tWPHWH
tELLH
tWHVPL
STATUS
REGISTER
READ
1ST POLLING
tQVVPL
tQVWPL
tELQV
tLHGL
Ai13802c
STATUS
REGISTER
VALID ADDRESS
VALID ADD.
tWHWPL
tWHKH
tWHEL
CMD OR DATA
VALID ADDRESS
VALID ADD.
tWHWL
tWHLL
tWHDX
tWHEH
tDVWH
BANK ADDRESS
tELWL
tLHAX
BANK ADD.
tAVAV
Note 1: Amax is equal to A22 in the M58LR128KC/D and to A23 in the M58LR256KC/D.
K
VPP
WP
W
G
E
L
tAVLH
A16-Amax(1)
ADQ0-ADQ15
tAVAV
PROGRAM OR ERASE
M58LRxxxKC, M58LRxxxKD
DC and AC parameters
Figure 14. Write AC waveforms, write enable controlled
65/108
DC and AC parameters
M58LRxxxKC, M58LRxxxKD
Write AC characteristics, write enable controlled(1)
Table 26.
Symbol
Alt
tAVAV
tWC
Unit
Min
70
70
ns
Address Valid to Latch Enable High
Min
4
7
ns
Data Valid to Write Enable High
Min
40
40
ns
Chip Enable Low to Latch Enable High
Min
9
10
ns
Chip Enable Low to Write Enable Low
Min
0
0
ns
tELQV
Chip Enable Low to Output Valid
Min
70
70
ns
tGHLL
Output Enable High to Latch Enable Low
Min
14
20
ns
tLHAX
Latch Enable High to Address Transition
Min
4
5
ns
tLHGL
Latch Enable High to Output Enable Low
Min
4
5
ns
tLLLH
Latch Enable Pulse Width
Min
7
7
ns
tDVWH
tDS
tELLH
Write Enable Controlled Timings
86 MHz 66 MHz
Address Valid to Next Address Valid
tAVLH
tELWL
tCS
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
ns
tWHEL(2)
Write Enable High to Chip Enable Low
Min
25
25
ns
tWHKH(2)
Write Enable High to Clock High
Min
35
35
ns
Write Enable High to Latch Enable Low
Min
25
25
ns
tWHLL
Protection Timings
Parameter
(2)
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
25
25
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
40
45
ns
tQVVPL
Output (Status Register) Valid to VPP Low Min
0
0
ns
tQVWPL
Output (Status Register) Valid to Write
Protect Low
Min
0
0
ns
VPP High to Write Enable High
Min
200
200
ns
tWHVPL
Write Enable High to VPP Low
Min
200
200
ns
tWHWPL
Write Enable High to Write Protect Low
Min
200
200
ns
tWPHWH
Write Protect High to Write Enable High
Min
200
200
ns
tVPHWH
tVPS
1. Sampled only, not 100% tested.
2. tWHEL , tWHLL, and tWHKH have the values shown when reading in the targeted bank or when reading
following a Set Configuration Register command.System designers should take this into account and may
insert a software No-Op instruction to delay the first read in the same bank after issuing any command and
to delay the first read to any address after issuing a Set Configuration Register command. If the first read
after the command is a Read Array operation in a different bank and no changes to the Configuration
Register have been issued, tWHEL and tWHLL are 0 ns, whilst tWHKH is equal to tELKH.
66/108
tLLLH
tAVLH
SET-UP
COMMAND
tELEH
tELLH
tGHLL
tWLEL
tDVEH
tLHAX
BANK ADDRESS
COMMAND
BANK ADD
tEHWH
tEHEL
tEHLL
tEHDX
CMD OR DATA
CONFIRM
COMMAND
tVPHEH
tWPHEH
VALID ADDRESS
VALID ADD
tAVAV
Note 1: Amax is equal to A22 in the M58LR128KC/D and to A23 in the M58LR256KC/D.
K
VPP
WP
W
G
E
L
A16-Amax(1)
ADQ0-ADQ15
tAVAV
tEHKH
tEHVPL
tEHWPL
tWHEL
tELLH
STATUS
REGISTER
READ
1ST POLLING
tELQV
Ai13803c
tQVVPL
tQVWPL
STATUS
REGISTER
tLHGL
VALID ADDRESS
VALID ADD
PROGRAM OR ERASE
M58LRxxxKC, M58LRxxxKD
DC and AC parameters
Figure 15. Write AC waveforms, chip enable controlled
67/108
DC and AC parameters
M58LRxxxKC, M58LRxxxKD
Write AC characteristics, chip enable controlled(1)
Table 27.
Symbol
tAVAV
Alt
tWC
Chip Enable Controlled Timings
tAVLH
86 MHz 66 MHz Unit
Address Valid to Next Address Valid
Min
70
70
ns
Address Valid to Latch Enable High
Min
4
7
ns
tDVEH
tDS
Data Valid to Chip Enable High
Min
40
40
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
ns
tEHEL
(2)
tWPH Chip Enable High to Chip Enable Low
Min
25
25
ns
(2)
Chip Enable High to Clock High
Min
35
35
ns
Chip Enable High to Latch Enable Low
Min
0
0
ns
tEHKH
tEHLL
tEHWH
tCH
Chip Enable High to Write Enable High
Min
0
0
ns
tELEH
tWP
Chip Enable Low to Chip Enable High
Min
40
45
ns
tELLH
Chip Enable Low to Latch Enable High
Min
9
10
ns
tELQV
Chip Enable Low to Output Valid
Min
70
70
ns
tGHLL
Output Enable High to Latch Enable Low
Min
14
20
ns
tLHAX
Latch Enable High to Address Transition
Min
4
5
ns
tLHGL
Latch Enable High to Output Enable Low
Min
4
5
ns
tLLLH
Latch Enable Pulse Width
Min
7
7
ns
Write Enable High to Chip Enable Low
Min
25
25
ns
Write Enable Low to Chip Enable Low
Min
0
0
ns
tEHVPL
Chip Enable High to VPP Low
Min
200
200
ns
tEHWPL
Chip Enable High to Write Protect Low
Min
200
200
ns
tQVVPL
Output (Status Register) Valid to VPP Low
Min
0
0
ns
tQVWPL
Output (Status Register) Valid to Write
Protect Low
Min
0
0
ns
VPP High to Chip Enable High
Min
200
200
ns
Write Protect High to Chip Enable High
Min
200
200
ns
tWHEL(2)
tWLEL
Protection Timings
Parameter
tVPHEH
tWPHEH
tCS
tVPS
1. Sampled only, not 100% tested.
2. tWHEL, tEHEL , and tEHKH have the values shown when reading in the targeted bank or when reading
following a Set Configuration Register command.System designers should take this into account and may
insert a software No-Op instruction to delay the first read in the same bank after issuing any command and
to delay the first read to any address after issuing a Set Configuration Register command. If the first read
after the command is a Read Array operation in a different bank and no changes to the Configuration
Register have been issued, tWHEL and tEHEL are 0 ns, whilst tEHKH is equal to tELKH.
68/108
M58LRxxxKC, M58LRxxxKD
DC and AC parameters
Figure 16. Reset and power-up AC waveforms
tPHWL
tPHEL
tPHGL
tPHLL
W, E, G, L
tPLWL
tPLEL
tPLGL
tPLLL
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI06976
Table 28.
Symbol
Reset and power-up AC characteristics
Parameter
tPLWL
tPLEL
tPLGL
tPLLL
Reset Low to
Write Enable Low,
Chip Enable Low,
Output Enable Low,
Latch Enable Low
tPHWL
tPHEL
tPHGL
tPHLL
tPLPH(1),(2)
tVDHPH(3)
Test condition
Unit
During program
Min
25
µs
During erase
Min
25
µs
Other conditions
Min
80
ns
Reset High to
Write Enable Low
Chip Enable Low
Output Enable Low
Latch Enable Low
Min
30
ns
RP pulse width
Min
50
ns
Supply voltages High to Reset High
Min
300
µs
1. The device Reset is possible but not guaranteed if tPLPH < 50 ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during power-up or reset.
69/108
Part ordering information
13
M58LRxxxKC, M58LRxxxKD
Part ordering information
Table 29.
Ordering information scheme
Example:
M58LR256KD
76
5
Device type
M58
Architecture
L = multilevel, multiple bank, burst mode
Operating voltage
R = VDD = 1.7 V to 2.0 V, VDDQ = 1.7 V to 2.0 V
Density
128 = 128 Mbit (x16)
256 = 256 Mbit (×16)
Technology
K = 65 nm technology
Parameter location
C = top boot, mux I/O
D = bottom boot, mux I/O
Speed
76 = 70 ns, 66 Mhz speed class
78 = 70 ns, 86 MHz speed class
Package
Not packaged separately(1)
Temperature range
5 = –25 to 85 °C
1. The M58LRxxxKC/D are only available as part of a multichip package
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (speed, package, etc.), for daisy chain ordering information or
for further information on any aspect of this device, please contact the Numonyx sales office
nearest to you.
70/108
M58LRxxxKC, M58LRxxxKD
Appendix A
Block address tables
Block address tables
The following set of equations can be used to calculate a complete set of block addresses
for the M58LRxxxKC/D using the information contained in Tables 33 to 41.
To calculate the block base address from the block number:
First it is necessary to calculate the bank number and the block number offset. This can be
achieved using the following formulas:
Bank_Number = (Block_Number −3) / 8
Block_Number_Offset = Block_Number −3 −(Bank_Number x 8),
If Bank_Number= 0, the block base address can be directly read from Tables 33 and 39
(parameter bank block addresses) in the address range column, in the row that corresponds
to the given block number.
Otherwise:
Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset
To calculate the bank number and the block number from the block base address:
If the address is in the range of the parameter bank, the bank number is 0 and the block
number can be directly read from Tables 33 and 39 (parameter bank block addresses), in
the block number column, in the row that corresponds to the address given. Otherwise, the
block number can be calculated using the formulas below:
For the top configuration (M58LR256KC and M58LR128KC):
Block_Number = ((NOT address) / 216) + 3
For the bottom configuration (M58LR256KD and M58LR128KD):
Block_Number = (address / 216) + 3
For both configurations the bank number and the block number offset can be calculated
using the following formulas:
Bank_Number = (Block_Number −3) / 8
Block_Number_Offset = Block_Number − 3 −(Bank_Number x 8)
71/108
Block address tables
M58LRxxxKC, M58LRxxxKD
Table 30.
M58LR128KC - parameter bank block addresses
Block number
Size (KWords)
Address range
0
16
7FC000-7FFFFF
1
16
7F8000-7FBFFF
2
16
7F4000-7F7FFF
3
16
7F0000-7F3FFF
4
64
7E0000-7EFFFF
5
64
7D0000-7DFFFF
6
64
7C0000-7CFFFF
7
64
7B0000-7BFFFF
8
64
7A0000-7AFFFF
9
64
790000-79FFFF
10
64
780000-78FFFF
Table 31.
M58LR128KC - main bank base addresses
Bank number(1)
Block numbers
Bank base address
1
11-18
70 0000
2
19-26
68 0000
3
27-34
60 0000
4
35-42
58 0000
5
43-50
50 0000
6
51-58
48 0000
7
59-66
40 0000
8
67-74
38 0000
9
75-82
30 0000
10
83-90
28 0000
11
91-98
20 0000
12
99-106
18 0000
13
107-114
10 0000
14
115-122
08 0000
15
123-130
00 0000
1. There are two bank regions: bank region 1 contains all the banks that are made up of main blocks only;
bank region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
72/108
M58LRxxxKC, M58LRxxxKD
Table 32.
Block address tables
M58LR128KC - block addresses in main banks
Block number offset
Block base address offset
0
07 0000
1
06 0000
2
05 0000
3
04 0000
4
03 0000
5
02 0000
6
01 0000
7
00 0000
Table 33.
M58LR256KC - parameter bank block addresses
Block number
Size (KWords)
Address range
0
16
FFC000-FFFFFF
1
16
FF8000-FFBFFF
2
16
FF4000-FF7FFF
3
16
FF0000-FF3FFF
4
64
FE0000-FEFFFF
5
64
FD0000-FDFFFF
6
64
FC0000-FCFFFF
7
64
FB0000-FBFFFF
8
64
FA0000-FAFFFF
9
64
F90000-F9FFFF
10
64
F80000-F8FFFF
11
64
F70000-F7FFFF
12
64
F60000-F6FFFF
13
64
F50000-F5FFFF
14
64
F40000-F4FFFF
15
64
F30000-F3FFFF
16
64
F20000-F2FFFF
17
64
F10000-F1FFFF
18
64
F00000-F0FFFF
73/108
Block address tables
M58LRxxxKC, M58LRxxxKD
Table 34.
M58LR256KC - main bank base addresses
Bank number(1)
Block numbers
Bank base address
1
19-34
E00000
2
35-50
D00000
3
51-66
C00000
4
67-82
B00000
5
83-98
A00000
6
99-114
900000
7
115-130
800000
8
131-146
700000
9
147-162
600000
10
163-178
500000
11
179-194
400000
12
195-210
300000
13
211-226
200000
14
227-242
100000
15
243-258
000000
1. There are two bank regions: bank region 1 contains all the banks that are made up of main blocks only;
bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank).
Table 35.
74/108
M58LR256KC - block addresses in main banks
Block number offset
Block base address offset
0
0F0000
1
0E0000
2
0D0000
3
0C0000
4
0B0000
5
0A0000
6
090000
7
080000
8
070000
9
060000
10
050000
11
040000
12
030000
13
020000
14
010000
15
000000
M58LRxxxKC, M58LRxxxKD
Table 36.
Block address tables
M58LR128KD - parameter bank block addresses
Block number
Size (KWords)
Address range
10
64
070000-07FFFF
9
64
060000-06FFFF
8
64
050000-05FFFF
7
64
040000-04FFFF
6
64
030000-03FFFF
5
64
020000-02FFFF
4
64
010000-01FFFF
3
16
00C000-00FFFF
2
16
008000-00BFFF
1
16
004000-007FFF
0
16
000000-003FFF
75/108
Block address tables
M58LRxxxKC, M58LRxxxKD
Table 37.
M58LR128KD - main bank base addresses
Bank number(1)
Block numbers
Bank base address
15
123-130
78 0000
14
115-122
70 0000
13
107-114
68 0000
12
99-106
60 0000
11
91-98
58 0000
10
83-90
50 0000
9
75-82
48 0000
8
67-74
40 0000
7
59-66
38 0000
6
51-58
30 0000
5
43-50
28 0000
4
35-42
20 0000
3
27-34
18 0000
2
19-26
10 0000
1
11-18
08 0000
1. There are two bank regions: bank region 2 contains all the banks that are made up of main blocks only;
bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank).
Table 38.
76/108
M58LR128KD - block addresses in main banks
Block number offset
Block base address offset
7
070000
6
060000
5
050000
4
040000
3
030000
2
020000
1
010000
0
000000
M58LRxxxKC, M58LRxxxKD
Table 39.
Block address tables
M58LR256KD - parameter bank block addresses
Block number
Size (KWords)
Address range
18
64
0F0000-0FFFFF
17
64
0E0000-0EFFFF
16
64
0D0000-0DFFFF
15
64
0C0000-0CFFFF
14
64
0B0000-0BFFFF
13
64
0A0000-0AFFFF
12
64
090000-09FFFF
11
64
080000-08FFFF
10
64
070000-07FFFF
9
64
060000-06FFFF
8
64
050000-05FFFF
7
64
040000-04FFFF
6
64
030000-03FFFF
5
64
020000-02FFFF
4
64
010000-01FFFF
3
16
00C000-00FFFF
2
16
008000-00BFFF
1
16
004000-007FFF
0
16
000000-003FFF
77/108
Block address tables
M58LRxxxKC, M58LRxxxKD
Table 40.
M58LR256KD - main bank base addresses
Bank number
Block numbers
Bank base address
15
243-258
F00000
14
227-242
E00000
13
211-226
D00000
12
195-210
C00000
11
179-194
B00000
10
163-178
A00000
9
147-162
900000
8
131-146
800000
7
115-130
700000
6
99-114
600000
5
83-98
500000
4
67-82
400000
3
51-66
300000
2
35-50
200000
1
19-34
100000
1. There are two bank regions: bank region 2 contains all the banks that are made up of main blocks only;
bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank).
Table 41.
78/108
M58LR256KD - block addresses in main banks
Block number offset
Block base address offset
15
0F0000
14
0E0000
13
0D0000
12
0C0000
11
0B0000
10
0A0000
9
090000
8
080000
7
070000
6
060000
5
050000
4
040000
3
030000
2
020000
1
010000
0
000000
M58LRxxxKC, M58LRxxxKD
Appendix B
Common Flash interface
Common Flash interface
The common Flash interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the Read CFI Query Command is issued the device enters CFI query mode and the
data structure is read from the memory. Tables 42, 43, 44, 45, 46, 47, 48, 49, 50 and 51
show the addresses used to retrieve the data. The query data is always presented on the
lowest order data outputs (ADQ0-ADQ7), and the other outputs (ADQ8-ADQ15) are set to 0.
The CFI data structure also contains a security area where a 64-bit unique security number
is written (see Figure 4: Protection Register memory map). This area can be accessed only
in read mode by the final user. It is impossible to change the security number after it has
been written by Numonyx. Issue a Read Array command to return to read mode.
Table 42.
Query structure overview
Offset
Sub-section name
Description
000h
Reserved
Reserved for algorithm-specific information
010h
CFI Query identification string
Command set ID and algorithm data offset
01Bh
System interface information
Device timing and voltage information
027h
Device geometry definition
Flash device layout
P
Primary algorithm-specific extended query Additional information specific to the primary
table
algorithm (optional)
A
Alternate algorithm-specific extended
query table
Additional information specific to the alternate
algorithm (optional)
Security code area
Lock Protection Register
Unique device number and
user programmable OTP
080h
1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are
listed the main sub-sections detailed in Tables 43, 44, 45 and 46. Query data is always presented on the
lowest order data outputs.
79/108
Common Flash interface
Table 43.
80/108
M58LRxxxKC, M58LRxxxKD
CFI query identification string
Offset
Sub-section name
000h
0020h
001h
882Eh
882Fh
881Ch
881Dh
002h-00Fh
Reserved
010h
0051h
011h
0052h
012h
0059h
013h
0001h
014h
0000h
015h
Offset = P = 000Ah
016h
0001h
017h
0000h
018h
0000h
019h
Value = A = 0000h
01Ah
0000h
Description
Value
Manufacturer code
Device code
Numonyx
M58LR128KC
M58LR128KD
M58LR256KC
M58LR256KD
Top
Bottom
Reserved
"Q"
Query unique ASCII string "QRY"
"R"
"Y"
Primary algorithm command set and control
interface ID code 16-bit ID code defining a specific
algorithm
Address for primary algorithm extended query table
(see Table 46)
p = 10Ah
Alternate vendor command set and control Interface
ID code second vendor - specified algorithm
supported
NA
Address for alternate algorithm extended query table
NA
M58LRxxxKC, M58LRxxxKD
Table 44.
Common Flash interface
CFI query system interface information
Offset
Data
01Bh
0017h
VDD logic supply minimum program/erase or write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
1.7 V
01Ch
0020h
VDD logic supply maximum program/erase or write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
2V
01Dh
0085h
VPP [programming] supply minimum program/erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
8.5 V
01Eh
0095h
VPP [programming] supply maximum program/erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
9.5 V
01Fh
0004h
Typical timeout per single byte/word program = 2n µs
16 µs
020h
0009h
Description
Value
n
Typical timeout for buffer program = 2 µs
512 µs
021h
000Ah
Typical timeout per individual block erase =
022h
0000h
Typical timeout for full chip erase = 2n ms
023h
024h
0004h
0004h
2n
ms
NA
n
Maximum timeout for word program = 2 times typical
Maximum timeout for buffer program =
2n
1s
256 µs
times typical
8192 µs
n
025h
0002h
Maximum timeout per individual block erase = 2 times typical
4s
026h
0000h
Maximum timeout for chip erase = 2n times typical
NA
81/108
Common Flash interface
Table 45.
Offset
M58LRxxxKC, M58LRxxxKD
Device geometry definition
Data
0018h
027h
TOP DEVICES
n
16 Mbytes
M58LR256KC/D device size = 2 in number of bytes
028h
029h
0001h
0000h
Flash device interface code description
02Ah
02Bh
0006h
0000h
Maximum number of bytes in multi-byte program or page = 2n
02Ch
0002h
Number of identical sized erase block regions within the
device
bit 7 to 0 = x = number of erase block regions
007Eh
0000h
M58LR128KC/D erase block region 1 information
Number of identical-size erase blocks = 007Eh+1
127
00FEh
0000h
M58LR256KC/D erase block region 1 information
Number of identical-size erase blocks = 00FEh+1
255
02Fh
030h
0000h
0002h
Erase block region 1 information
Block size in region 1 = 0200h * 256 bytes
031h
032h
0003h
0000h
Erase block region 2 information
Number of identical-size erase blocks = 0003h+1
033h
034h
0080h
0000h
Erase block region 2 information
Block size in region 2 = 0080h * 256 bytes
035h
038h
BOTTOM DEVICES
M58LR128KC/D device size = 2n in number of bytes
Value
0019h
02Dh
02Eh
Reserved Reserved for future erase block region information
32 Mbytes
x16
async.
64 bytes
2
128 KByte
4
32 KByte
NA
02Dh
02Eh
0003h
0000h
Erase block region 1 information
Number of identical-size erase block = 0003h+1
02Fh
030h
0080h
0000h
Erase block region 1 information
Block size in region 1 = 0080h * 256 bytes
007Eh
0000h
M58LR128KC/D Erase block region 2 information
Number of identical-size erase block = 007Eh+1
127
00FEh
0000h
M58LR256KC/D Erase block region 2 information
Number of identical-size erase block = 00FEh+1
255
0000h
0002h
Erase block region 2 information
Block size in region 2 = 0200h * 256 bytes
031h
032h
033h
034h
035h
038h
82/108
Description
Reserved Reserved for future erase block region information
4
32 KBytes
128 KBytes
NA
M58LRxxxKC, M58LRxxxKD
Table 46.
Common Flash interface
Primary algorithm-specific extended query table
Offset
Data
(P)h = 10Ah
0050h
0052h
Description
Value
"P"
Primary algorithm extended query table unique ASCII string
“PRI”
0049h
"R"
"I"
(P+3)h =10Dh
0031h
Major version number, ASCII
"1"
(P+4)h = 10Eh
0033h
Minor version number, ASCII
"3"
(P+5)h = 10Fh
00E6h
Extended query table contents for primary algorithm. Address
(P+5)h contains less significant byte.
0003h
(P+7)h = 111h
(P+8)h = 112h
0000h
0000h
bit 0 Chip Erase supported(1 = Yes, 0 = No)
bit 1 Erase Suspend supported(1 = Yes, 0 = No)
bit 2 Program Suspend supported(1 = Yes, 0 = No)
bit 3 Legacy Lock/Unlock supported(1 = Yes, 0 = No)
bit 4 Queued Erase supported(1 = Yes, 0 = No)
bit 5 Instant individual block locking supported(1 = Yes, 0 = No)
bit 6 Protection bits supported(1 = Yes, 0 = No)
bit 7 Page mode read supported(1 = Yes, 0 = No)
bit 8 Synchronous read supported(1 = Yes, 0 = No)
bit 9 Simultaneous operation supported(1 = Yes, 0 = No)
bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then
another 31 bit field of optional features follows at the end of the
bit-30 field.
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query
(P+9)h = 113h
0001h
bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
(P+A)h = 114h
0003h
(P+B)h = 115h
0000h
Yes
Block Protect Status
Defines which bits in the Block Status Register section of the
query are implemented.
bit 0 Block protect Status Register Lock/Unlock
bit active (1 = Yes, 0 = No)
bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes,
0 = No)
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
Yes
Yes
VDD logic supply optimum program/erase voltage (highest
performance)
(P+C)h = 116h
1.8V
0018h
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
VPP Supply Optimum Program/Erase voltage
(P+D)h = 117h
0090h
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
9V
83/108
Common Flash interface
Table 47.
M58LRxxxKC, M58LRxxxKD
Protection Register information
(1)
Offset
Data
Description
Number of protection register fields in JEDEC ID space.
0000h indicates that 256 fields are available.
(P+E)h = 118h
0002h
(P+F)h = 119h
(P+12)h = 11Ch
0080h Protection Field 1: Protection Description
0000h Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
0003h
Bits 16-23 2n bytes in factory pre-programmed region
0003h Bits 24-31 2n bytes in user programmable region
(P+13)h = 11Dh
0089h
(P+10)h = 11Ah
(P+ 11)h = 11Bh
(P+14)h = 11Eh
0000h
(P+15)h = 11Fh
0000h
(P+16)h = 120h
0000h
(P+17)h = 121h
0000h
(P+18)h = 122h
0000h
(P+19)h = 123h
0000h
(P+1A)h = 124h
0010h
(P+1B)h = 125h
0000h
(P+1C)h = 126h
0004h
Value
2
80h
00h
8 bytes
8 bytes
89h
Protection Register 2: Protection Description
Bits 0-31 protection register address
Bits 32-39 n number of factory programmed regions (lower
byte)
Bits 40-47 n number of factory programmed regions (upper
byte)
Bits 48-55 2n bytes in factory programmable region
Bits 56-63 n number of user programmable regions (lower
byte)
Bits 64-71 n number of user programmable regions (upper
byte)
Bits 72-79 2n bytes in user programmable region
00h
00h
00h
0
0
0
16
0
16
1. The variable P is a pointer that is defined at CFI offset 015h.
Table 48.
Burst read information
Offset(1)
Data
Description
(P+1D)h = 127h
Page-mode read capability
bits 0-7 n’ such that 2n HEX value represents the number of
0003h
read-page bytes. See offset 0028h for device word width to
determine page-mode data output width.
(P+1E)h = 128h
0004h
(P+1F)h = 129h
Synchronous mode read capability configuration 1
bit 3-7 Reserved
bit 0-2 n’ such that 2n+1 HEX value represents the maximum
number of continuous synchronous reads when the device is
configured for its maximum word width. A value of 07h indicates
0001h
that the device is capable of continuous linear bursts that will
output data until the internal burst counter reaches the end of
the device’s burstable address space. This field’s 3-bit value
can be written directly to the read configuration register bit 0-2 if
the device is configured for its maximum word width. See offset
0028h for word width to determine the burst data output width.
4
(P+20)h = 12Ah
0002h Synchronous mode read capability configuration 2
8
(P-21)h = 12Bh
(P+22)h = 12Ch
0003h Synchronous mode read capability configuration 3
0007h Synchronous mode read capability configuration 4
16
Number of synchronous mode read configuration fields that
follow.
1. The variable P is a pointer that is defined at CFI offset 015h.
84/108
Value
8
bytes
4
Cont.
M58LRxxxKC, M58LRxxxKD
Table 49.
Common Flash interface
Bank and erase block region information(1) (2)
Flash memory (top)
Flash memory (bottom)
Description
Offset
Data
Offset
Data
(P+23)h = 12Dh
02h
(P+23)h = 12Dh
02h
Number of bank regions within the device
1. The variable P is a pointer that is defined at CFI offset 015h.
2. bank regions. There are two bank regions, see Table 31, Table 34, Table 37 and Table 40.
Table 50.
Bank and erase block region 1 information
Flash memory (top)
Flash memory (bottom)
Description
Offset(1)
Data
Offset(1)
Data
(P+24)h = 12Eh
0Fh
(P+24)h = 12Eh
01h
(P+25)h = 12Fh
00h
(P+25)h = 12Fh
00h
Number of identical banks within bank region 1
(P+26)h = 130h
(P+27)h = 131h
(P+28)h = 132h
(P+29)h = 133h
(P+2A)h = 134h
11h
Number of program or erase operations
allowed in bank region 1:
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
00h
Number of program or erase operations
allowed in other banks while a bank in same
region is programming
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
00h
Number of program or erase operations
allowed in other banks while a bank in this
region is erasing
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
(P+29)h = 133h
02h
Types of erase block regions in bank region 1
n = number of erase block regions with
contiguous same-size erase blocks.
Symmetrically blocked banks have one
blocking region(2)
07h(3)
(P+2A)h = 134h
0Fh(4)
03h
11h
00h
00h
01h
(P+26)h = 130h
(P+27)h = 131h
(P+28)h = 132h
(P+2B)h = 135h
00h
(P+2B)h = 135h
00h
(P+2C)h = 136h
00h
(P+2C)h = 136h
80h
(P+2D)h = 137h
02h
(P+2D)h = 137h
00h
(P+2E)h = 138h
64h
(P+2E)h = 138h
64h
(P+2F)h = 139h
00h
(P+2F)h = 139h
00h
Bank region 1 erase block type 1 information
Bits 0-15: n+1 = number of identical-sized
erase blocks
Bits 16-31: n×256 = number of bytes in erase
block region
Bank region 1 (erase block type 1)
Minimum block erase cycles × 1000
85/108
Common Flash interface
Table 50.
M58LRxxxKC, M58LRxxxKD
Bank and erase block region 1 information (continued)
Flash memory (top)
Offset(1)
(P+30)h = 13Ah
(P+31)h = 13Bh
Data
01h
03h
Flash memory (bottom)
Offset(1)
(P+30)h = 13Ah
(P+31)h = 13Bh
Description
Data
01h
Bank region 1 (erase block type 1): BIts per
cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank region 1 (erase block type 1): Page mode
and Synchronous mode capabilities
Bit 0: Page-mode reads permitted(5)
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
06h(3)
Bank region 1 erase block type 2 information
0Eh(4)
Bits 0-15: n+1 = number of identical-sized
(P+33)h = 13Dh
00h erase blocks
(P+34)h = 13Eh
00h Bits 16-31: n×256 = number of bytes in erase
block region
(P+35)h = 13Fh
02h
(P+32)h = 13Ch
(P+36)h = 140h
64h
(P+37)h = 141h
00h
(P+38)h = 142h
(P+39)h = 143h
Bank region 1 (erase block type 2)
Minimum block erase cycles × 1000
01h
Bank regions 1 (erase block type 2): BIts per
cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank region 1 (erase block type 2): Page mode
and Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
1. The variable P is a pointer that is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Table 31, Table 34, Table 37 and Table 40.
3. Applies to M58LR128KC/D only.
4. Applies to M58LR256KC/D only.
5. Although the device supports Page Read mode, this is not described in the datasheet as its use is not
advantageous in a multiplexed device.
86/108
M58LRxxxKC, M58LRxxxKD
Table 51.
Common Flash interface
Bank and erase block region 2 information
Flash memory (top)
Flash memory (bottom)
Description
Offset(1)
Data
Offset(1)
Data
(P+32)h = 13Ch
01h
(P+3A)h = 144h
0Fh
(P+33)h = 13Dh
00h
(P+3B)h = 145h
00h
Number of identical banks within bank region 2
(P+34)h = 13Eh
(P+35)h = 13Fh
(P+36)h = 140h
(P+37)h = 141h
(P+38)h = 142h
11h
00h
00h
02h
(P+3C)h = 146h
(P+3D)h = 147h
(P+3E)h = 148h
(P+3F)h = 149h
06h(3)
(P+40)h = 14Ah
0Eh(4)
11h
Number of program or erase operations
allowed in bank region 2:
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
00h
Number of program or erase operations
allowed in other banks while a bank in this
region is programming
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
00h
Number of program or erase operations
allowed in other banks while a bank in this
region is erasing
Bits 0-3: Number of simultaneous program
operations
Bits 4-7: Number of simultaneous erase
operations
01h
Types of erase block regions in bank region 2
n = number of erase block regions with
contiguous same-size erase blocks.
Symmetrically blocked banks have one
blocking region.(2)
07h(3)
Bank region 2 erase block type 1 information
0Fh(4)
Bits 0-15: n+1 = number of identical-sized
00h erase blocks
00h Bits 16-31: n×256 = number of bytes in erase
block region
02h
(P+39)h = 143h
00h
(P+41)h = 14Bh
(P+3A)h = 144h
00h
(P+42)h = 14Ch
(P+3B)h = 145h
02h
(P+43)h = 14Dh
(P+3C)h = 146h
64h
(P+44)h = 14Eh
64h
(P+3D)h = 147h
00h
(P+45)h = 14Fh
00h
(P+3E)h = 148h
01h
(P+46)h = 150h
01h
Bank region 2 (erase block type 1)
Minimum block erase cycles × 1000
Bank region 2 (erase block type 1): BIts per
cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
87/108
Common Flash interface
Table 51.
M58LRxxxKC, M58LRxxxKD
Bank and erase block region 2 information (continued)
Flash memory (top)
Offset(1)
Data
(P+3F)h = 149h
03h
(P+40)h = 14Ah
03h
(P+41)h = 14Bh
00h
(P+42)h = 14Ch
80h
(P+43)h = 14Dh
00h
(P+44)h = 14Eh
64h
(P+45)h = 14Fh
00h
(P+46)h = 150h
(P+47)h = 151h
Flash memory (bottom)
Offset(1)
(P+47)h = 151h
Description
Data
03h
Bank region 2 (erase block type 1):Page mode
and Synchronous mode capabilities (defined in
Table 48)
Bit 0: Page-mode reads permitted(5)
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
Bank region 2 erase block type0 2 information
Bits 0-15: n+1 = number of identical-sized
erase blocks
Bits 16-31: n×256 = number of bytes in erase
block region
Bank region 2 (erase block type 2)
Minimum block erase cycles × 1000
01h
Bank region 2 (erase block type 2): BIts per
cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
03h
Bank region 2 (Erase block type 2): Page mode
and Synchronous mode capabilities (defined in
Table 48)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
(P+48)h = 152h
(P+48)h = 152h
Feature Space definitions
(P+49)h = 153h
(P+43)h = 153h
Reserved
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Table 31, Table 34, Table 37 and Table 40.
3. Applies to M58LR128KC/D only.
4. Applies to M58LR256KC/D only.
5. Although the device supports Page Read mode, this is not described in the datasheet as its use is not
advantageous in a multiplexed device.
88/108
M58LRxxxKC, M58LRxxxKD
Appendix C
Flowcharts and pseudocodes
Flowcharts and pseudocodes
Figure 17. Program flowchart and pseudocode
Start
program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0x40);
/*writeToFlash (addressToProgram, 0x10);*/
/*see note (3)*/
Write 40h or 10h (3)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (addressToProgram);
"see note (3)";
/* E or G must be toggled*/
Read Status
Register (3)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06170b
1. Status check of SR1 (protected block), SR3 (VPP Invalid) and SR4 (program error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
89/108
Flowcharts and pseudocodes
M58LRxxxKC, M58LRxxxKD
Figure 18. Blank check flowchart and pseudocode
Start
blank_check_command (blockToCheck) {
writeToFlash (blockToCheck, 0xBC);
Write Block
Address & BCh
writeToFlash (blockToCheck, 0xCB);
/* Memory enters read status state after
the Blank Check Command */
Write Block
Address & CBh
do {
status_register = readFlash (blockToCheck);
/* see note (1) */
/* E or G must be toggled */
Read
Status Register (1)
} while (status_register.SR7==0);
SR7 = 1
NO
YES
SR4 = 1
SR5 = 1
SR5 = 0
YES
NO
Command Sequence
Error (2)
if (status_register.SR4==1) && (status_register.SR5==1)
/* command sequence error */
error_handler () ;
Blank Check Error (2)
if (status_register.SR5==1)
/* Blank Check error */
error_handler () ;
End
}
ai10520c
1. Any address within the bank can equally be used.
2. If an error is found, the Status Register must be cleared before further program/erase operations.
90/108
M58LRxxxKC, M58LRxxxKD
Flowcharts and pseudocodes
Figure 19. Buffer program flowchart and pseudocode
Start
Buffer Program E8h
Command,
Start Address
status_register=readFlash (Start_Address);
Read Status
Register
SR7 = 1
Buffer_Program_command (Start_Address, n, buffer_Program[] )
/* buffer_Program [] is an array structure used to store the address and
data to be programmed to the Flash memory (the address must be within
the segment Start Address and Start Address+n) */
{
do {writeToFlash (Start_Address, 0xE8) ;
NO
} while (status_register.SR7==0);
YES
writeToFlash (Start_Address, n);
Write n(1),
Start Address
Write Buffer Data,
Start Address
writeToFlash (buffer_Program[0].address, buffer_Program[0].data);
/*buffer_Program[0].address is the start address*/
X=0
X=n
x = 0;
YES
while (x<n)
NO
Write Next Buffer Data,
Next Program Address(2)
{ writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data);
x++;
X=X+1
}
Program
Buffer to Flash
Confirm D0h
writeToFlash (Start_Address, 0xD0);
Read Status
Register
SR7 = 1
do {status_register=readFlash (Start_Address);
NO
} while (status_register.SR7==0);
YES
Full Status
Register Check(3)
full_status_register_check();
}
End
AI08913b
1. n + 1 is the number of data being programmed.
2. Next program data is an element belonging to buffer_Program[].data; next program address is an element belonging to
buffer_Program[].address
3. Routine for error check by reading SR3, SR4 and SR1.
91/108
Flowcharts and pseudocodes
M58LRxxxKC, M58LRxxxKD
Figure 20. Program suspend and resume flowchart and pseudocode
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
program has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR2 = 1
NO
Program Complete
if (status_register.SR2==0) /*program completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
YES
Read Data
}
else
Write FFh
{ writeToFlash (bank_address, 0xFF) ;
Read data from
another address
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write D0h
writeToFlash (bank_address, 0x70) ;
/*read status register to check if program has completed */
Write 70h(1)
}
Program Continues with
Bank in Read Status
Register Mode
}
AI10117b
1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
92/108
M58LRxxxKC, M58LRxxxKD
Flowcharts and pseudocodes
Figure 21. Block erase flowchart and pseudocode
Start
erase_command ( blockToErase ) {
writeToFlash (blockToErase, 0x20) ;
/*see note (2) */
Write 20h (2)
writeToFlash (blockToErase, 0xD0) ;
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
status_register=readFlash (blockToErase) ;
/* see note (2) */
/* E or G must be toggled*/
Read Status
Register (2)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1)
YES
Command
Sequence Error (1)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
YES
SR4, SR5 = 1
if ( (status_register.SR4==1) && (status_register.SR5==1) )
/* command sequence error */
error_handler ( ) ;
NO
SR5 = 0
NO
Erase Error (1)
if ( (status_register.SR5==1) )
/* erase error */
error_handler ( ) ;
YES
SR1 = 0
NO
Erase to Protected
Block Error (1)
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI10976
1. If an error is found, the Status Register must be cleared before further program/erase operations.
2. Any address within the bank can equally be used.
93/108
Flowcharts and pseudocodes
M58LRxxxKC, M58LRxxxKD
Figure 22. Erase suspend and resume flowchart and pseudocode
Start
erase_suspend_command ( ) {
writeToFlash (bank_address, 0xB0) ;
Write B0h
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
erase has already completed */
Write 70h
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
Read Status
Register
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR6 = 1
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */
{ writeToFlash (bank_address, 0xFF) ;
Write FFh
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Read Data
YES
Write FFh
}
else
{ writeToFlash (bank_address, 0xFF) ;
read_program_data ( );
Read data from another block
or
Program
or
Block Lock/Unlock/Lock-Down
or
Set Configuration Register
/*read or program data from another block*/
writeToFlash (bank_address, 0xD0) ;
/*write 0xD0 to resume erase*/
writeToFlash (bank_address, 0x70) ;
/*read status register to check if erase has completed */
Write D0h
}
Write 70h(1)
Erase Continues with
Bank in Read Status
Register Mode
}
AI10116c
1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
94/108
M58LRxxxKC, M58LRxxxKD
Flowcharts and pseudocodes
Figure 23. Locking operations flowchart and pseudocode
Start
locking_operation_command (address, lock_operation) {
writeToFlash (address, 0x60) ; /*configuration setup*/
/* see note (1) */
Write 60h (1)
if (lock_operation==LOCK) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (lock_operation==UNLOCK) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
else if (lock_operation==LOCK-DOWN) /*to lock the block*/
writeToFlash (address, 0x2F) ;
Write
01h, D0h or 2Fh
writeToFlash (address, 0x90) ;
/*see note (1) */
Write 90h (1)
Read Block
Lock States
Locking
change
confirmed?
if (readFlash (address) ! = locking_state_expected)
error_handler () ;
/*Check the locking state (see Read Block Signature table )*/
NO
YES
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/
/*see note (1) */
Write FFh (1)
}
End
AI06176b
1. Any address within the bank can equally be used.
95/108
Flowcharts and pseudocodes
M58LRxxxKC, M58LRxxxKD
Figure 24. Protection Register program flowchart and pseudocode
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0xC0) ;
/*see note (3) */
Write C0h (3)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
status_register=readFlash (addressToProgram) ;
/* see note (3) */
/* E or G must be toggled*/
Read Status
Register (3)
SR7 = 1
NO
} while (status_register.SR7== 0) ;
YES
SR3 = 0
NO
VPP Invalid
Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
NO
Program
Error (1, 2)
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
NO
Program to Protected
Block Error (1, 2)
YES
SR4 = 0
YES
SR1 = 0
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
YES
End
}
AI06177b
1. Status check of SR1 (protected block), SR3 (VPP invalid) and SR4 (program error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
96/108
M58LRxxxKC, M58LRxxxKD
Flowcharts and pseudocodes
Figure 25. Buffer enhanced factory program flowchart and pseudocode
Start
NO
writeToFlash (start_address, 0x80) ;
Write D0h to
Address WA1
writeToFlash (start_address, 0xD0) ;
Read Status
Register
do {
do {
status_register = readFlash (start_address);
SR7 = 0
Initialize count
X=0
SR4 = 1
Read Status Register
SR3 and SR1for errors
Write PDX
Address WA1
Exit
Increment Count
X=X+1
NO
Buffer_Enhanced_Factory_Program_Command
(start_address, DataFlow[]) {
Write 80h to
Address WA1
YES
NO
SETUP PHASE
if (status_register.SR4==1) { /*error*/
if (status_register.SR3==1) error_handler ( ) ;/*VPP error */
if (status_register.SR1==1) error_handler ( ) ;/* Locked Block */
PROGRAM AND }
VERIFY PHASE while (status_register.SR7==1)
x=0; /* initialize count */
do {
writeToFlash (start_address, DataFlow[x]);
x++;
X = 32
NO
YES
}while (x<32)
do {
Read Status
Register
status_register = readFlash (start_address);
SR0 = 0
}while (status_register.SR0==1)
YES
NO
Last data?
} while (not last data)
YES
Write FFFFh to
Address = NOT WA1
Read Status
Register
NO
writeToFlash (another_block_address, FFFFh)
EXIT PHASE
do {
status_register = readFlash (start_address)
SR7 = 1
}while (status_register.SR7==0)
YES
Full Status Register
Check
full_status_register_check();
End
}
AI07302a
97/108
Command interface state tables
Appendix D
Table 52.
M58LRxxxKC, M58LRxxxKD
Command interface state tables
Command interface states - modify table, next state(1)
Command Input
Current CI State
Ready
Block
Buffer
BEFP
Read Program Program Erase,
(3)(4)
Setup
Array(2) Setup
(3)(4)
Setup(3)(4)
(FFh)
(80h)
(10/40h)
(E8h)
(20h)
Ready
Program
Setup
Lock/CR Setup
BP
Setup
Erase
Setup
BEFP
Setup
Erase
Read
Confirm
Buffer
Clear
Electronic
Blank P/E Resume, Blank Program, Read
Status
Check Block Unlock Check Program/ Status Register Signature
, Read
confirm,
confirm Erase Register
setup
(5)
CFI Query
BEFP
(CBh) Suspend (70h)
(BCh)
(3)(4)
(50h)
Confirm
(B0h)
(90h, 98h)
(D0h)
Blank
Check
setup
Ready (unlock
block)
Ready (Lock Error)
Setup
Busy
OTP
OTP
Busy
IS in OTP
Busy
OTP Busy
Program Busy
IS in
Program
Program
Program
Busy
Busy
Busy
IS in Program
Busy
IS in
Program
Busy
Program Busy
Program
Suspend
Program Busy
Program Busy
PS
IS in PS
PS
IS in Program
Suspend
PS
Program Busy
Program Suspend
IS in PS
Program Suspend
Setup
Buffer Program Load 1 (give word count load (N-1));
Buffer
Load 1
if N=0 go to Buffer Program Confirm. Else (N ≠ 0) go to Buffer Program Load 2 (data load)
Buffer
Load 2
Buffer Program Confirm when count =0; Else Buffer Program Load 2
(note: Buffer Program will fail at this point if any block address is different from the first address)
Busy
IS in BP
Busy
Suspend
IS in BP
Suspend
98/108
IS in OTP Busy
Setup
Confirm
Buffer
Program
OTP
busy
OTP Busy
Suspend
Ready (Lock Error)
OTP Busy
IS in
OTP
busy
Busy
Program
Ready
Ready (error)
BP Busy IS in BP
Busy
BP Busy
BP Busy
IS in BP Busy
BP Busy
Ready (error)
BP
Suspend
Buffer Program Busy
Buffer Program Busy
BP
BP
IS in BP
BP
IS in BP Suspend
Suspend
Suspend Suspend Suspend
BP busy
Buffer Program Suspend
Buffer Program Suspend
M58LRxxxKC, M58LRxxxKD
Table 52.
Command interface state tables
Command interface states - modify table, next state(1) (continued)
Command Input
Current CI State
Block
Buffer
BEFP
Read Program Program Erase,
(3)(4)
Setup
Array(2) Setup
(3)(4)
Setup(3)(4)
(FFh)
(80h)
(10/40h)
(E8h)
(20h)
Setup
Busy
Erase
Erase
Busy
IS in
Erase
Busy
Erase
Read
Confirm
Buffer
Clear
Electronic
Blank P/E Resume, Blank Program, Read
Status
Check Block Unlock Check Program/ Status Register Signature
, Read
confirm,
setup
confirm Erase Register
(5)
CFI Query
BEFP
(BCh)
(CBh) Suspend (70h)
(3)(4)
(50h)
Confirm
(B0h)
(90h, 98h)
(D0h)
Ready (error)
Erase Busy
Erase
Busy
Erase Busy
IS in Erase Busy
IS in
Erase
Busy
Suspend
Erase
Suspend
Erase Busy
Erase Busy
Erase Program
BP in ES
Suspend
in ES
IS in Erase
Suspend
ES
Erase Busy
IS in ES
Erase Suspend
Setup
Program Busy in Erase Suspend
Busy
Ready (error)
IS in
Program
Program
Busy in
Busy in
ES
ES
Program
Busy in
ES
IS in Program
Busy in ES
Program IS in
in Erase Program
Suspend busy in
ES
Erase Suspend
Program Busy in ES
PS in ES
Program Busy in Erase
Suspend
Program busy in Erase Suspend
Suspend PS in ES
IS in PS in
PS in ES
ES
IS in Program
Suspend in ES
PS in ES
Program Busy
in ES
Program Suspend in Erase Suspend
IS in PS
in ES
Program Suspend in Erase Suspend
Setup
Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N ≠ 0) go to
Buffer Program Load 2
Buffer
Load 1
Buffer Program Load 2 in Erase Suspend (data load)
Buffer Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program
Load 2
will fail at this point if any block address is different from the first address)
Confirm
Buffer
Program
in Erase
Suspend
Busy
IS in BP
busy in
ES
Erase Suspend (sequence error)
BP Busy
in ES
IS in BP
Busy in
ES
BP busy
in ES
BP Busy in ES
IS in BP busy in
ES
BP
Suspend
in ES
BP Busy in ES
Buffer Program Busy in ES
Buffer Program Busy in Erase Suspend
BP
BP
IS in BP
BP
IS in BP Suspend Suspend
Suspend Suspend Suspend Suspend in
Erase Suspend
in
ES
in
ES
in ES
in ES
IS in BP
Suspend
in ES
Erase Suspend (sequence error)
BP Busy in
Erase
Suspend
Buffer Program Suspend in Erase Suspend
BP Suspend in Erase Suspend
99/108
Command interface state tables
Table 52.
M58LRxxxKC, M58LRxxxKD
Command interface states - modify table, next state(1) (continued)
Command Input
Current CI State
Block
Buffer
BEFP
Read Program Program Erase,
(3)(4)
Setup
Array(2) Setup
(3)(4)
Setup(3)(4)
(FFh)
(80h)
(10/40h)
(E8h)
(20h)
Setup
Blank
Check
Busy
Lock/CR Setup in
Erase Suspend
Buffer
EFP
Setup
Erase
Read
Confirm
Buffer
Clear
Electronic
Blank P/E Resume, Blank Program, Read
Status
Check Block Unlock Check Program/ Status Register Signature
, Read
confirm,
setup
confirm Erase Register
(5)
CFI Query
BEFP
(BCh)
(CBh) Suspend (70h)
(3)(4)
(50h)
Confirm
(B0h)
(90h, 98h)
(D0h)
Blank
Check
busy
Ready (error)
Blank IS in Blank
Check
Check
busy
busy
Blank
Check
busy
IS in Blank Check
busy
Ready (error)
Blank Check busy
Erase Suspend (Lock Error)
Erase
Suspend
Erase Suspend (Lock Error)
Ready (error)
BEFP Busy
Ready (error)
Busy
BEFP Busy(6)
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase
controller, IS = Illegal State, BP = Buffer Program, ES = Erase Suspend.
2. At power-up, all banks are in read array mode. Issuing a Read Array command to a busy bank, results in undetermined
data output.
3. The two cycle command should be issued to the same bank address.
4. If the P/E C is active, both cycles are ignored.
5. The Clear Status Register command clears the SR error bits except when the P/E C. is busy or suspended.
6. BEFP is allowed only when Status Register bit SR0 is reset to '0'. BEFP is busy if Block Address is first BEFP Address. Any
other commands are treated as data.
100/108
M58LRxxxKC, M58LRxxxKD
Table 53.
Command interface state tables
Command interface states - modify table, next output state(1) (2)
Command Input
Current CI State
Erase Confirm
Block
Blank P/E Resume,
Buffer Erase, BEFP
Block Unlock
(4)
Setup Check
Program Setup
(5)
setup confirm, BEFP
(5)
(E8h)
(80h) (BCh) Confirm(4)(5)
(10/40h)
(20h)
(D0h)
Read Program
Array Setup(4)
(3)
(FFh)
Read
Clear Electronic
Blank Program/ Read
Status Status signature,
Check
Erase
confirm Suspend Register Register Read CFI
Query
(CBh)
(B0h)
(70h)
(50h)
(90h, 98h)
Program Setup
Erase Setup
OTP Setup
Program Setup in
Erase Suspend
BEFP Setup
BEFP Busy
Buffer Program
Setup
Buffer Program
Load 1
Buffer Program
Load 2
Buffer Program
Confirm
Status Register
Buffer Program
Setup in Erase
Suspend
Buffer Program
Load 1 in Erase
Suspend
Buffer Program
Load 2 in Erase
Suspend
Buffer Program
Confirm in Erase
Suspend
Blank Check setup
Lock/CR Setup
Lock/CR Setup in
Erase Suspend
101/108
Command interface state tables
Table 53.
M58LRxxxKC, M58LRxxxKD
Command interface states - modify table, next output state(1) (2) (continued)
Command Input
Current CI State
Erase Confirm
Block
Blank P/E Resume,
Buffer Erase, BEFP
Block Unlock
(4)
Setup Check
Program Setup
(5)
setup confirm, BEFP
(5)
(E8h)
(80h) (BCh) Confirm(4)(5)
(10/40h)
(20h)
(D0h)
Read Program
Array Setup(4)
(3)
(FFh)
Read
Clear Electronic
Blank Program/ Read
Status Status signature,
Check
Erase
confirm Suspend Register Register Read CFI
Query
(CBh)
(B0h)
(70h)
(50h)
(90h, 98h)
Status
Register
OTP Busy
Ready
Program Busy
Erase Busy
Buffer Program
Busy
Program/Erase
Suspend
Buffer Program
Suspend
Array
Status Register
Output Unchanged
Program Busy in
Erase Suspend
Output
Status
Unchang
Electronic
Register
ed
Signature/
CFI
Buffer Program
Busy in Erase
Suspend
Program Suspend
in Erase Suspend
Buffer Program
Suspend in Erase
Suspend
Blank Check busy
Illegal State
Output Unchanged
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command
address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode,
depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank.
The next state does not depend on the bank output state.
2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. =
Program/Erase Controller.
3. At Power-Up, all banks are in read array mode. Issuing a Read Array command to a busy bank, results in undetermined
data output.
4. The two cycle command should be issued to the same bank address.
5. If the P/EC is active, both cycles are ignored.
102/108
M58LRxxxKC, M58LRxxxKD
Command interface state tables
Command interface states - lock table, next state(1)
Table 54.
Command Input
Current CI State
Ready
Lock/CR Setup
Lock/CR Setup(2)
(60h)
OTP
Setup(2)
(C0h)
Lock/CR Setup
OTP Setup
Busy
Block
Address
(WA0)(3)
(XXXXh)
Illegal
Command(4)
Ready
P/E C
operation
completed
(5)
N/A
Ready (Lock error)
OTP Busy
N/A
N/A
IS in OTP Busy
OTP Busy
Ready
IS in OTP
busy
OTP Busy
IS Ready
Setup
Program Busy
N/A
Busy
Program
Set CR
Confirm
(03h)
Ready
Ready (Lock error)
Setup
OTP
Block
LockDown
Confirm
(2Fh)
Block
Lock
Confirm
(01h)
IS in Program Busy
IS in Program
busy
Suspend
Program Busy
Ready
Program busy
IS in PS
IS Ready
Program Suspend
N/A
IS in PS
Program Suspend
Setup
Buffer Program Load 1 (give word count load (N-1));
Buffer Program Load 2(6)
Buffer Load 1
Buffer
Program
Exit
see note (6)
N/A
Buffer Load 2
Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail at
this point if any block address is different from the first address)
N/A
Confirm
Ready (error)
N/A
Busy
IS in BP Busy
IS in Buffer
Program
busy
Suspend
Buffer Program Busy
Buffer Program Busy
IS in BP Suspend
Buffer Program Suspend
N/A
Buffer Program Suspend
Setup
Ready (error)
IS in Erase Busy
IS in Erase
busy
Suspend
IS in ES
Ready
IS Ready
IS in BP
Suspend
Busy
Erase
N/A
N/A
Erase Busy
Erase Busy
Lock/CR Setup in
ES
IS in ES
Ready
IS ready
Erase Suspend
N/A
Erase Suspend
103/108
Command interface state tables
Table 54.
M58LRxxxKC, M58LRxxxKD
Command interface states - lock table, next state(1) (continued)
Command Input
Current CI State
Lock/CR Setup(2)
(60h)
OTP
Setup(2)
(C0h)
Setup
Busy
Program
in Erase
Suspend
Block
LockDown
Confirm
(2Fh)
Block
Address
(WA0)(3)
(XXXXh)
Set CR
Confirm
(03h)
Illegal
Command(4)
P/E C
operation
completed
Program Busy in Erase Suspend
IS in Program busy in ES
ES
Program Busy in Erase Suspend
IS in PS in ES
(5)
N/A
Program Busy in Erase Suspend
IS in Program
busy in ES
Suspend
Block
Lock
Confirm
(01h)
IS in ES
Program Suspend in Erase Suspend
N/A
IS in PS in ES
Program Suspend in Erase Suspend
Setup
Buffer Program Load 1 in Erase Suspend (give word count load (N-1))
Buffer Load 1
Buffer
Program
in Erase
Suspend
Buffer Program Load 2 in Erase Suspend(7)
Buffer Load 2
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase
Suspend (note: Buffer Program will fail at this point if any block address is different from the first
address)
Confirm
Erase Suspend (sequence error)
Busy
IS in BP busy in ES
Buffer Program Busy in Erase Suspend
IS in BP busy
in ES
Suspend
Blank
Check
see note (7)
Exit
BP busy in ES
IS in BP suspend in ES
Buffer Program Suspend in Erase Suspend
N/A
Buffer Program Suspend in Erase Suspend
Setup
Ready (error)
Lock/CR Setup in ES
ES
IS in ES
IS in BP
Suspend in
ES
Blank Check
busy
N/A
IS in Blank Check busy
N/A
Blank Check busy
Erase Suspend (Lock error)
Setup
Erase Suspend
Ready
Erase Suspend (Lock error)
Ready (error)
N/A
N/A
BEFP
Busy
BEFP Busy(8)
Exit
BEFP Busy(8)
N/A
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase
controller, IS = Illegal State, BP = Buffer program, ES = Erase suspend, WA0 = Address in a block different from first BEFP
address.
2. If the P/E C is active, both cycle are ignored.
3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
4. Illegal commands are those not defined in the command set.
5. N/A: not available. In this case the state remains unchanged.
6. If N=0 go to Buffer Program Confirm. Else (not =0) go to Buffer Program Load 2 (data load)
7. If N=0 go to Buffer Program Confirm in Erase suspend. Else (not =0) go to Buffer Program Load 2 in Erase suspend.
8. BEFP is allowed only when Status Register bit SR0 is set to '0'. BEFP is busy if Block Address is first BEFP Address. Any
other commands are treated as data.
104/108
M58LRxxxKC, M58LRxxxKD
Table 55.
Command interface state tables
Command interface states - lock table, next output state (1) (2)
Command Input
Current CI State
Lock/CR
Setup(3)(
60h)
Blank
Check
setup
(BCh)
OTP
Setup(3)
(C0h)
Blank
Check
confirm
(CBh)
P. E./C.
Illegal
Block Lock Block Lock- Set CR BEFP
Confirm
Down
Confirm Exit(4) Command Operation
(5)
Completed
(01h)
Confirm (2Fh) (03h) (FFFFh)
Program Setup
Erase Setup
OTP Setup
Program Setup in Erase
Suspend
BEFP Setup
BEFP Busy
Buffer Program Setup
Buffer Program Load 1
Status Register
Buffer Program Load 2
Output
Unchanged
Buffer Program Confirm
Buffer Program Setup in
Erase Suspend
Buffer Program Load 1 in
Erase Suspend
Buffer Program Load 2 in
Erase Suspend
Buffer Program Confirm in
Erase Suspend
Blank Check setup
Lock/CR Setup
Lock/CR Setup in Erase
Suspend
Status Register
Array
Status Register
105/108
Command interface state tables
Table 55.
M58LRxxxKC, M58LRxxxKD
Command interface states - lock table, next output state (continued)(1) (2)
Command Input
Current CI State
Lock/CR
Setup(3)(
60h)
Blank
Check
setup
(BCh)
OTP
Setup(3)
(C0h)
Blank
Check
confirm
(CBh)
P. E./C.
Block Lock Block Lock- Set CR BEFP
Illegal
Confirm
Down
Confirm Exit(4) Command Operation
(5)
Completed
(01h)
Confirm (2Fh) (03h) (FFFFh)
OTP Busy
Ready
Program Busy
Erase Busy
Buffer Program Busy
Program/Erase Suspend
Buffer Program Suspend
Status Register
Output Unchanged
Array
Output Unchanged
Program Busy in Erase
Suspend
Buffer Program Busy in
Erase Suspend
Program Suspend in Erase
Suspend
Buffer Program Suspend in
Erase Suspend
Blank Check busy
Illegal State
Output Unchanged
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command
address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode,
depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank.
The next state does not depend on the bank's output state.
2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. =
Program/Erase Controller.
3. If the P/EC is active, both cycles are ignored.
4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
5. Illegal commands are those not defined in the command set.
106/108
M58LRxxxKC, M58LRxxxKD
14
Revision history
Table 56.
Document revision history
Revision history
Date
Revision
Changes
09-Jul-2007
1
Initial release.
28-Feb-2008
2
Added 256 Mb density device to document to make the M58LRxxxKCD family
datasheet.
20-Mar-2008
3
Applied Numonyx branding.
107/108
M58LRxxxKC, M58LRxxxKD
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108/108