Audio Accessory ICs for Mobile Devices Mixer & Selector ICs with 16bit D/A Converter BU7858KN,BU7893GU No.10087EAT03 ●Description This LSI is mounted with stereo 16bit D/A Converter and suitable for higher sound quality and miniaturization of cellular phone with music play. BU7893GU has a 3D surround enhancement function and hence can play the wide-spreading stereo sound from stereo speakers that are arranged nearby. ●Features 1) Mounted with Stereo 16bit audio D/A converter 2) Compatible with Stereo analogue interface 3) Stereo headphone amplifier (16Ω) 4) Low-band corrective circuit in headphone amplifier 5) Volume that can adjust the gain 6) Flexible mixing function ●Applications Portable information & communication equipments such as cellular phone and PDA (Personal Digital Assistant) etc. Cellular phone with music play ●Line up matrix Function BU7858KN BU7893GU 16bit 16bit 16bit Right justified 18bit Right justified IIS 16bit Left justified 16bit Right justified IIS 3D surround enhancement function No Yes 3 band equalizer No Yes 16Ω driver 16Ω driver Yes No Built-in Built-in Yes (headphone only) Yes VQFN28 VCSP85H3 Stereo audio D/A converter Stereo audio interface format Stereo headphone amplifier Line output (600Ω driver) Headphone amplifier low-band correction function Click noise reduction function Package www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ●Absolute maximum ratings Parameter BU7858KN Power-Supply Voltage BU7893GU Symbol Ratings Unit VDD -0.3 ～ 4.5 V DVDDIO AVDD -0.3 ～ 4.5 DVDDCO -0.3 ～ 2.5 BU7858KN Power Dissipation 580 Pd BU7858KN mW -20 ～ +85 TOPR ℃ BU7893GU -30 ～ +85 BU7858KN Storage Temperature -55 ～ +125 TSTG ℃ BU7893GU *1 : *2: *1 700 *2 BU7893GU Operating Temperature V -50 ～ +125 5.8mW is decreased every 1℃ when using it over 25℃. (Mounted on the ROHM standard PCB ) 7.0mW is decreased every 1℃ when using it over 25℃. ●Operating conditions 【BU7858KN】 Parameter Power-Supply Voltage Symbol VDD Ratings Min. Typ. Max. 2.7 3.0 3.3 Unit V 【BU7893GU】 Parameter Symbol Ratings Unit Min. Typ. Max. AVDD 2.6 2.8 3.3 V Digital I/O Power-Supply Voltage DVDDIO DVDDCO 1.8 3.3 V Digital Core Power-Supply Voltage DVDDCO 1.62 1.8 1.98 V Analog Power-Supply Voltage www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ●Electrical characteristics 【BU7858KN】 Unless otherwise specified, Ta=25℃, AVDD=DVDD=3.0V ・Analog Parameter Symbol Limits Unit Conditions Min. Typ. Max. Idd3 - 2.3 3.7 mA DAC S/(N+D) SN+D - 85 - dB DAC S/N SNR - 92 - dB THDhp - 0.05 0.5 % PO - 10 - mW fin=1kHz, THD=10%, RL=16Ω VNO - -94 -80 dBV A-weighted SPO Maximum Output Level VOMAX1 2.0 - - VP-P fin=1kHz, THD≦1%, 10kΩLoad EXTO Maximum Output Level VOMAX2 2.0 - - VP-P fin=1kHz, THD≦1%, 600ΩLoad Current Consumption Headphone Amplifier Total Harmonic Distortion Headphone Amplifier Maximum Output Headphone Amplifier Output Noise Voltage 16Ω driver part and no signal fs=44.1kHz, fin=1kHz, 20kHz LPF, Vin=-0.5dBFS fs=44.1kHz, fin=1kHz , A-weighted, Vin=0dBFS fin=1kHz, 20kHz LPF, Vin=-10dBV ・Digital (DC) Parameter Symbol Limits Min. Typ. Max. Unit Conditions Digital Input Voltage “L” VIL - - 0.2 x DVDD V Digital Input Voltage “H” VIH 0.8 x DVDD - - V Digital Output Voltage “L” VOL - - 0.5 V Iol=-500µA Digital Output Voltage “H” VOH DVDD -0.5 - - V Ioh=500µA Input Leakage Current 1 IIN1 - - ±2 µA at 0V, 3V ・Audio Interface Parameter Symbol Limits Min. Typ. Max. Unit MCLKI Frequency fMCLK 4.096 - 18.432 MHz MCLKI Duty Ratio dMCLK 45 - 55 % LRCLK Frequency fs 16 - 48 kHz LRCLK Duty Ratio dLR 45 - 55 % BCLK Frequency fBCK 0.512 - 3.072 MHz BCLK Duty Ratio dBCK 45 - 55 % LRCLK edge to BCLK↑ Time tLRS 50 - - ns BCLK↑ to LRCLK Edge Time tSLR 50 - - ns Data Hold Time tSDH 50 - - ns Data Set-up Time tSDS 50 - - ns www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/24 Conditions 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU 【BU7893GU】 ･Whole Block Unless otherwise specified, Ta=25℃, DVDD_CORE=1.8V, DVDD_IO=1.8V, AVDD=2.8V, Digital input terminal is fixed with DVDD_IO “L” or “H” level, The gain settings of the audio paths are all 0dB, and no signal Limits Parameter Symbol Unit Conditions Min. Typ. Max. DVDD_CORE Stand-by Current (Core logic block) ISTCO - - 10 µA standby,CLKI = DVSS DVDD_IO Stand-by Current ISTIO - - 5 µA standby,CLKI = DVSS AVDD Stand-by Current ISTA - - 5 µA standby DVDD_CORE Operation Current IDDCO - 5 10 mA DVDD_IO Operation Current IDDIO - 0.1 1 mA AVDD Operation Current 1 (Analog melody) IDDA1 - 1.6 2.8 mA AVDD Operation Current 2 (Digital melody) IDDA2 - 6.0 10.0 mA BCLK,LRCLK = Input mode MCLK = L output ANAINL→MIX1→SPOL ANAINR→MIX2→SPOR SDI→MIX1→SPOL SDI→MIX2→SPOR TCXOI = 19.8MHz,fs = 44.1kHz ･DC Characteristic Parameter Symbol Terminal Limits Min. Max. Unit Conditions All output 1 terminal※ All output 1 terminal※ All input 2 terminal※ Vold 0 0.30 V Iol=+0.8mA Vohd DVDD_IO -0.30 DVDD_IO V Ioh=-0.8mA Vild1 -0.3 DVSS+0.5 V L Level Input Voltage 2 CLKI※3 Vild2 -0.3 ※3 V H Level Input Voltage 1 All input 2 terminal※ Vihd1 DVDD_IO -0.5 H Level Input Voltage 2 CLKI※3 Vihd2 ※3 DVDD_IO +0.3 DVDD_CORE +0.3 Iild -1 1 µA Iihd1 -1 1 µA L Output Voltage H Output Voltage L Level Input Voltage1 L Level Input Current H Level Input Current 1 All input 2 terminal※ All input terminal※2 V V H Level Input Current 2 CLKI※3 Iihd2 -1 1 µA Output OFF Current Hi-Z terminal※4 Iozd -10 10 µA Input terminal voltage is DVSS Input terminal voltage is DVDD_IO Input terminal voltage is DVDD_CORE ※1 : They also contain interactive terminals that are set output state. ※2 : They also contain interactive terminals that are set input state. ※3 : Please connect 100pF coupling capacitor and input 0.5VP-P or more when you input through coupling capacitor. (In address 15h CLKSEL1=0, CLKSEL0=1) ※4 : At interactive terminals of input state or three-state terminals of output-disable state ・Audio Path(MIX) Unless otherwise specified, Ta=25℃, AVDD=2.8V, reference input level=-6dBV, f=1kHz, A-weighted, path gain =0dB Parameter Symbol Limits Min. Typ. Max. Unit Conditions ANAL_V Volume Setting GDACL -11 - +3 dB 1dB step ANAR_V Volume Setting GDACR -11 - +3 dB 1dB step www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 4/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ・Audio Path (SP PREamp) Unless otherwise specified,Ta=25℃,AVDD=2.8V, Reference input level =-6dBV, f=1kHz, A-weighted, path gain =0dB, RL=33kΩ Limits Parameter Symbol Unit Min. Typ. Max. THD+N THDSP - -70 -60 dB Output Noise Voltage VNOSP - -90 -80 dBV Mute Level MLSP - -90 -80 dB Conditions 20kHz LPF At no a signal 1kHz BPF ・Audio Path (HP amp) Unless otherwise specified, Ta=25℃, AVDD=2.8V, reference input level =-6dBV, f=1kHz, A-weighted, path gain =0dB, RL=16Ω Limits Parameter Symbol Unit Min. Typ. Max. Conditions THD+N THDHP - -65 -55 dB 20kHz LPF Output Noise Voltage VNOHP - -90 -80 dBV At no signal The Maximum Output Power POHP 10 - - mW THD=10%,16Ω load Channel Separation CSHP - -80 -70 dB Vo=-14dBV,1kHz BPF Mute Level MLHP - -90 -80 dB 1kHz BPF HPL_V Volume Setting 1 GA1HPL -48 - 0 dB 2dB step HPL_V Volume Setting 2 GA2HPL -42 - +6 dB 2dB step HPR_V Volume Setting 1 GA1HPR -48 - 0 dB 2dB step HPR_V Volume Setting 2 GA2HPR -42 - +6 dB 2dB step ・3D Surround, Equalizer, and Audio DAC Unless otherwise specified, Ta=25℃, AVDD=2.8V, BCLK=64fs, LRCLK=256fs, f=1kHz, path gain=0dB, SPOL/SPOR output, SPOL/SPOR= no load, output=0dBFS Limits Parameter Symbol Unit Conditions Min. Typ. Max. Full-scale Amplitude S/N1 (A-Weighted) VMAX 1.40 1.68 2.00 VP-P 0.6×AVDD DACsn1 70 75 - dB THD+N1 (20kHz LPF) DACthd1 - -70 -60 dB fs=8,11.025kHz THD+N2 (20kHz LPF) DACthd2 - -75 -65 dB fs=16,22.05,32,44.1,48kHz ・Audio I/F Format Unless otherwise specified, Ta=25℃, DVDD_IO=1.62～3.3V, DVDD_CORE=1.62～1.98V Limits Parameter Symbol Unit Min. Typ. Max. BCLK Output Frequency LRCLK Output Frequency SDI Set-up Time SDI Hold Time FBCKO 0.512 - 3.072 MHz FLRCKO 8 - 48 kHz tSDSU 100 - - nsec tSDH 100 - - nsec ・PLL Unless otherwise specified, Ta=25℃, AVDD=2.8V, BCLK = no load Limits Parameter Symbol Min. Typ. Max. Unit PLL Lock-up Time Tlock1 - - 10 msec PLL Jitter Tjitter1 - 200 - psec www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 5/24 Conditions 64fs Conditions BCLK terminal,fVCO=65.536MHz 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ●Reference Data 【BU7858KN】 8.0 6.0 4.0 2.0 CIRCUIT CURRENT : ICC (mA) 12.0 CIRCUIT CURRENT : ICC (mA) 10.0 8.0 6.0 4.0 2.0 0.0 0.0 2.0 2.5 3.0 3.5 4.0 SUPLLY VOLTAGE : VDD(V) 4.5 Fig.1 Stand-by Current 4.0 3.0 2.0 1.0 2.5 3.0 3.5 4.0 SUPLLY VOLTAGE : VDD(V) 2.0 4.5 Fig.2 16bit D/A Converter Operation Current -30 -30 -40 -40 -40 -50 -50 -50 -60 -60 -60 -70 -80 -90 -70 -80 -90 -80 -90 -100 -100 -110 -110 -110 -120 -110 -120 -110 -10 -30 -120 -90 -70 -50 -30 INPUT LEVEL : VIN(dBFS) -10 10 100 1000 10000 100000 INPUT SIGNAL Freq : FI N(Hz) Fig.5 16bit D/A Converter Total Harmonic Distortion (Rch) Fig.4 16bit D/A Converter Total Harmonic Distortion (Lch) 4.5 -70 -100 -90 -70 -50 -30 INPUT LEVEL : VIN(dBFS) 2.5 3.0 3.5 4.0 SUPLLY VOLTAGE : VDD(V) Fig.3 Headphone Amplifier Operation Current -30 THD+N (dB) THD+N (dB) 5.0 0.0 2.0 THD+N (dB) STAND BY CURRENT : ICC ( μA) 6.0 14.0 10.0 Fig.6 16bit D/A Converter Total Harmonic Distortion (Lch) 100.00 100.00 10.00 10.00 -40 -70 -80 -90 THD+N (%) -60 THD+N (%) THD+N (dB) -50 1.00 0.10 0.10 -100 1.00 -110 -120 10 100 1000 10000 INPUT SIGNAL Freq : FIN(Hz) 0.01 -100 100000 100.00 100.00 10.00 10.00 1.00 0 Fig.8 Headphone Amplifier Total Harmonic Distortion (HP_L) THD+N (%) THD+N (%) Fig.7 16bit D/A Converter Total Harmonic Distortion (Rch) -80 -60 -40 -20 INPUT LEVEL : VIN(dBV) 0.01 -100 -80 -60 -40 -20 INPUT LEVEL : VIN(dBV) 0 Fig.9 Headphone Amplifier Total Harmonic Distortion (HP_R) 1.00 0.10 0.10 0.01 -100 -80 -60 -40 -20 INPUT LEVEL : VIN(dBV) 0 Fig.10 SPO Total Harmonic Distortion www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 0.01 -100 -80 -60 -40 -20 INPUT LEVEL : VIN(dBV) 0 Fig.11 EXTO Total Harmonic Distortion 6/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU 5.0 5.0 4.5 4.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 CIRCUIT BY CURRENT : ICC ( μA) 5.0 STAND BY CURRENT : ICC ( μA) STAND BY CURRENT : ICC ( μA) 【BU7893GU】 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1.6 1.7 1.8 1.9 2.6 2.0 2.8 3.0 3.2 SUPLLY VOLTAGE : AVDD(V) SUPLLY VOLTAGE : DVDD_CORE(V) 1.7 1.6 1.5 2.6 2.8 3.0 3.2 SUPLLY VOLTAGE : AVDD(V) 4.0 3.5 3.0 2.5 1.0 0.5 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 1.7 1.8 1.9 2.0 SUPLLY VOLTAGE : DVDD_CORE(V) 2.6 Fig.16 DVDD_CORE Operation Current (digital melody) 0.0 -10.0 -10.0 -20.0 -20.0 -20.0 -30.0 -30.0 -30.0 -60.0 THD+N (dB) 0.0 -50.0 -50.0 -60.0 -60.0 -70.0 -80.0 -80.0 -80.0 -90.0 -100 -90.0 -100 -40 -20 0 -90.0 -80 INPUT LEVEL (dBFS) -60 -40 -20 INPUT LEVEL (dBFS) 0 10 0.0 100 1000 10000 100000 INPUT SIGNAL FREQUENCY (Hz) Fig.19 16bit D/A Converter Total Harmonic Distortion 1kHz (SPOR) Fig.18 16bit D/A Converter Total Harmonic Distortion 1kHz (SPOL) 3.4 -50.0 -70.0 -60 3.2 -40.0 -70.0 -80 3.0 Fig.17 AVDD Operation Current (digital melody) -10.0 -40.0 2.8 SUPLLY VOLTAGE : AVDD(V) 0.0 -40.0 1.7 1.8 1.9 2.0 SUPLLY VOLTAGE : DVDD_CORE(V) 3.0 1.6 THD+N (dB) THD+N (dB) 4.5 3.4 Fig.15 AVDD Operation Current (Analog melody) 1.5 4.0 2.0 1.4 2.0 Fig.14 DVDD_CORE Operation Current (Analog melody) CIRCUIT CURRENT : ICC (mA) CIRCUIT CURRENT : ICC (mA) CIRCUIT CURRENT : ICC (mA) 1.8 2.5 1.6 5.0 1.9 3.0 3.4 Fig.13 AVDD Standby Current Fig.12 DVDD_CORE Standby Current 2.0 3.5 0.0 0.0 0.0 4.0 Fig.20 16bit D/A Converter Total Harmonic Distortion (SPOL) 100.00 100.0 10.00 10.0 -30.0 THD+N (%) THD+N (dB) -20.0 -40.0 -50.0 -60.0 THD+N (%) -10.0 1.00 0.10 -70.0 1.0 0.1 -80.0 -90.0 10 100 1000 10000 100000 INPUT SIGNAL FREQUENCY (Hz) Fig.21 16bit D/A Converter Total Harmonic Distortion (SPOR) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 0.01 -100.0 -80.0 -60.0 -40.0 -20.0 INPUT LEVEL (dBV) 0.0 Fig.22 Headphone Amplifier Total Harmonic Distortion (HPOL / HPOR) 7/24 0.0 -100 -80 -60 -40 -20 0 INPUT LEVEL (dBV) Fig.23 Speaker Preamp Total Harmonic Distortion (SPOL / SPOR) 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ●Block diagram and pin assignment 【BU7858KN】 DVDD PLLC SW1 Digital Audio I/F 16bit DAC Digit al ATT SPO SP Amp ATT3 + LPF 16bit DAC + - MIXSEL3 ATT SDTI + MIXSEL2 ATT1 MCLKI ATT2 + SW2 RING LRCLK AVSS MIXSEL1 RXI BCLK AVDD PLL BCLK MCLKO DVSS 16Ω ATT4 + - MIXSEL4 HP_R CA_R LPF MEL_R EXTO 600Ω 16Ω ATT5 HP_L CA_L ATT MEL_L EXTI BIAS Serial Control CVCOM NRST SCLK SDATA CSTEP SCS CSTART EXTI SPO EXTO AVDD AVSS HP_L CA_L Fig.24 BU7858KN Block Diagram 21 20 19 18 17 16 15 24 12 CVCOM RXI 25 11 CSTART PLLC 26 10 CSTEP MCLKO 27 9 NRST MCLKI 28 8 NCS 1 2 3 4 5 6 7 SDATA RING SCLK 13 HP_R DVSS 23 DVDD MEL_R BCLK 14 CA_R LRCLK 22 SDTI MEL_L Fig.25 BU7858KN Pin Assignment (TOP VIEW) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU 【BU7893GU】 Serial I/F 1μF 0.1μF CSTEP 1μF RSTB SCLK SO SIO CSB CPOP COMOUT COMIN DVSS DVDD_IODVDD_CORE AVSS AVDD VREF SPI CPOP 1μF CCL RX VOL EXT VOL DACL -6dB CLKI 100μ 16Ω DACR + 19.2MHz/ 19.68MHz/ 19.8MHz 6800p HPOL + VOL RX -6dB PLLC HPOR EXT VOL DACL PLL + Stereo Analog Interface (From Melody LSI) ANAINL ANAINR 100μ 16Ω 6800p CCR DACR RX MCLK DACL LRCLK BCLK SDI Sonaptic 3D 8Ω SP Amp 8Ω RX -6dB DAI SP Amp DACR DAC + Stereo PCM Interface (MP3,AAC,etc) SPOL EXT Equalizer SPOR EXT DACL -6dB DACR DAC Fig.26 BU7893GU Block diagram 1 2 3 4 5 6 A TEST3 HPOR HPOL CPOP SPOL TEST4 B CCR RSTB DVSS CCL SPOR COMIN C SCLK SO CSTEP AVSS D SIO MCLK COMOUT ANAINR E CSB PLLC AVDD DVDD_CORE SDI ANAINL F TEST2 CLKI DVDD_IO BCLK LRCLK TEST1 ( TOP VIEW ) Fig.27 BU7893GU Ball Assignment www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 9/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ●Digital interface of 16 bit audio D/A converter 16bit audio D/A converter equipped with this series can be used with the following audio format. 【BU7858KN】 1) MSB first 16bit data (Right justified) LRCLK(fs) Rch Lch BCLK(64fs） 2 SDTI 1 0 Don’t 15 Care 14 13 12 11 3 4 2 1 0 Don’t Care 15 14 13 12 11 3 4 2 1 0 15:MSB, 0:LSB 2) MSB first 18bit data (Right justified) LRCLK(fs) Rch Lch BCLK(64fs） 2 SDTI 1 0 Don’t 17 Care 16 15 14 11 3 4 2 1 0 Don’t Care 17 16 15 14 11 4 3 2 1 0 17:MSB, 0:LSB 3) IIS mode 18bit data (Left justified) LRCK(fs) Lch Rch BCLK(64fs) Don’t Care SDTI 17 16 4 3 2 1 Don’t 0 Care 17 4 16 3 2 1 0 Don’t Care 17 16 17:MSB, 0:LSB 4) IIS mode 16bit data (BCLK=32fs) LRCLK(fs) Lch Rch BCLK(32fs) SDTI 2 1 0 15 14 13 12 11 10 9 8 7 6 3 2 1 0 15 14 13 12 11 10 9 8 7 6 3 2 1 0 15 14 13 15:MSB, 0:LSB Fig.28 AUDIO I/F FORMAT (BU7858KN) BU7858KN is provided with a mode that generates MCLK (Master Clock) by using the built-in PLL, so it is possible to make a D/A converter operate even if the clocks are only BCLK (64fs/32fs), LRCLK (fs). The PLL generates MCLK (Master Clock), which is necessary for driving of D/A converter, from BCLK (Bit Clock). Please connect a capacitor (PLLC) for the filter with DVSS. Moreover, please place the capacitor nearest DVSS of IC in order to reduce the noise interference. Then it is possible to monitor the master clock that is generated internally from MCLKO, which is after all the monitor terminal, and hence does not guarantee drivability and phase-margin. Please tie the MCLKI terminal to DVSS when PLL is used. And please tie the PLLC terminal to DVSS when PLL is not used. Moreover, it is not necessary to set the “PLLPDN” and “SMPR” when PLL is not used. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 10/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU 【BU7893GU】 1. MSB first left justified format Lch LRCLK 0 1 2 3 Rch 13 14 15 16 17 18 29 30 31 0 1 2 13 14 15 16 17 18 3 29 30 31 0 BCLK SDI 15 14 13 2 1 0 Don't care 15 14 13 Don't care 2 1 0 Don't care Don't care 15 2. MSB first right justified format SDI 15 14 13 Don't care 2 1 0 Don't care 15 14 13 Don't care 2 1 0 Don't care 3. IIS format LRCLK Lch 0 1 2 3 4 Rch 14 15 16 17 18 19 30 31 0 1 2 3 4 14 15 16 17 18 19 30 31 0 BCLK SDI Don't care 15 14 13 2 1 0 Don't care Don't care 15 14 13 2 1 0 Don't care Don't care Fig.29 AUDIO I/F Format (BU7893GU) ●3D Surround enhancement function 【BU7893GU】 Even under the circumstances of adjacent arrangement of stereo speakers, the wide-spreading acoustic effect can be achieved because of the output resulting from the digital audio input to which the 3D surround effect has been applied. Moreover, the stereo sound at the time of audio recording can also be played truly. Please tell us about the parameter setting when you use this function. ●Low-band corrective circuit In the headphone output terminals (HP_L, HP_R or HPOL, HPOR), there is a low-band corrective circuit, which corrects the low-band attenuation. 200kΩ CCHPx CA_X or CCX 200kΩ 100kΩ CL + + HP_X or HPOX OUTPUT RL Fig.30 BU7858KN & BU7893GU Headphone Output Equivalent Circuit Low-band cut-off frequency Low-band boost frequency Boost gain fC= 1/(2･π･CL･RL) fBOOST = 1/(2･π･CCHPx･200kΩ) ABOOST = 20･log((200 kΩ+1/(2･π･f･CCHPx))/100 kΩ) (the maximum low-band boost is 6dB) For parameter setting, determine the output coupling capacitance CL and the headphone impedance RL before calculating the low-band cut-off frequency fC. Then determine CCHPx so that the low-band cut-off frequency fC is roughly in agreement with the low-band boost frequency fBOOST. The recommended parameter setting of BU7858KN and BU7893GU is CCHPx = 6800pF at the time of CL = 100µF and RL = 16Ω. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU The frequency characteristic (theorical value) when the recommended constants are used is shown below. 10 5 Amplifier output 0 -5 After correction Gain [dB] -10 Before correction -15 -20 -25 -30 -35 -40 1 10 100 1000 10000 100000 Frequency [Hz] Fig.31 Low-band corrective circuit Frequency characteristic ●CPU Interface BU7858KN and BU7893GU can be controlled by using CPU interface. 【BU7858KN】 NCS tch tcyc tcs SCLK tds SDATA A7 tdh A6 A5 A4 A3 A2 A1 A0 D6 D7 Fig.32 CPU I/F Timing Chart 1 D5 D4 D3 D2 D1 D0 (BU7858KN) After the falling edge of NCS, SDATA inputs are settled by 16 clock of SCLK, and data is written in the rising edge of NCS. The data format is “16bit right justified”. CPU interface is that 1Byte=16bit. It is absolutely necessary to insert the interval of NCS=”H” between first Byte and Second Byte because it is not compatible with continuous data transmission. For the following th, please wait the time more than 1 SCLK Clock. (th≧tcyc) th NCS SCLK SDATA Fig.33 CPU I/F Timing Chart 2 (BU7858KN) ・AC Characteristics Ta=25℃, AVDD=DVDD=3.0V Parameter Symbol Limits Min. Typ. Max. 250 - - Unit SCLK Width tcyc SDATA Input Hold Time tdh 50 - - ns SDATA Input Set-up Time tds 50 - - ns NCS Set-up Time tcs 50 - - ns NCS Hold Time tch 50 - - ns Conditions ns *It is recommended to use exclusive lines for CPU interface. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 12/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU 【BU7893GU】 ・Timing Chart SCLK Thc Tsc AD[6] SIO AD[5] AD[4] AD[0] Direction DT[7] DT[6] DT[1] DT[0] DT[1] DT[0] SEL Tscss When direction is "1": Write operation When direction is "0": Read operation ・Write Operation SCLK SIO AD[6] AD[4] AD[5] DT[7] AD[0] DT[6] Direction”H” SEL ・Read Operation (mode 1): SO_ENABLE (bit0 at register address 14h)=0 SCLK Tsd SIO AD[6] AD[5] AD[4] AD[0] Hi-Z DT[6] DT[7] DT[1] DT[0] Direction”L” Output data SEL ・Read Operation (mode 2): SO_ENABLE (bit0 at register address 14h)=1 SCLK Tsd SIO AD[6] AD[5] AD[4] AD[0] Direction”L” SO DT[7] Hi-Z DT[6] DT[5] DT[1] DT[0] Hi-Z Output data SEL Fig.34 CPU I/F Timing Chart (BU7893GU) DVDD_IO=1.62～3.3V, Ta=-30～+85℃ Parameter Symbol Limits Unit Min Typ Max Ncha 16 - - bit FSCLK - - 15 MHz SCLK ‘L’ Pulse Width Tlsclk 25 - - ns SCLK ‘H’ Pulse Width Thsclk 25 - - ns SCLK-SEL Set-up Time Bit Length SCLK Input Frequency Tscss 10 - - ns Data Set-up Time Tsc 10 - - ns Data Hold Time Thc 10 - - ns Delay Time of Data Output Tsd - - 30 ns Conditions MSB first SIO: Time from SCLK falling edge SO : Time from SCLK rising edge *It is recommended to use exclusive lines for CPU interface. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ●I2C Interface 【BU7893GU】 2 In the BU7893GU, the LSI can be controlled by using I C interface. 2 The device’s address (slave address) is "1100011(63h)". It is based on the Philips I C-BUS V2.1’s fast-mode, the maximum transfer rate of a bit is 400kbps. A7 A6 A5 A4 A3 A2 A1 W/R 1 1 0 0 0 1 1 0/1 I2C Slave addresses ・Bit Transfer A data is transferred during the HIGH period of the clock . The data on the SIO line must be stable during this period. The HIGH or LOW state of the data line can only change when the clock signal on the SCLK line is LOW. When SCL is H and SDA changes, the START conditions or the STOP condition is generated, and it is interpreted as the control signal. SIO SCLK SIO is stable. Valid Data SIO is possible to change ・START & STOP Conditions 2 When SIO and SCLK are “H”, there is no data transfer performed on the I C bus. A HIGH to LOW transition on the SIO line while SCLK is HIGH is one such unique case. This situation indicates a START condition (S). A LOW to HIGH transition on the SIO line while SCLK is HIGH defines a STOP condition (P). SIO SCL S P START conditions STOP conditions The consecutive START and STOP conditions are acceptable. ・Acknowledge After START condition, 8 bits of data is transferred at a time. The transmitter releases the SIO line, and the receiver returns the Acknowledge signal by assuming SIO to be “L”. SIO output by the transmitter Non-Acknowledge SIO output by the receiver Acknowledge SCLK S 1 www.rohm.com 8 9 Clock pulse for Acknowledge START condition © 2010 ROHM Co., Ltd. All rights reserved. 2 14/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ・Writing Protocol The write protocol is shown below. The register address is transferred in a byte after the slave address and write command are transferred. The third byte writes the data into the internal register that is indicated by the second byte. After that, the register address is incremented on automatically (when the register address is between 00h and 16h). However, when the register address reaches 16h, the register address does not change with the next byte transfer, rather, it accesses the same register address (16h). The register address is incremented after transfer completion. S 1 1 0 0 0 1 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A Slave address Register address D7 D6 D5 D4 D3 D2 D1 D0 A Data Data Register address Increment R/W=0(Write) from master to slave P Register address Increment A=Acknowledge A=Non-Acknowledge S=START condition P=STOP condition from slave to master ・Reading Protocol It reads from the next byte after writing the slave address and R/W bit. The read register is the following address accessed at the end. After that, the data of the address incremented is read out. The register addresses are incremented after transfer completion. S 1 1 0 0 0 1 1 1 A D7 D6 D5 D4 D3 D2 D1 D0 A Slave address D7 D6 D5 D4 D3 D2 D1 D0 A P Data Data Register address Increment Register address Increment R/W=1(Read) A=Acknowledge A=Non-Acnkowledge S=START condition P=STOP condition from master to slave from slave to master ・Combined Reading Protocol After specifying an internal address, it reads by generating resending start conditions and changing the direction of data transfer. Afterwards, data from incremented addresses is read. The register addresses are incremented after transfer completion. Compound writing is possible by writing R/W=0 after resending start condition. S 1 1 0 0 0 1 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A Sr 1 Slave address Register address 1 0 0 Data 1 A D7 D6 D5 D4 D3 D2 D1 D0 A P Data Register address Increment from slave to master www.rohm.com 1 R/W=1 ( Read) D7 D6 D5 D4 D3 D2 D1 D0 A © 2010 ROHM Co., Ltd. All rights reserved. 1 Slave address R/W=0 ( Write) from master to slave 0 15/24 Register address Increment A=Acknowledge A=Non-acknowledge S=START condition P=STOP condition Sr=Repeated START condition 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ・Timing Diagram （Repeated） START conditions t SU;STA BIT 7 BIT 6 Acknowledge STOP condition t LOW t HIGH 1/fSCLK SCL SIO t BUF t HD;STA tSU;DAT t HD;DAT tSU;STO 2 Fig.35 I C Timing Diagram DVDD_IO=1.62～3.3V, Ta=-30～+85℃ Parameter Symbol Hold Time at Start Condition tHD;STA Min 0.6 Limits Typ - Max - µsec Unit SCLK “H” Level Time tHIGH 0.6 - - µsec SCLK “L” Level Time tLOW 1.3 - - µsec Set-up Time for Repeated Start Condition tSU;STA 0.6 - - µsec Data Hold Time tHD;DAT 0 - 0.9 µsec Data Set-up Time tSU;DAT 100 - - nsec Set-up Time for Stop Condition tSU;STO 0.6 - - µsec tBUF 1.3 - - µsec Bus Release Time between Stop Condition and Start Condition Conditions ●Pin function 【BU7858KN】 Power Equivalent Circuit Diagram Audio DAC Serial Data Input DVDD A I Audio DAC LR Clock DVDD A BCLK I Audio DAC BIT Clock DVDD A 4 DVDD - Digital Power Supply - - 5 DVSS - Digital Ground DVDD - 6 SCLK I Serial Clock for CPU Interface DVDD A 7 SDATA I Serial Data for CPU Interface DVDD A 8 NCS I Serial Chip Selection for CPU Interface DVDD A 9 NRST I Reset Input DVDD A 10 CSTEP - Capacitor Connection Terminal for Pop Noise Reduction AVDD C 11 CSTART - Capacitor Connection Terminal for Pop Noise Reduction at Start-up AVDD G 12 CVCOM - Capacitor Connection Terminal for Internal Reference Voltage Output AVDD G 13 HP_R O Headphone Amplifier Output R-ch AVDD H 14 CA_R - Low-band Correction Capacitor for Headphone Amplifier R-ch AVDD C No. Pin Name I/O 1 SDTI I 2 LRCLK 3 Pin Function www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. L: Reset 16/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU Power Equivalent Circuit Diagram Low-band Correction Capacitor for Headphone Amplifier L-ch AVDD C O Headphone Amplifier Output L-ch AVDD H AVSS - Analog Ground - - 18 AVDD - Analog Power Supply - - 19 EXTO O 600Ω Driver Output AVDD H 20 SPO O Line Output for Speaker AVDD H 21 EXTI I External Input AVDD D 22 MEL_L I Melody Input L ch AVDD D 23 MEL_R I Melody Input R ch AVDD D 24 RING I RING Input AVDD E 25 RXI I RXI Input AVDD D 26 PLLC - Capacitor Connection Terminal for PLL Loop Filter DVDD C 27 MCLKO O Master Clock Output DVDD B 28 MCLKI I Master Clock Input DVDD A No. Pin Name I/O 15 CA_L - 16 HP_L 17 Pin Function PAD PAD A B C 100kΩ (TYP) 200kΩ (TYP) PAD PAD D PAD E F PAD G PAD PAD H Fig.36 Equivalent Circuit Diagrams (BU7858KN) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 17/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU 【BU7893GU】 No. Matrix Pin Name No. I/O Pin Function Terminal Conditions at Reset Power Equivalent Circuit Diagram 1 E3 AVDD - Analog Power Supply - AVDD - 2 C6 AVSS - Analog Ground - AVDD - 3 E6 ANAINL I DAC L-ch Input - AVDD G 4 D6 ANAINR I DAC R-ch Input - AVDD G 5 A3 HPOL O Headphone Amplifier Output L-ch Pull-down AVDD H 6 A2 HPOR O Headphone Amplifier Output R-ch Pull-down AVDD H 7 B4 CCL I Pull-down AVDD I 8 B1 CCR I Pull-down AVDD I 9 A5 SPOL O L-ch Line Output for Speaker Pull-down AVDD H 10 B5 SPOR O R-ch Line Output for Speaker Pull-down AVDD H 11 D5 COMOUT O Analog Reference Voltage Output Hi-Z AVDD J 12 B6 COMIN I Analog Reference Voltage Input Hi-Z AVDD K 13 A4 CPOP Hi-Z AVDD L 14 C5 CSTEP Hi-Z AVDD L 15 E2 PLLC - AVDD L 16 E4 DVDD_CORE - Digital Core Power Supply - DVDD_CORE - 17 F3 DVDD_IO - Digital IO Power Supply - DVDD_IO - 18 B3 DVSS - Digital Ground - DVDD_IO, DVDD_CORE - 19 F2 CLKI I PLL Reference Clock Input (19.2/19.68/19.8 MHz) - DVDD_IO D 20 B2 RSTB I Reset Input L: Reset - DVDD_IO A 21 E1 CSB I CPU Interface Select Pin 2 (L :CPU I/F DVDD_IO : I C I/F) - DVDD_IO B 22 C1 SCLK I CPU Interface Clock - DVDD_IO A 23 D1 SIO Hi-Z DVDD_IO F 24 C2 SO Hi-Z DVDD_IO E 25 E5 SDI Hi-Z DVDD_IO C 26 F4 BCLK I/O Audio DAC Bit Clock (Input State at Reset) Hi-Z DVDD_IO E 27 F5 LRCLK I/O Audio DAC LR Clock (Input State at Reset) Hi-Z DVDD_IO E 28 D2 MCLK I/O Audio DAC Master Clock (Input State at reset ) Hi-Z DVDD_IO E 29 F6 TEST1 I Pull-down DVDD_IO C 30 F1 TEST2 I Pull-down DVDD_IO C 31 A1 TEST3 - DVDD_IO E 32 A6 TEST4 - AVDD - Low-band Correction Capacitor for Headphone Amplifier L-ch Low-band Correction Capacitor for Headphone Amplifier R-ch Capacitor Connection Terminal for Pop Noise Reduction Capacitor Connection Terminal I/O for Noise Reduction during Volume Change Capacitor Connection Terminal I/O for PLL Loop Filter I/O CPU Interface Data Input/Output (at Reset Input) CPU Interface Data Output I/O (connected to DVSS when not in use) I/O I Audio DAC Digital Data Input Test Pin (connected to DVSS during normal operation) Test Pin (connected to DVSS during normal operation) I/O Test Pin (released during normal operation) I Test Pin (released during normal operation) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 18/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU Schmitt Trigger IN IN PAD A IN PAD B PAD C Schmitt Trigger IN PAD INOUT PAD E D IN OUT IN PAD H G OUT J PAD I IN/OUT IN/OUT + - PAD F + PAD INOUT PAD PAD PAD L K Fig.37 Equivalent Circuit Diagrams (BU7893GU) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 19/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ●Recommended sequence 【BU7858KN】 Mode setting Flow Power Supply ON Power Supply OFF Reference Voltage ON (VCOM=1) Stand-by mode Input Path Setting Mixing Path Setting RESET NRST=0 or PLLPDN=0, VCOM=0 *1 Analog Power ON (PDN=1) PLL Setting (PLLPDN=1) (Using PLL) DAC Setting (Using DAC) HPAMP RESET (HPRST=0) *2 Analog Power OFF (PDN=0) PLL OFF (PLLPDN=0) (Using PLL) *1 DAC MUTE OFF (Using DAC) DAC MUTE ON (Using DAC) HPAMP RESET Lifting (Using HPAMP) HPAMP MUTE ON (Using HPAMP) Play *1 : When the analog path setting is not changed (Repeated play) *2 : When the power supply OFF, after playing Fig.38 BU7858KN Recommended Sequence Flow Chart www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 20/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU 【BU7893GU】 SAMPLE# AUDIO PATH+ AUDIO DAC BLOCK SETTING SEQUENCE After powering up and canceling reset, set paths according to the sequence shown as below: (1) Start up reference voltage Start up the reference voltage in the REF_PWR register (00h). To start up the VREF block fast, set the REF_ON bit (bit-0) and BST_ON bit (bit-1) to "1" simultaneously. starting up the reference voltage startup, set just the BST_ON bit (bit-1) to "0". After (2) Start up Audio DAC When using Audio DAC (2-1) Enable PLL block clock input and start up PLL Start up the power supply of the PLL and enable clock input to the PLL in the PLL_PWR register (16h). Set REF1_ON (bit-1) and PLL_ON (bit-0) to "1" simultaneously. (2-2) Caution concerning interim between starting up PLL block and starting up Audio DAC block After starting up the power supply of the PLL in the PLL_PWR register (16h), wait 10 msec before starting up the Audio DAC. (2-3) Start up Audio DAC block Start up the power supply of the Audio DAC in the DAC SET4 register (13h). Set DAC_ON (bit-5) and DAC_RSTB (Bit-4) to "1". (2-4) Set 3D surround and Equalyzer parameter Please tell us about the parameter setting when you use this function. (3) Start up analog input amplifier to use Start up the power supply of the input amplifier and input volume in the IAMP_PWR register (01h). (4) Set input volume Set the input volume in the IVR_1 register (09h). (5) Set mixing path Make mixing path settings in the MIX1 register (02h), MIX2 register (03h), MIX3 register (04h), and MIX4 register (05h). (6) Set startup noise reduction sequence Set the sequence time in the POP_TM register (07h). (7) Set click noise reduction sequence Set the sequence time in the OVR_TM register (0Ah). (8) Set output path Enable the relevant output path in the PATH_CNT register (06h). (9) Set output volume Set output volume values =0x18(-48dB) in the OVR_1 register (0Bh). (10) Ramp up output driver amplifier Ramp up the output driver amplifier in the DRV_PWR register (08h). (11) Caution concerning interim between ramping up output driver amplifier and canceling mute After setting the DRV_PWR register (08h), wait the sequence time set in the POP_TM register (07h) before canceling mute. (12) Cancel mute Cancel mute state of the output driver amplifier in the DRV_MT register (0Ch). (13) Caution concerning interim between canceling mute and setting output volume After setting the DRV_MT register (0Ch), wait the sequence time that is set in the OVR_TM register (0Ah) before subsequently setting output volume. (14) Set output volume Set output volume values in the OVR_1 register (0Bh). www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 21/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU Path Modification Sequence (1) Set output mute Put the output driver amplifier in a mute state by setting the DRV_MT register (0Ch). (2) Caution concerning interim between setting mute and ramping down output driver amplifier After setting the DRV_MT register (0Ch), wait the sequence time that is set in the OVR_TM register (0Ah) before subsequently ramping down the output driver amplifier. (3) Ramp down output driver amplifier Ramp down the output driver amplifier by setting the DRV_PWR register (08h). (4) Set AUDIO DAC (Refer to P.20) (5) Modify input path, mixing path, output path (Refer to P.20) (6) Ramp up output driver amplifier Ramp up output driver amplifier in the DRV_PWR register (08h) After ramping down output driver at (3), wait the sequence time that is set in the POP_TM register (07h) before subsequently ramping up. (7) Caution concerning interim between ramping up output driver amplifier and canceling mute After setting the DRV_PWR register (08h) at (6), wait the sequence time that is set in the POP_TM register (07h) before subsequently canceling mute. (8) Cancel mute Cancel output mute in the DRV_MT register (0Ch). Power-Down Sequence (1) Set output volume Set output volume values =0x18(-48dB) in the OVR_1 register (0Bh). (2) Caution concerning interim between setting output volume and setting mute After setting the OVR_1 register (0Bh), wait the sequence time that is set in the DRV_MT register (0Ch) before subsequently setting mute. (3) Put the output driver amplifier in a mute state by using the DRV_MT register (0Ch). (4) Caution concerning interim between setting mute and ramping down output driver amplifier After setting the DRV_MT register (0Ch), wait the sequence time that is set in the OVR_TM register (0Ah) before subsequently ramping down the output driver amplifier. (5) Ramp down output driver amplifier Ramp down the output driver amplifier in the DRV_PWR register (08h). (6) Power down AUDIO DAC When using AUDIO DAC (6-1) Power down AUDIO DAC block Power down the AUDIO DAC according to the DAC SET4 register (13h). Set DAC_ON (bit-5) and DAC_RSTB (Bit-4) to "0". (6-2) Mask clock input and power down PLL block Power down the PLL and mask clock input to the PLL according to the PLL_PWR register (16h). Set REF_ON (bit-1) and PLL_ON (bit-0) to "0" simultaneously. (7) Input reset Put a reset state by using RSTB pin input. (8) Power down www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 22/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ●Notes for use 1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. 2) Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. 3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. 4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. 5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. 6) Short circuit between terminals and erroneous mounting In order mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs, Erroneous mounting can break down the ICs. Furthermore, if a shout circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. 7) Operation in a strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. 8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. 9) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals, a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. 10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. 11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the normal capacitance due to DC bias and changes in the capacitance due to temperature, etc. 12) No Connecting input terminals In terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state brings the inside gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And unstable state can also causes unexpected operation of IC. So unless otherwise specified, input terminals not being used should be connected to the power supply or GND line. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 23/24 2010.09 - Rev.A Technical Note BU7858KN,BU7893GU ●Ordering part number B U 7 Part No. 8 5 8 K Part No. 7858 7893 N - E Package KN: VQFN28 GU: VCSP85H3 2 Packaging and forming specification E2: Embossed tape and reel VQFN28 22 Embossed carrier tape (with dry pack) Quantity 2500pcs 28 8 Direction of feed 7 0.22±0.05 M 0.22±0.05 0.05 0.95MAX 1 +0.03 0.02 −0.02 5.0±0.1 Tape 14 15 21 5.2±0.1 <Tape and Reel information> 5.2±0.1 5.0±0.1 (1.1) E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 0.05 +0.1 0.6 −0.3 5) .3 (0 3− (0 .2 2) ) .5 (0 Notice : Do not use the dotted line area for soldering 0.5 1pin Reel (Unit : mm) Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. VCSP85H3(BU7893GU) <Tape and Reel information> 3.5±0.1 A 0.05 A B F E D C B A B 1 0.5±0.1 2 3 4 5 Embossed carrier tape Quantity 2500pcs Direction of feed S E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) P=0.5 × 5 32- φ 0.30±0.05 (φ0.15)INDEX POST Tape 0.5± 0.1 0.08 S 1.0MAX 0.25±0.1 3.5± 0.1 1PIN MARK 1pin 6 P=0.5×5 Reel (Unit : mm) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 24/24 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2010.09 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. R1010A