LODEV LF2301 Image resampling sequencer Datasheet

LF2301
LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
Image Resampling Sequencer
DEVICES INCORPORATED
FEATURES
DESCRIPTION
❑ 40 MHz Clock Rate
❑ High-Speed Image Manipulation
❑ Maximum Image Size: 4096 x 4096
Pixels
❑ Supports Following Interpolation
Algorithms:
• Nearest-Neighbor
• Bilinear Interpolation
• Cubic Convolution
❑ Applications:
• Video Special-Effects
• Image Recognition
• High-Speed Data Encoding/
Decoding
❑ Replaces TRW/Raytheon/Fairchild
TMC2301
❑ 68-pin PLCC, J-Lead
The LF2301 is a self-sequencing
address generator designed to filter
a two-dimensional image or remap
and resample it from one set of
Cartesian coordinates (x,y) into a
new set (u,v).
The LF2301 can resample digitized
images or perform such manipulations as rotation, panning, zooming,
and warping as well as compression
in real-time.
By using two LF2301s in a Image
Transformation System (ITS),
nearest-neighbor, bilinear interpolation, and cubic convolution algorithms, with kernel sizes up to 4 x 4
pixels, are all possible (see Figure 1).
This system can also implement
simple static filters with kernel sizes
up to 16 x 16 pixels.
LF2301 BLOCK DIAGRAM
LDR
WEN
B3-0
P11-0
NOOP
PARAMETER
STORAGE
INIT
CONTROL
WALK COUNT
SOURCE
ADDRESS
GENERATOR
FRACTION
INTER
ACC
DONE
END
DETAILS OF OPERATION
Most video applications use a pair
of LF2301s in tandem to construct
an ITS. One LF2301 is the row
coordinate generator (x to u) and the
other is the column generator (y to
v). External RAM is needed for
storage of the interpolation coefficient lookup table, as well as for
buffers of the source and destination
images. An external MultiplierAccumulator is required when
performing interpolation or implementing static filters.
The ITS is capable of performing the
general second-order coordinate
transformation of the form:
x(u,v) = Au 2+Bu+Cuv+Dv2+Ev+F
y(u,v) = Gu2+Hu+Kuv+Lv2+Mv+N
where parameters A through N of
the transform are user-defined.
The system steps sequentially
through each pixel in the “target”
image lying within a user-defined
rectangle. For each “target” pixel
at (u,v), the LF2301 points to a
corresponding “source” pixel at
(x,y).
TARGET
ADDRESS
GENERATOR
INPUT IMAGE
BOUNDARY
COMPARATOR
INTEGER
OETA
CA7-0
X11-0
CZERO
UWRI
U11-0
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LF2301
DEVICES INCORPORATED
SIGNAL DEFINITIONS
Image Resampling Sequencer
FIGURE 1. IMAGE TRANSFORMATION SYSTEM (ITS)
Power
IMAGE DATA IN
Vcc and GND
+5V power supply. All pins must be
connected.
Clock
12
P11-0
12
X11-0
4
B3-0
INIT, LDR,
WEN, NOOP, OETA
5
INTER
LF2301
Row
Address
Generator
(X)
12
24
ACC
SOURCE
IMAGE
RAM
UWRI
U11-0
12
END
CLK — Master Clock
CA7-0
8
12
The rising edge of CLK strobes all
enabled registers.
X
ACC
Inputs
INTERPOLATION
COEFFICIENT
RAM
P11-0 — Parameter Register Data Input
12
LMA1009/2009
12 x 12 bit
MultiplierAccumulator
Y
X,Y,P
P11-0 is the 12-bit Parameter Register
Data input port. P11-0 is latched on
the rising edge of CLK.
DOUT
12
8
CA7-0
B3-0 — Parameter Register Address Input
B3-0 is the 4-bit Parameter Register
Address input port. B3-0 is latched on
the rising edge of CLK.
Outputs
INTER
LF2301
Column
Address
Generator
(Y)
Y11-0
V11-0
12
12
DESTINATION
IMAGE
RAM
24
END
12
CLK
IMAGE DATA OUT
X11-0 — Source Address Output
X11-0 is the 12-bit registered Source
Address output port.
CA7-0 — Coefficient Address Output
CA7-0 is the 8-bit registered Coefficient Address output port.
U11-0 — Target Address Output
U11-0 is the 12-bit registered Target
Address output port.
Controls
INIT — Initialize
When INIT is HIGH for a minimum of
two clock cycles, the control logic is
cleared and initialized for the start of a
new image transformation. When
INIT goes LOW, normal operation
begins after two clock cycles. INIT is
latched on the rising edge of CLK.
WEN — Write Enable
When WEN is LOW, data latched into
the device on P11-0 is loaded into the
preload register addressed by the data
latched into the device on B3-0. When
WEN is HIGH, data cannot be loaded
into the preload registers and their
contents will not be changed. WEN is
latched on the rising edge of CLK.
LDR — Load Data Register
When LDR is HIGH, data in all
preload registers is latched into the
Transformation Parameter Registers.
When LDR is LOW, data cannot be
loaded into the Transformation
Parameter Registers and their contents
will not be changed. LDR is latched
on the rising edge of CLK.
ACC — Accumulate
The registered ACC output initializes
the accumulation register of the
external multiplier-accumulator. At
the start of each interpolation “walk,”
ACC goes LOW for one cycle effectively clearing the storage register by
loading in only the new first product.
ACC from either the row or column
LF2301 may be used.
UWRI — Target Memory Write Enable
The Target Memory Write Enable goes
LOW for one clock cycle after the end
of each interpolation “walk.” When
OETA is HIGH, this registered output
is forced to the high-impedance state.
UWRI from either the row or column
LF2301 may be used.
INTER — Interconnect
When two LF2301s are used to form
an ITS, the END flag on each device
is connected to INTER on the other
device. The END flag from the row
device indicates an “end of line” to the
column device. The END flag from the
column device indicates a “bottom of
frame” to the row device, forcing a
reset of the address counter.
NOOP — No Operation
When NOOP is LOW, the clock is
overridden holding all address
generators in their current state. X11-0
and CA 7-0 are forced to the high-
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LF2301
DEVICES INCORPORATED
impedance state. Users may then
access external memory. Normal
operation resumes on the next clock
cycle after NOOP goes HIGH. NOOP
is latched on the rising edge of CLK.
OETA — Target Memory Output Enable
When OETA is HIGH, UWRI and U11-0
are forced to the high-impedance
state. When OETA is LOW, UWRI
and U11-0 are enabled on the next
clock cycle. OETA is latched on the
rising edge of CLK.
Flags
CZERO — Coefficient Zero
If in a row device x<0,
XMIN≤x≤XMAX, or x≥4096, the
registered CZERO flag goes HIGH . If
0≤x<XMIN or XMAX<x<4096, CZERO
goes LOW. In an ITS, when the source
address falls outside a rectangle with
vertices (XMIN, YMIN), (XMAX,
YMIN), (XMIN, YMAX), and (XMAX,
YMAX), the logical AND of the
CZERO flags from the row and
column of the LF2301s will go LOW
representing an invalid address.
END — End of Row/Frame
When two LF2301s are used to form
an ITS, the END flag on each device
is connected to INTER on the other
device. The END flag from the row
device indicates an “end of line” to the
column device. The END flag from
the column device indicates a “bottom
of frame” to the row device, forcing a
reset of the address counter.
When Mode is set to “00” or “10”
END goes HIGH on the row device
for (K+1) x (K+1) clock cycles
starting[2 x (K+1) x (K+1)] + 1 clock
cycles before the last X address of a
row. END goes HIGH on the column
device for (K+1)3 x (UMAX-UMIN)
clock cycles starting at (K+1)3 x
(UMAX-UMIN) + 1 clock cycles before
the last X address of a frame.
Image Resampling Sequencer
When Mode is set to “01” or “11”
END goes HIGH on the row device
for K+1 clock cycles starting at (K+1) +
2 clock cycles before the last X address
of a row. END goes HIGH on the
column device for (K+1) x (K+1)
clock cycles starting at [(K+1) x (K+1)] +
1 clock cycles before the last X address
of a frame.
DONE — End of Transform
In a two LF2301 system, after the last
walk of the last row of an image, the
registered DONE flag goes HIGH
indicating the end of the transform.
DONE goes HIGH one clock cycle
before the last X address of a frame. If
AIN is HIGH, DONE will remain
HIGH for one clock cycle. If AIN is
LOW, DONE will remain HIGH until
a new transform begins.
Transformation Control Parameters
XMIN, XMAX, YMIN, YMAX
XMIN, XMAX, YMIN, YMAX define
the valid area in the source image
from which pixels may be read. The
CZERO flags will denote a valid
memory read whenever the LF2301s
generate an (x,y) address within this
boundary.
UMIN, UMAX, VMIN, VMAX
UMIN, UMAX, VMIN, VMAX define
the area in the destination image into
which pixels will be written.
(UMIN, VMIN) is the top left corner
and (UMAX + 1, VMAX) is the bottom
right corner. The following conditions
must be met: UMAX>UMIN and
VMAX>VMIN.
x0, y0
x0, y0 determine what the first pixel read
out of the source image will be at the
beginning of an image transformation.
x0, y0 will be the upper left corner of the
original image in non-inverting, nonreversing applications.
dx/du
dx/du is the displacement along the
x axis corresponding to a one-pixel
movement along the u axis.
dx/dv
dx/dv is the displacement along the
x axis corresponding to each one-pixel
movement along the v axis.
dy/du
dy/du is the displacement along the
y axis corresponding to each one-pixel
movement along the u axis.
dy/dv
dy/dv is the displacement along the
y axis corresponding to each one-pixel
movement along the v axis.
d2x/du2
d2x/du2 determines the rate of change
of dx/du with each step along a line
in the output image.
d2x/dv2
d2x/dv2 determines the rate of change
of dx/dv with each step down a
column in the output image.
d2y/du2
d2y/du2 determines the rate of change
of dy/du with each step along a line
in the output image.
d2y/dv2
d2y/dv2 determines the rate of change
of dy/dv with each step down a
column in the output image.
d2x/dudv
d2x/dudv determines the rate of
change of dx/du while moving
vertically through the output image.
d2x/dudv also determines the rate of
change of dx/dv while moving
horizontally through the output
image.
d2y/dudv
d2y/dudv determines the rate of
change of dy/dv while moving
horizontally through the output
image. d2y/dudv also determines the
rate of change of dy/du while
moving vertically through the output
image.
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LF2301
DEVICES INCORPORATED
TABLE 1. MODE SELECTION
M1 M0
MODE
0 0 single-pass operation (CW)
0
1 pass 1 of two-pass operation
1
0 single-pass operation (CCW)
1
1 pass 2 of two-pass operation
R/C — Row/Column Select
When set to 0, the LF2301 functions as
a row device. When set to 1, the
LF2301 functions as a column device.
M1-0 — Mode
This 2-bit control word defines four
modes as follows (see table 1):
The 1st and 3rd modes are singlepass operations where the device
walks through a (K + 1) x (K + 1)
kernel for each output pixel. K is the
kernel size determined by K3-0 in
Parameter Register 7. In mode 00, the
spiral walk is in the clockwise direction. In mode 10, the spiral walk is in
the counter clockwise direction.
The 2nd and 4th modes are used
together to perform a two-pass
operation. The first pass (mode 01)
performs a (K+1) kernel in the
horizontal dimension. The second
pass (mode 11) performs a (K+1)
kernel in the vertical dimension.
The result of pass 1 is stored in the
destination image memory and is used
as the source image data for the second
pass. A system to switch source and
destination memory banks could be
designed, or utilization of a second
LF2301 pair in a pipelined architecture
could be used. In this case, the system
would require a third image buffer for
the final destination image.
K3-0 — Kernel
Kernel determines the length of the
spiral walk when performing image
transformations and the size of the
filter when implementing static filters
(see table 2). When performing image
transformations, the longest spiral walk
Image Resampling Sequencer
possible is 4 x 4 pixels (Kernel = 3). For
static filters, kernels of up to 16 x 16
pixels (Kernel = 15) are possible.
FOV — Field of View
FOV determines the distance between
pixels in a spiral walk. An FOV of 1
means each step in a spiral walk is one
pixel. An FOV of 2 means each step is
two pixels, and so on. FOV can be set
as high as 7 (see Table 3). It is important to note when FOV is 0, the x and
y addresses will not change during a
spiral walk. They will remain fixed at
the first pixel address of the spiral
walk.
ALR — Autoload
When set HIGH and upon INIT being
strobed, the LDR control is automatically
asserted which causes the data
currently stored in the Preload Registers
to be loaded into the Transformation
Parameter Registers.
AIN — Autoinit
A new transform automatically begins
if the AIN bit is HIGH when the end of
an image is reached. The DONE flag
will go HIGH for one clock cycle. If
AIN is LOW, UWRI and the DONE flag
remain HIGH until the user strobes the
INIT control to begin a new image
transformation.
PIPE — Pipe Control
In order to compensate for buffered
source image RAM, PIPE adjusts the
timing of UWRI and ACC. If the PIPE
bit is HIGH, UWRI and ACC will have
a one clock cycle delay added relative
to the generation of the target address.
LOW, the source image address is fed
to X11-0. Two clock cycles are required
to access both the MS and LS words of
the internal accumulator.
Functional Description
The LF2301 is an address generator
designed to be used in an image
transformation system (ITS). When
implementing an LF2301-based ITS,
second-order image transformations
can be performed like resampling,
rotation, warping, panning, and
rescaling, all at real-time video rates.
2D filtering operations, like pixel
convolutions, can also be performed.
In most applications two LF2301s are
used, one to generate the row addresses
and the other to generate the column
TABLE 2. KERNEL
K3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
K2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
K1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
K0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Kernel
1x1
2x2
3x3
4x4
5x5
6x6
7x7
8x8
9x9
10 x 10
11 x 11
12 x 12
13 x 13
14 x 14
15 x 15
16 x 16
TABLE 3. FIELD OF VIEW
TM — Test Mode
Calculations of the source image and
coefficient addresses are made by an
internal 28-bit accumulator. TM
allows access to the sign bit and the
seven bits below the four coefficient
address bits in the accumulator. When
TM is HIGH the sign bit and 11 bits
below the source image address are fed
to X11-0 (see Figure 2). When TM is
F2
0
0
0
0
1
1
1
1
F1
0
0
1
1
0
0
1
1
F0
0
1
0
1
0
1
0
1
FOV
0
1
2
3
4
5
6
7
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LF2301
DEVICES INCORPORATED
addresses. An example of an ITS
implemented with two LF2301s is
shown in Figure 1. In this system the
following components are used: two
LF2301s, a multiplier-accumulator
(MAC), interpolation coefficient RAM,
and source/target image RAM.
Maximum image size is 4096 x 4096
pixels. Data word size is determined
by the word size of the external RAM.
Image Resampling Sequencer
FIGURE 2. TEST MODE DATA ROUTING
28-BIT INTERNAL
ACCUMULATOR
1
SIGN
12
12
A typical ITS performs image transformations as follows:
4
12
a. The LF2301s generate sequential
pixel addresses (left to right, top to
bottom) which fill the rectangle in the
target image RAM defined by
(UMIN,VMIN) and (UMAX +1, VMAX).
It is important to note that the U value
of the last pixel address on each line of
the target RAM is UMAX + 1.
7
b. The LF2301s calculate the address
of the corresponding pixel in the
source image RAM for each target
pixel address generated.
c. If interpolation is needed, the
external MAC sums the products of
the source pixels and the interpolation coefficients. Control signals for
the MAC and address signals for the
interpolation coefficient RAM are
provided by the LF2301s.
d. The new pixel value is written into
the target image RAM.
The LF2301s generate source pixel
addresses according to the following
general second order equations:
X11-0/T11-0
4
4
WALK COUNTER
CA7-4
CA3-0
FIGURE 3. ADDRESS TRANSFORMATION EQUATIONS
x = x0 +
dx m +
du
dx n + d 2 x mn + d 2 x m2– m + d 2 x
du2
2
dv 2
dv
dudv
n2– n
2
+ FOV · CAX(w) + FOV · m · CAX(ker)
y = y0 +
dy m +
du
dy n + d 2 y mn + d 2 y m2– m + d 2 y
du2
2
dv 2
dv
dudv
n2– n
2
+ FOV · CAY(w) + FOV · m · CAY(ker)
u = UMIN + m
v = VMIN + n
NOTE:
m2– m APPROXIMATES THE EXPONENTIAL CHARACTERISTIC OF m2.
2
x = Au2 + Bu + Cuv + Dv2 + Ev + F
y = Gu2 + Hu + Kuv + Lv2 + Mv + N
where (x,y) and (u,v) are the source
and target coordinates respectively.
A through N are user-defined parameters. The actual second order equations used are shown in Figure 3.
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LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
Transformation Parameter Register
Loading
FIGURE 4. LDR CONTROL FOR PARAMETER UPDATE
The LF2301 allows Transformation
Parameters to be updated on-the-fly.
The loading of these registers is
double-buffered (see Figure 4). Any
or all of the first level registers can
be loaded using P11-0, B3-0 , and
WEN without affecting the parameters currently in use.
P11-0
12
TRANSFORMATION
PARAMETER
REGISTERS
C15
C14
C13
4
DECODE
B3-0
LDR simultaneously updates all
Transformation Parameter Registers.
If Autoload (ALR) is active, these
registers will be updated automatically at the beginning of each new
image. Note that NOOP does not
affect the loading of the Transformation Parameter Registers.
C2
C1
C0
WEN
PRELOAD
REGISTERS
LDR
CLK
TABLE 4.
ADDR
PARAMETER REGISTER FORMATS (ROW OR COLUMN MODE)
MSB
11
FORMAT
10
2
8
2
7
2
6
2
LSB
5
COLUMN
210
29
28
27
26
25
24
23
22
21
20
0010
26
25
24
23
22
21
20
2–1
2–2
2–3
2–4
2–5
x0 (LS)
y0 (LS)
11
10
9
8
27
Controls, x0 (MS)
Controls, y0 (LS)
M1
M0
2–4
2–5
2–6
2–7
2–8
2–9
2–10
2–11
2–12
F0
–27
26
25
24
23
22
21
20
2–4
2–5
2–6
2–7
2–8
2–9
2–10
2–11
7
6
5
4
3
2
1
ALR
AIN
PIPE
R/C
0100
2–1
2–2
2–3
0101
TM
F2
F1
0110
2–1
2–2
2–3
dx/dv (LS)
dy/dv (LS)
0
Kernel, dx/dv (MS)
Kernel, dy/dv (MS)
d2x/dudv (LS)
d2y/dudv (LS)
K1
K0
–2
2–10
2–11
2–12
2–13
2–14
2–15
2–16
2–17
2–18
2–19
2–20
1001
3
2
2
2
1
2
0
2
–1
2
–2
2
–3
2
–4
2
–5
2
–6
2
–7
2
–8
2
–10
2
–11
2
–12
2
–13
2
–14
2
–15
2
–16
2
–17
2
–18
2
–19
2
–20
2
2
2
1
2
0
2
–1
2
–2
2
–3
2
–4
2
–5
2
–6
2
–7
2
–8
1011
1100
1101
–2
2–9
–23
2
2–12
K2
3
2
dy/du (LS)
Controls, dy/du (MS)
2–9
2
2
YMIN
YMAX
dx/du (LS)
K3
1010
2
XMIN
XMAX
Controls, dx/du (MS)
1000
–9
2
2
0111
–2
2
2
2
ROW
0
2
2
2
1
211
2
2
2
2
–2
2
3
0001
12
2
4
0000
0011
2
9
2
2
d x/dudv (MS)
d2y/dudv (MS)
2
2
d2y/du2 (LS)
2
2
d2y/du2 (MS)
d x/du (LS)
d x/du (MS)
2–10
2–11
2–12
2–13
2–14
2–15
2–16
2–17
2–18
2–19
2–20
d2x/dv2 (LS)
d2y/dv2 (LS)
22
21
20
2–1
2–2
2–3
2–4
2–5
2–6
2–7
2–8
d2x/dv2 (MS)
d2y/dv2 (MS)
1110
211
210
29
28
27
26
25
24
23
22
21
20
UMIN
VMIN
1111
11
10
9
8
7
6
5
4
3
2
1
0
UMAX
VMAX
2
2
2
2
2
2
2
2
2
2
2
2
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LF2301
DEVICES INCORPORATED
Static Filter
Static filtering at real-time video
rates can be performed as shown in
Figure 5. This mode is selected by
loading M1-0 with “00” for a clockwise spiral walk. A counterclockwise spiral walk could be selected
by loading M1-0 with “10.” In this
example, a static filter with a kernel
size of 3 x 3 pixels is desired. Loading K3-0 with “0010” selects a kernel
size of 3 x 3. The first pixel selected
is determined by x0 and y0. In this
example, the first pixel is (6,6). In
this case, the LF2301s should address consecutive pixels during each
spiral walk. For this to occur, FOV
must be set to 1 (F2-0 loaded with
“001”).
After the last pixel of a spiral walk
has been selected, the next pixel
address is determined by adding
dx/du to the current X address and
by adding dy/du to the current Y
address (unless the kernel just
Image Resampling Sequencer
completed was the last for that line).
At the end of the first spiral walk,
pixel (7,5) is addressed. Since the
first pixel of the next spiral walk
should be (7,6), dx/du is selected to
be 0 and dy/du is selected to be 1.
After the last pixel of the last spiral
walk on the first line has been
selected, the first pixel address of
the second line is determined by
adding dx/dv to x0 and by adding
dy/dv to y0. Since the first pixel of
the first spiral walk on the second
line should be (6,7), dx/dv is
selected to be 0 and dy/dv is selected to be 1. Second order differential terms are not used in this
filter and are therefore set to 0.
UMIN and VMIN are both selected
to be 6. UMAX and VMAX are both
selected to be 7. Table 5 shows the
values loaded into all Parameter
Registers. Table 6 shows the ITS
outputs for the 3 x 3 static filter.
FIGURE 5. 3 × 3 STATIC FILTER
5
6
7
8
9
4
5
1
2
6
7
8
1 = 1st pixel of 1st spiral walk,
2 = 1st pixel of 2nd spiral walk, etc.
TABLE 5. PARAMETER REGISTERS
ADDR Row (HEX) Column (HEX)
0000
000
000
0001
FFF
FFF
0010
0C0
0C0
0011
000
100
0100
000
000
0101
100
101
0110
000
000
0111
200
201
1000
000
000
1001
000
000
1010
000
000
1011
000
000
1100
000
000
1101
000
000
1110
006
006
1111
007
007
Video Imaging Products
2-7
08/16/2000–LDS.2301-H
LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
TABLE 6. ITS OUTPUTS FOR 3 × 3 STATIC FILTER
Cycle
1
2
3
x
6
6
6
y
6
6
6
CAx (HEX)
00
00
00
CAy (HEX)
00
00
00
u
x
x
x
v
x
x
x
INIT
1
0
0
ACC
0
0
0
UWRI
1
1
1
ENDx
0
0
0
ENDy
0
0
0
DONE
0
0
0
4
5
6
7
8
9
10
11
12
6
7
7
6
5
5
5
6
7
6
6
7
7
7
6
5
5
5
00
01
02
03
04
05
06
07
08
00
01
02
03
04
05
06
07
08
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
13
14
15
16
17
18
19
20
21
7
8
8
7
6
6
6
7
8
6
6
7
7
7
6
5
5
5
00
01
02
03
04
05
06
07
08
00
01
02
03
04
05
06
07
08
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
22
23
24
25
26
27
28
29
30
8
9
9
8
7
7
7
8
9
6
6
7
7
7
6
5
5
5
00
01
02
03
04
05
06
07
08
00
01
02
03
04
05
06
07
08
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
31
32
33
34
35
36
37
38
39
6
7
7
6
5
5
5
6
7
7
7
8
8
8
7
6
6
6
00
01
02
03
04
05
06
07
08
00
01
02
03
04
05
06
07
08
8
8
8
8
8
8
8
8
8
6
6
6
6
6
6
6
6
6
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
40
41
42
43
44
45
46
47
48
7
8
8
7
6
6
6
7
8
7
7
8
8
8
7
6
6
6
00
01
02
03
04
05
06
07
08
00
01
02
03
04
05
06
07
08
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
49
50
51
52
53
54
55
56
57
8
9
9
8
7
7
7
8
9
7
7
8
8
8
7
6
6
6
00
01
02
03
04
05
06
07
08
00
01
02
03
04
05
06
07
08
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
58
6
6
00
00
8
7
0
0
1
0
0
1
Video Imaging Products
2-8
08/16/2000–LDS.2301-H
LF2301
DEVICES INCORPORATED
Image Rotation & Bilinear Interpolation
Figure 8 shows an example of rotating
an image 30º and using bilinear
interpolation. This mode is selected by
loading M1-0 with “00” for a clockwise
spiral walk. A counterclockwise spiral
walk could be selected by loading M1-0
with “10.” Bilinear interpolation
requires a kernel size of 2 x 2 pixels.
Loading K3-0 with “0001” selects a
kernel size of 2 x 2. The first pixel
selected is determined by x0 and y0. In
this example, the first pixel is (0,0). In
this case, the LF2301s should address
consecutive pixels during each spiral
walk. For this to occur, FOV must be
set to 1 (F2-0 loaded with “001”).
After the last pixel of a spiral walk has
been selected, the next pixel address is
determined by adding dx/du to the
current X address and by adding
dy/du to the current Y address
(unless the kernel just completed was
the last for that line). At the end of the
first spiral walk, pixel (0,1) is addressed. Since the next calculated
pixel should be (0.866,0.5), dx/du is
selected to be 0.866 and dy/du is
selected to be 0.5. However, after
adding dx/du and dy/du to the X
and Y addresses respectively, the
generated address is (0.866,1.5). The Y
address is off by a value of 1. This is
due to the fact that the last pixel
address of a spiral walk is used to
calculate the first pixel address of
the next spiral walk. In order for the
LF2301s to generate the correct result,
dy/du must be modified by subtracting a 1 from it. The correct value of
dy/du is -0.5. Figure 6 shows how the
unmodified differential terms were
calculated.
After the last pixel of the last spiral
walk on the first line has been selected,
the first pixel address of the second
line is determined by adding dx/dv to
x0 and by adding dy/dv to y0. Since
the first calculated pixel of the first
Image Resampling Sequencer
spiral walk on the second line should
be (-0.5,0.866), dx/dv is selected to
be -0.5 and dy/dv is selected to be
0.866. Second order differential terms
are not used in this transform and are
therefore set to 0.
It is important to note that the integer
portion of the address generated in
the LF2301 is used as the X or Y
pixel address. The fractional portion
(sub-pixel portion) is used as the
coefficient RAM address.
UMIN and VMIN are both selected to
be 0. UMAX and VMAX are both
selected to be 2. Table 7 shows the
values loaded into all Parameter
Registers. Table 8 shows the ITS
outputs for this example.
FIGURE 6. DIFFERENTIAL TERMS
dx = cos 30º = 0.866
du
dy = sin 30º = 0.5
du
dx = –sin 30º = –0.5
dv
dy = cos 30º = 0.866
dv
FIGURE 7. 30°° IMAGE ROTATION
dx
dv
dx
du
-1
0
1
0
5
1
2
3
1,2
3
4
2
3
4
1 = 1st pixel of 1st spiral walk,
2 = 1st pixel of 2nd spiral walk, etc.
source image pixels
calculated pixels
TABLE 7. PARAMETER REGISTERS
ADDR Row (HEX) Column (HEX)
0000
000
000
0001
FFF
FFF
0010
000
000
0011
000
100
0100
DDB
800
0101
100
1FF
0110
800
DDB
0111
1FF
100
1000
000
000
1001
000
000
1010
000
000
1011
000
000
1100
000
000
1101
000
000
1110
000
000
1111
002
002
x
len
gth
dy
dv
FIGURE 8. 30°° IMAGE ROTATION
30º
=1
dy
du
u
v
y
source image pixels
calculated pixels
Video Imaging Products
2-9
08/16/2000–LDS.2301-H
LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
TABLE 8. ITS OUTPUTS FOR 30°° IMAGE ROTATION WITH BILINEAR INTERPOLATION
Cycle
1
2
3
x
0
0
0
y
0
0
0
CAx (HEX)
00
00
00
CAy (HEX)
00
00
00
u
x
x
x
v
x
x
x
INIT
1
0
0
ACC
0
0
0
UWRI
1
1
1
ENDx
0
0
0
ENDy
0
0
0
DONE
0
0
0
4
5
6
7
0
1
1
0
0
0
1
1
00
01
02
03
00
01
02
03
x
x
x
x
x
x
x
x
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
8
9
10
11
0
1
1
0
0
0
1
1
D0
D1
D2
D3
80
81
82
83
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
12
13
14
15
1
2
2
1
1
1
2
2
B0
B1
B2
B3
00
01
02
03
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
16
17
18
19
2
3
3
2
1
1
2
2
90
91
92
93
80
81
82
83
2
2
2
2
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
20
21
22
23
-1
0
0
-1
0
0
1
1
80
81
82
83
D0
D1
D2
D3
3
3
3
3
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
24
25
26
27
0
1
1
0
1
1
2
2
50
51
52
53
50
51
52
53
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
28
29
30
31
1
2
2
1
1
1
2
2
30
31
32
33
D0
D1
D2
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
32
33
34
35
2
3
3
2
2
2
3
3
10
11
12
13
50
51
52
53
2
2
2
2
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
36
37
38
39
-1
0
0
-1
1
1
2
2
00
01
02
03
B0
B1
B2
B3
3
3
3
3
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
40
41
42
43
-1
0
0
-1
2
2
3
3
D0
D1
D2
D3
30
31
32
33
0
0
0
0
2
2
2
2
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
44
45
46
47
0
1
1
0
2
2
3
3
B0
B1
B2
B3
B0
B1
B2
B3
1
1
1
1
2
2
2
2
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
48
49
50
51
1
2
2
1
3
3
4
4
90
91
92
93
30
31
32
33
2
2
2
2
2
2
2
2
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
52
53
54
55
0
1
1
0
0
0
1
1
00
01
02
03
00
01
02
03
3
3
3
3
2
2
2
2
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
Video Imaging Products
2-10
08/16/2000–LDS.2301-H
LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
Pass 1 of Two-Pass Operation
FIGURE 9. PASS 1 OF TWO-PASS
Pass 1 of the two-pass operation
performs horizontal filtering on an
image as shown in Figure 9. This
mode is selected by loading M1-0 with
“01.” In this example, a horizontal
filter with a kernel size of 3 pixels is
desired. Loading K3-0 with “0010”
selects a kernel size of 3. The first
pixel selected is determined by x0 and
y0. In this example, the first pixel is
(0,0). In this case, the LF2301s should
address consecutive pixels during each
pixel walk. For this to occur, FOV must
be set to 1 (F2-0 loaded with “001”).
After the last pixel of a pixel walk has
been selected, the next pixel address is
determined by adding dx/du to the
current X address and by adding dy/
du to the current Y address (unless the
kernel just completed was the last for
that line). At the end of the first pixel
walk, pixel (2,0) is addressed. Since
the first pixel of the next pixel walk
should be (1,0), dx/du is selected to be
-1 and dy/du is selected to be 0. After
the last pixel of the last pixel walk on
the first line has been selected, the first
1
0
2
3
4
-1
1
2
3
4
5
6
0
1
7
2
3
1 = 1st pixel of 1st walk,
2 = 1st pixel of 2nd walk, etc.
pixel address of the second line is
determined by adding dx/dv to x0
and by adding dy/dv to y0. Since the
first pixel of the first pixel walk on the
second line should be (0,1), dx/dv is
selected to be 0 and dy/dv is selected
to be 1. Second order differential
terms are not used in this filter and are
therefore set to 0.
TABLE 9. PARAMETER REGISTERS
ADDR Row (HEX) Column (HEX)
0000
000
000
0001
FFF
FFF
0010
000
000
0011
040
140
0100
000
000
0101
1FF
000
0110
000
000
0111
200
201
1000
000
000
1001
000
000
1010
000
000
1011
000
000
1100
000
000
1101
000
000
1110
005
005
1111
006
006
UMIN and VMIN are both selected to
be 5. UMAX and VMAX are both
selected to be 6. Table 9 shows the
values loaded into all Parameter
Registers. Table 10 shows the ITS
outputs for the Pass 1 of a Two-Pass
operation.
TABLE 10. ITS OUTPUTS FOR PASS 1 OF TWO-PASS
Cycle
1
2
3
x
0
0
0
y
0
0
0
CAx (HEX)
00
00
00
CAy (HEX)
00
00
00
u
x
x
x
v
x
x
x
INIT
1
0
0
ACC
0
0
0
UWRI
1
1
1
ENDx
0
0
0
ENDy
0
0
0
DONE
0
0
0
4
5
6
0
1
2
0
0
0
00
01
02
00
01
02
x
x
x
x
x
x
0
0
0
0
1
1
1
0
1
0
1
1
0
0
0
0
0
0
7
8
9
1
2
3
0
0
0
00
01
02
00
01
02
5
5
5
5
5
5
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
10
11
12
2
3
4
0
0
0
00
01
02
00
01
02
6
6
6
5
5
5
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
0
0
0
13
14
15
0
1
2
1
1
1
00
01
02
00
01
02
7
7
7
5
5
5
0
0
0
0
1
1
1
0
1
0
1
1
1
1
1
0
0
0
16
17
18
1
2
3
1
1
1
00
01
02
00
01
02
5
5
5
6
6
6
0
0
0
0
1
1
1
0
1
1
0
0
1
1
1
0
0
0
19
20
21
2
3
4
1
1
1
00
01
02
00
01
02
6
6
6
6
6
6
0
0
0
0
1
1
1
0
1
0
0
0
1
0
0
0
1
1
22
23
24
0
1
2
0
0
0
00
01
02
00
01
02
7
7
7
6
6
6
0
0
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
Video Imaging Products
2-11
08/16/2000–LDS.2301-H
LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
Pass 2 of Two-Pass Operation
FIGURE 10. PASS 2 OF TWO-PASS
Pass 2 of the two-pass operation
performs vertical filtering on an image
as shown in Figure 10. This mode is
selected by loading M1-0 with “11.” In
this example, a vertical filter with a
kernel size of 3 pixels is desired.
Loading K 3-0 with “0010” selects a
kernel size of 3. The first pixel selected is determined by x0 and y0. In
this example, the first pixel is (0,0). In
this case, the LF2301s should address
consecutive pixels during each pixel
walk. For this to occur, FOV must be
set to 1 (F2-0 loaded with “001”).
After the last pixel of a pixel walk has
been selected, the next pixel address
is determined by adding dx/du to the
current X address and by adding
dy/du to the current Y address
(unless the kernel just completed was
the last for that line). At the end of
the first pixel walk, pixel (0,2) is
addressed. Since the first pixel of the
next pixel walk should be (1,0), dx/du
is selected to be 1 and dy/du is selected
to be -2. After the last pixel of the last
pixel walk on the first line has been
-1
1
0
2
0
1
2
1
4
5
3
3
2
3
4
1 = 1st pixel of 1st walk,
2 = 1st pixel of 2nd walk, etc.
selected, the first pixel address of the
second line is determined by adding
dx/dv to x 0 and by adding dy/dv to
y0. Since the first pixel of the first
pixel walk on the second line should be
(0,1), dx/dv is selected to be 0 and
dy/dv is selected to be 1. Second
order differential terms are not used
in this filter and are therefore set to 0.
TABLE 11. PARAMETER REGISTERS
ADDR Row (HEX) Column (HEX)
0000
000
000
0001
FFF
FFF
0010
000
000
0011
0C0
1C0
0100
000
000
0101
101
1FE
0110
000
000
0111
200
201
1000
000
000
1001
000
000
1010
000
000
1011
000
000
1100
000
000
1101
000
000
1110
005
005
1111
006
006
UMIN and VMIN are both selected to
be 5. UMAX and VMAX are both
selected to be 6. Table 11 shows the
values loaded into all Parameter
Registers. Table 12 shows the ITS
outputs for the Pass 2 of a Two-Pass
operation.
TABLE 12. ITS OUTPUTS FOR PASS 2 OF TWO-PASS
Cycle
1
2
3
x
0
0
0
y
0
0
0
CAx (HEX)
00
00
00
CAy (HEX)
00
00
00
u
x
x
x
v
x
x
x
INIT
1
0
0
ACC
0
0
0
UWRI
1
1
1
ENDx
0
0
0
ENDy
0
0
0
DONE
0
0
0
4
5
6
0
0
0
0
1
2
00
01
02
00
01
02
x
x
x
x
x
x
0
0
0
0
1
1
1
0
1
0
1
1
0
0
0
0
0
0
7
8
9
1
1
1
0
1
2
00
01
02
00
01
02
5
5
5
5
5
5
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
10
11
12
2
2
2
0
1
2
00
01
02
00
01
02
6
6
6
5
5
5
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
0
0
0
13
14
15
0
0
0
1
2
3
00
01
02
00
01
02
7
7
7
5
5
5
0
0
0
0
1
1
1
0
1
0
1
1
1
1
1
0
0
0
16
17
18
1
1
1
1
2
3
00
01
02
00
01
02
5
5
5
6
6
6
0
0
0
0
1
1
1
0
1
1
0
0
1
1
1
0
0
0
19
20
21
2
2
2
1
2
3
00
01
02
00
01
02
6
6
6
6
6
6
0
0
0
0
1
1
1
0
1
0
0
0
1
0
0
0
1
1
22
23
24
0
0
0
0
1
2
00
01
02
00
01
02
7
7
7
6
6
6
0
0
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
Video Imaging Products
2-12
08/16/2000–LDS.2301-H
LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
Active Operation, Commercial
Active Operation, Military
Supply Voltage
0°C to +70°C
4.75 V ≤ VCC ≤ 5.25 V
–55°C to +125°C
4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
VCC = Min., IOH = –2.0 mA
2.4
VOL
Output Low Voltage
VCC = Min., IOL = 4.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
IOZ
Typ
Max
Unit
V
0.4
V
2.0
VCC
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±10
µA
Output Leakage Current
Ground ≤ VOUT ≤ VCC (Note 12)
±10
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
75
mA
ICC2
VCC Current, Quiescent
(Note 7)
5
mA
CIN
Input Capacitance
TA = 25°C, f = 1 MHz
10
pF
COUT
Output Capacitance
TA = 25°C, f = 1 MHz
10
pF
Video Imaging Products
2-13
08/16/2000–LDS.2301-H
LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
Symbol
1234567890123456
1234567890123456
1234567890123456
66*
1234567890123456
1234567890123456
1234567890123456
Min
Max
1234567890123456
1234567890123456
1234567890123456
66
1234567890123456
1234567890123456
1234567890123456
30
1234567890123456
1234567890123456
1234567890123456
20
1234567890123456
1234567890123456
1234567890123456
2
1234567890123456
1234567890123456
1234567890123456
1234567890123456
10
1234567890123456
1234567890123456
1234567890123456
35
1234567890123456
1234567890123456
1234567890123456
45
1234567890123456
1234567890123456
1234567890123456
35
1234567890123456
1234567890123456
1234567890123456
20
1234567890123456
Parameter
tCYC
Cycle Time
tPW
Clock Pulse Width
tS
Input Setup Time
tH
Input Hold Time
tHI
Input Hold Time, INTER
tD
Output Delay
tDE
Output Delay, END
tENA
Three-State Output Enable Delay (Note 11)
tDIS
Three-State Output Disable Delay (Note 11)
LF2301–
55
Min
Max
25
Min
55
25
25
10
18
10
2
0
10
5
Max
27
18
37
18
27
15
18
15
MILITARY OPERATING RANGE (-55°C to +125°C) Notes 9, 10 (ns)
Symbol
1234567890123456789012345678901212345678901234
LF2301–
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
*
1234567890123456789012345678901212345678901234
66
55*
30*
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
Min
Max
Min
Max
Min
Max
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
66
55
30
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
30
25
10
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
20
18
12
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
2
2
0
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
10
10
6
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
35
27
20
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
45
37
20
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
35
27
18
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
1234567890123456789012345678901212345678901234
20
18
18
1234567890123456789012345678901212345678901234
Parameter
tCYC
Cycle Time
tPW
Clock Pulse Width
tS
Input Setup Time
tH
Input Hold Time
tHI
Input Hold Time, INTER
tD
Output Delay
tDE
Output Delay, END
tENA
Three-State Output Enable Delay (Note 11)
tDIS
Three-State Output Disable Delay (Note 11)
123456789012345678901234
123456789012345678901234
123456789012345678901234
*DISCONTINUED SPEED GRADE
123456789012345678901234
Video Imaging Products
2-14
08/16/2000–LDS.2301-H
LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
SWITCHING WAVEFORMS: DATA INPUTS (PARAMETER STORAGE)
tCYC
tPW
tPW
CLK
tS
tH
P11-0
B3-0
WEN
LDR
SWITCHING WAVEFORMS: DATA OUTPUTS AND CONTROL LINES
tCYC
tPW
tPW
CLK
tS
tH
NOOP
tS
tH
OETA
tD
tDIS
HIGH IMPEDANCE
X11-0, CA7-0
tENA
tDIS
HIGH IMPEDANCE
U11-0
tDIS
HIGH IMPEDANCE
UWRI
tENA
tENA
CZERO, ACC,
DONE
tDE
END
tS
tHI
INTER
Video Imaging Products
2-15
08/16/2000–LDS.2301-H
LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damagsources of IOH and I OL respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF
less, conventional precautions should minimum, and may be distributed.
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
transient undershoot and overshoot. In- measures are recommended:
put levels below ground or above VCC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device VCC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
4. Actual test conditions may vary from b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and
VCC noise to maintain required DUT inNCV2 F
put levels relative to the DUT ground pin.
4
where
10. Each parameter is shown as a mini-
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
IOL
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.5V Vth
0
1.5 V
1.5 V
Z
1
VOL*
0.2 V
VOH*
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
mum or maximum value. Input requirements are specified from the point of
view of the external system driving the
chip. Setup time, for example, is specified
as a minimum since the external system
6. Tested with no output load at must supply at least that much time to
meet the worst-case requirements of all
15 MHz clock rate.
parts. Responses from the internal cir7. Tested with all inputs within 0.1 V of cuitry are specified from the point of view
VCC or Ground, no load.
of the device. Output delay, for example,
8. These parameters are guaranteed is specified as a maximum since worstcase operation of any device always probut not 100% tested.
vides data within that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
Video Imaging Products
2-16
08/16/2000–LDS.2301-H
LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
ORDERING INFORMATION
GND
XO
CA7
CA6
CA5
CA4
CA3
CA2
GND
VCC
CA1
CA0
CZERO
ACC
UWRI
U11
U10
68-pin
10
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
15
55
16
54
17
Top
View
18
19
53
52
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
GND
U9
U8
U7
U6
U5
U4
U3
GND
U2
U1
U0
DONE
END
INTER
OETA
INIT
P6
P5
P4
P3
P2
P1
P0
CLK
GND
VCC
NOOP
LDR
B0
B1
B2
B3
WEN
X1
X2
X3
X4
X5
X6
X7
X8
GND
X9
X10
X11
P11
P10
P9
P8
P7
Plastic J-Lead Chip Carrier
(J2)
Speed
0°C to +70°C — COMMERCIAL SCREENING
55 ns
25 ns
LF2301JC55
LF2301JC25
Video Imaging Products
2-17
08/16/2000–LDS.2301-H
LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
ORDERING INFORMATION
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
68-pin
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1
2
3
4
5
6
7
8
9
10
11
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
A
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
B1 LDR VCC CLK P1
P5
WEN B3
P3
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
B
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
B0 NOOP GND P0
P7
P2
P4
P6
OETA INIT B2
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
C
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
P9
P8
END INTER
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
D
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
P11 P10
U0 DONE
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
E
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
Top View
X10 X11
U2
U1
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
Through
Package
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
F
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
U3 GND
GND X9
(i.e., Component Side Pinout)
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
G
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
U5
X8
U4
X7
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
H
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
X5
X6
U7
U6
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
J
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
U9
U8
X3
X4
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
K
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
GND U10 UWRI CZERO CA1 GND CA3 CA5 CA7 X1
X2
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
L
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
U11 ACC CA0 VCC CA2 CA4 CA6 X0 GND
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
Discontinued Package
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121
Ceramic Pin Grid Array
(G1)
Speed
0°C to +70°C — COMMERCIAL SCREENING
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Video Imaging Products
2-18
08/16/2000–LDS.2301-H
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