ATMEL AT89C51SND1 Based on the intel hex-type record Datasheet

Features
• Protocol
– UART Used as a Physical Layer
– Based on the Intel Hex-type Records
– Autobaud
• In-System Programming
– Read/Write Flash Memory
– Read Device IDs
– Block Erase
– Full-chip Erase
– Read/Write Configuration Bytes
– Security Setting From ISP Command
– Remote Application Start Command
• In-Application Programming/Self-Programming
– Read/Write Flash Memory
– Read Device IDs
– Block Erase
– Read/Write Configuration Bytes
– Bootloader Start
MP3
Microcontrollers
AT89C51SND1
UART
Bootloader
Description
This document describes the UART bootloader functionalities as well as the serial
protocol to efficiently perform operations on the on-chip Flash memory. Additional
information for the AT89C51SND1 product can be found in the AT89C51SND1 data
sheet and the AT89C51SND1 errata sheet available on the Atmel web site,
www.atmel.com.
The bootloader software package (source code and binary) currently used for production is available from the Atmel web site.
Bootloader Revision
Purpose of Modifications
Date
Revision 1.0.0
New release increasing programming
speed
June 2002
Revision 1.1.0
Bug fix in boot process
October 2002
4241B–MP3–07/04
1
Functional
Description
The AT89C51SND1 bootloader facilitates In-System Programming and In-Application
Programming.
In-System Programming
Capability
In-System Programming (ISP) allows the user to program or reprogram a microcontroller’s on-chip Flash memory without removing it from the system and without the need of
a pre-programmed application.
The UART bootloader can manage a communication with a host through the serial network. It can also access and perform requested operations on the on-chip Flash
memory.
In-Application
Programming or SelfProgramming Capability
In-Application Programming (IAP) allows the reprogramming of a microcontroller’s onchip Flash memory without removing it from the system and while the embedded application is running.
The UART bootloader contains some Application Programming Interface routines
named API routines allowing IAP by using the user’s firmware.
Block Diagram
This section describes the different parts of the bootloader. Figure 1 shows the on-chip
bootloader and IAP processes.
Figure 1. Bootloader Process Description
External Host via the
UART Protocol
Communication
On-chip
User
Application
IAP
User Call
Management
ISP Communication
Management
Flash memory
Management
Flash
Memory
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AT89C51SND1 UART Bootloader
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AT89C51SND1 UART Bootloader
ISP Communication
Management
The purpose of this process is to manage the communication and its protocol between
the on-chip bootloader and an external device (host). The on-chip bootloader implements a serial protocol (see Section “Protocol”, page 9). This process translates serial
communication frames (UART) into Flash memory accesses (read, write, erase, etc.).
User Call Management
Several Application Program Interface (API) calls are available to the application program to selectively erase and program Flash pages. All calls are made through a
common interface (API calls) included in the bootloader. The purpose of this process is
to translate the application request into internal Flash memory operations.
Flash Memory Management
This process manages low level accesses to the Flash memory (performs read and
write accesses).
Bootloader
Configuration
Configuration and
Manufacturer Information
The table below lists configuration and manufacturer byte information used by the bootloader. This information can be accessed through a set of API or ISP commands.
Table 1. Configuration and Munfacturer Byte Information
Mapping and Default Value of
Hardware Security Byte
Mnemonic
Description
Default Value
BSB
Boot Status Byte
FFh
SBV
Software Boot Vector
F0h
SSB
Software Security Byte
FCh
Manufacturer
58h
ID1: Family code
D7h
ID2: Product Name
ECh
ID3: Product Revision
FFh
The 4 Most Significant Bytes (MSB) of the Hardware Byte can be read/written by software (this area is called Fuse bits). The 4 Least Significant Bytes (LSB) can only be
read by software and written by hardware in parallel mode (with parallel programmer
devices).
Table 2. Mapping and Default Value of HSB
Bit Position
Mnemonic
Default Value
7
X2B
U
To start in x1 mode
6
BLJB
P
To map the boot area in code area between F000hFFFFh
5
Reserved
U
4
Reserved
U
3
Reserved
U
2
LB2
P
1
LB1
U
0
LB0
U
Note:
Description
To lock the chip (see datasheet)
U: Unprogrammed = 1, P: Program = 0
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Software Security Byte
The bootloader has Software Security Byte (SSB) to protect itself from user access or
ISP access.
The Software Security Byte (SSB) protects from ISP accesses. The command “Program
Software Security Bit” can only write a higher priority level. There are three levels of
security:
•
level 0: NO_SECURITY (FFh)
From level 0, one can write level 1 or level 2.
•
level 1: WRITE_SECURITY (FEh)
In this level it is impossible to write in the Flash memory, BSB and SBV.
The bootloader returns an error message.
From level 1, one can write only level 2.
•
level 2: RD_WR_SECURITY (FCh)
This is the default level.
Level 2 forbids all read and write accesses to/from the Flash memory.
The bootloader returns an error message.
Only a full-chip erase command can reset the software security bits.
Table 3. Software Security Byte Levels
Software Boot Vector
Level 0
Level 1
Level 2
Flash
Any access allowed
Read only access allowed
All access not allowed
Fuse bit
Any access allowed
Read only access allowed
All access not allowed
BSB & SBV
Any access allowed
Read only access allowed
All access not allowed
SSB
Any access allowed
Write level2 allowed
Read only access allowed
Manufacturer info
Read only access allowed
Read only access allowed
Read only access allowed
Bootloader info
Read only access allowed
Read only access allowed
Read only access allowed
Erase block
Allowed
Not allowed
Not allowed
Full chip erase
Allowed
Allowed
Allowed
Blank Check
Allowed
Allowed
Allowed
The Software Boot Vector (SBV) forces the execution of a user bootloader starting at
address [SBV]00h in the application area (FM0).
The way to start this user bootloader is described in the Section “Regular Boot Process”,
page 7.
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AT89C51SND1 UART Bootloader
4241B–MP3–07/04
AT89C51SND1 UART Bootloader
Figure 2. Software Boot Vector
UART Bootloader
User Bootloader
[SBV]00h
Application
FM1
FM0
FLIP Software Program
FLIP is a PC software program running under Windows® 9x//2000/XP, Windows NT®
and LINUX® that supports all Atmel Flash microcontrollers.
This free software program is available on the Atmel web site.
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In-System
Programming
The ISP allows the user to program or reprogram a microcontroller’s on-chip Flash
memory through the serial line without removing it from the system and without the need
of a pre-programmed application.
This section describes how to start the UART bootloader and the higher level protocol
over the serial line.
Bootloader Execution
As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented
to allow boot memory to be mapped in the code space for execution at addresses from
F000h to FFFFh. The boot memory is enabled by setting the ENBOOT bit in AUXR1.
The three ways to set this bit are detailed below.
Software Boot Mapping
The software way to set ENBOOT consists in writing to AUXR1 from the user’s software. This enables bootloader or API routines execution.
Hardware Condition Boot
Mapping
The hardware condition is based on the ISP# pin. When driving this pin to low level, the
chip reset sets ENBOOT and forces the reset vector to F000h instead of 0000h in order
to execute the bootloader software.
As shown in Figure 3, the hardware condition always allows In-System recovery when
user’s memory has been corrupted.
Programmed Condition Boot
Mapping
6
The programmed condition is based on the Bootloader Jump Bit (BLJB) in HSB. As
shown in Figure 3, this bit is programmed (by hardware or software programming
mode), the chip reset set ENBOOT and forces the reset vector to F000h instead of
0000h, in order to execute the bootloader software.
AT89C51SND1 UART Bootloader
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AT89C51SND1 UART Bootloader
Regular Boot Process
Figure 3. Boot Process Algorithm
RESET
Hardware
Process
Hard Cond?
ISP# = L?
Prog Cond?
BLJB = P?
Standard Init
ENBOOT = 0
PC = 0000h
FCON = F0h
Hard Cond Init
ENBOOT = 1
PC = F000h
FCON = 00h
Prog Cond Init
ENBOOT = 1
PC = F000h
FCON = F0h
Software
Process
Hard Init?
FCON = 00h?
User Boot?
SBV < F0h?
User’s
Application
User’s
Bootloader
Atmel’s
Bootloader
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Physical Layer
Frame Description
The UART used to transmit information has the following configuration:
•
Character: 8-bit data
•
Parity: none
•
Stop: 1 bit
•
Flow control: none
•
Baud rate: auto baud is performed by the bootloader to compute the baud rate
chosen by the host.
The Serial Protocol is based on the Intel Hex-type records.
Intel Hex records consist of ASCII characters used to represent hexadecimal values and
are summarized in Table 4.
Table 4. Intel Hex Type Frame
Record Mark ‘:’
Record length
Load Offset
Record Type
Data or Info
Checksum
1 byte
1 byte
2 bytes
1 byte
n byte
1 byte
•
Record Mark:
•
Record length:
–
–
•
Data/Info is a variable length field. It consists of zero or more Bytes encoded as
pairs of hexadecimal digits. The meaning of data depends on the Record Type.
Checksum:
–
8
Record Type specifies the command type. This field is used to interpret the
remaining information within the frame.
Data/Info:
–
•
Load Offset specifies the 16-bit starting load offset of the data Bytes, therefore
this field is used only for Data Program Record.
Record Type:
–
•
Record length specifies the number of Bytes of information or data which
follows the Record Type field.
Load Offset:
–
•
Record Mark is the start of frame. This field must contain “:”.
The two’s complement of the 8-bit Bytes that result from converting each pair of
ASCII hexadecimal digits to one Byte of binary, and include the Record Length
field to the last Byte of the Data/Info field inclusive. Therefore, the sum of all the
ASCII pairs in a record after converting to binary, from the Record Length field
to and the Checksum field inclusive, is zero.
AT89C51SND1 UART Bootloader
4241B–MP3–07/04
AT89C51SND1 UART Bootloader
Protocol
Overview
An initialization step must be performed after each Reset. After microcontroller reset,
the bootloader waits for an auto baud sequence (see Section “Autobaud Performances”,
page 9).
When the communication is initialized the protocol depends on the record type issued
by the host.
Communication Initialization
The host initiates the communication by sending a “U” character to help the bootloader
to compute the baud rate (auto baud).
Figure 4. Initialization
Bootloader
Host
Init Communication
"U"
If (not received "U")
Else
Communication Opened
"U"
Performs Autobaud
Sends Back ‘U’ Character
Time-out
Autobaud Performances
The bootloader supports a wide range of baud rates. It is also adaptable to a wide range
of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in
a received character. This information is then used to program the baud rate in terms of
timer counts based on the oscillator frequency. Table 5 shows the auto baud
capabilities.
Table 5. Autobaud Performances
FOSC = 12 MHz
Baudrate
FOSC = 20 MHz
Status
Error%
Status
Error%
Status
Error%
9600
OK
0.16
OK
0.16
OK
0.16
19200
OK
0.16
OK
0.16
OK
0.16
2.34
OK
38400
57600
115200
Note:
Command Data Stream
Protocol
FOSC = 16 MHz
1
OK/KO
OK
0.16
0.16
OK
1.36
1
2.12
OK
1.36
1
3.55
OK
1.36
OK/KO
OK/KO
1. Depending on the host, error values may lead to unsupported baudrate.
All commands are sent using the same flow. Each frame sent by the host is echoed by
the bootloader.
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Figure 5. Command Flow
Host
Bootloader
Sends First Character of the
Frame
":"
If (Not Received ":")
":"
Else
Sends Echo and Start
Reception
Sends Frame (Made of 2 ASCII
Characters per Byte)
Echo Analysis
Programming the Flash Data
Gets Frame, and Sends Back Echo
for Each Received Byte
The flow described in Figure 6 shows how to program data in the Flash memory.
The bootloader programs on a page of 128 bytes basis when it is possible.
The host must take care that the data to program transmitted within a frame are in the
same page.
Requests from Host
Answers from Bootloader
10
Command Name
Record
Type
Load
Offset
Program Flash
00h
Start
Address
Record
Length
Data[0]
...
Data[127]
nb of Data
x
...
x
The bootloader answers with:
•
“.” & “CR” & “LF” when the data are programmed
•
“X" & “CR" & “LF" if the checksum is wrong
•
“P" & “CR" & “LF" if the Security is set
AT89C51SND1 UART Bootloader
4241B–MP3–07/04
AT89C51SND1 UART Bootloader
Flow Description
Figure 6. Programming Command
Bootloader
Host
Write Command
Send Write Command
Wait Write Command
OR
Checksum Error
Wait Checksum Error
“X” & CR & LF
Send Checksum Error
COMMAND ABORTED
NO_SECURITY
OR
Wait Security Error
“P” & CR & LF
Send Security Error
COMMAND ABORTED
Wait Programming
“.” & CR & LF
Wait COMMAND_OK
Send COMMAND_OK
COMMAND FINISHED
Programming Example
Programming Data (write 55h at address 0010h in the Flash)
HOST
: 01 0010 00 55 9A
BOOTLOADER
: 01 0010 00 55 9A . CR LF
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Reading the Flash Data
The flow described in Figure 7 allows the user to read data in the Flash memory. A blank
check command is possible with this flow.
The device splits into blocks of 16 bytes the data to transfer to the Host if the number of
data to display is greater than 16 data bytes.
Requests from Host
Command Name
Record
Type
Load
Offset
Record
Length
Data[0]
Data[1]
Data[2]
Data[3]
Read Flash
Blank check on
Flash
Note:
Answers from Bootloader
Data[4]
00h
04h
x
05h
Start Address
End Address
01h
The field “Load offset” is not used.
The bootloader answers to a read Flash data memory command:
•
"Address = data " & "CR" & "LF"
up to 16 data by line.
•
"X" & "CR" & "LF" if the checksum is wrong
•
"L" & "CR" & "LF" if the Security is set
The bootloader answers to blank check command:
•
"." & "CR" & "LF" when the blank check is OK
•
"First Address wrong" "CR" & "LF" when the blank check is fail
•
"X" & "CR" & "LF" if the checksum is wrong
•
"P" & "CR" & "LF" if the Security is set
Flow Description
Figure 7. Blank Check Command
Bootloader
Host
Send Blank Check Command
Blank Check Command
Wait Blank Check Command
OR
Wait Checksum Error
Checksum Error
“X” & CR & LF
Send Checksum Error
COMMAND ABORTED
Flash Blank
OR
Wait COMMAND_OK
“.” & CR & LF
Send COMMAND_OK
COMMAND FINISHED
Wait Address not
Erased
Address & CR & LF
Send First Address
Not Erased
COMMAND FINISHED
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AT89C51SND1 UART Bootloader
4241B–MP3–07/04
AT89C51SND1 UART Bootloader
Blank Check Example
Blank Check ok
HOST
: 05 0000 04 0000 7FFF 01 78
BOOTLOADER
: 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ok at address xxxx
HOST
: 05 0000 04 0000 7FFF 01 78
BOOTLOADER
: 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check with checksum error
HOST
: 05 0000 04 0000 7FFF 01 70
BOOTLOADER
: 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
Flow Description
Figure 8. Read Command Flow
Host
Send Display Command
Bootloader
Display Command
Wait Display Command
OR
Wait Checksum Error
Checksum Error
’X’ & CR & LF
Send Checksum Error
COMMAND ABORTED
RD_WR_SECURITY
OR
Wait Security Error
’L’ & CR & LF
Send Security Error
COMMAND ABORTED
Read Data
All Data Read
Complete Frame
Wait Display Data
All Data Read
COMMAND FINISHED
"Address = "
"Reading value"
CR & LF
Send Display Data
All Data Read
COMMAND FINISHED
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Blank Check Example
Display data from address 0000h to 0020h
HOST
Program Configuration
Information
: 05 0000 04 0000 0020 00 D7
BOOTLOADER
: 05 0000 04 0000 0020 00 D7
BOOTLOADER
0000=-----data------ CR LF
(16 data)
BOOTLOADER
0010=-----data------ CR LF
(16 data)
BOOTLOADER
0020=data CR LF
(1 data)
The flow described in Figure 9 allows the user to program Configuration Information
regarding the bootloader functionality.
The Boot Process Configuration:
BSB
SBV
Fuse bits (BLJB and X2 bits) (see Section “Mapping and Default Value of Hardware
Security Byte”, page 3)
SSB
Requests from Host
Command Name
Record
Type
Load
Offset
Erase SBV & BSB
Record
Length
Data[0]
Data[1]
02h
04h
00h
02h
05h
Program SSB level1
00h
Program SSB level2
Program BSB
01h
03h
x
00h
03h
06h
Program SBV
value
01h
Program bit BLJB
04h
03h
Program bit X2
Note:
Data[2]
0Ah
bit value
08h
1. The field “Load Offset” is not used
2. To program the BLJB and X2 bit the “bit value” is 00h or 01h.
Answers from Bootloader
14
The bootloader answers with:
•
“.” & ”CR” & “LF” when the value is programmed
•
“X” & “CR” & “LF” if the checksum is wrong
•
“P” & “CR” & “LF” if the Security is set
AT89C51SND1 UART Bootloader
4241B–MP3–07/04
AT89C51SND1 UART Bootloader
Figure 9. Write Command Flow
Bootloader
Host
Write Command
Send Write Command
Wait Write Command
OR
Checksum Error
Wait Checksum Error
“X” & CR & LF
Send Checksum Error
COMMAND ABORTED
NO_SECURITY
OR
Wait Security Error
“P” & CR & LF
Send Security Error
COMMAND ABORTED
Wait Programming
“.” & CR & LF
Wait COMMAND_OK
Send COMMAND_OK
COMMAND FINISHED
Program Configuration Example
Programming Atmel function (write SSB to level 2)
HOST
: 02 0000 03 05 01 F5
BOOTLOADER
: 02 0000 03 05 01 F5. CR LF
Writing Frame (write BSB to 55h)
HOST
: 03 0000 03 06 00 55 9F
BOOTLOADER
: 03 0000 03 06 00 55 9F . CR LF
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Read Configuration
Information or Manufacturer
Information
The flow described in Figure 10 allows the user to read the configuration or manufacturer information.
Requests from Host
Record
Type
Command Name
Load
Offset
Record
Length
Data[0]
Read Manufacturer Code
Data[1]
00h
Read Family Code
01h
00h
Read Product Name
02h
Read Product Revision
03h
Read SSB
00h
Read BSB
05h
x
02h
07h
Read SBV
01h
02h
Read HSB (Fuse bit)
0Bh
Read Device ID1
00h
00h
0Eh
Read Device ID2
01h
Read bootloader version
Note:
Answers from Bootloader
0Fh
00h
The field “Load Offset” is not used.
The bootloader answers with:
•
“value” & “.” & “CR” & “LF” when the value is programmed
•
“X” & “CR” & “LF” if the checksum is wrong
•
“P” & “CR” & “LF” if the Security is set
Figure 10. Read Command
Bootloader
Host
Send Read Command
Read Command
Wait Read Command
OR
Wait Checksum Error
Checksum Error
“X” & CR & LF
Send Checksum Error
COMMAND ABORTED
RD_WR_SECURITY
OR
Wait Security Error
“L” & CR & LF
Send Security Error
COMMAND ABORTED
Read Value
Wait Value of Data
“value” & “.” & CR & LF
Send Data Read
COMMAND FINISHED
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AT89C51SND1 UART Bootloader
4241B–MP3–07/04
AT89C51SND1 UART Bootloader
Read Example
Read function (read SBV)
HOST
: 02 0000 05 07 02 F0
BOOTLOADER
: 02 0000 05 07 02 F0 Value . CR LF
Atmel Read function (read bootloader version)
Erase the Flash
HOST
: 02 0000 01 02 00 FB
BOOTLOADER
: 02 0000 01 02 00 FB Value . CR LF
The flow described in Figure 11 allows the user to erase the Flash memory.
Two modes of Flash erasing are possible:
•
Full Chip erase
•
Block erase
The Full Chip erase command erases the whole Flash and sets some Configuration
Bytes at their default values:
•
BSB = FFh
•
SBV = F0h
•
SSB = FFh (NO_SECURITY)
The full chip erase is always executed whatever the Software Security Byte value is.
The Block erase command erases only a part of the Flash.
Four Blocks are defined in the AT89C51SND1:
•
block0 (From 0000h to 1FFFh)
•
block1 (From 2000h to 3FFFh)
•
block2 (From 4000h to 7FFFh)
•
block3 (From 8000h to FFFFh)
Requests from Host
Command Name
Record
Type
Load
Offset
Record
Length
Data[0]
Erase block0 (0k to 8k)
00h
Erase block1 (8k to 16k)
20h
02h
Erase block2 (16k to 32k)
03h
01h
x
40h
Erase block2 (32k to 64k)
Full chip erase
Answers from Bootloader
Data[1]
80h
01h
07h
-
As the Program Configuration Information flows, the erase block command has three
possible answers:
•
“.” & “CR” & “LF” when the data are programmed
•
“X” & “CR” & “LF” if the checksum is wrong
•
“P” & “CR” & ”LF” if the Security is set
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Figure 11. Erase Command
Bootloader
Host
Erase Command
Send Erase Command
Wait Erase Command
OR
Checksum Error
Wait Checksum Error
“X” & CR & LF
Send Checksum Error
COMMAND ABORTED
NO_SECURITY
OR
Wait Security Error
“P” & CR & LF
Send Security Error
COMMAND ABORTED
Wait Erasing
“.” & CR & LF
Wait COMMAND_OK
Send COMMAND_OK
COMMAND FINISHED
Example
Full Chip Erase
HOST
: 01 0000 03 07 F5
BOOTLOADER
: 01 0000 03 07 F5 . CR LF
Erase Block1(8k to 16k)
18
HOST
: 02 0000 03 01 20 DA
BOOTLOADER
: 02 0000 03 01 20 DA . CR LF
AT89C51SND1 UART Bootloader
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AT89C51SND1 UART Bootloader
Start the Application
The command described below allows to start the application directly from the bootloader upon a specific command reception.
Two options are possible:
•
Start the application with a reset pulse generation (using watchdog).
When the device receives this command, the watchdog is enabled and the
bootloader enters a waiting loop until the watchdog resets the device.
Take care that if an external reset chip is used, the reset pulse in output may be
wrong and in this case the reset sequence is not correctly executed.
•
Start the application without reset
A jump at the address 0000h is used to start the application without reset.
Requests from Host
Command Name
Record
Type
Load
Offset
03h
x
Start application with a
reset pulse generation
Data[0]
02h
Start application with a
jump at “address”
Answer from Bootloader
Record
Length
Data[1]
Data[2]
Data[3]
00h
03h
04h
01h
Address
No answer is returned by the device.
Start Application Example
Start Application with reset pulse
HOST
: 02 0000 03 03 00 F8
BOOTLOADER
: 02 0000 03 03 00 F8
Start Application without reset at address 0000h
HOST
: 04 0000 03 03 01 00 00 F5
BOOTLOADER
: 04 0000 03 03 01 00 00 F5
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In-Application
Programming/SelfProgramming
The IAP allows to reprogram the microcontroller’s on-chip Flash memory without removing it from the system and while the embedded application is running.
The user application can call some Application Programming Interface (API) routines
allowing IAP. These API are executed by the bootloader.
To call the corresponding API, the user must use a set of Flash_api routines which can
be linked with the application.
Example of Flash_api routines are available on the Atmel web site on the software application note:
–
C Flash Drivers for the AT89C51SND1.
The flash_api routines on the package work only with the UART bootloader.
The flash_api routines are listed in APPENDIX B.
API Call
Process
The application selects an API by setting R1, ACC, DPTR0 and DPTR1 registers.
All calls are made through a common interface “USER_CALL” at the address FFF0h.
The jump at the USER_CALL must be done by LCALL instruction to be able to comeback in the application.
Before jump at the USER_CALL, the bit ENBOOT in AUXR1 register must be set.
Constraints
The interrupts are not disabled by the bootloader.
Interrupts must be disabled by user prior to jump to the USER_CALL, then re-enabled
when returning.
The user must take care of hardware watchdog before launching a Flash operation.
For more information regarding the Flash writing time refer to the AT89C51SND1
datasheet.
API Commands
Read/Program Flash Memory
Several types of APIs are available:
•
Read/Program Flash Data memory
•
Read Configuration and Manufacturer Information
•
Program Configuration Information
•
Erase Flash
•
Start bootloader
All routines to access Flash data are managed directly from the application without
using bootloader resources.
To read the Flash memory the bootloader is not involved.
For more details on these routines see the AT89C51SND1 Datasheet sections “Program/Code Memory”.
Two routines are available to program the Flash:
20
–
__api_wr_code_byte
–
__api_wr_code_page
AT89C51SND1 UART Bootloader
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AT89C51SND1 UART Bootloader
•
The application program loads the column latches of the Flash then calls the
__api_wr_code_byte or __api_wr_code_page see datasheet in section
“Program/Code Memory ”.
•
Parameter Settings
API_name
R1
DPTR0
__api_wr_code_byte
02h
Address in Flash memory to write
09h
Address of the first Byte to program in
the Flash memory
__api_wr_code_page
•
•
Value to write
Address in
XRAM of the
first data to
program
Number of Bytes
to program
No special resources are used by the bootloader during this operation
Parameter Settings
API_name
R1
DPTR0
DPTR1
ACC
__api_rd_HSB
0Bh
0000h
x
return HSB
__api_rd_BSB
07h
0001h
x
return BSB
__api_rd_SBV
07h
0002h
x
return SBV
__api_rd_SSB
07h
0000h
x
return SSB
__api_rd_manufacturer
00h
0000h
x
return
manufacturer id
__api_rd_device_id1
00h
0001h
x
return id1
__api_rd_device_id2
00h
0002h
x
return id2
__api_rd_device_id3
00h
0003h
x
return id3
__api_rd_bootloader_v
ersion
0Fh
0000h
x
return version
value
•
Instruction: LCALL FFF0h.
•
At the complete API execution by the bootloader, the value to read is in the
api_value variable.
Note:
Program Configuration
Information
ACC
Instruction: LCALL FFF0h.
Note:
Read Configuration and
Manufacturer Information
DPTR1
•
No special resources are used by the bootloader during this operation.
Parameter Settings
API_name
R1
DPTR0
DPTR1
ACC
__api_set_X2
0Ah
0008h
x
00h
__api_clr_X2
0Ah
0008h
x
01h
__api_set_BLJB
0Ah
0004h
x
00h
__api_clr_BLJB
0Ah
0004h
x
01h
__api_wr_BSB
06h
0000h
x
value to write
__api_wr_SBV
06h
0001h
x
value to write
__api_wr_SSB_LEVEL0
05h
FFh
x
x
21
4241B–MP3–07/04
•
Parameter Settings (Continued)
API_name
R1
DPTR0
DPTR1
ACC
__api_wr_SSB_LEVEL1
05h
FEh
x
x
05h
FCh
x
x
__api_wr_SSB_LEVEL2
•
Instruction: LCALL FFF0h.
Note:
1. Refer to the AT89C51SND1 datasheet for information on write operation timing.
2. No special resources are used by the bootloader during these operations.
Erase Flash
The AT89C51SND1 Flash memory is divided in four blocks:
Block 0: from address 0000h to 1FFFh (64 pages)
Block 1: from address 2000h to 3FFFh (64 pages)
Block 2: from address 4000h to 7FFFh (128 pages)
Block 3: from address 8000h to FFFFh (256 pages)
•
Parameter Settings
API_name
R1
DPTR0
DPTR1
ACC
0000h
x
x
2000h
x
x
__api_erase_block2
4000h
x
x
__api_erase_block3
8000h
x
x
__api_erase_block0
__api_erase_block1
01h
•
Instruction: LCALL FFF0h.
Note:
1. Refer to the AT89C51SND1 datasheet for information on write operation timing and
multiply this timing by the number of pages.
2. No special resources are used by the bootloader during these operations
Start Bootloader
22
This routine allows to start at the beginning of the bootloader as after a reset. After calling this routine the regular boot process is performed and the communication must be
opened before any action.
•
No special parameter setting
•
Set bit ENBOOT in AUXR1 register
•
instruction: LJUMP or LCALL at address F000h
AT89C51SND1 UART Bootloader
4241B–MP3–07/04
AT89C51SND1 UART Bootloader
Appendix A
Table 6. Summary of Frames From Host
Command
Record
Type
Record
Length
Offset
Data[0]
Data[1]
Data[2]
Data[3]
Data[4]
nb of data
start
address
x
x
x
x
x
00h
–
–
–
20h
–
–
–
Erase block2 (4000h-7FFFh)
40h
–
–
–
Erase block3 (8000h-FFFFh)
80h
–
–
–
00h
–
–
–
Program Nb Data Byte in Flash.
00h
(up to 128)
Erase block0 (0000h-1FFFh)
Erase block1 (2000h-3FFFh)
02h
Start application with a reset pulse
generation
02h
x
01h
x
03h
Start application with a jump at
“address”
Erase SBV & BSB
04h
03h
Program SSB level 1
x
x
02h
01h
04h
x
address
–
00h
–
–
–
00h
–
–
–
01h
–
–
–
00h
value
–
–
01h
value
–
–
-
–
–
–
04h
bit value
–
–
08h
bit value
–
–
05h
Program SSB level 2
x
Program BSB
x
03h
Program SBV
06h
x
Full Chip Erase
01h
Program bit BLJB
x
07h
x
03h
Program bit X2
0Ah
x
Read Flash
00h
04h
05h
x
Start Address
End Address
Blank Check
01h
Read Manufacturer Code
00h
–
–
–
01h
–
–
–
Read Product Name
02h
–
–
–
Read Product Revision
03h
–
–
–
Read SSB
00h
–
–
–
01h
–
–
–
02h
–
–
–
00h
–
–
–
00h
–
–
–
01h
–
–
–
00h
–
–
–
Read Family Code
00h
Read BSB
05h
02h
x
07h
Read SBV
Read Hardware Byte
0Bh
Read Device Boot ID1
0Eh
Read Device Boot ID2
Read bootloader Version
0Fh
23
4241B–MP3–07/04
Appendix B
Table 7. API Summary
Function_Name
Bootloader
Execution
R1
DPTR0
DPTR1
ACC
__api_rd_code_byte
no
__api_wr_code_byte
yes
02h
Address in Flash
memory to write
–
Value to write
__api_wr_code_page
yes
09h
Address of first Byte to
program in Flash
memory
Address in XRAM of
the first data to
program
Number of Byte to program
__api_erase_block0
yes
01h
0000h
x
x
__api_erase_block1
yes
01h
2000h
x
x
__api_erase_block2
yes
01h
4000h
x
x
__api_erase_block3
yes
01h
8000h
x
x
__api_rd_HSB
yes
0Bh
0000h
x
return value
__api_set_X2
yes
0Ah
0008h
x
00h
__api_clr_X2
yes
0Ah
0008h
x
01h
__api_set_BLJB
yes
0Ah
0004h
x
00h
__api_clr_BLJB
yes
0Ah
0004h
x
01h
__api_rd_BSB
yes
07h
0001h
x
return value
__api_wr_BSB
yes
06h
0000h
x
value
__api_rd_SBV
yes
07h
0002h
x
return value
__api_wr_SBV
yes
06h
0001h
x
value
__api_erase_SBV
yes
06h
0001h
x
FCh
__api_rd_SSB
yes
07h
0000h
x
return value
__api_wr_SSB_level0
yes
05h
00FFh
x
x
__api_wr_SSB_level1
yes
05h
00FEh
x
x
__api_wr_SSB_level2
yes
05h
00FCh
x
x
__api_rd_manufacturer
yes
00h
0000h
x
return value
__api_rd_device_id1
yes
00h
0001h
x
return value
__api_rd_device_id2
yes
00h
0002h
x
return value
__api_rd_device_id3
yes
00h
0003h
x
return value
__api_rd_bootloader_version
yes
0Fh
0000h
x
return value
__api_start_bootloader
no
–
–
–
–
24
AT89C51SND1 UART Bootloader
4241B–MP3–07/04
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/xM