ICST ICS307G-03LF Serially programmable clock source Datasheet

ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
Description
Features
The ICS307-03 is a dynamic, serially programmable
clock source which is flexible and takes up minimal
board space. Output frequencies are programmed via
a 3-wire SPI port.
• Crystal or clock reference input
• 3.3 V CMOS outputs
• Three outputs can be individually configured or shut
An advanced PLL coupled to an array of configurable
output dividers and three outputs allows low-jitter
generation of frequencies from 200 Hz to 270 MHz.
•
•
•
•
•
The device can be reprogrammed during operation,
making it ideal for applications where many different
frequencies are required, or where the output
frequency must be determined at run time. Glitch-free
frequency transitions, where the clock period changes
slightly over many cycles, are possible.
off
Small 16-pin TSSOP package
Reprogrammable during operation
3-wire SPI serial interface
Glitch-free output frequency switching
User selectable charge pump current and damping
resistor
• Power-down control via hardware pin or software
control bit
• Programming word can be generated by ICS
VersaClock II Software
• Directly programmable via VersaClock II Software
and a Windows PC parallel port
• Available in Pb (lead) free package
Block Diagram
Charge Pump
(Table 3)
Resistor
(Table 4)
(Table 1)
X1
REF Divide
1-2055
CP
11pF
300
pF
[Bit 122]
Divider
2 - 8232
CLK1
[Bit 110]
(Table 5)
VCO DIVIDE
12-2055
X2
(Table 2)
1
0
DIN
CS
SCLK
[Bit 123]
Programming
Register
(132 bits)
1
(Table 6)
0
Divider
2 - 34
[Bit 124]
(Table 7)
CLK2
[Bit 111]
CLK3
[Bit 129]
1
MDS 307-03 C
I n t e gra te d C i r c u i t S y s t e m s
Divider
2 - 34
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ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
Pin Assignment
1
16
X2
VDD
2
15
PD
VDD
3
14
CLK3
VDD
4
13
GND
GND
5
12
CLK2
ICS307-03
X1
GND
6
11
DIN
GND
7
10
CS
CLK1
8
9
SCLK
16-pin TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
X1
XI
2
VDD
Power
Power connection for crystal oscillator.
3
VDD
Power
Power connection for PLL.
4
VDD
Power
Power connection for inputs and outputs.
5
GND
Power
Ground connection for crystal oscillator.
6
GND
Power
Ground connection for PLL.
7
GND
Power
Ground connection for inputs and outputs.
8
CLK1
Output
Clock 1 output.
9
SCLK
Input
Programming interface - Serial clock input. Internal pull-up.
10
CS
Input
Programming interface - LOAD input. Internal pull-down.
11
DIN
Input
Programming interface - Serial data input. Internal pull-up.
12
CLK2
Output
Clock 2 output.
13
GND
Power
Ground connection.
14
CLK3
Output
Clock 3 output.
15
PD
Input
16
X2
-
Connect to input reference clock or crystal.
Crystal, PLL, and outputs are powered-down when low. Internal pull-up.
Connect to crystal. Leave open if reference clock input is used.
2
MDS 307-03 C
In te grated Circuit Systems
Pin Description
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Table 1. Input Divider
Divide Value
12
11
10
9
8
7
Bits
6
5
4
3
2
1
0
Rule
1
X
X
X
X
X
X
X
X
X
X
X
0
0
1+ Bit 0
2
X
X
X
X
X
X
X
X
X
X
X
0
1
1 + Bit 0
3
X
X
X
X
X
X
X
1
1
1
0
1
0
4
X
X
X
X
X
X
X
1
1
0
1
1
0
5
X
X
X
X
X
X
X
1
1
0
0
1
0
6
X
X
X
X
X
X
X
1
0
1
1
1
0
subtract 2 from the
desired value, convert to
binary, invert, and apply
to bits 5...2
Bits [1..0] = 10
7
X
X
X
X
X
X
X
1
0
1
0
1
0
8
X
X
X
X
X
X
X
1
0
0
1
1
0
9
X
X
X
X
X
X
X
1
0
0
0
1
0
10
X
X
X
X
X
X
X
0
1
1
1
1
0
11
X
X
X
X
X
X
X
0
1
1
0
1
0
12
X
X
X
X
X
X
X
0
1
0
1
1
0
13
X
X
X
X
X
X
X
0
1
0
0
1
0
14
X
X
X
X
X
X
X
0
0
1
1
1
0
15
X
X
X
X
X
X
X
0
0
1
0
1
0
16
X
X
X
X
X
X
X
0
0
0
1
1
0
17
X
X
X
X
X
X
X
0
0
0
0
1
0
18
0
0
0
0
0
0
0
1
0
1
0
1
1
19
0
0
0
0
0
0
0
1
0
1
1
1
1
20
0
0
0
0
0
0
0
1
1
0
0
1
1
21
0
0
0
0
0
0
0
1
1
0
1
1
1
2054
1
1
1
1
1
1
1
1
1
1
0
1
1
2055
1
1
1
1
1
1
1
1
1
1
1
1
1
subtract 8 from the
desired divide value,
convert to binary, and
apply to bits 11...2
Bits [1..0] = 11
…
Table 2. VCO Divider
Bits
23
22
21
20
19
18
17
16
15
14
13
Rule
12
0
0
0
0
0
0
0
0
1
0
0
13
0
0
0
0
0
0
0
0
1
0
1
14
0
0
0
0
0
0
0
0
1
1
0
subtract 8 from the desired
divide value, convert to
binary, and apply to bits
23...13
2054
1
1
1
1
1
1
1
1
1
1
0
2055
1
1
1
1
1
1
1
1
1
1
1
…
Divide Value
3
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SERIALLY PROGRAMMABLE CLOCK SOURCE
Table 3. Charge Pump Current
Charge Pump Current (µA)
1.25
2.5
2.5
3.75
3.75
5
5
5
6.25
7.5
7.5
7.5
70
10
10
10
11.25
12.5
15
15
15
17.5
18.75
20
20
22.5
25
26.25
30
30
35
40
93
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
92
1
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
0
1
0
0
Bits
91
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
1
0
0
0
1
1
0
0
1
0
127
0
0
1
0
0
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
1
0
0
1
1
1
128
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Rule
Icp = ([127...128]+1)*1.25µA*([93 92 91] + 1)
Table 4. Loop Filter Resistor
Bits
Resistor Value
89
90
64 k
0
0
52 k
0
1
16 k
1
0
4k
1
1
4
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In te grated Circuit Systems
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Table 5. Output Divider for Output 1
Divide
Value
2
3
4
5
6
7
8
9
10
11
12
13
14
15
36
37
38
39
…
1029
1030
1032
…
2056
2058
2060
2064
…
4112
4116
4120
4128
…
8224
8232
109 108 107 106 105 104 103
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
(increments of 1)
1
1
1
0
1
1
0
1
1
(increments of 2)
1
1
1
1
1
1
0
1
1
0
1
1
(increments of 4)
1
1
1
1
1
1
0
1
1
0
1
1
(increments of 8)
1
1
1
1
1
1
Bits
102 101 100 99 98 97 96 95 Rule
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
1
X
1
X
1
1
X
X
X
X
X
X
1
X
1
X
1
X
0
0
X
X
X
X
X
X
1
X
0
X
0
X
1
1
X
X
X
X
X
0
0
1
1
0
0
1
1
1
0
0
1
X
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
0
0
X
X
0
0
X
X
1
1
X
X
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
0
0
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
apply Rule from Divide Values 14-37
apply Rule from Divide Values 14-37
subtract 6 from the desired
divide value, convert to binary,
invert, and apply to bits 102..98
set bits [97..95] = 100
output divide =
((([109..101]+3)*2)+[98])*2^[100
set bits [95..97] = 101 †
(† this Rule applies to Divide
Values 38-8232)
5
MDS 307-03 C
In te grated Circuit Systems
apply Rule from Divide Values 14-37
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SERIALLY PROGRAMMABLE CLOCK SOURCE
Table 6. Output Divider for Output 2
Divide Value
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
117
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
116
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Bits
115
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
114
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
113
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rule
output divide = ([117..114]+2)*2^[113])
94
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rule
output divide = ([121..118]+2)*2^[94])
Table 7. Output Divider for Output 3
Divide Value
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
121
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Bits
119
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
118
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
6
MDS 307-03 C
In te grated Circuit Systems
120
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
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Table 8. Miscellaneous Control Bits
Bit
24~88
110
111
112
122
123
124
125
126
129
130
131
Function
Reserved—set to 0
OE1—set to 1 to enable CLK1
OE2—set to 1 to enable CLK2
1 = Normal Operation, 0 = power down feedback counter, charge pump and VCO
Crystal Input = 1, Clock Input = 0
Selects source for CLK2 (see block diagram)
Selects source for CLK3 (see block diagram)
Reserved—set to 0
Reserved—set to 0
OE3—set to 1 to enable CLK3
Reserved—set to 0
Reserved—set to 0
External Components
The ICS307-03 requires a minimum number of external components for proper operation.
Decoupling Capacitors
TheICS307-03 requires 0.01µF decoupling capacitors to be connected between each VDD pin and the Ground
Plane. The 0.01µF capacitors must be placed as close to the ICS307-03’s power pins as possible to minimize lead
inductance.
Output Termination
The ICS307-03 has advanced output pads that allows the device to achieve very high speed (270 MHz) operation
with single ended clock outputs. The clock outputs on the ICS307-03 are designed to be directly connected to a 50
Ohm transmission line without the need for any series resistors.
Crystal Selection
A parallel resonant, fundamental mode crystal with a load (correlation) capacitance of 12 C should be used. For
crystals with a specified load capacitance greater than 12, additional crystal capacitors may be connected from
each of the pins X1 and X2 to ground as shown in the Block Diagram on page 1. The value (in pF) of these crystal
caps should be = (CL-12)*2, where CL is the crystal load capacitance in pF and C is the capacitance value from
Table 4.
For a single ended clock input, connect it to X1 and leave X2 unconnected with no capacitors on either pin.
7
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ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
Initial Output Frequency
ICS307-03 on-chip registers are initially configured to provide a 1x output clock on the CLK1 output, and 0.5x clock
on CLK2 and CLK3. The output frequency will be the same as the input clock or crystal for input frequencies from
10 - 50 MHz. This is useful when the ICS307-03 needs to provide an initial system clock at power-up.
Determining and Controlling the Output Frequency with VersaClockTM II
The ICS307-03 is directly supported by the ICS provided software called VersaClock II. Complete programming
words for this device can be calculated on any Windows PC by running the VersaClock II software and simple
inputting desired input and output frequencies. Once the software generates an appropriate programming word, it
may then be either copied to the Windows clipboard or even directly programmed into the ICS307-03 via the host
computers parallel port.
For more information on VersaClock II, please visit www.icst.com or send an e-mail to [email protected].
Manually Determining the Output Frequency
The user has full control over the desired output frequency as long as it is operated within the limits shown in the
AC Electrical Characteristics.
The output of the ICS307-03 can be determined by the following equation:
V
CLK1Frequency = InputFrequency ⋅ -----------------R ⋅ OD
Where:
VCO Divider (V) = 12 to 2055
Reference Divider Word (R) = 1 to 2055
Output Divider = values in tables 5, 6, 7
Also, the following operating ranges should be observed.
V
VCOmin < InputFrequency ⋅ ---- < VCOmaxfreq
R
Input Frequency
20kHz < ------------------------------------------- < 100MHz
R
To determine the best combination of VCO, reference, and output dividers, please use the VersaClock II software
mentioned above. If more information is needed, please contact ICS by sending an e-mail to [email protected].
8
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In te grated Circuit Systems
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ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
Programming Interface
The dynamic register within the ICS307-03 controls the entire device and may be reprogrammed any time
after power is properly applied. If V or R values are changed, the frequency will transition smoothly to the
new value without glitches or short cycles. However, changing any divider or mux in the output signal path
may generate a glitch.
The register is 132 bits in length and accepts the MSB first. The SCLK signal latches the current data bit
value in the rising edge of It latches the most recently shifted 132 bit values into the control register of
device whenever CS is high. Care must be taken to ensure that CS is always low until the system is ready
to load in a new register value and that SCLK is never toggled high when CS is high.
The register can be programmed any time after power is applied, even while in power-down (pin 15 or bit
112 held low) with the waveform and timing shown below:.
Figure 2: ICS307-03 Programming Timing Diagram
DIN
131
130
129
tsetup
128
2
1
0
thold
SCLK
tw
ts
CS
Table 8: AC Parameters for Programming the ICS307-03
Parameter
Condition
Min.
tSETUP
Setup time
2.5
ns
tHOLD
Hold time after SCLK
2.5
ns
tW
Data wait time
2.5
ns
tS
Strobe pulse width
10
ns
SCLK Frequency
Max.
Units
200
MHz
Programming with VersaClock Software
The VersaClock II Software not only generates the programming word for the user, it can also be used to program
the device via the host computer’s parallel port. Demonstration boards are available from ICS that allows the
VersaClock II S/W to directly connect the ICS307-03 to a Windows based PC’s DB-25 parallel port connector and
programmed simply by pressing the “Program Part” button.
Contact [email protected] for more details.
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MDS 307-03 C
In te grated Circuit Systems
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ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS307-03. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability.
Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
5V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Storage Temperature
-65 to +150°C
Soldering Temperature
260°C
Recommended Operating Conditions
Parameter
Min.
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Typ.
Max.
Units
0
+70
°C
+3.0
+3.6
V
DC Electrical Characteristics
VDD=3.3 V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Operating Voltage
VDD
3.0
Input High Voltage
VIH
2
Input Low Voltage
VIL
Output High Voltage
VOH
IOH = -4 mA
Output Low Voltage
VOL
IOL = 4 mA
Output High Voltage,
CMOS level
VOH
IOH = -6.5 mA
IDD
Short Circuit Current
Max.
Units
3.6
V
V
0.8
2.4
V
V
0.4
VDD-0.4
Tri-state Output Leakage
Operating Supply Current
Typ.
V
V
1
µA
27 MHz crystal
No load, 100 MHz out,
all outputs enabled
24
mA
CLK outputs
±60
mA
Input Capacitance
CIN
4
pF
On-Chip Pull-up Resistor
RPU
240
kΩ
On-Chip Pull-down
Resistor
RPD
100
kΩ
10
MDS 307-03 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 101705
●
tel (4 08) 297 -1 201
●
w w w. i c s t . c o m
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
AC Electrical Characteristics
VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Input Frequency
Symbol
FIN
Clock Output Frequency
Output Clock Rise/Fall Time
Conditions
Min.
Max.
Units
3
0.1
27
300
MHz
MHz
5 pF load
0.0002
270
MHz
15 pF load
0.0002
200
MHz
Fundamental crystal
Clock
FOUT
tR, tF
20 to 80% (5 pF load)
Output Clock Duty Cycle
Typ.
1.5
Output Divides <> 3
45
Output Divide = 3
40
ns
49-51
55
%
60
%
10
ms
Frequency Transition time
STROBE high to CLK
out
3
One Sigma Clock Period Jitter
Note 2
50
ps
±120
ps
Maximum Absolute Jitter
VCO Frequency
tja
Deviation from mean,
Note 2
100
730
MHz
Output divider 1 = 2
(5 pF load)
540
MHz
Output divider 1 = 2
(15 pF load)
400
MHz
Output divider 1 = 3
(5 pF load)
720
MHz
Output divider 1 = 3
(15 pF load)
600
MHz
Output divider 1 = 38
~ 1029
570
MHz
All other Output
Divider 1 values
730
MHz
Output divider 2, 3 = 2
(5 pF load)
540
MHz
Output divider 2, 3 = 2
(15 pF load)
400
MHz
Output divider 2, 3=12
440
MHz
Output divider 2, 3 =
16, 24, 28 and 32
500
MHz
All other Output
Divider 2 & 3 values
730
MHz
VCOF
Divider 1 Input
Divider 2 and 3 Inputs
Note 1: Measured with 15 pF load.
Note 2: Jitter performance will change depending on configuration settings.
11
MDS 307-03 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 101705
●
tel (4 08) 297 -1 201
●
w w w. i c s t . c o m
ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
16
Symbol
E1
E
IN D EX
AR EA
1
2
D
A
2
Min
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
Inches
Max
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Min
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
A
A
1
c
-C e
S E A T IN G
P LA N E
b
L
aaa C
Ordering Information
Part / Order Number
ICS307G-03
ICS307G-03T
ICS307G-03LF
ICS307G-03LFT
Marking
ICS307G-03
ICS307G-03
307G-03LF
307G-03LF
Shipping packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
Package
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
Temperature
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
12
MDS 307-03 C
In te grated Circuit Systems
●
525 Ra ce Street, San Jose, CA 9512 6
Revision 101705
●
tel (4 08) 297 -1 201
●
w w w. i c s t . c o m