FastEdge™ Series CY2PP3220 Dual 1:10 Differential Clock/Data Fanout Buffer Features Functional Description • Two sets of ten ECL/PECL differential outputs • Two ECL/PECL differential inputs • Hot-swappable/-insertable • 50 ps output-to-output skew • 150 ps device-to-device skew • 500 ps propagation delay (typical) • 1.5 GHz Operation (2.7 GHz max. toggle frequency) • PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V • ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5% with VCC = 0V • Industrial temperature range: –40°C to 85°C • 52-pin 1.4-mm TQFP package • Temperature compensation like 100K ECL The CY2PP3220 is a low-skew, low propagation delay dual 1-to-10 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths that are differential internally. The CY2PP3220 may function not only as a differential clock buffer but also as a signal-level translator and fanout on ECL/PECL signal to twenty ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to ground via a 0.01-µF capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single-ended input that might have a different self-bias point. Since the CY2PP3220 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2PP3220 delivers consistent performance over various platforms. • Pin compatible with MC100ES6220 CLKA VCC CLKA# VEE VCC 3901 North First Street VCC QA5# QA5 QA4# QA4 QA3# QA3 QA2# 34 QA8# CLKB 7 33 QA9 CLKB# 8 32 QA9# VEE QB9# 9 31 QB0 10 30 QB0# QB9 11 29 QB1 QB8# 12 28 QB1# • CY2PP3220 San Jose, CA 95134 VCC QB2 QB2# QB3 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 QB3# QB8 VCC • QA2 6 VBB Cypress Semiconductor Corporation Document #: 38-07513 Rev.*C QA1# QA8 VBB QB4 QB9 QB9# 35 QB4# V EE 5 QB5 V EE QA7# CLKA# QB5# CLKB# QA7 36 QB6 CLKB QA6# 4 QB6# QB0 QB0# V CC QA6 CLKA QB7 QA9 QA9# 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 38 2 37 3 QB7# V EE V EE QA1 QA0 QA0# V CC QA0# QA0 Pin Configuration Block Diagram • 408-943-2600 Revised July 28, 2004 FastEdge™ Series CY2PP3220 Pin Definitions[1, 2, 3] Pin Name I/O 4 CLKA, 5 CLKA# I,PD 6 VBB[3] O 7 CLKB, I,PD 8 CLKB# 3,9 VEE[2] –PWR 1,2,14,27,40 VCC +PWR Type Description ECL/PECL ECL/PECL Differential input clocks I,PD/PU ECL/PECL ECL/PECL Differential input clocks Bias Reference Voltage Output ECL/PECL ECL/PECL Differential input clocks I,PD/PU ECL/PECL ECL/PECL Differential input clocks Power Negative Supply Power Positive Supply 52,50,48,46,44,42,39,37, QA(0:9) 35,33 O ECL/PECL True output 51,49,47,45,43,41,38,36, QA#(0:9) 34,32 O ECL/PECL Complement output 31,29,26,24,22,20,18,16, QB(0:9) 13,11 O ECL/PECL True output 30,28,25,23,21,19,17,15, QB#(0:9) 12,10 O ECL/PECL Complement output Governing Agencies The following agencies provide specifications that apply to the CY2PP3220. The agency name and relevant specification is listed below in Table 2. Table 1. Agency Name Specification JEDEC JESD 020B (MSL) JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–B (skew,jitter) Mil-Spec 883E Method 1012.1 (Thermal Theta JC) Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power 2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. 3. VBB is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|). Document #: 38-07513 Rev.*C Page 2 of 9 FastEdge™ Series CY2PP3220 Absolute Maximum Ratings Parameter Description Condition Min. Max. Unit VCC Positive Supply Voltage Non-Functional –0.3 4.6 V VEE Negative Supply Voltage Non-Functional -4.6 0.3 V TS Temperature, Storage Non-Functional –65 +150 °C TJ Temperature, Junction Non-Functional 150 °C ESDh ESD Protection Human Body Model MSL Moisture Sensitivity Level Gate Count Total Number of Used Gates 2000 V 3 N.A. 50 gates Assembled Die Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Operating Conditions Parameter Description Condition IBB Output Reference Current LUI Latch Up Immunity Functional, typical TA Temperature, Operating Ambient Functional Relative to VBB Min. Max. Unit – |200| uA 100 mA –40 +85 ØJc Dissipation, Junction to Case Functional 22[4] ØJa Dissipation, Junction to Ambient Functional 60[4] IEE Maximum Quiescent Supply Current CIN Input pin capacitance LIN Pin Inductance VIN Input Voltage VEE pin[5] 250 VTT Output Termination Voltage Relative to VCC Output Voltage Relative to VCC[6] IIN Input °C/W 3 pF – 1 nH –0.3 VCC + 0.3 V [6] VOUT °C/W mA – Relative to VCC[6] Current[7] °C VCC – 2 –0.3 VIN = VIL, or VIN = VIH V VCC + 0.3 V l150l uA PECL DC Electrical Specifications Parameter Description Condition VCC Operating Voltage 2.5V ± 5%, VEE = 0.0V 3.3V ± 5%, VEE = 0.0V VCMR Differential Cross Point Voltage[8] Differential operation mA[9] Min. Max. Unit 2.375 3.135 2.625 3.465 V V 1.2 VCC V VCC – 1.25 VCC – 0.7 V VCC – 1.995 VCC –1.995 VCC – 1.5 VCC – 1.3 V V VOH Output High Voltage IOH = –30 VOL Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% IOL = –5 mA[9] VIH Input Voltage, High Single-ended operation VCC – 1.165 VCC – 0.880 [10] V VIL Input Voltage, Low Single-ended operation VCC – 1.945 [10] VCC – 1.625 V VBB[3] Output Reference Voltage Relative to VCC[6] VCC – 1.620 VCC – 1.220 Notes: 4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1 5. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip. 6. where VCC is 3.3V±5% or 2.5V±5% 7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current. 8. Refer to Figure 1 9. Equivalent to a termination of 50Ω to VTT. IOHMIN=(VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50; 10. VIL will operate down to VEE; VIH will operate up to VCC Document #: 38-07513 Rev.*C V Page 3 of 9 FastEdge™ Series CY2PP3220 ECL DC Electrical Specifications Parameter Description Condition VEE Negative Power Supply VCMR Differential cross point voltage[8] Differential operation VOH Output High Voltage IOH = –30 mA[9] VOL Output Low Voltage VEE = –3.3V ± 5% VEE = –2.5V ± 5% IOL = –5 mA[9] VIH Input Voltage, High Single-ended operation –2.5V ± 5%, VCC = 0.0V –3.3V ± 5%, VCC = 0.0V VIL Input Voltage, Low VBB[3] Output Reference Voltage Single-ended operation Min. Max. Unit –2.625 –3.465 –2.375 –3.135 V VEE + 1.2 0V V –1.25 –0.7 V –1.995 –1.995 –1.5 –1.3 V –1.165 –0.880 [10] V [10] –1.945 –1.625 V – 1.620 – 1.220 V Min. Max. Unit 0.1 1.3 V 1.5 GHz 400 750 ps 0.375 – V AC Electrical Specifications Parameter Description Voltage[8] Condition VPP Differential Input FCLK Input Frequency 50% duty cycle Standard load TPD Propagation Delay CLKA or CLKB to Output pair 660 MHz [11] Vo Output Voltage (peak-to-peak; see Figure 2) < 1 GHz VCMRO Output Common Voltage Range (typ.) tsk(0) Output-to-output Skew 660 MHz [11], See Figure 3 – 50 ps tsk(PP) Part-to-Part Output Skew 660 MHz [11] – 150 ps 660 MHz [11] – 1.2 ps – 50 ps 0.08 0.3 ns TPER Output Period Jitter (rms)[12] Skew[13] tsk(P) Output Pulse TR,TF Output Rise/Fall Time (see Figure 2) Differential operation VCC – 1.425 660 MHz [11], See Figure 3 660 MHz 50% duty cycle Differential 20% to 80% V Timing Definitions VCC VCM R Max = VCC VIH VPP VPP range 0.1V - 1.3V VCM R VIL VCMR M in = VEE + 1.2 VEE Figure 1. PECL/ECL Input Waveform Definitions Notes: 11. 50% duty cycle; standard load; differential operation 12. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000 data points 13. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. Document #: 38-07513 Rev.*C Page 4 of 9 FastEdge™ Series CY2PP3220 tr, tf, 20-80% VO Figure 2. ECL/LVPECL Output In p u t C lo c k V P P TP L H , TP H L T P D O u tp u t C lo c k V O tS K (O ) A n o th e r O u tp u t C lo c k Figure 3. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O)) for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL Test Configuration Standard test load using a differential pulse generator and differential measurement instrument. VTT VTT RT = 50 ohm RT = 50 ohm P u ls e G e n e ra to r Z = 50 ohm 5" Zo = 50 ohm Zo = 50 ohm 5" RT = 50 ohm DUT CY2PP3220 VTT RT = 50 ohm VTT Figure 4. CY2PP3220 AC Test Reference Document #: 38-07513 Rev.*C Page 5 of 9 FastEdge™ Series CY2PP3220 Applications Information Termination Examples CY2PP3220 VTT VCC RT = 50 ohm 5" Zo = 50 ohm 5" RT = 50 ohm VTT VEE Figure 5. Standard LVPECL – PECL Output Termination CY2PP3220 VTT RT = 50 ohm VCC 5" Zo = 50 ohm 5" VTT R T = 50 ohm V B B (3 .3 V ) VEE Figure 6. Driving a PECL/ECL Single-ended Input CY2PP3220 3 .3 V V C C = 3 .3 V 120 ohm LVDS 5" Zo = 50 ohm 33 ohm ( 2 p la c e s ) 5" 120 ohm 3 .3 V VEE = 0V 51 ohm ( 2 p la c e s ) L V P E C L to LVDS Figure 7. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface Document #: 38-07513 Rev.*C Page 6 of 9 FastEdge™ Series CY2PP3220 VDD-2 VCC X Y Z One output is shown for clarity Figure 8. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000 Ohms. See application note titled, “PECL Translation, SAW Oscillators, and Specs” for other signalling standards and supplies. Ordering Information Part Number Package Type Product Flow CY2PP3220AI 52-pin TQFP Industrial, –40° to 85°C CY2PP3220AIT 52-pin TQFP – Tape and Reel Industrial, –40° to 85°C Document #: 38-07513 Rev.*C Page 7 of 9 FastEdge™ Series CY2PP3220 Package Drawing and Dimensions 52-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A52 51-85131-** FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07513 Rev.*C Page 8 of 9 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. FastEdge™ Series CY2PP3220 Document History Page Document Title: CY2PP3220 FastEdge™ Series Dual 1:10 Differential Clock/Data Fanout Buffer Document Number: 38-07513 Issue Date Orig. of Change REV. ECN NO. ** 122437 02/13/03 RGL New Data Sheet *A 125459 04/16/03 RGL Interchanged Pin 30 and 31 from QB0 /QB0# to QB0#/QB0 Changed the title to FastEdge™ Series Dual 1:10 Differential Clock/Data Fanout Buffer *B 229372 See ECN RGL Supplied data to all TBD’s to match the device. *C 247613 See ECN Document #: 38-07513 Rev.*C Description of Change RGL/GGK Changed VOH and VOL to match the Char Data Page 9 of 9