TI LT1054I Switched-capacitor voltage converters with regulator Datasheet

 SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
D
D
D
D
D
D
D
D
P PACKAGE
(TOP VIEW)
Output Current . . . 100 mA
Low Loss . . . 1.1 V at 100 mA
Operating Range . . . 3.5 V to 15 V
Reference and Error Amplifier for
Regulation
External Shutdown
External Oscillator Synchronization
Devices Can Be Paralleled
Pin-to-Pin Compatible With the
LTC1044/7660
FB/SD
CAP+
GND
CAP−
1
8
2
7
3
6
4
5
VCC
OSC
VREF
VOUT
DW PACKAGE
(TOP VIEW)
NC
NC
FB/SD
CAP+
GND
CAP−
NC
NC
description/ordering information
The LT1054 is a bipolar, switched-capacitor
voltage converter with regulator. It provides higher
output current and significantly lower voltage
losses than previously available converters. An
adaptive-switch
drive
scheme
optimizes
efficiency over a wide range of output currents.
Total voltage drop at 100-mA output current
typically is 1.1 V. This applies to the full
supply-voltage range of 3.5 V to 15 V. Quiescent
current typically is 2.5 mA.
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
NC
NC
VCC
OSC
VREF
VOUT
NC
NC
NC − No internal connection
The LT1054 also provides regulation, a feature previously not available in switched-capacitor voltage
converters. By adding an external resistive divider, a regulated output can be obtained. This output is regulated
against changes in both input voltage and output current. The LT1054 also can be shut down by grounding the
feedback terminal. Supply current in shutdown typically is 100 µA.
The internal oscillator of the LT1054 runs at a nominal frequency of 25 kHz. The oscillator terminal can be used
to adjust the switching frequency or to externally synchronize the LT1054.
The LT1054C is characterized for operation over a free-air temperature range of 0°C to 70°C. The LT1054I is
characterized for operation over a free-air temperature range of −40°C to 85°C.
ORDERING INFORMATION
PDIP (P)
−40°C
−40
C to 85
85°C
C
SOIC (DW)
PDIP (P)
0°C
0
C to 70
70°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC (DW)
Tube of 50
LT1054IP
Tube of 40
LT1054IDW
Reel of 2000
LT1054IDWR
Tube of 50
LT1054CP
Tube of 40
LT1054CDW
Reel of 2000
LT1054CDWR
TOP-SIDE
MARKING
LT1054IP
LT1054I
LT1054CP
LT1054C
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright  2004, Texas Instruments Incorporated
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functional block diagram
VREF
VCC
6
8
2.5 V
Ref
R
Drive
+
FB/SD
OSC
1
CAP +
−
7
2
CIN†
Q
OSC
CAP −
Q
4
Drive
R
Drive
3
GND
COUT†
5
VOUT
Drive
† External capacitors
Pin numbers shown are for the P package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
Input voltage range, VI: FB/SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VCC
OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to Vref
Junction temperature, TJ (see Note 2): LT1054C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
LT1054I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135°C
Package thermal impedance, θJA (see Notes 3 and 4): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The absolute maximum supply-voltage rating of 16 V is for unregulated circuits. For regulation-mode circuits with VOUT ≤ 15 V, this
rating may be increased to 20 V.
2. The devices are functional up to the absolute maximum junction temperature.
3. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
2
VCC
Supply voltage
TA
Operating free-air temperature range
LT1054C
LT1054I
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MIN
MAX
3.5
15
0
70
−40
85
UNIT
V
°C
SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
VO
Regulated output voltage
VCC = 7 V, TJ = 25°C, RL = 500 Ω, See Note 5
VCC = 7 V to 12 V, RL = 500 Ω, See Note 5
TYP‡
MAX
−4.7
−5.2
5
25
mV
Full range
10
50
mV
0.35
0.55
1.1
1.6
Output resistance
VCC = 7 V, RL = 100 Ω to 500 Ω, See Note 5
IO = 10 mA
CI = CO = 100F tantalum
100-µF
IO = 100 mA
∆IO = 10 mA to 100 mA,
See Note 7
10
15
Ω
Oscillator frequency
VCC = 3.5 V to 15 V
Full range
kHz
Voltage loss,
VCC − |VO (see Note 6)
Reference voltage
I(REF) = 60 µA
A
Maximum switch current
Supply current
25°C
UNIT
MIN
−5
Output regulation
ICC
LT1054C
LT1054I
TA†
Full range
Input regulation
Vref
TEST CONDITIONS
Full range
Full range
15
25
35
25°C
2.35
2.5
2.65
Full range
2.25
25°C
VCC = 3.5 V
VCC = 15 V
IO = 0
Full range
2.75
300
V
V
V
mA
2.5
4
3
5
mA
Supply current in shutdown V(FB/SD) = 0 V
Full range
100
200
µA
† Full range is 0°C to 70°C for the LT1054C and −40°C to 85°C for the LT1054I.
‡ All typical values are at TA = 25°C.
NOTES: 5. All regulation specifications are for a device connected as a positive-to-negative converter/regulator with R1 = 20 kΩ, R2 = 102.5 kΩ,
external capacitor CIN = 10 µF (tantalum), external capacitor COUT = 100 µF (tantalum) and C1 = 0.002 µF (see Figure 15).
6. For voltage-loss tests, the device is connected as a voltage inverter, with terminals 1, 6, and 7 unconnected. The voltage losses
may be higher in other configurations. CIN and COUT are external capacitors.
7. Output resistance is defined as the slope of the curve (∆VO versus ∆IO) for output currents of 10 mA to 100 mA. This represents
the linear portion of the curve. The incremental slope of the curve is higher at currents less than 10 mA due to the characteristics
of the switch transistors.
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Shutdown threshold voltage vs Free-air temperature
1
Supply current vs Input voltage
2
Oscillator frequency vs Free-air temperature
3
Supply current in shutdown vs Input voltage
4
Average supply current vs Output current
5
Output voltage loss vs Input capacitance
6
Output voltage loss vs Oscillator frequency (10 µF)
7
Output voltage loss vs Oscillator frequency (100 µF)
8
Regulated output voltage vs Free-air temperature
9
Reference voltage change vs Free-air temperature
10
Voltage loss vs Output current
11
Table of Figures
FIGURE
4
Switched-Capacitor Building Block
12
Switched-Capacitor Equivalent Circuit
13
Circuit With Load Connected From VCC to VOUT
14
External-Clock System
15
Basic Regulation Configuration
16
Power-Dissipation-Limiting Resistor in Series With CIN
17
Motor-Speed Servo
18
Basic Voltage Inverter
19
Basic Voltage Inverter/Regulator
20
Negative-Voltage Doubler
21
Positive-Voltage Doubler
22
100-mA Regulating Negative Doubler
23
Dual-Output Voltage Doubler
24
5-V to ±12-V Converter
25
Strain-Gage Bridge Signal Conditioner
26
3.5-V to 5-V Regulator
27
Regulating 200-mA +12-V to −5-V Converter
28
Digitally Programmable Negative Supply
29
Positive Doubler With Regulation (5-V to 8-V Converter)
30
Negative Doubler With Regulator
31
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TYPICAL CHARACTERISTICS†
SHUTDOWN THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
INPUT VOLTAGE
0.6
5
0.5
0.4
I CC − Supply Current − mA
Shutdown Threshold Voltage − V
IO = 0
V(FB/SD)
0.3
0.2
3
2
1
0.1
0
−50
4
0
−25
0
25
50
75
100
0
5
10
VCC − Input Voltage − V
TA − Free-Air Temperature − °C
Figure 1
15
Figure 2
OSCILLATOR FREQUENCY
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT IN SHUTDOWN
vs
INPUT VOLTAGE
35
120
Supply Current in Shutdown − µA
Oscillator Frequency − kHz
33
31
29
VCC = 15 V
27
25
VCC = 3.5 V
23
21
19
100
V(FB/SD) = 0
80
60
40
20
17
15
−50
0
−25
0
25
50
75
100
0
TA − Free-Air Temperature − °C
Figure 3
10
5
VCC − Input Voltage − V
15
Figure 4
† Data at high and low temperatures are applicable only within the recommended operating free-air temperature range.
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TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE LOSS
vs
INPUT CAPACITANCE
140
1.4
120
1.2
IO = 100 mA
100
Output Voltage Loss − V
Average Supply Current − mA
AVERAGE SUPPLY CURRENT
vs
OUTPUT CURRENT
80
60
40
20
1.0
0.8
IO = 50 mA
0.6
IO = 10 mA
0.4
Inverter Configuration
COUT = 100-µF Tantalum
fOSC = 25 kHz
0.2
0
0
20
40
60
80
0
100
0
10
Figure 5
2.5
Inverter Configuration
CIN = 10-µF Tantalum
COUT = 100-µF Tantalum
50
60
70
80
90 100
Inverter Configuration
CIN = 100-µF Tantalum
COUT = 100-µF Tantalum
2.25
2
2
Output Voltage Loss − V
Output Voltage Loss − V
40
OUTPUT VOLTAGE LOSS
vs
OSCILLATOR FREQUENCY
2.5
1.75
1.5
IO = 100 mA
1.25
1
IO = 50 mA
0.75
0.5
1.75
1.5
1.25
IO = 100 mA
1
IO = 50 mA
0.75
0.5
IO = 10 mA
0.25
IO = 10 mA
0.25
0
0
1
10
Oscillator Frequency − kHz
100
1
Figure 7
6
30
Figure 6
OUTPUT VOLTAGE LOSS
vs
OSCILLATOR FREQUENCY
2.25
20
Input Capacitance − µF
IO − Output Current − mA
10
Oscillator Frequency − kHz
Figure 8
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TYPICAL CHARACTERISTICS†
REFERENCE VOLTAGE CHANGE
vs
FREE-AIR TEMPERATURE
−4.7
100
−4.8
80
∆V ref − Reference Voltage Change − mV
VO − Regulated Output Voltage − V
REGULATED OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
−4.9
−5
−5.1
−11.6
−11.8
−12
−12.2
−12.4
−12.6
−50
−25
0
25
75
50
60
40
20
0
−20
VREF at 0 = 2.500 V
−40
−60
−80
−100
−50
100
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
Figure 10
Figure 9
VOLTAGE LOSS
vs
OUTPUT CURRENT
2
3.5 V ≤ VCC ≤ 15 V
Ci = Co = 100 µF
1.8
Voltage Loss − V
1.6
TJ = 125°C
1.4
1.2
1
TJ = 25°C
0.8
0.6
0.4
TJ = −55°C
0.2
0
0
10
20
30
40
50
60
70
80
90 100
Output Current − mA
Figure 11
† Data at high and low temperatures are applicable only within the recommended operating free-air temperature range.
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PRINCIPLES OF OPERATION
A review of a basic switched-capacitor building block is helpful in understanding the operation of the LT1054. When
the switch shown in Figure 12 is in the left position, capacitor C1 charges to the voltage at V1. The total charge on
C1 is q1 = C1V1. When the switch is moved to the right, C1 is discharged to the voltage at V2. After this discharge
time, the charge on C1 is q2 = C1V2. The charge has been transferred from the source V1 to the output V2. The
amount of charge transferred is shown in equation 1.
Dq + q1 * q2 + C1(V1 * V2)
(1)
If the switch is cycled f times per second, the charge transfer per unit time (i.e., current) is as shown in equation 2.
I+f
Dq + f
C1(1 * V2)
(2)
To obtain an equivalent resistance for a switched-capacitor network, this equation can be rewritten in terms of voltage
and impedance equivalence as shown in equation 3.
I + V1 * V2 + V1 * V2
ǒ1ńfC1Ǔ
R EQUIV
(3)
V1
V2
f
RL
C1
C2
Figure 12. Switched-Capacitor Building Block
A new variable, REQUIV, is defined as REQUIV = 1 ÷ fC1. The equivalent circuit for the switched-capacitor network is
shown in Figure 13. The LT1054 has the same switching action as the basic switched-capacitor building block. Even
though this simplification does not include finite switch-on resistance and output-voltage ripple, it provides an insight
into how the device operates.
REQUIV
V1
R EQUIV + 1
fC1
V2
C2
RL
Figure 13. Switched-Capacitor Equivalent Circuit
These simplified circuits explain voltage loss as a function of oscillator frequency (see Figure 7). As oscillator
frequency is decreased, the output impedance eventually is dominated by the 1/fC1 term, and voltage losses rise.
Voltage losses also rise as oscillator frequency increases. This is caused by internal switching losses that occur due
to some finite charge being lost on each switching cycle. This charge loss per-unit-cycle, when multiplied by the
switching frequency, becomes a current loss. At high frequency, this loss becomes significant and voltage losses
again rise.
The oscillator of the LT1054 is designed to operate in the frequency band where voltage losses are at a minimum.
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PRINCIPLES OF OPERATION
Supply voltage VCC alternately charges CIN to the input voltage when CIN is switched in parallel with the input supply
and then transfers charge to COUT when CIN is switched in parallel with COUT. Switching occurs at the oscillator
frequency. During the time that CIN is charging, the peak supply current is approximately 2.2 times the output current.
During the time that CIN is delivering a charge to COUT, the supply current drops to approximately 0.2 times the output
current. An input supply bypass capacitor supplies part of the peak input current drawn by the LT1054 and averages
the current drawn from the supply. A minimum input-supply bypass capacitor of 2 µF, preferably tantalum or some
other low equivalent-series-resistance (ESR) type, is recommended. A larger capacitor is desirable in some cases.
An example of this would be when the actual input supply is connected to the LT1054 through long leads or when
the pulse currents drawn by the LT1054 might affect other circuits through supply coupling.
In addition to being the output terminal, VOUT is tied to the substrate of the device. Special care must be taken in
LT1054 circuits to avoid making VOUT positive with respect to any of the other terminals. For circuits with the output
load connected from VCC to VOUT or from some external positive supply voltage to VOUT, an external transistor must
be added (see Figure 14). This transistor prevents VOUT from being pulled above GND during startup. Any small
general-purpose transistor such as a 2N2222 or a 2N2219 device can be used. Resistor R1 should be chosen to
provide enough base drive to the external transistor so that it is saturated under nominal output voltage and maximum
output current conditions.
R1 v
ǒŤV OUTŤǓb
I OUT
(4)
VIN
1
2
CIN
+
3
4
FB/SD
VCC
CAP+
OSC
LT1054
GND
VREF
CAP−
VOUT
8
Load
VOUT
7
R1
6
5
+
COUT
Pin numbers shown are for the P package.
Figure 14. Circuit With Load Connected from VCC to VOUT
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PRINCIPLES OF OPERATION
The voltage reference (Vref) output provides a 2.5-V reference point for use in LT1054-based regulator circuits. The
temperature coefficient (TC) of the reference voltage has been adjusted so that the TC of the regulated output voltage
is near zero. As seen in the typical performance curves, this requires the reference output to have a positive TC. This
nonzero drift is necessary to offset a drift term inherent in the internal reference divider and comparator network tied
to the feedback terminal. The overall result of these drift terms is a regulated output that has a slight positive TC at
output voltages below 5 V and a slight negative TC at output voltages above 5 V. For regulator feedback networks,
reference output current should be limited to approximately 60 µA. Vref draws approximately 100 µA when shorted
to ground and does not affect the internal reference/regulator. This terminal also can be used as a pullup for LT1054
circuits that require synchronization.
CAP+ is the positive side of input capacitor CIN and is driven alternately between VCC and ground. When driven to
VCC, CAP+ sources current from VCC. When driven to ground, CAP+ sinks current to ground. CAP− is the negative
side of the input capacitor and is driven alternately between ground and VOUT. When driven to ground, CAP− sinks
current to ground. When driven to VOUT, CAP− sources current from COUT. In all cases, current flow in the switches
is unidirectional, as should be expected when using bipolar switches.
OSC can be used to raise or lower the oscillator frequency or to synchronize the device to an external clock. Internally,
OSC is connected to the oscillator timing capacitor (Ct ≈ 150 pF), which is charged and discharged alternately by
current sources of ±7 µA, so that the duty cycle is approximately 50%. The LT1054 oscillator is designed to run in
the frequency band where switching losses are minimized. However, the frequency can be raised, lowered, or
synchronized to an external system clock if necessary.
The frequency can be increased by adding an external capacitor (C2 in Figure 15) in the range of 5−20 pF from CAP+
to OSC. This capacitor couples a charge into Ct at the switch transitions. This shortens the charge and discharge
times and raises the oscillator frequency. Synchronization can be accomplished by adding an external pullup resistor
from OSC to Vref. A 20-kΩ pullup resistor is recommended. An open-collector gate or an npn transistor then can be
used to drive OSC at the external clock frequency as shown in Figure 15.
The frequency can be lowered by adding an external capacitor (C1 in Figure 15) from OSC to ground. This increases
the charge and discharge times, which lowers the oscillator frequency.
1
2
FB/SD
VCC
CAP+
OSC
LT1054
+
3
GND
VREF
8
C2
VIN
7
6
C1
4
CAP−
VOUT
5
Pin numbers shown are for the P package.
Figure 15. External-Clock System
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APPLICATION INFORMATION
regulation
The feedback/shutdown (FB/SD) terminal has two functions. Pulling FB/SD below the shutdown threshold
(≈ 0.45 V) puts the device into shutdown. In shutdown, the reference/regulator is turned off and switching stops.
The switches are set such that both CIN and COUT are discharged through the output load. Quiescent current
in shutdown drops to approximately 100 µA. Any open-collector gate can be used to put the LT1054 into
shutdown. For normal (unregulated) operation, the device will restart when the external gate is shut off. In
LT1054 circuits that use the regulation feature, the external resistor divider can provide enough pulldown to keep
the device in shutdown until the output capacitor (COUT) has fully discharged. For most applications, where the
LT1054 is run intermittently, this does not present a problem because the discharge time of the output capacitor
is short compared to the off time of the device. In applications where the device has to start up before the output
capacitor (COUT) has fully discharged, a restart pulse must be applied to FB/SD of the LT1054. Using the circuit
shown in Figure 16, the restart signal can be either a pulse (tp > 100 µs) or a logic high. Diode coupling the restart
signal into FB/SD allows the output voltage to rise and regulate without overshoot. The resistor divider R3/R4
shown in Figure 16 should be chosen to provide a signal level at FB/SD of 0.7−1.1 V.
FB/SD also is the inverting input of the LT1054 error amplifier and, as such, can be used to obtain a regulated
output voltage.
R3
VIN
1
2
CIN
10-µF
Tantalum
R4
+
VCC
CAP+
OSC
LT1054
3
4
Restart
FB/SD
GND
VREF
CAP−
VOUT
7
6
R1
5
R2
Shutdown
For example: To get VO = −5 V, referenced to the ground terminal of the LT1054
ǒ
R2 + R1
2.2 µF
+
8
Ť V OUTŤ
V REF
2
* 40 mV
Ǔ
)1
ǒ
+ 20 kW
|–5 V|
)1
2.5 V * 40 mV
2
Ǔ
VOUT
C1
+ 102.6 kW †
+
COUT
100-µF
Tantalum
Where: R1 = 20 kΩ
VREF = 2.5 V Nominal
† Choose the closest 1% value.
Pin numbers shown are for the P package.
Figure 16. Basic Regulation Configuration
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APPLICATION INFORMATION
regulation (continued)
The error amplifier of the LT1054 drives the pnp switch to control the voltage across the input capacitor (CIN),
which determines the output voltage. When the reference and error amplifier of the LT1054 are used, an external
resistive divider is all that is needed to set the regulated output voltage. Figure 16 shows the basic regulator
configuration and the formula for calculating the appropriate resistor values. R1 should be 20 kΩ or greater
because the reference current is limited to ±100 µA. R2 should be in the range of 100 kΩ to 300 kΩ. Frequency
compensation is accomplished by adjusting the ratio of CIN to COUT.
For best results, this ratio should be approximately 1:10. Capacitor C1, required for good load regulation, should
be 0.002 µF for all output voltages.
The functional block diagram shows that the maximum regulated output voltage is limited by the supply voltage.
For the basic configuration, VOUT  referenced to the ground terminal of the LT1054 must be less than the total
of the supply voltage minus the voltage loss due to the switches. The voltage loss versus output current due
to the switches can be found in the typical performance curves. Other configurations, such as the negative
doubler, can provide higher voltages at reduced output currents.
capacitor selection
While the exact values of CIN and COUT are noncritical, good-quality low-ESR capacitors, such as solid
tantalum, are necessary to minimize voltage losses at high currents. For CIN, the effect of the ESR of the
capacitor is multiplied by four, because switch currents are approximately two times higher than output current.
Losses occur on both the charge and discharge cycle, which means that a capacitor with 1 Ω of ESR for CIN
has the same effect as increasing the output impedance of the LT1054 by 4 Ω. This represents a significant
increase in the voltage losses. COUT alternately is charged and discharged at a current approximately equal
to the output current. The ESR of the capacitor causes a step function to occur in the output ripple at the switch
transitions. This step function degrades the output regulation for changes in output load current and should be
avoided. A technique used to gain both low ESR and reasonable cost is to parallel a smaller tantalum capacitor
with a large aluminum electrolytic capacitor.
output ripple
The peak-to-peak output ripple is determined by the output capacitor and the output current values.
Peak-to-peak output ripple is approximated as:
DV +
I OUT
2fC OUT
(5)
Where:
∆V = peak-to-peak ripple
fOSC = oscillator frequency
For output capacitors with significant ESR, a second term must be added to account for the voltage step at the
switch transitions. This step is approximately equal to:
ǒ2I OUTǓǒESR of C OUTǓ
12
(6)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
power dissipation
The power dissipation of any LT1054 circuit must be limited so that the junction temperature of the device does
not exceed the maximum junction-temperature ratings. The total power dissipation is calculated from two
components–the power loss due to voltage drops in the switches, and the power loss due to drive-current
losses. The total power dissipated by the LT1054 is calculated as:
P [ ǒV CC * ŤV OUTŤǓ I OUT ) ǒV CCǓǒI OUTǓ(0.2)
(7)
where both VCC and VOUT are referenced to ground. The power dissipation is equivalent to that of a linear
regulator. Limited power-handling capability of the LT1054 packages causes limited output-current
requirements, or steps can be taken to dissipate power external to the LT1054 for large input or output
differentials. This is accomplished by placing a resistor in series with CIN as shown in Figure 17. A portion of
the input voltage is dropped across this resistor without affecting the output regulation. Since switch current is
approximately 2.2 times the output current and the resistor causes a voltage drop when CIN is both charging
and discharging, the resistor chosen is as shown:
RX +
VX
4.4 I OUT
(8)
Where:
VX ≈ VCC − [(LT1054 voltage loss)(1.3) + |VOUT|]
and
IOUT = maximum required output current
The factor of 1.3 allows some operating margin for the LT1054.
When using a 12-V to −5-V converter at 100-mA output current, calculate the power dissipation without an
external resistor.
P + (12 V * |*5 V|)(100 mA) ) (12 V)(100 mA)(0.2)
P + 700 mW ) 240 mW + 940 mW
(9)
VIN
1
Rx
2
FB/SD
VCC
CAP+
OSC
8
7
LT1054
CIN
+
3
4
GND
VREF
CAP−
VOUT
6
R1
5
R2
VOUT
C1
+
COUT
Pin numbers shown are for the P package.
Figure 17. Power-Dissipation-Limiting Resistor in Series With CIN
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
power dissipation (continued)
At RθJA of 130°C/W for a commercial plastic device, a junction temperature rise of 122°C occurs. The device
exceeds the maximum junction temperature at an ambient temperature of 25°C. To calculate the power
dissipation with an external resistor (RX), determine how much voltage can be dropped across RX. The
maximum voltage loss of the LT1054 in the standard regulator configuration at 100 mA output current is 1.6 V.
V X + 12 V * [(1.6 V)(1.3) ) |*5 V|] + 4.9 V
(10)
and
RX +
4.9 V
+ 11 W
(4.4)(100 mA)
(11)
The resistor reduces the power dissipated by the LT1054 by (4.9 V)(100 mA) = 490 mW. The total power
dissipated by the LT1054 is equal to (940 mW − 490 mW) = 450 mW. The junction-temperature rise is 58°C.
Although commercial devices are functional up to a junction temperature of 125°C, the specifications are tested
to a junction temperature of 100°C. In this example, this means limiting the ambient temperature to 42°C. To
allow higher ambient temperatures, the thermal resistance numbers for the LT1054 packages represent
worst-case numbers, with no heat sinking and still air. Small clip-on heat sinks can be used to lower the thermal
resistance of the LT1054 package. Airflow in some systems helps to lower the thermal resistance. Wide printed
circuit board traces from the LT1054 leads help remove heat from the device. This is especially true for plastic
packages.
10 V
1N4002
100 kΩ
1
2
10 µF
−
+
+
3
1N5817
4
Tach
OSC
CAP+
GND
VREF
CAP−
VOUT
Motor
NOTE: Motor-Tach is Canon CKT26-T5-3SAE.
Pin numbers shown are for the P package.
Figure 18. Motor-Speed Servo
14
8
7
LT1054
+
−
VCC
FB/SD
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6
5
5 µF
+
100-kΩ
Speed Control
SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
1
FB/SD
2
VCC
CAP+
OSC
8
VIN
+
2 µF
7
LT1054
10 µF
3
+
4
GND
VREF
CAP−
VOUT
6
5
−VOUT
100 µF
+
Pin numbers shown are for the P package.
Figure 19. Basic Voltage Inverter
1
FB/SD
VCC
2
10 µF
+
7
CAP+
4
GND
VREF
CAP−
VOUT
6
R1
20 kΩ
5
R2
VOUT
0.002 µF
+
+
ǒ
R2 + R1
VIN
2 µF
OSC
LT1054
3
+
8
100 µF
ŤVOUT Ť
V REF
2
* 40 mV
Ǔ
)1
ǒŤ
+ 20 kW
Ǔ
V OUTŤ
)1
1.21 V
Pin numbers shown are for the P package.
Figure 20. Basic Voltage Inverter/Regulator
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
1
2
10 µF
FB/SD
VCC
CAP+
OSC
+
8
+
VOUT
7
−
LT1054
3
VIN
2 µF
+
4
GND
VREF
CAP−
VOUT
6
QX
5
RX
100 µF
+
VIN = −3.5 V to −15 V
VOUT = 2 VIN + (LT1054 Voltage Loss) + (QX Saturation Voltage)
VIN
Pin numbers shown are for the P package.
Figure 21. Negative-Voltage Doubler
VIN
3.5 V to 15 V
1N4001
1N4001
+
+
100 µF
+
10 µF
VOUT
1
−
2
FB/SD
VCC
CAP+
OSC
8
7
LT1054
3
VIN = 3.5 V to 15 V
VOUT ≈ 2 VIN − (VL + 2 V Diode)
VL = LT1054 Voltage Loss
4
GND
VREF
CAP−
VOUT
Pin numbers shown are for the P package.
Figure 22. Positive-Voltage Doubler
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
6
5
+
2 µF
SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
VIN
3.5 V to 15 V
+
2.2 µF
1
2
+ 10 µF
10 µF
FB/SD
VCC
7
CAP+
LT1054 #1
6
GND
VREF
4
5
CAP−
1N4002
VOUT
+
+ 10 µF
R1
40 kΩ
10 µF
0.002 µF
+
100 µF
3
4
+
10 µF
+
FB/SD
VCC
8
7
CAP+
OSC
LT1054 #2
6
GND
VREF
CAP−
VOUT
HP5082-2810
CAP+ of
LT1054 #1
20 kΩ
5
1N4002
R2
500 kΩ
1N4002
1N4002
2
VOUT
SET
OSC
3
+
1
8
+
10 µF
1N4002
VOUT
IOUT ≅ 100 mA MAX
VIN = 3.5 V to 15 V
VOUT MAX ≈ −2 VIN + [LT1054 Voltage Loss +2 (VDiode)]
ǒ
R2 + R1
ŤVOUT Ť
V REF
2
* 40 mV
Ǔ ǒŤ
)1
+ R1
V
OUT
Ť
1.21 V
Ǔ
)1
Pin numbers shown are for the P package.
Figure 23. 100-mA Regulating Negative Doubler
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• DALLAS, TEXAS 75265
17
SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
VI
3.5 V to 15 V
1N4001
1N4001
+
+
+VO
100 µF
10 µF
−
+
1
2
10 µF
3
+
4
10 µF
FB/SD
VCC
CAP+
OSC
LT1054
GND
VREF
CAP−
VOUT
8
7
6
100 µF
+
5
+
1N4001
1N4001
−
VI = 3.5 V to 15 V
+VO ≈ 2 VIN − (VL + 2 VDiode) −VO ≈ −2 VI + (VL + 2 VDiode)
VL = LT1054 Voltage Loss
1N4001
+
100 µF
−VO
+
Pin numbers shown are for the P package.
Figure 24. Dual-Output Voltage Doubler
VI = 5 V
+
1
2
10 µF
+
3
FB/SD
CAP+
VCC
OSC
LT1054 #1
GND
8
100 µF
1N914
1N914
VO ≈ +12 V
IO = 25 mA
+
10 µF
+
7
1
6
2
VOUT
FB/SD
CAP+
VREF
4
CAP−
5 µF
5
10 µF
2N2219
100 µF
1 kΩ
+
5 µF
+
3
VCC
OSC
LT1054 #2
GND
VREF
4
CAP−
VOUT
8
CAP− of
LT1054 #1
7
6
20 kΩ
5
+
Pin numbers shown are for the P package.
Figure 25. 5-V to ±12-V Converter
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VO ≈ −12 V
IO = 25 mA
100 µF
SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
5V
10 kΩ
Input TTL or
CMOS Low
for On
+
10 kΩ
40 Ω
2N2907
8
0.022 µF
−
1
10 µF
Zero Trim
10 kΩ
2
1/2
LT1013
3
+
A1
301 kΩ
100 kΩ
100 kΩ
5 kΩ
Gain Trim
5 kΩ
10 kΩ
350 Ω
1 µF
200 kΩ
1
2
10 µF
FB/SD
VCC
CAP+
OSC
+
8
4
−
1 MΩ
A2
1/2
LT1013
5
+
4
7
VOUT
5V
7
3 kΩ
LT1054 #1
3
6
GND
VREF
CAP−
VOUT
2N2222
6
5
+ 100-µF
Tantalum
Adjust Gain Trim For 3 V Out From
Full-Scale Bridge Output of 24 mV
Pin numbers shown are for the P package.
Figure 26. Strain-Gage Bridge Signal Conditioner
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
VI
3.5 V to 5.5 V
1
20 kΩ
2
1 µF
1N914
(All)
1
2
10 µF
+
3
4
FB/SD
VCC
CAP+
OSC
VREF
CAP−
VOUT
3
8
7
LT1054
GND
+
6
5
4
5 µF
FB/SD
VCC
CAP+
OSC
ǒ
R2 + R1
ŤVOUT Ť
GND
VREF
CAP−
VOUT
+
V REF
2
* 40 mV
Ǔ ǒŤ
+ R1
V
OUT
Ť
1.21 V
Ǔ
)1
5
R1
20 kΩ
+
0.002 µF
R2
125 kΩ
1N5817
Pin numbers shown are for the P package.
Figure 27. 3.5-V to 5-V Regulator
20
6
R2
125 kΩ
+
100 µF
3 kΩ
2N2219
)1
7
LTC1044
−
VI = 3.5 V to 5.5 V
VO = 5 V
IO MAX = 50 mA
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1N914
1 µF
VO
+
SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
12 V
5 µF
+
1
FB/SD
2
10 Ω
1/2 W
VCC
OSC
CAP+
LT1054 #1
3
GND
4
VREF
VOUT
CAP−
+
10 µF
1
8
10 Ω
1/2 W
7
R1
39.2
kΩ
6
+
0.002 µF
5
10 µF
VCC
CAP+
OSC
GND
R2 + R1
HP5082-2810
7
VREF
6
20 kΩ
4
ǒ
200 µF
8
LT1054 #2
3
+
R2
200 kΩ
+
2
FB/SD
ŤV OUT Ť
V REF
2
* 40 mV
VOUT
CAP−
Ǔ ǒŤ
)1
+ R1
V
OUT
Ť
1.21 V
5
VO = −5 V
IO = 0-200 mA
Ǔ
)1
Pin numbers shown are for the P package.
Figure 28. Regulating 200-mA +12-V to −5-V Converter
15 V
5 µF
+
11
20 kΩ
2.5 V
1
2
10 µF
+
3
4
FB/SD
VCC
CAP+
OSC
16
LT1004-2.5
8
15
14
7
Digital
Input
AD558
13
12
20 kΩ
LT1054
GND
VREF
CAP−
VOUT
6
5
VO = −VI (Programmed)
+
100 µF
Pin numbers shown are for the P package.
Figure 29. Digitally Programmable Negative Supply
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SLVS033F − FEBRUARY 1990 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
VI = 5 V
50 kΩ
1
1N5817
100 µF
10 µF
+
1N5817
VO
8V
CAP+
OSC
10 kΩ
10 kΩ
7
LT1054
3
5.5 kΩ
5V
10 kΩ
VCC
2
+
0.03 µF
8
FB/SD
6
GND
VREF
CAP−
VOUT
4
5
−
1/2
LT1013
+
2.5 kΩ
0.1 µF
Pin numbers shown are for the P package.
Figure 30. Positive Doubler With Regulation (5-V to 8-V Converter)
VI
3.5 V to 15 V
1
2
FB/SD
VCC
CAP+
OSC
8
7
R1
60 kΩ
LT1054
10 µF
+
3
4
10 µF
GND
VREF
CAP−
VOUT
2 µF
+
6
100 µF
+
5
R2
1 MΩ
+
+
0.002 µF
1N4001
1N4001
−VO
VI = 3.5 V to 15 V
VO MAX ≈ 2 VIN + (VL + 2 VDiode)
VL = LT1054 Voltage Loss
ǒ
R2 + R1
ŤV OUT Ť
V REF
2
* 40 mV
+
Ǔ ǒŤ
)1
+ R1
V
OUT
Ť
1.21 V
100 µF
Ǔ
)1
Pin numbers shown are for the P package.
Figure 31. Negative Doubler With Regulator
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2 µF
+
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
LT1054CDW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LT1054CDWE4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LT1054CDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LT1054CDWRE4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LT1054CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
LT1054CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
LT1054IDW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LT1054IDWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LT1054IDWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LT1054IDWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LT1054IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
LT1054IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
LT1054Y
OBSOLETE
XCEPT
Y
0
TBD
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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