AD AD660BRZ Monolithic 16-bit serial/byte dacport Datasheet

Monolithic 16-Bit
Serial/Byte DACPORT
AD660
FEATURES
FUNCTIONAL BLOCK DIAGRAM
DB0/
LBE/
DB8/ DB1/DB9/ DB7/
CLEAR SELECT CS SIN DATADIR DB15
15
14
12
11
5
AD660
HBE 16
SER 17
CONTROL
LOGIC
CLR 18
SPAN/
10kΩ
22 BIPOLAR
16-BIT LATCH
OFFSET
10.05kΩ
LDAC 19
REF IN 23
13 SOUT
16-BIT LATCH
10kΩ
16-BIT DAC
21 VOUT
10V REF
20 AGND
24
1
REF OUT –VEE
2
3
4
+VCC
+VLL
DGND
01813-001
Complete 16-bit digital-to-analog function
On-chip output amplifier
On-chip buried Zener voltage reference
±1 LSB integral linearity
15-bit monotonic over temperature
Microprocessor compatible
Serial or byte input
Double-buffered latches
Fast (40 ns) write pulse
Asynchronous clear (to 0 V) function
Serial output pin facilitates daisy-chaining
Unipolar or bipolar output
Low glitch: 15 nV-s
Low THD + N: 0.009%
Figure 1.
GENERAL DESCRIPTION
The AD660 DACPORT® is a complete 16-bit monolithic digitalto-analog converter with an on-board voltage reference, doublebuffered latches, and an output amplifier. It is manufactured on
the Analog Devices, Inc., BiMOS II process. This process allows
the fabrication of low power CMOS logic functions on the same
chip as high precision bipolar linear circuitry.
The AD660 architecture ensures 15-bit monotonicity over time
and temperature. Integral and differential nonlinearity is maintained at ±0.003% maximum. The on-chip output amplifier
provides a voltage output settling time of 10 μs to within ½ LSB for
a full-scale step.
The AD660 has an extremely flexible digital interface. Data can
be loaded into the AD660 in serial mode or as two 8-bit bytes.
This is made possible by two digital input pins that have dual
functions. The serial mode input format is pin selectable to be
MSB or LSB first. The serial output pin allows the user to daisychain several AD660 devices by shifting the data through the
input latch into the next DAC, thus minimizing the number of
control lines required to SIN, CS and LDAC. The byte mode input
format is also flexible in that the high byte or low byte data can
be loaded first. The double buffered latch structure eliminates
data skew errors and provides for simultaneous updating of DACs
in a multiDAC system.
The AD660 is available in five grades. AN and BN versions are
specified from −40°C to +85°C and are packaged in a 24-lead
300 mil plastic DIP. AR and BR versions are also specified from
−40°C to +85°C and are packaged in a 24-lead SOIC. The SQ
version is packaged in a 24-lead 300 mil CERDIP package and
is also available compliant to MIL-STD-883. Refer to the
AD660SQ/883B military data sheet for specifications and test
conditions.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
The AD660 is a complete 16-bit DAC, with a voltage
reference, double-buffered latches, and an output amplifier
on a single chip.
The internal buried Zener reference is laser trimmed to
10.000 V with a ±0.1% maximum error and a temperature
drift performance of ±15 ppm/°C. The reference is available
for external applications.
The output range of the AD660 is pin programmable and
can be set to provide a unipolar output range of 0 V to 10 V
or a bipolar output range of −10 V to +10 V. No external
components are required.
The AD660 is both dc and ac specified. DC specifications
include ±1 LSB INL and ±1 LSB DNL errors. AC specifications include 0.009% THD + N and 83 dB SNR.
The double-buffered latches on the AD660 eliminate data
skew errors and allow simultaneous updating of DACs in
multiDAC applications.
The clear function can asynchronously set the output
to 0 V regardless of whether the DAC is in unipolar or
bipolar mode.
The output amplifier settles within 10 μs to ±½ LSB for a
full-scale step and within 2.5 μs for a 1 LSB step over temperature. The output glitch is typically 15 nV-s when a full-scale
step is loaded.
Rev. B
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Fax: 781.461.3113 ©1993–2008 Analog Devices, Inc. All rights reserved.
AD660* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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• AD660: Military Data Sheet
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AD660
TABLE OF CONTENTS
Features .............................................................................................. 1
Bipolar Configuration................................................................ 11
Functional Block Diagram .............................................................. 1
Internal/External Reference Use .............................................. 11
General Description ......................................................................... 1
Output Settling and Glitch ........................................................ 13
Product Highlights ........................................................................... 1
Digital Circuit Details ................................................................ 14
Revision History ............................................................................... 2
Microprocessor Interface............................................................... 15
Specifications..................................................................................... 3
AD660 to MC68HC11 (SPI Bus) Interface ............................. 15
AC Performance Characteristics ................................................ 4
AD660 to MICROWIRE Interface........................................... 15
Timing Characteristics ................................................................ 5
AD660 to ADSP-210x Family Interface .................................. 15
Absolute Maximum Ratings............................................................ 7
AD660 to Z80 Interface ............................................................. 16
ESD Caution .................................................................................. 7
Noise ............................................................................................ 16
Pin Configuration and Function Descriptions ............................. 8
Board Layout ................................................................................... 17
Terminology ...................................................................................... 9
Supply Decoupling ..................................................................... 17
Theory of Operation ...................................................................... 10
Grounding ................................................................................... 17
Analog Circuit Connections ..................................................... 10
Outline Dimensions ....................................................................... 18
Unipolar Configuration ............................................................. 10
Ordering Guide .......................................................................... 19
REVISION HISTORY
6/08—Rev. A to Rev. B
Updated Format .................................................................. Universal
Updated Pin Name MSB/LSB to DATADIR Throughout........... 1
Updated Pin Name UNI/BIP CLEAR to CLEAR SELECT
Throughout ....................................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Endnote 3 in Table 1 .................................................... 4
Changes to Figure 2 .......................................................................... 5
Changes to Figure 3 and Figure 5 ................................................... 6
Changes to Table 4.............................................................................7
Added Pin Configuration and Function Descriptions Section ...8
Changes to Internal/External Reference Use Section ................ 11
Changes to Figure 12...................................................................... 12
Changes to Figure 13, Figure 14, Figure 15, and Figure 16....... 13
Changes to Figure 17 and Figure 18............................................. 15
Changes to Figure 19...................................................................... 16
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
Rev. B | Page 2 of 20
AD660
SPECIFICATIONS
TA = 25°C, +VCC = 15 V, −VEE = −15 V, +VLL = 5 V unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DIGITAL INPUTS (TMIN to TMAX)
VIH (Logic 1)
VIL (Logic 0)
IIH (VIH = 5.5 V)
IIL (VIL = 0 V)
TRANSFER FUNCTION CHARACTERISTICS1
Integral Nonlinearity
Bipolar Operation
TMIN to TMAX
Unipolar Operation
TMIN to TMAX
Differential Nonlinearity
TMIN to TMAX
Monotonicity Over Temperature
Gain Error2, 3
Gain Drift (TMIN to TMAX)
DAC Gain Error4
DAC Gain Drift4
Unipolar Offset
Unipolar Offset Drift (TMIN to TMAX)
Bipolar Zero Error
Bipolar Zero Error Drift (TMIN to TMAX)
REFERENCE INPUT
Input Resistance
Bipolar Offset Input Resistance
REFERENCE OUTPUT
Voltage
Drift
External Current5
Capacitive Load
Short-Circuit Current
OUTPUT CHARACTERISTICS
Output Voltage Range
Unipolar Configuration
Bipolar Configuration
Output Current
Capacitive Load
Short-Circuit Current
Min
16
AD660AN/AR/SQ
Typ
Max
Min
16
AD660BN/BR
Typ
Max
Unit
Bits
2.0
0
−10
−10
5.5
0.8
+10
+10
2.0
0
−10
−10
5.5
0.8
+10
+10
V
V
μA
μA
−2
−4
−2
−4
−2
−4
14
−0.1
+2
+4
+2
+4
+2
+4
−1
−2
−1
−2
−1
−2
15
−0.1
+1
+2
+1.5
+2
+1
+2
+0.1
15
+0.05
10
+2.5
3
+7.5
5
LSB
LSB
LSB
LSB
LSB
LSB
Bits
% of FSR
ppm/°C
% of FSR
ppm/°C
mV
ppm/°C
mV
ppm/°C
+0.1
25
+0.05
10
+2.5
3
+7.5
5
−0.05
−2.5
−7.5
−0.05
−2.5
−7.5
7
7
10
10
13
13
7
7
10
10
13
13
kΩ
kΩ
9.99
10.00
10.01
25
9.99
10.00
10.01
15
2
4
2
4
V
ppm/°C
mA
pF
mA
1000
1000
25
0
−10
5
25
+10
+10
0
−10
5
+10
+10
1000
25
Rev. B | Page 3 of 20
1000
25
V
V
mA
pF
mA
AD660
Parameter
POWER SUPPLIES
Voltage
+VCC6
−VEE6
+VLL
Current (No Load)
ICC
IEE
ILL
@ VIH = 5 V, VIL = 0 V
@ VIH = 2.4 V, VIL = 0.4 V
Power Supply Sensitivity
Power Dissipation (Static, No Load)
TEMPERATURE RANGE
Specified Performance (A, B)
Specified Performance (S)
Min
AD660AN/AR/SQ
Typ
Max
+13.5
−13.5
+4.5
+16.5
−16.5
+5.5
Min
AD660BN/BR
Typ
Max
+13.5
−13.5
+4.5
Unit
+16.5
−16.5
+5.5
V
V
V
+12
−12
+18
−18
+12
−12
+18
−18
mA
mA
0.3
3
1
365
2
7.5
2
625
0.3
3
1
365
2
7.5
2
625
mA
mA
ppm/%
mW
+85
°C
°C
−40
−55
+85
+125
−40
1
For 16-bit resolution, 1 LSB = 0.0015% of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR. For 14-bit resolution, 1 LSB = 0.006% of FSR. FSR stands for full-scale range
and is 10 V in a unipolar mode and 20 V in bipolar mode.
Gain error and gain drift are measured using the internal reference. The internal reference is the main contributor to gain drift. If lower gain drift is required, the AD660
can be used with a precision external reference such as the AD587, AD586, or AD688.
3
Gain error is measured with fixed 50 Ω resistors as shown in the Theory of Operation section. Eliminating these resistors increases the gain error by 0.25% of FSR
(unipolar mode) or 0.50% of FSR (bipolar mode).
4
DAC gain error and drift are measured with an external voltage reference. They represent the error contributed by the DAC alone, for use with an external reference.
5
External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD660.
6
Operation on ±12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference Use
section.
2
AC PERFORMANCE CHARACTERISTICS
With the exception of total harmonic distortion + noise (THD + N) and signal-to-noise (SNR) ratio, these characteristics are included for
design guidance only and are not subject to test. THD + N and SNR are 100% tested.
TMIN ≤ TA ≤ TMAX, +VCC = 15 V, −VEE = −15 V, +VLL = 5 V except where noted.
Table 2.
Parameter
OUTPUT SETTLING TIME
(Time to ±0.0008% FS
with 2 kΩ, 1000 pF Load)
Limit
13
8
10
6
8
2.5
Unit
μs max
μs typ
μs typ
μs typ
μs typ
μs typ
Test Conditions/Comments
20 V step, TA = 25°C
20 V step, TA = 25°C
20 V step, TMIN ≤ TA ≤ TMAX
10 V step, TA = 25°C
10 V step, TMIN ≤ TA ≤ TMAX
1 LSB step, TMIN ≤ TA ≤ TMAX
TOTAL HARMONIC DISTORTION + NOISE
A, B, S Grade
A, B, S Grade
A, B, S Grade
SIGNAL-TO-NOISE RATIO
DIGITAL-TO-ANALOG GLITCH IMPULSE
DIGITAL FEEDTHROUGH
0.009
0.056
5.6
83
15
2
% max
% max
% max
dB min
nV-s typ
nV-s typ
0 dB, 990.5 Hz, sample rate = 96 kHz, TA = 25°C
−20 dB, 990.5 Hz, sample rate = 96 kHz, TA = 25°C
−60 dB, 990.5 Hz, sample rate = 96 kHz, TA = 25°C
TA = 25°C
DAC alternately loaded with 0x8000 and 0x7FFF
DAC alternately loaded with 0x0000 and 0xFFFF, CS high
OUTPUT NOISE VOLTAGE
Density (1 kHz to 1 MHz)
REFERENCE NOISE
120
125
nV/√Hz typ
nV/√Hz typ
Measured at VOUT, 20 V span, excludes reference
Measured at REF OUT
Rev. B | Page 4 of 20
AD660
TIMING CHARACTERISTICS
+VCC = 15 V, −VEE = −15 V, +VLL = 5 V, VHIGH = 2.4 V, VLOW = 0.4 V.
Table 3.
Parameter
BYTE LOAD (see Figure 2)
tCS
Limit at TA = 25°C
Limit at TA = −55°C to +125°C
Unit
tDS
tDH
tBES
40
40
0
40
50
50
10
50
ns min
ns min
ns min
ns min
tBEH
0
10
ns min
80
40
100
50
ns min
ns min
80
30
30
0
40
0
0
80
40
100
50
50
10
50
10
10
100
50
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
80
80
0
110
110
10
ns min
ns min
ns min
50
50
100
80
ns min
ns min
tLH
tLW
SERIAL LOAD (see Figure 3)
tCLK
tLOW
tHIGH
tSS
tDS
tDH
tSH
tLH
tLW
ASYNCHRONOUS CLEAR TO BIPOLAR
OR UNIPOLAR ZERO (see Figure 4)
tCLR
tSET
tHOLD
SERIAL OUT (see Figure 5)
tPROP
tDS
DB0 TO DB7
tDS
tDH
HBE OR LBE
tBES
tBEH
tCS
CS
tLW
01813-002
tLH
LDAC
Figure 2. AD660 Byte Load Timing
Rev. B | Page 5 of 20
AD660
DB0
VALID 1
VALID 16
tDS
SER
DB1
(DATADIR)
tSS
tSH
tDH
1 = MSB FIRST, 0 = LSB FIRST
tLOW
tHIGH
CS
tLH
tLW
01813-003
tCLK
LDAC
Figure 3. AD660 Serial Load Timing
tCLR
tHOLD
tSET
LBE
01813-004
CLR
1 = BIPOLAR 0, 0 = UNIPOLAR 0
Figure 4. Asynchronous Clear to Bipolar or Unipolar Zero
DB0
VALID 16
VALID 17
tDS
SER
DB1
(DATADIR)
CS
SOUT
VALID SOUT 1
Figure 5. Serial Out Timing
Rev. B | Page 6 of 20
01813-005
tPROP
AD660
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
+VCC to AGND
−VEE to AGND
+VLL to DGND
AGND to DGND
Digital Inputs (Pin 5 through Pin 23)
to DGND
REF IN to AGND
SPAN/BIPOLAR OFFSET to AGND
REF OUT, VOUT
Power Dissipation (Any Package)
To +60°C
Derates Above +60°C
Storage Temperature
Lead Temperature
Soldering
Rating
−0.3 V to +17.0 V
+0.3 V to −17.0 V
−0.3 V to +7 V
±1 V
−1.0 V to +7.0 V
±10.5 V
±10.5 V
Indefinite short to AGND,
DGND, +VCC, −VEE, and +VLL
ESD CAUTION
1000 mW
8.7 mW/°C
−65°C to +150°C
JEDEC industry standard
J-STD-020
Rev. B | Page 7 of 20
AD660
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–VEE 1
24 REF OUT
+VCC 2
23 REF IN
DGND 4
22 SPAN/BIPOLAR OFFSET
21 VOUT
DB5/DB13
AD660 20 AGND
TOP VIEW 19 LDAC
(Not to Scale)
7
18 CLR
DB4/DB12
DB7/DB15
5
DB6/DB14
6
8
17 SER
DB3/DB11 9
16 HBE
DB2/DB10 10
15 LBE/CLEAR SELECT
DB1/DB9/DATADIR 11
DB0/DB8/SIN 12
14 CS
13 SOUT
01813-006
+VLL 3
Figure 6. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Mnemonic
−VEE
+VCC
+VLL
DGND
DB7/DB15
DB6/DB14
DB5/DB13
DB4/DB12
DB3/DB11
DB2/DB10
DB1/DB9/DATADIR
DB0/DB8/SIN
SOUT
CS
LBE/CLEAR SELECT
HBE
SER
CLR
LDAC
AGND
VOUT
SPAN/BIPOLAR OFFSET
REF IN
REF OUT
Description
Negative Analog Supply Pin
Positive Analog Supply Pin
Digital Supply Pin
Digital Ground Reference Pin
DB7 and DB15 Byte Load Data Input Pin
DB6 and DB14 Byte Load Data Input Pin
DB5 and DB13 Byte Load Data Input Pin
DB4 and DB12 Byte Load Data Input Pin
DB3 and DB11 Byte Load Data Input Pin
DB2 and DB10 Byte Load Data Input Pin
DB1 and DB9 Byte Load Data Input Pin/MSB or LSB First Data Direction Serial Input Select Pin
DB0 and DB8 Byte Load Data Input Pin/Serial Data Input Pin
Serial Data Output Pin
Chip Select Pin
Low Byte Enable Pin/Unipolar or Bipolar Clear Select Pin
High Byte Enable Pin
Serial Input Enable Pin
Output Clear Pin
Load DAC Pin
Analog Ground Reference Pin
Voltage Output Pin
Output Span Configuration Pin
External Reference Voltage Input Pin
Internal Reference Voltage Output Pin
Rev. B | Page 8 of 20
AD660
TERMINOLOGY
Integral Nonlinearity
Integral nonlinearity is the maximum deviation of the actual,
adjusted DAC output from the ideal analog output (a straight
line drawn from 0 to FS − 1 LSB) for any bit combination. This
is also referred to as relative accuracy.
Differential Nonlinearity
Differential nonlinearity is the measure of the change in the
analog output, normalized to full scale, associated with a 1 LSB
change in the digital input code. Monotonic behavior requires
that the differential linearity error be greater than or equal to
−1 LSB over the temperature range of interest.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital inputs with the result that the
output is always a single-valued function of the input.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out.
Offset Error
Offset error is a combination of the offset errors of the voltagemode DAC and the output amplifier and is measured with all 0s
loaded in the DAC.
Bipolar Zero Error
When the AD660 is connected for bipolar output and 10…000
is loaded in the DAC, the deviation of the analog output from
the ideal midscale value of 0 V is called the bipolar zero error.
Drift
Drift is the change in a parameter (such as gain, offset, and bipolar
zero) over a specified temperature range. The drift temperature
coefficient, specified in ppm/°C, is calculated by measuring the
parameter at TMIN, 25°C, and TMAX, and dividing the change in
the parameter by the corresponding temperature change.
Total Harmonic Distortion + Noise
Total harmonic distortion + noise (THD + N) is defined as the
ratio of the square root of the sum of the squares of the values of
the harmonics and noise to the value of the fundamental input
frequency. It is usually expressed in percent (%).
THD + N is a measure of the magnitude and distribution of
linearity error, differential linearity error, quantization error,
and noise. The distribution of these errors may be different,
depending upon the amplitude of the output signal. Therefore,
to be the most useful, THD + N should be specified for both
large and small signal amplitudes.
Signal-To-Noise Ratio
The signal-to-noise ratio is the ratio of the amplitude of the output
when a full-scale signal is present to the output with no signal
present. The signal-to-noise ratio is measured in decibels (dB).
Digital-To-Analog Glitch Impulse
Digital-to-analog glitch impulse is the amount of charge
injected from the digital inputs to the analog output when the
inputs change state. This is measured at half scale when the DAC
switches around the MSB and as many as possible switches
change state, that is, from 011…111 to 100…000.
Digital Feedthrough
When the DAC is not selected (that is, CS is held high), high
frequency logic activity on the digital inputs is capacitively
coupled through the device to show up as noise on the VOUT pin.
This noise is digital feedthrough.
Rev. B | Page 9 of 20
AD660
THEORY OF OPERATION
DB0/
LBE/
DB8/ DB1/DB9/ DB7/
CLEAR SELECT CS SIN DATADIR DB15
The AD660 uses an array of bipolar current sources with MOS
current steering switches to develop a current proportional to the
applied digital word, ranging from 0 mA to 2 mA. A segmented
architecture is used, where the most significant four data bits
are thermometer decoded to drive 15 equal current sources.
The lesser bits are scaled using a R-2R ladder, then applied
together with the segmented sources to the summing node of
the output amplifier. The internal span/bipolar offset resistor
can be connected to the DAC output to provide a 0 V to 10 V
span, or it can be connected to the reference input to provide a
−10 V to +10 V span.
15
12
11
5
AD660
SER
16-BIT LATCH
CONTROL
LOGIC
17
13
10kΩ
CLR 18
22
16-BIT LATCH
SPAN/
BIPOLAR
OFFSET
10.05kΩ
LDAC 19
REF IN
SOUT
10kΩ
23
R2
50Ω
16-BIT DAC
21
VOUT
OUTPUT
10V REF
20
REF OUT
24
R1
50Ω
5
1
2
–VEE
+VCC
3
AGND
4
01813-008
14
11
12
HBE 16
DB0/
LBE/
DB8/ DB1/DB9/ DB7/
CS
CLEAR SELECT
SIN DATADIR DB15
15
14
+VLL DGND
AD660
SER 17
CONTROL
LOGIC
CLR 18
If it is desired to adjust the gain and offset errors to zero, this
can be accomplished using the circuit shown in Figure 9. The
adjustment procedure is as follows:
22 BIPOLAR
OFFSET
10.05kΩ
10kΩ
Figure 8. 0 V to 10 V Unipolar Voltage Output
SPAN/
10kΩ
16-BIT LATCH
LDAC 19
REF IN 23
13 SOUT
16-BIT LATCH
1.
16-BIT DAC
21 VOUT
Zero adjust.
Turn all bits off and adjust the zero trimmer, R4, until the
output reads 0.000000 V (1 LSB = 153 μV).
Gain adjust.
Turn all bits on and adjust the gain trimmer, R1, until the
output is 9.999847 V. (Full scale is adjusted to 1 LSB less
than the nominal full scale of 10.000000 V.)
10V REF
20 AGND
1
REF OUT –VEE
2
3
4
+VCC
+VLL
DGND
2.
01813-007
24
Figure 7. Functional Block Diagram
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD660 can be connected
to produce a unipolar output range of 0 V to 10 V or a bipolar
output range of −10 V to +10 V. Gain and offset drift are minimized in the AD660 because of the thermal tracking of the
scaling resistors with other device components.
UNIPOLAR CONFIGURATION
DB0/
LBE/
DB8/ DB1/DB9/ DB7/
CLEAR SELECT CS SIN DATADIR DB15
15
14
12
11
5
AD660
HBE 16
16-BIT LATCH
CONTROL
LOGIC
SER 17
CLR 18
16-BIT LATCH
REF IN
13
R3
16k
10kΩ
23
+VCC
R4
10k
22
10.05kΩ
LDAC 19
The configuration shown in Figure 8 provides a unipolar 0 V to
10 V output range. In this mode, 50 Ω resistors are tied between
the SPAN/BIPOLAR OFFSET terminal (Pin 22) and VOUT (Pin 21),
and between REF OUT (Pin 24) and REF IN (Pin 23). It is possible
to use the AD660 without any external components by tying Pin 24
directly to Pin 23 and Pin 22 directly to Pin 21. Eliminating
these resistors increases the gain error by 0.25% of FSR.
SOUT
SPAN/
BIPOLAR
10kΩ OFFSET
–VEE
R2
50Ω
16-BIT DAC
VOUT
21
OUTPUT
10V REF
20 AGND
REF OUT
24
1
2
–VEE
+VCC
3
4
+VLL DGND
01813-009
HBE 16
R1
100Ω
Figure 9. 0 V to 10 V Unipolar Voltage Output with Gain and Offset
Adjustment
Rev. B | Page 10 of 20
AD660
R2
100Ω
BIPOLAR CONFIGURATION
The circuit shown in Figure 10 provides a bipolar output voltage
from −10.000000 V to +9.999694 V with positive full scale occurring with all bits on. As in the unipolar mode, Resistor R1 and
Resistor R2 can be eliminated altogether to provide AD660 bipolar
operation without any external components. Eliminating these
resistors increases the gain error by 0.50% of FSR in bipolar mode.
DB0/
DB8/ DB1/DB9/ DB7/
LBE/
CLEAR SELECT CS SIN DATADIR DB15
15
14
12
11
5
AD660
HBE 16
SER 17
R2
50Ω
16-BIT LATCH
CLR 18
10kΩ
10.05kΩ
14
12
11
5
AD660
HBE 16
SER 17
16-BIT LATCH
CLR 18
10kΩ
R1
50Ω
22
16-BIT LATCH
10.05kΩ
LDAC 19
23
13
CONTROL
LOGIC
REF IN
10kΩ
16-BIT DAC
21
SOUT
2
3
+VCC
+VLL
VOUT
Figure 10. ±10 V Bipolar Voltage Output
Gain offset and bipolar zero errors can be adjusted to zero using
the circuit shown in Figure 11 as follows:
1.
2.
3.
24
1
2
3
–VEE
+VCC
+VLL
VOUT
4
DGND
4
DGND
21
Figure 11. ±10 V Bipolar Voltage Output with Gain and Offset Adjustment
01813-010
1
16-BIT DAC
OUTPUT
REF OUT
SPAN/
BIPOLAR
OFFSET
20 AGND
–VEE
10kΩ
20 AGND
OUTPUT
24
REF IN
SPAN/
BIPOLAR
OFFSET
10V REF
10V REF
REF OUT
23
SOUT
01813-011
15
R1
50Ω
22
16-BIT LATCH
LDAC 19
DB0/
DB8/ DB1/DB9/ DB7/
LBE/
CLEAR SELECT CS SIN DATADIR DB15
13
CONTROL
LOGIC
Offset adjust.
Turn off all bits. Adjust the trimmer, R2, to give 10.000000 V
output.
Gain adjust.
Turn all bits on and adjust R1 to give a reading of 9.999694 V.
Bipolar zero adjust (optional).
In applications where an accurate zero output is required, set
the MSB on, all other bits off, and readjust R2 for 0 V output.
Note that using external resistors introduces a small temperature
drift component beyond that inherent in the AD660. The internal resistors are trimmed to ratio-match and temperature-track
other resistors on-chip, even though their absolute tolerances are
±20% and absolute temperature coefficients are approximately
−50 ppm/°C. In the case that external resistors are used, the
temperature coefficient mismatch between internal and external
resistors, multiplied by the sensitivity of the circuit to variations
in the external resistor value, is the resultant additional temperature drift.
INTERNAL/EXTERNAL REFERENCE USE
The AD660 has an internal low noise buried Zener diode
reference that is trimmed for absolute accuracy and temperature
coefficient. This reference is buffered and optimized for use in a
high speed DAC and gives long-term stability equal or superior to
the best discrete Zener diode references. The performance of
the AD660 is specified with the internal reference driving the
DAC and with the DAC alone (for use with a precision external
reference).
The internal reference has sufficient buffering to drive external
circuitry in addition to the reference currents required for the
DAC (typically 1 mA to REF IN and 1 mA to SPAN/BIPOLAR
OFFSET). A minimum of 2 mA is available for driving external
loads. The AD660 reference output should be buffered with an
external op amp if it is required to supply more than 4 mA total
current. The reference is tested and guaranteed to ±0.2%
maximum error.
Rev. B | Page 11 of 20
AD660
It is also possible to use external references other than 10 V with
slightly degraded linearity specifications. The recommended
range of reference voltages is 5 V to 10.24 V, which allows 5 V,
8.192 V, and 10.24 V ranges to be used. For example, by using
the AD586 5 V reference, outputs of 0 V to 5 V unipolar or ±5 V
bipolar can be realized. Using the AD586 voltage reference
makes it possible to operate the AD660 with ±12 V supplies
with 10% tolerances.
zero errors in a manner similar to that described in the Bipolar
Configuration section. Use −5.000000 V and +4.999847, as the
output values.
Figure 12 shows the AD660 using the AD586 precision 5 V
reference in the bipolar configuration. The highest grade
AD586MN is specified with a drift of 2 ppm/°C, which is a
7.5× improvement over the AD660 internal reference. This
circuit includes two optional potentiometers and one optional
resistor that can be used to adjust the gain, offset, and bipolar
Figure 13 shows the AD660 using the AD688 precision
±10 V reference, in the unipolar configuration. The highest
grade AD688BQ is specified with a temperature coefficient of
1.5 ppm/°C. The ±10 V output is also ideal for providing precise
biasing for the offset trim resistor, R4.
The AD660 can also be used with the AD587 10 V reference,
using the same configuration shown in Figure 12 to produce a
±10 V output. The highest grade AD587UQ is specified at
5 ppm/°C, which is a 3× improvement over the AD660 internal
reference.
R2
50Ω
DB0/
LBE/
DB8/ DB1/DB9/ DB7/
CLEAR SELECT CS SIN DATADIR DB15
14
12
11
5
AD660
HBE 16
SER 17
2
TRIM
4
23
R1
50Ω
AD586
GND
10kΩ
5
R2
10kΩ
22
16-BIT LATCH
10.05kΩ
LDAC 19
6
13
CONTROL
LOGIC
CLR 18
VIN
VOUT
16-BIT LATCH
REF IN
10kΩ
16-BIT DAC
21
SOUT
SPAN/
BIPOLAR
OFFSET
VOUT
OUTPUT
10V REF
20
24
1
2
3
REF OUT
–VEE
+VCC
+VLL
4
DGND
Figure 12. Using the AD660 with the AD586 5 V Reference
Rev. B | Page 12 of 20
AGND
01813-012
15
AD660
R2
50Ω
DB0/
DB8/ DB1/DB9/ DB7/
LBE/
CS
SIN DATADIR DB15
CLEAR SELECT
15
14
12
11
5
AD660
HBE 16
16-BIT LATCH
SER 17
CLR 18
10kΩ
10.05kΩ
REF IN
10kΩ
R1
50Ω
7
6
4
22
16-BIT LATCH
LDAC 19
23
13
CONTROL
LOGIC
16-BIT DAC
21
A1
A3
A4
A2
R6
9
10
8
12
11
VOUT
1
24
1
2
3
REF OUT
–VEE
+VCC
+VLL
4
DGND
15
2 +VS
R3
5
R2
100Ω
OUTPUT
0V TO 10V
14
R5
R4
10kΩ
13
16 –VS
01813-013
R1
SPAN/
BIPOLAR
OFFSET
20 AGND
R4
R2
R3
10kΩ
10V REF
3
AD688
RS
SOUT
Figure 13. Using the AD660 with the AD688 High Precision ±10 V Reference
OUTPUT SETTLING AND GLITCH
600
OUTPUT VOLTAGE (µV)
The digital-to-analog glitch impulse is specified as 15 nV-s
typical. Figure 16 shows the typical glitch impulse characteristic
at the 011…111 to 100…000 code transition when loading the
second rank register from the first rank register.
400
200
0
–200
–400
–600
01813-015
The AD660 output buffer amplifier typically settles to within
0.0008% FS (1/2 LSB) of its final value in 8 μs for a full-scale
step. Figure 14 and Figure 15 show settling for a full-scale and
an LSB step, respectively, with a 2 kΩ, 1000 pF load applied.
The guaranteed maximum settling time at 25°C for a full-scale
step is 13 μs with this load. The typical settling time for a 1 LSB
step is 2.5 μs.
0
1
2
3
4
5
TIME (µs)
Figure 15. LSB Step Settling
0
0
–200
–400
–10
–600
10
+10
0
–10
20
01813-016
0
OUTPUT VOLTAGE (mV)
200
OUTPUT VOLTAGE (µV)
400
+10
01813-014
OUTPUT VOLTAGE (V)
600
TIME (µs)
Figure 14. −10 V to +10 V Full-Scale Step Settling
0
1
2
3
TIME (µs)
Figure 16. Output Characteristics
Rev. B | Page 13 of 20
4
5
AD660
DIGITAL CIRCUIT DETAILS
The AD660 has several dual-use pins that allow flexible operation while maintaining the lowest possible pin count and
consequently the smallest package size. The user should,
therefore, pay careful attention to the following information
when applying the AD660.
Data can be loaded into the AD660 in serial or byte mode,
described as follows.
Serial mode operation is enabled by bringing SER (Pin 17) low.
This changes the function of DB0 (Pin 12) to that of the serial
input pin, SIN. It also changes the function of DB1 (Pin 11) to
a control input that tells the AD660 whether the serial data is
going to be loaded MSB or LSB first.
In serial mode, HBE and LBE are effectively disabled except
for the dual function of LBE, which is to control whether the
asynchronous clear function goes to unipolar or bipolar zero.
(A low on LBE, when CLR is strobed, sends the DAC output
to unipolar zero, a high to bipolar zero.) The AD660 does not
recognize the status of HBE when in serial mode.
Data is clocked into the input register on the rising edge of CS,
as shown in Figure 3. The data then resides in the first rank latch
and can be loaded into the DAC latch by taking LDAC high.
This causes the DAC to change to the appropriate output value.
CLR to be strobed has ended. Alternatively, new data can be
loaded into the first rank latch if desired.
The serial out pin (SOUT) can be used to daisy-chain several DACs
together in multiDAC applications to minimize the number of
isolators being used to cross an intrinsic safety barrier. The first
rank latch acts like a 16-bit shift register, and repeated strobing
of CS shifts the data out through SOUT and into the next DAC.
Each DAC in the chain requires its own LDAC signal unless all
of the DACs are to be updated simultaneously.
Byte mode operation is enabled simply by keeping SER high,
which configures DB0 to DB7 as data inputs. In this mode, HBE
and LBE are used to identify the data as either the high byte or
the low byte of the 16-bit input word. (The user can load the
data, in any order, into the first rank latch.) As in the serial mode
case, the status of LBE, when CLR is strobed, determines whether
the AD660 clears to unipolar or bipolar zero. Therefore, when in
byte mode, the user must take care to set LBE to the desired
status before strobing CLR. (In serial mode the user can simply
hardware LBE to the desired state.)
Note that CS is edge triggered. HBE, LBE, and LDAC are level
triggered.
It should be noted that the CLR function clears the DAC latch
but does not clear the first rank latch. Therefore, the data that
was previously residing in the first rank latch can be reloaded
simply by bringing LDAC high after the event that necessitated
Rev. B | Page 14 of 20
AD660
MICROPROCESSOR INTERFACE
AD660 TO MC68HC11 (SPI BUS) INTERFACE
68HC11
The most significant data byte (MSBY) is then retrieved from
memory and processed by the SENDAT subroutine. The SS pin
is driven low by indexing into the PORTD data register and
clearing Bit 5. This causes the 2nd rank latch of the AD660 to
become transparent. The MSBY is then set to the SPI data
register where it is automatically transferred to the AD660.
The HC11 generates the requisite eight clock pulses with data
valid on the rising edges. After the most significant byte is
transmitted, the least significant byte (LSBY) is loaded from
memory and transmitted in a similar fashion. To complete the
transfer, the LDAC pin is driven high, latching the complete
16-bit word into the AD660.
Software Initialization Example
INIT
NEXTPT
SENDAT
WAIT1
WAIT2
LDAA
#$2F
STAA
LDAA
PORTD
#$38
STAA
DDRD
LDAA
#$50
STAA
SPCR
LDAA
MSBY
BSR
SENDAT
JMP
NEXTPT
LDY
#$1000
BCLR
$08,Y,$20
STAA
SPDR
LDAA
SPSR
BPL
WAIT1
LDAA
LSBY
STAA
SPDR
LDAA
SPSR
BPL
WAIT2
BSET
$08,Y,$20
; SS = I; SCK = 0; MOSI
= I
;SEND TO SPI OUTPUTS
; SS, SCK,MOSI = OUTPUTS
;SEND DATA DIRECTION
INFO
;DABL INTRPTS,SPI IS
MASTER & ON
;CPOL = 0, CPHA = 0,1MHZ
BAUD RATE
;LOAD ACCUM WITH UPPER 8
BITS
;JUMP TO DAC OUTPUT
ROUTINE
;INFINITE LOOP
;POINT AT ON-CHIP
REGISTERS
;DRIVE SS (LDAC) LOW
;SEND MS-BYTE TO SPI
DATA REG
;CHECK STATUS OF SPIE
;POLL FOR END OF XMISSION
;GET LOW 8 BITS FROM
MEMORY
;SEND LS-BYTE TO SPI
DATA REG
;CHECK STATUS OF SPIE
;POLL FOR END OF XMISSION
;DRIV SS HIGH TO LATCH
DATA
SCK
SS
DB0/DB8/SIN
CS
LDAC
AD660
01813-017
MDSI
SER
Figure 17. AD660 to 68HC11 (SPI) Interface
AD660 TO MICROWIRE INTERFACE
The flexible serial interface of the AD660 is also compatible
with the National Semiconductor MICROWIRE™ interface.
The MICROWIRE interface is used on microcontrollers, such
as the COP400 and COP800 series of processors. A generic
interface to the MICROWIRE interface is shown in Figure 18.
The G1, SK, and SO pins of the MICROWIRE interface are respectively connected to the LDAC, CS and DB0/DB8/SIN pins of
the AD660.
MICROWIRE™
SO
DB0/DB8/SIN
SK
CS
G1
LDAC
AD660
SER
01813-018
The AD660 interface to the Motorola SPI (serial peripheral
interface) is shown in Figure 17. The MOSI, SCK, and SS pins
of the 68HC11 are respectively connected to the DB0/DB8/SIN,
CS, and LDAC pins of the AD660. The SER pin of the AD660 is
tied low causing the first rank latch to be transparent. The
majority of the interfacing issues are taken care of in the
software initialization. A typical routine such as the one shown
in the Software Initialization Example begins by initializing the
state of the various SPI data and control registers.
Figure 18. AD660 to MICROWIRE Interface
AD660 TO ADSP-210x FAMILY INTERFACE
The serial mode of the AD660 minimizes the number of control
and data lines required to interface to digital signal processors
(DSPs) such as the ADSP-210x family. The application in
Figure 19 shows the interface between an ADSP-210x and the
AD660. Both the TFS pin and the DT pins of the ADSP-210x
should be connected to the SER and DB0 pins of the AD660,
respectively. An inverter is required between the SCLK output
and the CS input of the AD660 to ensure that data transmitted
to the DB0 pin is valid on the rising edge of CS.
The serial port (SPORT) of the DSP should be configured for
alternate framing mode so that TFS complies with the word
length framing requirement of SER. Note that the INVTFS bit
in the SPORT control register should be set to invert the TFS
signal so that SER is the correct polarity. The LDAC signal,
which must meet the minimum hold specification of tHIGH, is
easily generated by delaying the rising edge of SER with a
74HC74 flip-flop. The CS signal clocks the flip-flop, resulting
in a delay of approximately one CS clock cycle.
RTS
Rev. B | Page 15 of 20
AD660
In applications such as waveform generation, accurate timing of
the output samples is important to avoid noise that is induced
by jitter on the LDAC signal. In this example, the ADSP-210x
is set up to use the internal timer to interrupt the processor at
the precise and desired sample rate. When the timer interrupt
occurs, the 16-bit data word of the processor is written to the
transmit register (TXn). This causes the DSP to automatically
generate the TFS signal and begin transmission of the data.
74HC04
DT
AD660
DB0/DB8/SIN
1k
SER
Q
LDAC
Figure 19. AD660 to ADSP-210x Interface
AD660 TO Z80 INTERFACE
Figure 20 shows a Zilog Z80 8-bit microprocessor connected to
the AD660 using the byte mode interface. The double-buffered
capability of the AD660 allows the microprocessor to independently write to the low and high byte registers, and update the
DAC output. Processor speeds up to 6 MHz on the Z80 require
no extra wait states to interface with the AD660 when using a
74ALS138 as the address decoder.
The address decoder analyzes the input-output address produced
by the processor to select the function to be performed by the
AD660, qualified by the coincidence of the input/output request
(IORQ) and write (WR) pins. The least significant address bit
(A0) determines if the low or high byte register of the AD660 is
active. More significant address bits select between input register
loading, DAC output update, and unipolar or bipolar clear.
A typical Z80 software routine begins by writing the low byte of
the desired 16-bit DAC data to Address 0, followed by the high
byte to Address 1. The DAC output is then updated by activating
LDAC with a write to Address 2 (or Address 3). A clear to unipolar
zero occurs on a write to Address 4, and a clear to bipolar zero
is performed by a write to Address 5. The actual data written to
Address 2 through Address 5 is irrelevant. The decoder can easily
be expanded to control as many AD660 devices as required.
100
10
1
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
DB0 TO DB7
IORQ
E2
Y2
CLR
WR
E1
Y1
LDAC
Y0
CS
A1 TO A15
HBE
SER
+VLL
AD660
LBE
DGND
A0
A0 TO A15
01813-020
ADDRESS
DECODE
Figure 20. Connections for 8-Bit Bus Interface
Rev. B | Page 16 of 20
10M
Figure 21. DAC Output Noise Voltage Spectral Density
1k
100
10
1
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 22. Reference Noise Voltage Spectral Density
D0 TO D7
Z80
NOISE VOLTAGE (nV/ Hz)
74HC74
01813-019
D
NOISE VOLTAGE (nV/ Hz)
TFS
01813-021
CS
SCLK
In high resolution systems, noise is often the limiting factor. A
16-bit DAC with a 10 V span has an LSB size of 153 μV (−96 dB).
Therefore, the noise floor must remain below this level in the
frequency range of interest. The noise spectral density of the
AD660 is shown in Figure 21 and Figure 22. Figure 21 shows
the DAC output noise voltage spectral density for a 20 V span
excluding the reference. This figure shows the 1/f corner frequency
at 100 Hz and the wideband noise to be below 120 nV/√Hz.
Figure 22 shows the reference noise voltage spectral density and
shows the reference wideband noise to be below 125 nV/√Hz.
10M
01813-022
ADSP-210x
NOISE
AD660
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is the first issue. A
306 μA current through a 0.5 Ω trace develops a voltage drop of
153 μV, which is 1 LSB at the 16-bit level for a 10 V full-scale
span. In addition to ground drops, inductive and capacitive
coupling need to be considered, especially when high accuracy
analog signals share the same board with digital signals. Finally,
power supplies need to be decoupled to filter out ac noise.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide
PC tracks, large gauge wire, and ground planes are highly
recommended to provide low impedance signal paths. Separate
analog and digital ground planes should also be used, with a
single interconnection point to minimize ground loops. Analog
signals should be routed as far as possible from digital signals
and should cross them at right angles.
One feature that the AD660 incorporates to help the user layout
is that the analog pins (+VCC, −VEE, REF OUT, REF IN, SPAN/
BIPOLAR OFFSET, VOUT and AGND) are adjacent to help
isolate analog signals from digital signals.
SUPPLY DECOUPLING
The AD660 power supplies should be well filtered, well regulated,
and free from high frequency noise. Switching power supplies
are not recommended due to their tendency to generate spikes,
which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout
proximity between all power supply pins and ground. A 10 μF
tantalum capacitor in parallel with a 0.1 μF ceramic capacitor
provides adequate decoupling. VCC and VEE should be bypassed
to analog ground, while VLL should be decoupled to digital ground.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD660, associated analog circuitry, and interconnections as
far as possible from logic circuitry. A solid analog ground plane
around the AD660 will isolate large switching ground currents.
For these reasons, the use of wire wrap circuit construction is
not recommended; careful printed circuit construction is
preferred.
GROUNDING
The AD660 has two ground pins, designated analog ground
(AGND) and digital ground (DGND.) The analog ground pin is
the high quality ground reference point for the device. Any
external loads on the output of the AD660 should be returned
to analog ground. If an external reference is used, this should
also be returned to the analog ground.
If a single AD660 is used with separate analog and digital ground
planes, connect the analog ground plane to AGND and the digital
ground plane to DGND keeping lead lengths as short as possible.
Then connect AGND and DGND together at the AD660. If
multiple AD660 devices are used or the AD660 shares analog
supplies with other components, connect the analog and digital
returns together once at the power supplies rather than at each
chip. This single interconnection of grounds prevents large
ground loops and consequently prevents digital currents from
flowing through the analog ground.
Rev. B | Page 17 of 20
AD660
OUTLINE DIMENSIONS
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
24
13
1
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
12
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
071006-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 23. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
0.098 (2.49)
MAX
0.005 (0.13)
MIN
24
13
1
12
PIN 1
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.310 (7.87)
0.220 (5.59)
1.280 (32.51) MAX
0.060 (1.52)
0.015 (0.38)
0.320 (8.13)
0.290 (7.37)
0.150 (3.81)
MIN
0.100
(2.54)
BSC
0.070 (1.78) SEATING
0.030 (0.76) PLANE
15°
0°
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 24. 24-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-24)
Dimensions shown in inches and (millimeters)
Rev. B | Page 18 of 20
AD660
15.60 (0.6142)
15.20 (0.5984)
13
24
7.60 (0.2992)
7.40 (0.2913)
12
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
0.25 (0.0098)
45°
8°
0°
0.33 (0.0130)
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
060706-A
1
Figure 25. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
AD660AN
AD660ANZ1
AD660AR
AD660AR-REEL
AD660ARZ1
AD660ARZ-REEL1
AD660BN
AD660BNZ1
AD660BR
AD660BR-REEL
AD660BRZ1
AD660BRZ-REEL1
AD660SQ
AD660SQ/883B2
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
−55°C to +125°C
Gain TC Max ppm/°C
25
25
25
25
25
25
15
15
15
15
15
15
25
Z = RoHS Compliant Part.
For further details, refer to the AD660SQ/883B military data sheet.
Rev. B | Page 19 of 20
Package Description
24-Lead PDIP
24-Lead PDIP
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead PDIP
24-Lead PDIP
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead SOIC_W
24-Lead CERDIP
Package Option
N-24-1
N-24-1
RW-24
RW-24
RW-24
RW-24
N-24-1
N-24-1
RW-24
RW-24
RW-24
RW-24
Q-24
AD660
NOTES
©1993–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01813-0-6/08(B)
Rev. B | Page 20 of 20