Intel E28F020-150 28f020 2048k (256k x 8) cmos flash memory Datasheet

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28F020 2048K (256K X 8) CMOS
FLASH MEMORY
Flash Electrical Chip-Erase
 2 Second Typical Chip-Erase
Quick-Pulse Programming Algorithm
 10 µS Typical Byte-Program
 4 second Chip-Program
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100,000 Erase/Program Cycles
12.0 V ±5% VPP
High-Performance Read
 90 ns Maximum Access Time
CMOS Low Power Consumption
 10 mA Typical Active Current
 50 µA Typical Standby Current
 0 Watts Data Retention Power
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Integrated Program/Erase Stop Timer
Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
Noise Immunity Features
 ±10% VCC Tolerance
 Maximum Latch-Up Immunity
through EPI Processing
ETOX™ Nonvolatile Flash Technology
 EPROM-Compatible Process Base
 High-Volume Manufacturing
Experience
JEDEC-Standard Pinouts
 32-Pin Plastic Dip
 32-Lead PLCC
 32-Lead TSOP
(See Packaging Spec., Order #231369)
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Extended Temperature Options
Intel’s 28F020 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F020 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after sale. The 28F020 increases
memory flexibility, while contributing to time and cost savings.
The 28F020 is a 2048-kilobit nonvolatile memory organized as 262,144 bytes of eight bits. Intel’s 28F020 is
offered in 32-pin plastic DIP, 32-lead PLCC, and 32-lead TSOP packages. Pin assignments conform to
JEDEC standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel’s ETOX™ (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0 V VPP supply, the
28F020 performs 100,000 erase and program cycles—well within the time limits of the quick-pulse
programming and quick-erase algorithms.
Intel’s 28F020 employs advanced CMOS circuitry for systems requiring high-performance access speeds,
low power consumption, and immunity to noise. Its 90 ns access time provides zero wait-state performance
for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 µA translates
into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel’s unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins, from –1 V to VCC + 1 V.
With Intel’s ETOX process technology base, the 28F020 builds on years of EPROM experience to yield the
highest levels of quality, reliability, and cost-effectiveness.
December 1997
Order Number: 290245-009
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F020 may contain design defects or errors known as errata. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s website at http://www.intel.com
Copyright © Intel Corporation 1996, 1997.
* Third-party brands and names are the property of their respective owners.
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28F020
CONTENTS
PAGE
1.0 APPLICATIONS ..............................................5
2.0 PRINCIPLES OF OPERATION .......................8
2.1 Integrated Stop Timer ..................................8
2.2 Write Protection ...........................................9
2.2.1 Bus Operations......................................9
2.2.1.1 Read...............................................9
2.2.1.2 Output Disable ..............................10
2.2.1.3 Standby ........................................10
2.2.1.4 Intelligent Identifier Operation .......10
2.2.1.5 Write .............................................10
2.2.2 Command Definitions ..........................10
2.2.2.1 Read Command............................11
2.2.2.2 Intelligent Identifier Command ......11
2.2.2.3 Set-Up Erase/Erase Commands...12
2.2.2.4 Erase Verify Command.................12
2.2.2.5 Set-Up Program/Program
Commands ..................................12
2.2.2.6 Program Verify Command ............12
2.2.2.7 Reset Command...........................13
2.2.3 Extended Erase/Program Cycling........13
2.2.4 Quick-Pulse Programming Algorithm ...13
2.2.5 Quick-Erase Algorithm.........................13
3.0 DESIGN CONSIDERATIONS ........................16
3.1 Two-Line Output Control ............................16
3.2 Power Supply Decoupling ..........................16
3.3 VPP Trace on Printed Circuit Boards...........16
3.4 Power-Up/Down Protection ........................16
3.5 28F020 Power Dissipation .........................16
PAGE
4.0 ELECTRICAL SPECIFICATIONS..................18
4.1 Absolute Maximum Ratings ........................18
4.2 Operating Conditions..................................18
4.3 Capacitance ...............................................18
4.4 DC Characteristics—TTL/NMOS
Compatible—Commercial Products...........19
4.5 DC Characteristics—CMOS Compatible—
Commercial Products ................................20
4.6 DC Characteristics—TTL/NMOS
Compatible—Extended Temperature
Products ....................................................22
4.7 DC Characteristics—CMOS Compatible—
Extended Temperature Products ...............24
4.8 AC Characteristics—Read Only
Operations—Commercial and Extended
Temperature Products...............................28
4.9 AC Characteristics—Write/Erase/Program
Only Operations—Commercial and
Extended Temperature Products ...............30
4.10 Erase and Programming Performance.....31
4.11 AC Characteristics—Alternate CE#
Controlled Writes—Commercial and
Extended Temperature Products ...............35
5.0 ORDERING INFORMATION.........................38
6.0 ADDITIONAL INFORMATION ......................38
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28F020
REVISION HISTORY
Number
Description
-004
Removed Preliminary Classification. Clarified AC and DC test conditions. Added “dimple”
to F TSOP package. Corrected serpentine layout.
-005
Added –80V05, –90 ns speed grades. Added extended temperature devices. Corrected
AC Waveforms.
-006
Added –70 ns speed. Deleted –80 V05 speed. Revised symbols, i.e., CE, OE, etc. to CE#,
OE#, etc.
-007
Updated Command Def. Table. Updated 28F020 Quick-Erase Algorithm. Updated AC
Characteristics. Removed serpentine layout diagram.
-008
Minor changes throughout document.
-009
Deleted –70 ns speed and F TSOP package. Added –120 ns speed and extended
temperature devices. Updated Ordering Information chart. Updated AC Characteristics.
Replaced references to –70 ns with –90 ns on first page. Removed F TSOP package pin
configuration diagram.
————
4
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1.0 APPLICATIONS
The 28F020 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These
features make the 28F020 an innovative alternative
to disk, EEPROM, and battery-backed static RAM.
Where periodic updates of code and data tables
are required, the 28F020’s reprogrammability and
nonvolatility make it the obvious and ideal
replacement for EPROM.
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption—a
consideration
particularly
important in portable equipment. Flash memory
increases flexibility with electrical chip-erasure and
in-system update capability of operating systems
and application code. With updatable code, system
manufacturers can easily accommodate lastminute changes as revisions are made.
In diskless workstations and terminals, network
traffic reduces to a minimum and systems are
instant-on. Reliability exceeds that of electromechanical media. Often in these environments,
power interruptions force extended re-boot periods
for all networked terminals. This mishap is no
longer an issue if boot code, operating systems,
communication protocols and primary applications
are flash resident in each terminal.
For embedded systems that rely on dynamic
RAM/disk for main system memory or nonvolatile
backup storage, the 28F020 flash memory offers a
solid state alternative in a minimal form factor. The
28F020 provides higher performance, lower power
consumption, instant-on capability, and allows an
“eXecute in place” (XIP) memory hierarchy for
code and data table reading. Additionally, the flash
memory is more rugged and reliable in harsh
environments where extreme temperatures and
shock can cause disk-based systems to fail.
The need for code updates pervades all phases of
a system’s life—from prototyping to system
manufacture to after sale service. The electrical
chip-erasure and reprogramming ability of the
28F020 allows in-circuit alterability; this eliminates
unnecessary handling and less reliable socketed
28F020
connections,
while
adding
greater
manufacture, and update flexibility.
test,
Material and labor costs associated with code
changes increases at higher levels of system
integration—the most costly being code updates
after sale. Code “bugs,” or the desire to augment
system functionality, prompt after sale code
updates. Field revisions to EPROM-based code
requires the removal of EPROM components or
entire boards. With the 28F020, code updates are
implemented locally via an edge connector, or
remotely over a communications link.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory’s inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Flash memory’s electrical chip-erasure, byte
programmability and complete nonvolatility fit well
with data accumulation and recording needs.
Electrical chip-erasure gives the designer a “blank
slate” in which to log or record data. Data can be
periodically off-loaded for analysis and the flash
memory erased producing a new “blank slate.”
A high degree of on-chip feature integration
simplifies memory-to-processor interfacing. Figure
3 depicts two 28F020s tied to the 80C186 system
bus. The 28F020’s architecture minimizes interface
circuitry needed for complete in-circuit updates of
memory contents.
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mm thickness. TSOP
is particularly suited for portable equipment and
applications requiring large amounts of flash
memory.
With cost-effective in-system reprogramming,
extended cycling capability, and true nonvolatility,
the 28F020 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straightforward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the
high standards of today’s designs.
5
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28F020
DQ0 - DQ7
VCC
VSS
VPP
Erase Voltage
Switch
Input/Output
Buffers
To Array Source
WE#
State
Control
Command
Register
Integrated Stop
Timer
PGM Voltage
Switch
Chip Enable
Output Enable
Logic
CE#
OE#
Address Latch
STB
A0 - A17
STB
Data Latch
Y-Decoder
Y-Gating
X-Decoder
2,097,152 Bit
Cell Matrix
0245_01
Figure 1. 28F020 Block Diagram
Table 1. Pin Description
Symbol
A0–A17
DQ0–DQ7
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Type
INPUT
INPUT/OUTPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are
internally latched during a write cycle.
DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active
high and float to tri-state off when the chip is deselected or the
outputs are disabled. Data is internally latched during a write cycle.
CE#
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers,
decoders and sense amplifiers. CE# is active low; CE# high
deselects the memory device and reduces power consumption to
standby levels.
OE#
INPUT
OUTPUT ENABLE: Gates the devices output through the data
buffers during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the control register and the
array. Write enable is active low. Addresses are latched on the
falling edge and data is latched on the rising edge of the WE#
pulse.
Note: With VPP ≤ 6.5 V, memory contents cannot be altered.
VPP
ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.
VCC
DEVICE POWER SUPPLY (5 V ±10%)
VSS
GROUND
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28F020
Figure 2. 28F020 Pin Configurations
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28F020
VCC
VPP
VCC
80C186
System Bus
VPP
A0-A17
VCC
A0-A17
A1-A18
VCC
DQ0-DQ7
DQ8 -DQ15
DQ0 -DQ7
DQ0-DQ7
28F020
Address Decoded
Chip Select
28F020
CE#
BHE#
CE#
WE#
WR#
A0
WE#
RD#
OE#
OE#
0245_03
Figure 3. 28F020 in an 80C186 System
2.0 PRINCIPLES OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming.
The 28F020 introduces a command register to
manage this new functionality. The command
register allows for 100% TTL-level control inputs,
fixed power supplies during erasure and
programming, and maximum EPROM compatibility.
In the absence of high voltage on the VPP pin, the
28F020 is a read-only memory. Manipulation of the
external memory control pins yields the standard
EPROM read, standby, output disable, and
intelligent identifier operations.
The same EPROM read, standby, and output
disable operations are available when high voltage
is applied to the VPP pin. In addition, high voltage
on VPP enables erasure and programming of the
device. All functions associated with altering
memory contents—intelligent identifier, erase,
erase verify, program, and program verify—are
accessed via the command register.
8
Commands are written to the register using
standard microprocessor write timings. Register
contents serve as input to an internal state
machine which controls the erase and
programming circuitry. Write cycles also internally
latch addresses and data needed for programming
or erase operations. With the appropriate
command written to the register, standard
microprocessor read timings output array data,
access the intelligent identifier codes, or output
data for erase and program verification.
2.1
Integrated Stop Timer
Successive command write cycles define the
durations of program and erase operations;
specifically, the program or erase time durations
are normally terminated by associated Program or
Erase Verify commands. An integrated stop timer
provides simplified timing control over these
operations; thus eliminating the need for maximum
program/erase timing specifications. Programming
and erase pulse durations are minimums only.
When the stop timer terminates a program or erase
operation, the device enters an inactive state and
remains inactive until receiving the appropriate
Verify or Reset command.
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28F020
Table 2. 28F020 Bus Operations
VPP(1)
A0
A9
CE#
OE#
WE#
Read
VPPL
A0
A9
VIL
VIL
VIH
Data Out
Output Disable
VPPL
X
X
VIL
VIH
VIH
Tri-State
Standby
VPPL
X
X
VIH
X
X
Tri-State
VIL
VIL
VIH
Data = 89H
Mode
READ-
DQ0–DQ7
Intelligent Identifier
(Mfr)(2)
VPPL
VIL
VID(3)
Intelligent Identifier
(Device)(2)
VPPL
VIH
VID(3)
VIL
VIL
VIH
Data = BDH
Read
VPPH
A0
A9
VIL
VIL
VIH
Data Out(4)
READ/
Output Disable
VPPH
X
X
VIL
VIH
VIH
Tri-State
WRITE
Standby(5)
VPPH
X
X
VIH
X
X
Tri-State
Write
VPPH
A0
A9
VIL
VIH
VIL
Data In(6)
ONLY
NOTES:
1. Refer to DC Characteristics. When VPP = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VID is the intelligent identifier high voltage. Refer to DC Characteristics.
4. Read operations with VPP = VPPH may access array data or the intelligent identifier codes.
5. With VPP at high voltage, the standby current equals ICC + IPP (standby).
6. Refer to Table 3 for valid data-in during a write operation.
7. X can be VIL or VIH.
2.2
Write Protection
The command register is only active when VPP is
at high voltage. Depending upon the application,
the system designer may choose to make the VPP
power supply switchable—available only when
memory updates are desired. When VPP = VPPL,
the contents of the register default to the Read
command, making the 28F020 a read only
memory. In this mode, the memory contents
cannot be altered.
Or, the system designer may choose to “hardwire”
VPP, making the high voltage supply constantly
available. In this case, all command register
functions are inhibited whenever VCC is below the
write lockout voltage VLKO (see Power-Up/Down
Protection). The 28F020 is designed to
accommodate either design practice, and to
encourage optimization of the processor memory
interface.
The two step program/erase write sequence to the
command register provides additional software
write protection.
2.2.1
2.2.1.1
BUS OPERATIONS
Read
The 28F020 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE#) is the power control
and should be used for device selection. Output
Enable (OE#) is the output control and should be
used to gate data from the output pins,
independent of device selection. Refer to AC read
timing waveforms.
When VPP is high (VPPH), the read operation can
be used to access array data, to output the
intelligent identifier codes, and to access data for
program/erase verification. When VPP is low (VPPL),
the read operation can only access the array data.
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28F020
2.2.1.2
Output Disable
With OE# at a logic-high level (VIH), output from
the device is disabled. Output pins are placed in a
high-impedance state.
2.2.1.3
Standby
With CE# at a logic-high level, the standby
operation disables most of the 28F020’s circuitry
and
substantially
reduces
device
power
consumption. The outputs are placed in a highimpedance state, independent of the OE# signal. If
the 28F020 is deselected during erasure,
programming, or program/erase verification, the
device draws active current until the operation is
terminated.
2.2.1.4
Intelligent Identifier Operation
The intelligent identifier operation outputs the
manufacturer code (89H) and device code (BDH).
Programming equipment automatically matches
the device with its proper erase and programming
algorithms.
With CE# and OE# at a logic low level, raising A9
to high voltage VID (see DC Characteristics)
activates the operation. Data read from locations
0000H and 0001H represent the manufacturer’s
code and the device code, respectively.
The manufacturer and device codes can also be
read via the command register, for instances where
the 28F020 is erased and reprogrammed in the
target system. Following a write of 90H to the
command register, a read from address location
0000H outputs the manufacturer code (89H). A
read from address 0001H outputs the device code
(BDH).
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2.2.1.5
Write
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Device
erasure
and
programming
are
accomplished via the command register, when high
voltage is applied to the VPP pin. The contents of
the register serve as input to the internal state
machine. The state machine outputs dictate the
function of the device.
The command register itself does not occupy an
addressable memory location. The register is a
latch used to store the command, along with
address and data information needed to execute
the command.
The command register is written by bringing WE#
to a logic-low level (VIL), while CE# is low.
Addresses are latched on the falling edge of WE#
while data is latched on the rising edge of the WE#
pulse. Standard microprocessor write timings are
used.
Refer to AC Characteristics—Write/Erase/Program
Only Operations and the erase/programming
waveforms for specific timing parameters.
2.2.2
COMMAND DEFINITIONS
When low voltage is applied to the VPP pin, the
contents of the command register default to 00H,
enabling read only operations.
Placing high voltage on the VPP pin enables
read/write operations. Device operations are
selected by writing specific data patterns into the
command register. Table 3 defines these 28F020
register commands.
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Command
28F020
Table 3. Command Definitions
Bus
Cycles
Req’d
First Bus Cycle
Second Bus Cycle
Operation(1)
Address(2)
Data(3)
Operation(1)
Address(2)
Data(3)
Read Memory
1
Write
X
00H
Read Intelligent
Identifier Codes(4)
3
Write
IA
90H
Read
IA
ID
Set-Up
Erase/Erase(5)
2
Write
X
20H
Write
X
20H
Erase Verify(5)
2
Write
EA
A0H
Read
X
EVD
Set-Up Program/
Program(6)
2
Write
X
40H
Write
PA
PD
Program Verify(6)
2
Write
X
C0H
Read
X
PVD
Reset(7)
2
Write
X
FFH
Write
X
FFH
NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: 00H for manufacturer code, 01H for device code.
EA = Erase Address: Address of memory location to be read during erase verify.
PA = Program Address: Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. ID = Identifier Address: Data read from location IA during device identification (Mfr = 89H, Device = BDH).
EVD = Erase Verify Data: Data read from location EA during erase verify.
PD = Program Data: Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes.
5. Figure 5 illustrates the 28F020 Quick-Erase Algorithm flowchart.
6. Figure 4 illustrates the 28F020 Quick-Pulse Programming Algorithm flowchart.
7. The second bus cycle must be followed by the desired command register write.
2.2.2.1
Read Command
While VPP is high, for erasure and programming,
memory contents can be accessed via the Read
command. The read operation is initiated by writing
00H into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register
contents are altered.
The default contents of the register upon VPP
power-up is 00H. This default value ensures that
no spurious alteration of memory contents occurs
during the VPP power transition. Where the VPP
supply is hardwired to the 28F020, the device
powers-up and remains enabled for reads until the
command register contents are changed. Refer to
the AC Characteristics—Read-Only Operations
and waveforms for specific timing parameters.
2.2.2.2
Intelligent Identifier Command
Flash memories are intended for use in
applications where the local CPU alters memory
contents. As such, manufacturer and device codes
must be accessible while the device resides in the
target system. PROM programmers typically
access signature codes by raising A9 to a high
voltage. However, multiplexing high voltage onto
address lines is not a desired system design
practice.
11
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28F020
The 28F020 contains an intelligent identifier
operation to supplement traditional PROMprogramming methodology. The operation is
initiated by writing 90H into the command register.
Following the command Write, a read cycle from
address 0000H retrieves the manufacturer code of
89H. A read cycle from address 0001H returns the
device code of BDH. To terminate the operation, it
is necessary to write another valid command into
the register.
2.2.2.3
Set-Up Erase/Erase Commands
Set-Up Erase is a command-only operation that
stages the device for electrical erasure of all bytes
in the array. The set-up erase operation is
performed by writing 20H to the command register.
In the case where the data read is not FFH,
another erase operation is performed. (Refer to
Section 2.2.2.3, Set-Up Erase/Erase Commands.)
Verification then resumes from the address of the
last verified byte. Once all bytes in the array have
been verified, the erase step is complete. The
device can be programmed. At this point, the verify
operation is terminated by writing a valid command
(e.g., Program Set-Up) to the command register.
Figure 5, the 28F020 Quick-Erase Algorithm
flowchart, illustrates how commands and bus
operations are combined to perform electrical
erasure of the 28F020. Refer to AC
Characteristics—Write/Erase/Program Only Operations and waveforms for specific timing
parameters.
2.2.2.5
To commence chip-erasure, the Erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
WE# pulse and terminates with the rising edge of
the next WE# pulse (i.e., Erase Verify command).
This two-step sequence of set-up followed by
execution ensures that memory contents are not
accidentally erased. Also, chip-erasure can only
occur when high voltage is applied to the VPP pin.
In the absence of this high voltage, memory
contents are protected against erasure. Refer to
AC Characteristics—Write/Erase/Program Only
Operations and waveforms for specific timing
parameters.
2.2.2.4
Erase Verify Command
The Erase command erases all bytes of the array
in parallel. After each erase operation, all bytes
must be verified. The erase verify operation is
initiated by writing A0H into the command register.
The address for the byte to be verified must be
supplied as it is latched on the falling edge of the
WE# pulse. The register write terminates the erase
operation with the rising edge of its WE# pulse.
The 28F020 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The Erase Verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
12
Set-Up Program/Program
Commands
Set-Up program is a command-only operation that
stages the device for byte programming. Writing
40H into the command register performs the set-up
operation.
Once the program set-up operation is performed,
the next WE# pulse causes a transition to an active
programming operation. Addresses are internally
latched on the falling edge of the WE# pulse. Data
is internally latched on the rising edge of the WE#
pulse. The rising edge of WE# also begins the
programming
operation.
The
programming
operation terminates with the next rising edge of
WE# used to write the Program Verify command.
Refer to AC Characteristics—Write/Erase/Program
Only Operations and waveforms for specific timing
parameters.
2.2.2.6
Program Verify Command
The 28F020 is programmed on a byte-by-byte
basis. Byte programming may occur sequentially or
at random. Following each programming operation,
the byte just programmed must be verified.
The program verify operation is initiated by writing
C0H into the command register. The register write
terminates the programming operation with the
rising edge of its WE# pulse. The program verify
operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F020 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison
E
between the programmed byte and true data
means that the byte is successfully programmed.
Programming then proceeds to the next desired
byte location. Figure 4, the 28F020 Quick-Pulse
Programming Algorithm flowchart, illustrates how
commands are combined with bus operations to
perform byte programming. Refer to AC
Characteristics—Write/Erase/Program Only Operations and waveforms for specific timing
parameters.
2.2.2.7
Reset Command
A Reset command is provided as a means to
safely abort the Erase or Program command
sequences. Following either Set-Up command
(Erase or Program) with two consecutive writes of
FFH will safely abort the operation. Memory
contents will not be altered. A valid command must
then be written to place the device in the desired
state.
2.2.3
EXTENDED ERASE/PROGRAM
CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin
oxide EEPROMs for tunneling can literally tear
apart the oxide at defect regions. To combat this,
some suppliers have implemented redundancy
schemes, reducing cycling failures to insignificant
levels. However, redundancy requires that cell size
be doubled—an expensive solution.
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting
improvements in cycling reliability come without
increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge
carrying ability ten-fold. Second, the oxide area per
cell subjected to the tunneling electric field is onetenth that of common EEPROMs, minimizing the
probability of oxide defects in the region. Finally,
the peak electric field during erasure is
approximately 2 MV/cm lower than EEPROM. The
lower electric field greatly reduces oxide stress and
the probability of failure.
The 28F020 is capable of 100,000 program/erase
cycles. The device is programmed and erased
using Intel’s quick-pulse programming and quickerase algorithms. Intel’s algorithmic approach uses
28F020
a series of operations (pulses), along with byte
verification, to completely and reliably erase and
program the device.
2.2.4
QUICK-PULSE PROGRAMMING
ALGORITHM
The quick-pulse programming algorithm uses
programming operations of 10 µs duration. Each
operation is followed by a byte verification to
determine when the addressed byte has been
successfully programmed. The algorithm allows for
up to 25 programming operations per byte,
although most bytes verify on the first or second
operation. The entire sequence of programming
and byte verification is performed with VPP at high
voltage. Figure 4 illustrates the 28F020 QuickPulse Programming Algorithm flowchart.
2.2.5
QUICK-ERASE ALGORITHM
Intel’s quick-erase algorithm yields fast and reliable
electrical erasure of memory contents. The
algorithm employs a closed-loop flow, similar to the
quick-pulse programming algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents.
The 28F020 is erased when shipped from the
factory. Reading FFH data from the device would
immediately be followed by device programming.
For devices being erased and reprogrammed,
uniform and reliable erasure is ensured by first
programming all bits in the device to their charged
state (Data = 00H). This is accomplished, using the
quick-pulse programming algorithm, in approximately four seconds.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address 0000H and continues through the array to
the last address, or until data other than FFH is
encountered. With each erase operation, an
increasing number of bytes verify to the erased
state. Erase efficiency may be improved by storing
the address of the last byte verified in a register.
Following the next erase operation, verification
starts at that stored address location. Erasure
typically occurs in two seconds. Figure 5 illustrates
the 28F020 Quick-Erase Algorithm flowchart.
13
E
28F020
Bus
Operation
Start
Programming (4)
Apply VPPH
Command
Wait for VPP Ramp to
VPPH(1)
Standby
(1)
Comments
PLSCNT = 0
Initialize Pulse-Count
Write Set-Up
Program Cmd
Write Program
Cmd (A/D)
Write
Set-Up
Program
Data = 40H
Write
Program
Valid Address/Data
Duration of Program
Operation (tWHWH1 )
Standby
Time Out 10 µs
Write
Write Program
Verify Cmd
Program
Verify(2)
Stand-by
Time Out 6 µs
tWHGL
Read Byte to Verify
Programming
Read
Read Data
from Device
Data = C0H; Stops
Program Operations(3)
N
Verify
Data
N
Inc
PLSCNT
=25?
Compare Data Output to
Data Expected
Standby
Y
Y
Increment
Address
N
Write
Last
Address?
Read
Data = 00H, Resets the
Register for Read
Operations
Y
Write Read Cmd
Apply VPPL (1)
Programming
Completed
Standby
Wait for VPP Ramp to VPPL(1)
Apply VPPL (1)
Program
Error
0245_04
NOTES:
1. See DC Characteristics for the value of VPPH and VPPL.
2. Program Verify is performed only after byte programming. A final read/compare may be performed (optional) after the
register is written with the Read command.
3. Refer of Principles of Operation.
4. Caution: The algorithm must be followed to ensure proper and reliable operation of the device.
Figure 4. 28F020 Quick-Pulse Programming Algorithm
14
E
28F020
Start Erasure (4)
Y
Bus
Operation
Command
Comments
Entire Memory Must = 00H
Before Erasure
Data = 00H?
N
Use Quick-Pulse
Programming Algorithm
(Figure 4)
Program All
Bytes to 00H
Standby
Apply VPPH (1)
Wait for VPP Ramp to VPPH
ADDR = 00H
PLSCNT = 0
(1)
Initialize Addresses and
Pulse-Count
Write Erase
Set-Up Cmd
Write
Set-Up
Erase
Data = 20H
Write Erase Cmd
Write
Erase
Data = 20H
Time Out 10 ms
Stand-by
Write Erase
Verify Cmd
Write
Time Out 6 µs
Standby
Read Data
from Device
Read
Duration of Erase Operation
(tWHWH2 )
Erase (2)
Verify
Addr = Byte to Verify;
Data = A0H; Stops Erase
Operation(3)
tWHGL
Read Byte to Verify Erasure
N
N
Data = FFH?
Y
Inc
PLSCNT =
1000?
Compare Output to FFH
Increment Pulse-Count
Standby
Y
N
Increment Addr
Last Address?
Write
Y
Read
Data = 00H, Resets the
Register for Read Operations
Write Read Cmd
Standby
Apply VPPL (1)
Apply VPPL (1)
Erasure
Completed
Erase Error
Wait for VPP Ramp to VPPL (1)
0245_05
NOTES:
1. See DC Characteristics for the value of VPPH and VPPL.
2. Erase Verify is performed only after chip-erasure. A final read/compare may be performed (optional) after the register is
written with the Read command.
3. Refer of Principles of Operation.
4. Caution: The algorithm must be followed to ensure proper and reliable operation of the device.
Figure 5. 28F020 Quick-Erase Algorithm
15
28F020
E
3.0 DESIGN CONSIDERATIONS
3.3
3.1
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the VPP power
supply trace. The VPP pin supplies the memory cell
current for programming. Use similar trace widths
and layout considerations given the VCC power bus.
Adequate VPP supply traces and decoupling will
decrease VPP voltage spikes and overshoots.
Two-Line Output Control
Flash memories are often used in larger memory
arrays. Intel provides two read control inputs to
accommodate multiple memory connections. Twoline control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
3.4
VPP Trace on Printed Circuit
Boards
Power-Up/Down Protection
To efficiently use these two control inputs, an
address decoder output should drive chip enable,
while the system’s read signal controls all flash
memories and other parallel memories. This
assures that only enabled memory devices have
active outputs, while deselected devices maintain
the low power standby condition.
The 28F020 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F020 is
indifferent as to which power supply, VPP or VCC,
powers up first. Power supply sequencing is not
required. Internal circuitry in the 28F020 ensures
that the command register is reset to the read
mode on power-up.
3.2
A system designer must guard against active
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and CE# must be low for a
command write, driving either to VIH will inhibit
writes. The control register architecture provides an
added level of protection since alteration of
memory contents only occurs after successful
completion of the two-step command sequences.
Power Supply Decoupling
Flash memory power-switching characteristics
require careful device decoupling. System
designers are interested in three supply current
(ICC) issues—standby, active, and transient current
peaks produced by falling and rising edges of chip
enable. The capacitive and inductive loads on the
device outputs determine the magnitudes of these
peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 µF ceramic
capacitor connected between VCC and VSS, and
between VPP and VSS.
Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices.
Also, for every eight devices, a 4.7 µF electrolytic
capacitor should be placed at the array’s power
supply connection, between VCC and VSS. The bulk
capacitor will overcome voltage slumps caused by
printed circuit board trace inductance, and will
supply charge to the smaller capacitors as needed.
16
3.5
28F020 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F020 does not consume any power to retain
code or data when the system is off. Table 4
illustrates the power dissipated when updating the
28F020.
E
28F020
Table 4. 28F020 Typical Update Power Dissipation(4)
Notes
Power Dissipation (Watt-Seconds)
Array Program/Program Verify
Operation
1
0.34
Array Erase/Erase Verify
2
0.37
One Complete Cycle
3
1.05
NOTES:
1. Formula to calculate typical Program/Program Verify Power = [VPP x # Bytes typical # Prog Pulse (tWHWH1 × IPP2 typical +
tWHGL × IPP4 typical)] + [VCC × # Bytes × typical # Prog Pulses (tWHWH1 × ICC2 typical + tWHGL × ICC4 typical)].
2. Formula to calculate typical Erase/Erase Verify Power = [VPP (IPP3 typical × tERASE typical + IPP5 typical × tWHGL × # Bytes)]
+ [VCC (ICC3 typical × tERASE typical + ICC5 typical × tWHGL × # Bytes)].
3. One Complete Cycle = Array Preprogram + Array Erase + Program.
4. “Typicals” are not guaranteed but based on a limited number of samples from 28F020-150 production lots.
17
E
28F020
4.0 ELECTRICAL SPECIFICATIONS
4.1
NOTICE: This is a production datasheet. The specifications
are subject to change without notice.
Absolute Maximum Ratings*
*WARNING: Stressing the device beyond the Absolute
Maximum Ratings may cause permanent damage. These
are stress ratings only. Operation beyond the Operating
Conditions is not recommended and extended exposure
beyond the Operating Conditions may affect device
reliability.
NOTES:
1. Operating temperature is for commercial product
defined by this specification.
2. Operating temperature is for extended temperature
product as defined by this specification.
3. Minimum DC input voltage is –0.5 V. During transitions,
inputs may undershoot to –2.0 V for periods less than
20 ns. Maximum DC voltage on output pins is VCC +
0.5 V, which may overshoot to VCC + 2.0 V for periods
less than 20 ns.
4. Maximum DC voltage on A9 or VPP may overshoot to
+14.0 V for periods less than 20 ns.
5. Output shorted for no more than one second. No more
than one output shorted at a time.
6. See Testing Input/Output Waveform (Figure 6) and AC
Testing Load Circuit (Figure 7) for testing
characteristics.
7. See High Speed AC Testing Input/Output Waveform
(Figure 8) and High Speed AC Testing Load Circuit
(Figure 9) for testing characteristics.
Operating Temperature
During Read .........................0 °C to +70 °C(1)
During Erase/Program ..........0 °C to +70 °C(1)
Operating Temperature
During Read .....................–40 °C to +85 °C(2)
During Erase/Program ......–40 °C to +85 °C(2)
Temperature Under Bias.........–10 °C to +80 °C(1)
Temperature Under Bias.........–50 °C to +95 °C(2)
Storage Temperature............... –65 °C to +125 °C
Voltage on Any Pin with
Respect to Ground ............–2.0 V to +7.0 V(2)
Voltage on Pin A9 with
Respect to Ground ........–2.0 V to +13.5 V(2,3)
VPP Supply Voltage with
Respect to Ground
During Erase/Program ...–2.0 V to +14.0 V(2,3)
VCC Supply Voltage with
Respect to Ground ............–2.0 V to +7.0 V(2)
Output Short Circuit Current.................. 100 mA(4)
4.2
Operating Conditions
Limits
Symbol
Parameter
Min
Max
Unit
TA
Operating
Temperature(1)
0
70
°C
Operating
Temperature(2)
TA
VCC
VCC
4.3
–40
+85
°C
VCC Supply Voltage
(10%)(6)
4.50
5.50
V
VCC Supply Voltage
(5%)(7)
4.75
5.25
V
Capacitance
TA = 25 °C, f = 1.0 MHz
Limits
Symbol
Parameter
Notes
Min
Max
Unit
Conditions
CIN
Address/Control Capacitance
1
8
pF
VIN = 0 V
COUT
Output Capacitance
1
12
pF
VOUT = 0 V
NOTE:
1. Sampled, not 100% tested.
18
E
4.4
28F020
DC Characteristics—TTL/NMOS Compatible—Commercial Products
Limits
Symbol
Parameter
Notes
Min
Typ(3)
Max
Unit
Test Conditions
ILI
Input Leakage
Current
1
±1.0
µA
VCC = VCC Max
VIN = VCC or VSS
ILO
Output Leakage
Current
1
±10
µA
VCC = VCC Max
VOUT = VCC or VSS
ICCS
VCC Standby
Current
1
0.3
1.0
mA
VCC = VCC Max
CE# = VIH
ICC1
VCC Active
Read Current
1
10
30
mA
VCC = VCC Max
CE# = VIL
f = 6 MHz
IOUT = 0 mA
ICC2
VCC
Programming
Current
1, 2
1.0
10
mA
Programming in
Progress
ICC3
VCC Erase
Current
1, 2
5.0
15
mA
Erasure in
Progress
ICC4
VCC Program
Verify Current
1, 2
5.0
15
mA
VPP = VPPH
Program Verify
in Progress
ICC5
VCC Erase
Verify Current
1, 2
5.0
15
mA
VPP = VPPH
Erase Verify
in Progress
IPPS
VPP Leakage
Current
1
±10
µA
VPP ≤ VCC
IPP1
VPP Read
Current, ID
Current
1
200
µA
VPP > VCC
90
or Standby
Current
VPP ≤ VCC
±10
IPP2
VPP
Programming
Current
1, 2
8
30
mA
VPP = VPPH
Programming in
Progress
IPP3
VPP Erase
Current
1, 2
10
30
mA
VPP = VPPH
IPP4
VPP Program
Verify Current
1, 2
2.0
5.0
mA
VPP = VPPH
Program Verify in
Progress
IPP5
VPP EraseVerify Current
1, 2
2.0
5.0
mA
VPP = VPPH
Erase Verify in
Progress
19
E
28F020
4.4
DC Characteristics—TTL/NMOS Compatible—Commercial Products
(Continued)
Limits
Symbol
Parameter
Notes
Min
Typ(3)
Max
Unit
Test Conditions
VIL
Input Low
Voltage
–0.5
0.8
V
VIH
Input High
Voltage
2.0
VCC
+ 0.5
V
VOL
Output Low
Voltage
0.45
V
VCC = VCC Min
IOL = 5.8 mA
VOH1
Output High
Voltage
2.4
V
VCC = VCC Min
IOH = –2.5 mA
VID
A9 Intelligent
Identifier
Voltage
11.50
IID
A9 Intelligent
Identifier
Current
VPPL
VPP during
Read-Only
Operations
VPPH
VPP during
Read/Write
Operations
VLKO
VCC
Erase/Write
Lock Voltage
13.00
V
200
µA
A9 = VID
0.00
6.5
V
NOTE:
Erase/Program
are Inhibited
when VPP = VPPL
11.40
12.60
V
1, 2
90
2.5
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, T = 25 °C. These currents are
valid for all product versions (packages and speeds).
2. Not 100% tested: Characterization data available.
3. “Typicals” are not guaranteed, but based on a limited number of samples from production lots.
4.5
DC Characteristics—CMOS Compatible—Commercial Products
Limits
Symbol
Parameter
Notes
Min
Typ(3)
Max
Unit
Test Conditions
ILI
Input Leakage
Current
1
±1.0
µA
VCC = VCC Max
VIN = VCC or VSS
ILO
Output Leakage
Current
1
±10
µA
VCC = VCC Max
VOUT = VCC or VSS
ICCS
VCC Standby
Current
1
100
µA
VCC = VCC Max
CE# = VCC ±0.2 V
20
50
E
4.5
28F020
DC Characteristics—CMOS Compatible—Commercial Products (Continued)
Limits
Typ(3)
Max
Unit
1
10
30
mA
VCC = VCC Max
CE# = VIL
f = 6 MHz,
IOUT = 0 mA
VCC
Programming
Current
1, 2
1.0
10
mA
Programming in
Progress
ICC3
VCC Erase
Current
1, 2
5.0
15
mA
Erasure in
Progress
ICC4
VCC Program
Verify Current
1, 2
5.0
15
mA
VPP = VPPH
Program Verify in
Progress
ICC5
VCC Erase
Verify Current
1, 2
5.0
15
mA
VPP = VPPH
Erase Verify in
Progress
IPPS
VPP Leakage
Current
1
±10
µA
VPP ≤ VCC
IPP1
VPP Read
Current,
ID Current or
Standby Current
1
200
µA
VPP > VCC
Symbol
Parameter
Notes
ICC1
VCC Active Read
Current
ICC2
Min
90
Test Conditions
VPP ≤ VCC
±10
IPP2
VPP
Programming
Current
1, 2
8
30
mA
VPP = VPPH
Programming in
Progress
IPP3
VPP Erase
Current
1, 2
10
30
mA
VPP = VPPH
Erasure in
Progress
IPP4
VPP Program
Verify Current
1, 2
2.0
5.0
mA
VPP = VPPH
Program Verify in
Progress
IPP5
VPP Erase Verify
Current
1, 2
2.0
5.0
mA
VPP = VPPH
Erase Verify in
Progress
VIL
Input Low
Voltage
–0.5
0.8
V
VIH
Input High
Voltage
0.7
VCC
VCC +
0.5
V
VOL
Output Low
Voltage
0.45
V
VCC = VCC Min
IOL = 5.8 mA
21
E
28F020
4.5
DC Characteristics—CMOS Compatible—Commercial Products (Continued)
Limits
Symbol
VOH1
Parameter
Notes
Output High
Voltage
Typ(3)
Max
0.85
VCC
VOH2
Unit
V
VCC –
0.4
VID
A9 Intelligent
Identifier Voltage
IID
A9 Intelligent
Identifier Current
VPPL
VPP during
Read-Only
Operations
VPPH
VPP during
Read/Write
Operations
VLKO
VCC Erase/Write
Lock Voltage
4.6
Min
Test Conditions
VCC = VCC Min
IOH = –2.5 mA
VCC = VCC Min
IOH = –100 µA
11.50
13.00
V
200
µA
A9 = VID
0.00
6.5
V
NOTE:
Erase/Programs
are Inhibited when
VPP = VPPL
11.40
12.60
V
1, 2
90
2.5
V
DC Characteristics—TTL/NMOS Compatible—Extended Temperature
Products
Limits
Symbol
Parameter
Notes
Min
Typ(3)
Max
Unit
Test Conditions
ILI
Input Leakage
Current
1
±1.0
µA
VCC = VCC Max
VIN = VCC or VSS
ILO
Output Leakage
Current
1
±10
µA
VCC= VCC Max
VOUT = VCC or
VSS
ICCS
VCC Standby
Current
1
0.3
1.0
mA
VCC = VCC Max
CE# = VIH
ICC1
VCC Active Read
Current
1
10
30
mA
VCC = VCC Max
CE# = VIL
f = 6 MHz
IOUT = 0 mA
ICC2
VCC
Programming
Current
1, 2
1.0
30
mA
Programming in
Progress
22
E
4.6
28F020
DC Characteristics—TTL/NMOS Compatible—Extended Temperature
Products (Continued)
Limits
Symbol
Parameter
Notes
Min
Typ(3)
Max
Unit
Test Conditions
ICC3
VCC Erase
Current
1, 2
5.0
30
mA
Erasure in
Progress
ICC4
VCC Program
Verify Current
1, 2
5.0
30
mA
VPP = VPPH
Program Verify in
Progress
ICC5
VCC Erase
Verify Current
1, 2
5.0
30
mA
VPP = VPPH
Erase Verify in
Progress
IPPS
VPP Leakage
Current
1
±10
µA
VPP ≤ VCC
IPP1
VPP Read
Current, ID
Current or
Standby Current
1
200
µA
VPP > VCC
90
VPP ≤ VCC
±10
IPP2
VPP
Programming
Current
1, 2
8
30
mA
VPP = VPPH
Programming in
Progress
IPP3
VPP Erase
Current
1, 2
10
30
mA
VPP = VPPH
IPP4
VPP Program
Verify Current
1, 2
2.0
5.0
mA
VPP = VPPH
Program Verify in
Progress
IPP5
VPP Erase
Verify Current
1, 2
2.0
5.0
mA
VPP = VPPH
Erase Verify in
Progress
VIL
Input Low
Voltage
–0.5
0.8
V
VIH
Input High
Voltage
2.0
VCC +
0.5
V
VOL
Output Low
Voltage
0.45
V
VCC = VCC Min
IOH = –2.5 mA
VOH1
Output High
Voltage
V
VCC = VCC Min
IOL = 5.8 mA
2.4
23
E
28F020
4.6
DC Characteristics—TTL/NMOS Compatible—Extended Temperature
Products (Continued)
Limits
Symbol
Parameter
Notes
Min
Typ(3)
11.50
Max
Unit
13.0
0
V
500
µA
A9 = VID
NOTE:
Erase/Program
are Inhibited
when VPP = VPPL
VID
A9 Intelligent
Identifier
Voltage
IID
A9 Intelligent
Identifier
Current
VPPL
VPP during
Read-Only
Operations
0.00
6.5
V
VPPH
VPP during
Read/Write
Operations
11.40
12.60
V
VLKO
VCC
Erase/Write
Lock Voltage
4.7
1, 2
90
2.5
Test Conditions
V
DC Characteristics—CMOS Compatible—Extended Temperature Products
Limits
Symbol
Parameter
Notes
Min
Typ(3)
Max
Unit
Test Conditions
ILI
Input Leakage
Current
1
±1.0
µA
VCC = VCC Max
VIN = VCC or VSS
ILO
Output Leakage
Current
1
±10
µA
VCC = VCC Max
VOUT = VCC or
VSS
ICCS
VCC Standby
Current
1
50
100
µA
VCC = VCC Max
CE# = VCC ±0.2 V
ICC1
VCC Active Read
Current
1
10
50
mA
VCC = VCC Max
CE# = VIL
f = 6 MHz
IOUT = 0 mA
ICC2
VCC
Programming
Current
1, 2
1.0
10
mA
Programming in
Progress
ICC3
VCC Erase
Current
1, 2
5.0
30
mA
Erasure in
Progress
24
E
4.7
28F020
DC Characteristics—CMOS Compatible—Extended Temperature Products
(Continued)
Limits
Symbol
Parameter
Notes
Min
Typ(3)
Max
Unit
Test Conditions
ICC4
VCC ProgramVerify Current
1, 2
5.0
30
mA
VPP = VPPH
Program Verify in
Progress
ICC5
VCC Erase Verify
Current
1, 2
5.0
30
mA
VPP = VPPH
Erase Verify in
Progress
IPPS
VPP Leakage
Current
1
±10
µA
VPP ≤ VCC
IPP1
VPP Read
Current,
ID Current or
Standby Current
1
90
200
µA
VPP > VCC
IPP2
VPP
Programming
Current
1, 2
8
30
mA
VPP = VPPH
Programming in
Progress
IPP3
VPP Erase
Current
1, 2
10
30
mA
VPP = VPPH
Erasure in
Progress
IPP4
VPP Program
Verify Current
1, 2
2.0
5.0
mA
VPP = VPPH
Program Verify
in Progress
IPP5
VPP Erase Verify
Current
1, 2
2.0
5.0
mA
VPP = VPPH
Erase Verify in
Progress
VIL
Input Low
Voltage
–0.5
0.8
V
VIH
Input High
Voltage
0.7
VCC
VCC +
0.5
V
VOL
Output Low
Voltage
0.45
V
VCC = VCC Min
IOL = 5.8 mA
VOH1
Output High
Voltage
V
VCC = VCC Min
IOH = –2.5 mA
VPP ≤ VCC
±10
VOH2
VID
0.85
VCC
VCC –
0.4
A9 Intelligent
Identifier Voltage
11.50
VCC = VCC Min
IOH = –100 µA
13.00
V
25
E
28F020
4.7
DC Characteristics—CMOS Compatible—Extended Temperature Products
(Continued)
Limits
Symbol
Parameter
Notes
IID
A9 Intelligent
Identifier Current
1, 2
VPPL
VPP during ReadOnly Operations
VPPH
VPP during
Read/Write
Operations
VLKO
VCC Erase/Write
Lock Voltage
Typ(3)
Max
Unit
90
500
µA
A9 = VID
0.00
6.5
V
NOTE:
Erase/Programs
are Inhibited
when VPP = VPPL
11.40
12.60
V
Min
2.5
Test Conditions
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, T = 25 °C. These currents are
valid for all product versions (packages and speeds).
2. Not 100% tested: Characterization data available.
3. “Typicals” are not guaranteed, but based on a limited number of samples from production lots.
26
E
2.4
28F020
2.0
Input
2.0
Output
0.8
Test Points
0.8
0.45
3.0
Input
1.5
Test Points
1.5
Output
0.0
0245_08
0245_06
AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1”
and VOL (0.45 VTTL) for a Logic “0.” Input timing begins at
VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH
and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 6. Testing Input/Output Waveform(1)
AC test inputs are driven at 3.0 V for a Logic “1” and 0.0 V
for a Logic “0.” Input timing begins, and output timing ends,
at 1.5 V. Input rise and fall times (10% to 90%) <10 ns.
Figure 8. High Speed AC Testing Input/Output
Waveforms(2)
1.3V
Device
Under Test
1.3V
1N914
1N914
RL = 3.3 kΩ
RL = 3.3 kΩ
Device
Under Test
Out
CL = 100 pF
0245_07
CL Includes Jig Capacitance
Figure 7. AC Testing Load Circuit(1)
Out
CL = 30 pF
0245_09
CL Includes Jig Capacitance
Figure 9. High Speed AC Testing Load Circuit(2)
NOTES:
1. Testing characteristics for 28F020-70 in standard configuration, and 28F020-90 and 28F020-150.
2. Testing characteristics for 28F020-70 in high speed configuration.
27
E
28F020
4.8
AC Characteristics—Read Only Operations—Commercial and Extended
Temperature Products
Versions
Symbol
Characteristics
Notes
28F020-90(4)
28F020-120(4)
28F020-150(4)
Min
Min
Min
Max
90
Max
120
Max
tAVAV/tRC
Read Cycle Time
tELQV/
tCE>
Chip Enable Access
Time
90
120
150
ns
tAVQV/
tACC
Address Access
Time
90
120
150
ns
tGLQV/
tOE
Output Enable
Access Time
35
50
50
ns
tELQX/
tLZ
Chip Enable to
Output in Low Z
2, 3
tEHQZ
Chip Disable to
Output in High Z
2
tGLQX/
tOLZ
Output Enable to
Output in Low Z
2, 3
tGHQZ/
tDF
Output Disable to
Output in High Z
2
tOH
Output Hold from
Address, CE#, or
OE# Change
1, 2
tWHGL
Write Recovery Time
before Read
0
150
Unit
0
45
0
0
55
0
30
ns
ns
55
0
30
ns
ns
30
ns
0
0
0
ns
6
6
6
µs
NOTES:
1. Whichever occurs first.
2. Sampled, not 100% tested.
3. Guaranteed by design.
4. See High Speed AC Testing Input/Output Waveform (Figure 8) and High Speed AC Testing Load Circuit (Figure 9) for
testing characteristics.
5. See Testing Input/Output Waveform (Figure 6) and AC Testing Load Circuit (Figure 7) for testing characteristics.
28
E
28F020
0245_10
Figure 10. AC Waveforms for Read Operations
29
28F020
4.9
(1)
AC Characteristics—Write/Erase/Program Only Operations —
Commercial and Extended Temperature Products
Versions
Symbol
Characteristics
Notes
E
28F020-90(4)
28F020-120(4)
28F020-150(4)
Min
Min
Min
Max
Max
Max
Unit
tAVAV/
tWC
Write Cycle Time
90
120
150
ns
tAVWL/
tAS
Address Set-Up
Time
0
0
0
ns
tWLAX/
tAH
Address Hold Time
40
40
40
ns
40
40
40
ns
55
55
5
tDVWH/
tDS
Data Set-Up Time
5
55
tWHDX/
tDH
Data Hold Time
10
10
10
ns
tWHGL
Write Recovery Time
before Read
6
6
6
µs
tGHWL
Read Recovery
Time before Write
0
0
0
ns
tELWL/
tCS
Chip Enable Set-Up
Time before Write
15
15
15
ns
tWHEH/
tCH
Chip Enable Hold
Time
0
0
0
ns
tWLWH/
tWP
Write Pulse Width
40
60
60
ns
55
55
20
20
20
ns
2
5
tWHWL/
tWPH
Write Pulse Width
High
tWHWH1
Duration of
Programming
Operation
3
10
10
10
µs
tWHWH2
Duration of Erase
Operation
3
9.5
9.5
9.5
ms
tVPEL
VPP Set-Up Time to
Chip Enable Low
2
1
1
1
µs
30
E
28F020
NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read-Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum
specification.
4. See High Speed AC Testing Input/Output Waveform (Figure 8) and High Speed AC Testing Load Circuit (Figure 9) for
testing characteristics.
5. Minimum Specification for Extended Temperature product.
6. See Testing Input/Output Waveform (Figure 6) and AC Testing Load Circuit (Figure 7) for testing characteristics.
4.10
Erase and Programming Performance
Limits
Parameter
Notes
Min
Typ
Max
Unit
Chip-Erase Time
1, 3, 4
2
30
Sec
Chip-Program Time
1, 2, 4
4
25
Sec
NOTES:
1. “Typicals” are not guaranteed, but based on a limited number of samples from production lots. Data taken at 25 °C, 12.0 V
VPP at 0 cycles.
2. Minimum byte programming time excluding system overhead is 16 µsec (10 µsec program + 6 µsec write recovery), while
maximum is 400 µsec/byte (16 µsec x 25 loops allowed by algorithm). Max chip-programming time is specified lower than
the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.
3. Excludes 00H programming prior to erasure.
4. Excludes System-Level Overhead.
31
E
28F020
0245_13
0245_11
Figure 11. 28F020 Typical Programming
Capability
NOTE:
Does not include Pre-Erase Program.
Figure 13. 28F020 Typical Erase Capability
0245_14
0245_12
Figure 12. 28F020 Typical Program Time at 12 V
32
NOTE:
Does not include Pre-Erase Program.
Figure 14. 28F020 Typical Erase Time at 12 V
E
28F020
0245_15
Figure 15. AC Waveforms for Programming Operations
33
E
28F020
0245_16
Figure 16. AC Waveforms for Erase Operations
34
E
4.11
28F020
AC Characteristics—Alternate CE# Controlled Writes(1) —Commercial and
Extended Temperature Products
Versions
Symbol
Characteristics
Notes
28F020-90(4)
28F020-120(4)
28F020-150(4)
Min
Min
Min
Max
Max
Max
Unit
tAVAV
Write Cycle Time
90
120
150
ns
tAVEL
Address Set-Up
Time
0
0
0
ns
tELAX
Address Hold Time
50
55
55
ns
60
60
40
45
45
ns
50
50
5
tDVEH
Data Set-Up Time
5
tEHDX
Data Hold Time
10
10
10
ns
tEHGL
Write Recovery Time
before Read
6
6
6
µs
tGHWL
Read Recovery
Time before Write
0
0
0
ns
tWLEL
Write Enable Set-Up
Time before Chip
Enable
0
0
0
ns
tEHWH
Write Enable Hold
Time
0
0
0
ns
tELEH
Write Pulse Width
70
ns
2
5
50
60
60
60
20
20
20
ns
tEHEL
Write Pulse Width
High
tEHEH1
Duration of Prog.
Operation
3
10
10
10
µs
tEHEH2
Duration of Erase
Operation
3
9.5
9.5
9.5
ms
tVPEL
VPP Set-Up Time to
Chip Enable Low
2
1
1
1
µs
35
28F020
E
NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read-Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum
specification.
4. See High Speed AC Testing Input/Output Waveform (Figure 8) and High Speed AC Testing Load Circuit (Figure 9) for
testing characteristics.
5. Minimum specification for extended temperature product.
6. See Testing Input/Output Waveform (Figure 6) and AC Testing Load Circuit (Figure 7) for testing characteristics.
36
E
28F020
0245_17
NOTE:
Alternative CE-Controlled Write Timings also apply to erase operations.
Figure 17. Alternate AC Waveforms for Programming Operations
37
E
28F020
5.0
ORDERING INFORMATION
E2 8 F0 2 0 - 1 5 0
Operating Temperature
T = Extended Temp
Blank = Commercial Temp
Access Speed (ns)
Package
P = 32-Pin PDIP
N = 32-Lead PLCC
E = 32-Lead TSOP
Density
020 = 2 Mbit
Product Line Designator
for all Intel Flash products
VALID COMBINATIONS:
E28F020-90
N28F020-90
E28F020-120
N28F020-120
E28F020-150
N28F020-150
TE28F020-90
TE28F020-120
TE28F020-150
6.0
P28F020-90
P28F020-120
P28F020-150
TN28F020-90
TN28F020-120
TN28F020-150
ADDITIONAL INFORMATION
Order Number
297847
Document
28F020 Specification Update
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.
38