CLC1003 Low Distortion, Low Offset, RRIO Amplifier FE ATU R E S ■■ 1mV maximum input offset voltage ■■ 0.00005% THD at 1kHz ■■ 5.3nV/√Hz input voltage noise > 10kHz ■■ -90dB/-85dB HD2/HD3 at 100kHz, R = 100Ω L ■■ <-100dB HD2 and HD3 at 10kHz, R = 1kΩ L ■■ Rail-to-rail input and output ■■ 55MHz unity gain bandwidth ■■ 12V/μs slew rate ■■ +80mA, -55mA output current ■■ -40°C to +125°C operating temperature range ■■ Fully specified at 3 and ±5V supplies ■■ CLC1003: ROHS compliant TSOT-5, SOIC-8 package options General Description The CLC1003 is a single channel, high-performance, voltage feedback amplifier with near precision performance, low input voltage noise, and ultra low distortion. The CLC1003 offers 1mV maximum input offset voltage, 3.5nV/√Hz broadband input voltage noise, and 0.00005% THD at 1kHz. These amplifiers also provide 55MHz gain bandwidth product and 12V/μs slew rate making them well suited for applications requiring precision DC performance and high AC performance. This high-performance amplifier also offers a rail-to-rail input and output, simplifying single supply designs and offering larger dynamic range possibilities. The inputs extend beyond the rails by 500mV. The CLC1003 is designed to operate from 2.5V to 12V supplies and operate over the extended temperature range of -40°C to +125°. A P P LICATION S ■■ Active filters ■■ Sensor interface ■■ HIgh-speed transducer amp ■■ Medical instrumentation ■■ Probe equipment ■■ Test equipment ■■ Smoke detectors ■■ Hand-held analytic instruments ■■ Current sense applications Ordering Information - back page THD vs. Frequency Typical Application -65 -70 VCC -75 CLC1003 THD (dB) + lph_1 – SPM (Smart Power Module) M -80 -85 -90 lph_2 VOUT = 1Vpp RL = 1K AV+1 -95 -100 lph_3 100 200 300 400 500 600 700 800 900 1000 Frequency (kHz) Current Sensing in 3-Phase Motor © 2007-2014 Exar Corporation 1 / 17 exar.com/CLC1003 Rev 1D CLC1003 Absolute Maximum Ratings Operating Conditions Stresses beyond the limits listed below may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Supply Voltage Range.................................................. 2.5V to 12V Operating Temperature Range................................-40°C to 125°C Junction Temperature............................................................ 150°C Storage Temperature Range....................................-65°C to 150°C Lead Temperature (Soldering, 10s).......................................260°C VS.................................................................................. 0V to +14V VIN............................................................. -VS - 0.5V to +VS +0.5V Package Thermal Resistance θJA (TSOT-5)......................................................................215°C/W θJA (SOIC-8)......................................................................150°C/W Package thermal resistance (θJA), JEDEC standard, multi-layer test boards, still air. © 2007-2014 Exar Corporation 2 / 17 exar.com/CLC1003 Rev 1D CLC1003 Electrical Characteristics at +3V TA = 25°C, VS = +3V, Rf = 1kΩ, RL = 1kΩ to VS/2; G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response GBWP -3dB Gain Bandwidth Product G = 10, VOUT = 0.05Vpp 31 MHz UGBW Unity Gain Bandwidth VOUT = 0.05Vpp, Rf = 0 50 MHz BWSS -3dB Bandwidth VOUT = 0.05Vpp 24 MHz BWLS Large Signal Bandwidth VOUT = 2Vpp 3.3 MHz tR, tF Rise and Fall Time VOUT = 2V step; (10% to 90%) 150 ns tS Settling Time to 0.1% VOUT = 2V step 78 ns OS Overshoot VOUT = 2V step 0.3 % SR Slew Rate 2V step 11 V/μs 2Vpp, 10kHz, RL = 1kΩ -98 dBc 2Vpp, 100kHz, RL = 100Ω -85 dBc 2Vpp, 10kHz, RL = 1kΩ -95 dBc 2Vpp, 100kHz, RL = 100Ω -81 dBc 0.0005 % >10kHz 5.5 nV/√Hz >100kHz 3.9 nV/√Hz Time Domain Distortion/Noise Response HD2 2nd Harmonic Distortion HD3 3rd Harmonic Distortion THD Total Harmonic Distortion en Input Voltage Noise 1Vpp, 1kHz, G = 1, RL = 2kΩ DC Performance VIO dVIO IB dIB Input Offset Voltage Average Drift Input Bias Current Average Drift 0.088 mV 1.3 μV/°C -0.340 μA 0.8 nA/°C 0.2 μA 100 dB IOS Input Offset Current PSRR Power Supply Rejection Ratio DC AOL Open Loop Gain VOUT = VS / 2 104 dB IS Supply Current per channel 1.85 mA Input Characteristics RIN Input Resistance CIN Input Capacitance CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio Non-inverting, G = 1 DC, VCM = 0.5V to 2.5V 30 MΩ 1.1 pF -0.5 to 3.5 V 94 dB Output Characteristics VOUT Output Swing 0.085 to 2.80 0.04 to 2.91 RL = 150Ω RL = 1kΩ IOUT Output Current ISC Short Circuit Current VOUT = VS / 2 © 2007-2014 Exar Corporation 3 / 17 V V +75, -40 mA +95, -50 mA exar.com/CLC1003 Rev 1D CLC1003 Electrical Characteristics at ±5V TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ to GND; G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response GBWP -3dB Gain Bandwidth Product G = 10, VOUT = 0.05Vpp 35 MHz UGBW Unity Gain Bandwidth VOUT = 0.05Vpp, Rf = 0 55 MHz BWSS -3dB Bandwidth VOUT = 0.05Vpp 25 MHz BWLS Large Signal Bandwidth VOUT = 2Vpp 3.6 MHz tR, tF Rise and Fall Time VOUT = 2V step; (10% to 90%) 125 ns tS Settling Time to 0.1% VOUT = 2V step 80 ns OS Overshoot VOUT = 2V step 0.3 % SR Slew Rate 4V step 12 V/μs 2Vpp, 10kHz, RL = 1kΩ -125 dBc 2Vpp, 100kHz, RL = 100Ω -90 dBc 2Vpp, 10kHz, RL = 1kΩ -127 dBc 2Vpp, 100kHz, RL = 100Ω -85 dBc 0.00005 % >10kHz 5.3 nV/√Hz >100kHz 3.5 nV/√Hz Time Domain Distortion/Noise Response HD2 2nd Harmonic Distortion HD3 3rd Harmonic Distortion THD Total Harmonic Distortion en Input Voltage Noise 1Vpp, 1kHz, G = 1, RL = 2kΩ DC Performance VIO dVIO IB dIB Input Offset Voltage -1 Average Drift 0.050 1 1.3 Input Bias Current -2.6 Average Drift -0.30 2.6 0.85 0.2 mV μV/°C μA nA/°C IOS Input Offset Current 0.7 PSRR Power Supply Rejection Ratio DC 82 100 μA AOL Open Loop Gain VOUT = VS / 2 95 115 IS Supply Current per channel 2.2 Non-inverting, G = 1 30 MΩ 1 pF ±5.5 V 95 dB dB dB 2.75 mA Input Characteristics RIN Input Resistance CIN Input Capacitance CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio DC, VCM = -3V to 3V 70 Output Characteristics VOUT Output Swing RL = 150Ω RL = 1kΩ IOUT Output Current ISC Short Circuit Current -4.7 VOUT = VS / 2 © 2007-2014 Exar Corporation 4 / 17 -4.826 to 4.534 -4.93 to 4.85 V 4.7 V +80, -55 mA +115, -90 mA exar.com/CLC1003 Rev 1D CLC1003 CLC1003 Pin Configurations CLC1003 Pin Assignments TSOT-5 TSOT-5 OUT 1 -Vs 2 +IN 3 5 + +Vs 4 -IN SOIC-8 Pin No. Pin Name Description 1 OUT Output 2 -VS Negative supply 3 +IN Positive input 4 -IN Negative input 5 +VS Positive supply SOIC-8 NC 1 -IN 2 +IN 3 -Vs 4 + 8 NC 7 +Vs 6 OUT 5 NC © 2007-2014 Exar Corporation Pin No. Pin Name Description 1 NC No Connect 2 -IN Negative input 3 +IN Positive input 4 -VS Negative supply 5 NC No Connect 6 OUT Output 7 +VS Positive supply 8 NC No Connect 5 / 17 exar.com/CLC1003 Rev 1D CLC1003 Typical Performance Characteristics TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted. Non-Inverting Frequency Response Inverting Frequency Response 3 1 0 0 -1 Normalized Gain (dB) Normalized Gain (dB) G=1 Rf = 0 G=2 -3 G=5 G = 10 -6 G = -1 -2 G = -2 -3 G = -5 G = -10 -4 -5 VOUT = 0.05Vpp -6 -9 0.1 1 10 VOUT = 0.05Vpp -7 100 0.1 Frequency (MHz) 1 10 100 Frequency (MHz) Frequency Response vs. CL Frequency Response vs. CL without RS 1 4 -1 2 CL = 500pF Rs = 10Ω -2 Normalized Gain (dB) Normalized Gain (dB) 0 CL = 1000pF Rs = 7.5Ω -3 CL = 3000pF Rs = 4Ω -4 -5 CL = 500pF 0 CL = 300pF -2 CL = 100pF -4 CL = 50pF -6 -6 -7 -8 0.1 1 10 100 CL = 10pF VOUT = 0.05Vpp Rs = 0Ω VOUT = 0.05Vpp 0.1 1 Frequency (MHz) 10 Frequency Response vs. VOUT Frequency Response vs. RL 3 2 RL = 50Ω 1 0 Normalized Gain (dB) Normalized Gain (dB) 100 Frequency (MHz) VOUT = 1Vpp VOUT = 2Vpp -3 VOUT = 4Vpp -6 RL = 150Ω 0 RL = 2.5KΩ -1 RL = 1KΩ -2 -3 -4 -5 -9 VOUT = 0.05Vpp -6 0.1 1 10 100 0.1 Frequency (MHz) © 2007-2014 Exar Corporation 1 10 100 Frequency (MHz) 6 / 17 exar.com/CLC1003 Rev 1D CLC1003 Typical Performance Characteristics TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted. Non-Inverting Frequency Response at VS = 3V Inverting Frequency Response at VS = 3V 1 3 0 -1 0 Normalized Gain (dB) Normalized Gain (dB) G=1 Rf = 0 G=2 -3 G=5 G = 10 G = -1 -2 G = -2 -3 G = -5 G = -10 -4 -5 -6 -6 VOUT = 0.05Vpp VOUT = 0.05Vpp -7 -9 0.1 1 10 0.1 100 1 10 Frequency Response vs. VOUT at VS = 3V Frequency Response vs. RL at VS = 3V 3 2 RL = 50Ω 1 0 Normalized Gain (dB) Normalized Gain (dB) 100 Frequency (MHz) Frequency (MHz) VOUT = 1Vpp VOUT = 2Vpp -3 VOUT = 2.5Vpp -6 RL = 150Ω 0 RL = 2.5KΩ -1 RL = 1KΩ -2 -3 -4 -5 -9 VOUT = 0.05Vpp -6 0.1 1 10 100 0.1 1 Frequency (MHz) 10 100 Frequency (MHz) -3dB Bandwidth vs. Output Voltage at VS = 3V -3dB Bandwidth vs. Output Voltage 24 24 21 18 -3dB Bandwidth (MHz) -3dB Bandwidth (MHz) 21 15 12 9 6 3 18 15 12 9 6 3 0 0.0 0.5 1.0 1.5 2.0 0 2.5 0.0 VOUT (VPP) © 2007-2014 Exar Corporation 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOUT (VPP) 7 / 17 exar.com/CLC1003 Rev 1D CLC1003 Typical Performance Characteristics TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted. Open Loop Gain and Phase vs. 80 0.5 0 -75 PHASE -150 20 -225 GAIN 0 -300 -20 -375 -40 -450 -60 0.3 PHASE (°) 40 0.4 Vout (V) 60 GAIN (dB) CMIR 0.1 0 -525 10 100 1,000 10,000 100,000 0.2 -0.1 1,000,000 -6 -4 -2 0 FREQ (KHz) 2 4 6 Vcm(V) Input Voltage Noise CMIR at VS = 3V 0.5 14 12 0.4 11 10 0.3 9 Vout (V) Input Voltage Noise (nV/√Hz) 13 8 7 6 0.2 0.1 5 4 0 3 2 0.0001 0.001 0.01 0.1 -0.1 1 -1 -0.5 0 0.5 Frequency (MHz) 2 2.5 3 3.5 4 PSRR vs. Frequency 110 110 100 100 90 90 PSRR (dB) CMRR (dB) 1.5 Vcm(V) CMRR vs. Frequency 80 70 80 70 60 60 50 40 0.001 1 0.01 0.1 1 10 100 50 0.001 1000 1000 Frequency (MHz) © 2007-2014 Exar Corporation 0.01 0.1 1 10 100 1000 1000 Frequency (MHz) 8 / 17 exar.com/CLC1003 Rev 1D CLC1003 Typical Performance Characteristics TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted. 2nd Harmonic Distortion vs. RL 3rd Harmonic Distortion vs. RL -50 -50 -60 RL = 100Ω RL = 10KΩ -70 Distortion (dBc) Distortion (dBc) -60 -80 -90 RL = 10KΩ RL = 1KΩ -70 RL = 100Ω -80 -90 RL = 500Ω RL = 1KΩ RL = 500Ω -100 -100 VOUT = 2Vpp VOUT = 2Vpp -110 -110 100 200 300 400 500 600 700 800 900 1000 100 200 300 400 Frequency (KHz) 2nd Harmonic Distortion vs. VOUT 600 700 800 900 1000 3rd Harmonic Distortion vs. VOUT -40 -30 -50 -40 -50 -60 RF=RL=1K Distortion (dBc) Distortion (dBc) 500 Frequency (KHz) -70 -80 RF=RL=10K -100 2.5 3.5 4.5 5.5 -70 -90 FREQ = 500KHz 1.5 RF=RL=1K -80 RF=RL=10K -90 0.5 -60 6.5 7.5 8.5 FREQ = 500KHz -100 9.5 0.5 Output Amplitude (Vpp) 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 Output Amplitude (Vpp) THD vs. Frequency -65 -70 THD (dB) -75 -80 -85 -90 VOUT = 1Vpp RL = 1K AV+1 -95 -100 100 200 300 400 500 600 700 800 900 1000 Frequency (kHz) © 2007-2014 Exar Corporation 9 / 17 exar.com/CLC1003 Rev 1D CLC1003 Typical Performance Characteristics TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted. 3rd Harmonic Distortion vs. RL at VS = 3V -40 -40 -50 -50 RL = 100Ω -60 -70 -80 RL = 10KΩ RL = 1KΩ RL = 500Ω Distortion (dBc) Distortion (dBc) 2nd Harmonic Distortion vs. RL at VS = 3V -60 RL = 100Ω -70 -80 RL = 500Ω RL = 10KΩ RL = 1KΩ -90 -90 VOUT = 2Vpp VOUT = 2Vpp -100 -100 100 200 300 400 500 600 700 800 900 100 1000 200 300 -40 -40 -50 -50 -60 RF=RL=10K -70 RF=RL=1K -90 1 1.25 1.5 700 800 900 1000 1.75 2 2.25 -60 RF=RL=10K -70 -80 RF=RL=1K FREQ = 500KHz -100 0.75 600 -90 FREQ = 500KHz 0.5 500 3rd Harmonic Distortion vs. VOUT at VS = 3V Distortion (dBc) Distortion (dBc) 2nd Harmonic Distortion vs. VOUT at VS = 3V -80 400 Frequency (KHz) Frequency (KHz) -100 2.5 0.5 Output Amplitude (Vpp) 0.75 1 1.25 1.5 1.75 2 2.25 2.5 Output Amplitude (Vpp) THD vs. Frequency at VS = 3V -65 -70 THD (dB) -75 -80 -85 -90 VOUT = 1Vpp RL = 1K AV+1 -95 -100 100 200 300 400 500 600 700 800 900 1000 Frequency (kHz) © 2007-2014 Exar Corporation 10 / 17 exar.com/CLC1003 Rev 1D CLC1003 Typical Performance Characteristics TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted. Small Signal Pulse Response Small Signal Pulse Response at VS = 3V 0.5 1.6 0.25 1.55 Voltage (V) 1.65 Voltage (V) 0.75 0 -0.25 1.5 1.45 -0.5 1.4 -0.75 0 0.5 1 1.5 1.35 2 0 Time (ns) 1 1.5 2 Time (ns) Large Signal Pulse Response Large Signal Pulse Response at VS = 3V 6 3 4 2.5 2 2 Voltage (V) Voltage (V) 0.5 0 -2 1.5 1 -4 0.5 -6 0 1 2 3 4 5 6 7 8 9 0 10 0 Time (ns) 0.5 1 1.5 2 Time (ns) Input Offset Voltage vs. Temperature Input Offset Voltage Distribution 5000 0.1 0.05 4000 0 Units Vio (V) 3000 -0.05 2000 -0.1 1000 -0.15 0 -0.2 -40 -20 0 20 40 60 80 100 120 Temperature (°C) © 2007-2014 Exar Corporation Input Offset Voltage (mV) 11 / 17 exar.com/CLC1003 Rev 1D CLC1003 Application Information Where TAmbient is the temperature of the working environment. Basic Information Figures 1 and 2 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations. +Vs 6.8μF In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. PD = Psupply - Pload Supply power is calculated by the standard power equation. Psupply = Vsupply × IRMSsupply Input 0.1μF + Vsupply = VS+ - VSOutput RL 0.1μF Rg 6.8μF -Vs Power delivered to a purely resistive load is: Rf Pload = ((Vload)RMS2)/Rloadeff G = 1 + (Rf/Rg) Figure 1: Typical Non-Inverting Gain Circuit +Vs R1 Input Rg + The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, Rloadeff in Figure 2 would be calculated as: 6.8μF RL || (Rf + Rg) 0.1μF These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from Output RL 0.1μF 6.8μF -Vs Rf G = - (Rf/Rg) For optimum input offset voltage set R1 = Rf || Rg PD = PQuiescent + PDynamic - Pload Quiescent power can be derived from the specified IS values along with known supply voltage, Vsupply. Load power can be calculated as above with the desired signal amplitudes using: Figure 2: Typical Inverting Gain Circuit (Vload)RMS = Vpeak / √2 ( Iload)RMS = ( Vload)RMS / Rloadeff Power Dissipation Power dissipation should not be a factor when operating under the stated 500Ω load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it’s intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150°C. To calculate the junction temperature, the package thermal resistance value ThetaJA (θJA) is used along with the total die power dissipation. TJunction = TAmbient + (θJA × PD) © 2007-2014 Exar Corporation The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDynamic = (VS+ - Vload)RMS × ( Iload)RMS Assuming the load is referenced in the middle of the power rails or Vsupply/2. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available. 12 / 17 exar.com/CLC1003 Rev 1D CLC1003 Overdrive Recovery Maximum Power Dissipation (W) 2 An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies based on whether the input or output is overdriven and by how much the ranges are exceeded. The CLC1003 will typically recover in less than 20ns from an overdrive condition. Figure 5 shows the CLC1003 in an overdriven condition. 1.5 SOIC-8 1 0.5 TSOT-6 3 0 -40 -20 0 20 40 60 80 100 2 VIN = .8Vpp G=5 120 Ambient Temperature (°C) 2 2 1 Input Voltage (V) Driving Capacitive Loads Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 4. 1 Input 1 0 0 Output -1 -1 Output Voltage (V) Figure 3. Maximum Power Derating -1 -2 -2 -3 -2 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 Time (us) Input + Figure 5: Overdrive Recovery Rs Rf Output CL RL Considerations for Offset and Noise Performance Offset Analysis Rg Figure 4. Addition of RS for Driving Capacitive Loads The CLC1003 is capable of driving up to 300pF directly, with no series resistance. Directly driving 500pF causes over 4dB of frequency peaking, as shown in the plot on page 6. Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in ≤ 1dB peaking in the frequency response. The Frequency Response vs. CL plots, on page 6, illustrate the response of the CLC1003. There are three sources of offset contribution to consider; input bias current, input bias current mismatch, and input offset voltage. The input bias currents are assumed to be equal with and additional offset current in one of the inputs to account for mismatch. The bias currents will not affect the offset as long as the parallel combination of Rf and Rg matches Rt. Refer to Figure 6. – Rt CL (pF) RS (Ω) -3dB BW (MHz) 500 10 27 1000 7.5 20 3000 4 15 Table 1: Recommended RS vs. CL For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. © 2007-2014 Exar Corporation +Vs Rf Rg IN CLC1003 + RL -Vs Figure 6: Circuit for Evaluating Offset The first place to start is to determine the source resistance. If it is very small an additional resistance may need to be added to keep the values of Rf and Rg to practical levels. For this analysis we assume that Rt is the total resistance present on the non-inverting input. This gives us one equation that we must solve: 13 / 17 exar.com/CLC1003 Rev 1D CLC1003 Rt = Rg||Rf The complete equation can be simplified to: This equation can be rearranged to solve for Rg: 2 v o Rg = (Rt * Rf) / (Rf - Rt) The other consideration is desired gain (G) which is: ( 2 ) ( ) = 3 ∗ 4kT ∗ G ∗ RT + enG ( + 2 ∗ in ∗ RT 2 ) It’s easy to see that the effect of amplifier voltage noise is proportionate to gain and will tend to dominate at large gains. The other terms will have their greatest impact at large Rt values at lower gains. G = (1 + Rf/Rg) By plugging in the value for Rg we get Rf = G * Rt And Rg can be written in terms of Rt and G as follows: Rg = (G * Rt) / (G - 1) The complete input offset equation is now only dependent on the voltage offset and input offset terms given by: VI OS = 2 2 Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Exar has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: ( VIO ) + (IOS ∗ RT) ■■ And the output offset is: VO OS = G ∗ 2 2 ( V IO ) + (I OS ∗ RT ) Include 6.8µF and 0.1µF ceramic capacitors for power supply decoupling ■■ Place the 6.8µF capacitor within 0.75 inches of the power pin ■■ Place the 0.1µF capacitor within 0.1 inches of the power pin ■■ ■■ Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information. Noise analysis The complete equivalent noise circuit is shown in Figure 7. Rg Evaluation Board Information Rf +– +– The following evaluation boards are available to aid in the testing and layout of these devices: – CLC1003 Rg +– + +– w + – Evaluation Board # RL Figure 7: Complete Equivalent Noise Circuit 2 RF = vorext + en 1 + RG 2 + ibp ∗ RT 1 + RF RG 2 ( + ibn ∗ RF CEB002 CLC1003 in TSOT CEB003 CLC1003 in SOIC Evaluation Board Schematics The complete noise equation is given by: 2 v o Products 2 ) Evaluation board schematics and layouts are shown in Figures 8-12 These evaluation boards are built for dualsupply operation. Follow these steps to use the board in a single-supply application: 1. Short -VS to ground. Where Vorext is the noise due to the external resistors and is given by: 2 v o = en 1 + RF RG 2 + eG ∗ RF RG 2 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane. 2 + eF © 2007-2014 Exar Corporation 14 / 17 exar.com/CLC1003 Rev 1D CLC1003 Figure 10. CEB002 Bottom View Figure 8. CEB002 & CEB003 Schematic Figure 11. CEB003 Top View Figure 9. CEB002 Top View Figure 12. CEB003 Bottom View © 2007-2014 Exar Corporation 15 / 17 exar.com/CLC1003 Rev 1D CLC1003 Mechanical Dimensions TSOT-5 Package SOIC-8 Package © 2007-2014 Exar Corporation 16 / 17 exar.com/CLC1003 Rev 1D CLC1003 Ordering Information Part Number Package Green Operating Temperature Range Packaging Quantity CLC1003IST5X TSOT-5 Yes -40°C to +125°C 2.5k Tape & Reel CLC1003IST5MTR TSOT-5 Yes -40°C to +125°C 250 Tape & Reel CLC1003IST5EVB Evaluation Board N/A N/A N/A CLC1003 Ordering Information CLC1003ISO8X SOIC-8 Yes -40°C to +125°C 2.5k Tape & Reel CLC1003ISO8MTR SOIC-8 Yes -40°C to +125°C 250 Tape & Reel CLC1003ISO8EVB Evaluation Board N/A N/A N/A Moisture sensitivity level for all parts is MSL-1. Revision History Revision 1D (ECN 1441-07) Date September 2014 Description Reformat into Exar data sheet template. Updated ordering information table to include MTR and EVB part numbers. Increased “I” temperature range from +85 to +125°C. Removed “A” temp grade parts, since “I” is now equivalent. Updated thermal resistance numbers and package outline drawings. For Further Assistance: Email: [email protected] or [email protected] Exar Technical Documentation: http://www.exar.com/techdoc/ Exar Corporation Headquarters and Sales Offices 48760 Kato Road Tel.: +1 (510) 668-7000 Fremont, CA 94538 - USA Fax: +1 (510) 668-7001 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. © 2007-2014 Exar Corporation 17 / 17 exar.com/CLC1003 Rev 1D