SHARC Processors ADSP-21367/ADSP-21368/ADSP-21369 SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—2M bits of on-chip SRAM and 6M bits of on-chip mask programmable ROM Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 400 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface, S/PDIF transceiver, serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 58. S/PDIF-compatible digital audio receiver/transmitter 4 independent asynchronous sample rate converters (SRC) 16 PWM outputs configured as four groups of four outputs ROM-based security features include JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multiplier/divider ratios Available in 256-ball BGA_ED and 208-lead LQFP_EP packages Internal Memory SIMD Core Block 0 RAM/ROM Instruction Cache 5 stage Sequencer DAG1/2 Timer PEx DMD 64-BIT B1D 64-BIT Block 2 RAM B2D 64-BIT Block 3 RAM B3D 64-BIT DMD 64-BIT Core Bus Cross Bar PEy PMD 64-BIT FLAGx/IRQx/ TMREXP B0D 64-BIT S Block 1 RAM/ROM Internal Memory I/F PMD 64-BIT IOD0 32-BIT EPD BUS 32-BIT JTAG PERIPHERAL BUS 32-BIT IOD1 32-BIT IOD0 BUS MTM PERIPHERAL BUS CORE PCG FLAGS C-D TIMER 2-0 TWI EP SPI/B UART 1-0 DPI Routing/Pins S/PDIF PCG Tx/Rx A-D ASRC IDP/ SPORT 7-0 3-0 PDAP 7-0 DAI Routing/Pins DPI Peripherals DAI Peripherals CORE PWM FLAGS 3-0 AMI SDRAM External Port Pin MUX Peripherals External Port Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADSP-21367/ADSP-21368/ADSP-21369 TABLE OF CONTENTS Summary ............................................................... 1 ESD Caution ...................................................... 18 Dedicated Audio Components .................................... 1 Maximum Power Dissipation ................................. 18 General Description ................................................. 3 Absolute Maximum Ratings ................................... 18 SHARC Family Core Architecture ............................ 4 Timing Specifications ........................................... 18 Family Peripheral Architecture ................................ 7 Output Drive Currents ......................................... 48 I/O Processor Features ......................................... 10 Test Conditions .................................................. 48 System Design .................................................... 10 Capacitive Loading .............................................. 48 Development Tools ............................................. 11 Thermal Characteristics ........................................ 50 Additional Information ........................................ 12 256-Ball BGA_ED Pinout ......................................... 51 Pin Function Descriptions ....................................... 13 208-Lead LQFP_EP Pinout ....................................... 54 Specifications ........................................................ 16 Package Dimensions ............................................... 56 Operating Conditions .......................................... 16 Surface-Mount Design .......................................... 57 Electrical Characteristics ....................................... 17 Automotive Products .............................................. 58 Package Information ........................................... 18 Ordering Guide ..................................................... 58 REVISION HISTORY 7/09—Rev. D to Rev. E Corrected all outstanding document errata. Also replaced core clock references (CCLK) in the timing specifications with peripheral clock references (PCLK). Revised Functional Block Diagram ................................1 Added Context Switch ...............................................5 Added Universal Registers ..........................................5 Clarified VCO operations. See Voltage Controlled Oscillator .................................... 18 Corrected the pins names for the DAI and DPI in 256-Ball BGA_ED Pinout ......................................... 51 208-Lead LQFP_EP Pinout ....................................... 54 Added 366 MHz LQFP EPAD models for the ADSP-21367 and ADSP-21369. For additional specifications for these models, refer to the following: Specifications ......................................................... 16 Clock Input ........................................................... 21 SDRAM Interface Timing (166 MHz SDCLK) ............... 28 Serial Ports ............................................................ 34 Ordering Guide ...................................................... 58 Rev. E | Page 2 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 GENERAL DESCRIPTION ADSP-21368 Feature ADSP-21369/ ADSP-21369W Table 2. ADSP-2136x Family Features1 (Continued) ADSP-21367 The ADSP-21367/ADSP-21368/ADSP-21369 SHARC® processors are members of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. These processors are source code-compatible with the ADSP-2126x and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32-bit/40-bit floating-point processors optimized for high performance automotive audio applications with its large on-chip SRAM, mask programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI). Serial Ports 8 IDP Yes As shown in the functional block diagram on Page 1, the processors use two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21367/ADSP-21368/ ADSP-21369 processors achieve an instruction cycle time of up to 2.5 ns at 400 MHz. With its SIMD computational hardware, the processors can perform 2.4 GFLOPS running at 400 MHz. DAI Yes SPI 2 Table 1 shows performance benchmarks for these devices. TWI Yes UART DAI and DPI 1 AMI Interface Bus Width 32/16/8 bits SRC Performance Package Speed Benchmark Algorithm (at 400 MHz) 1024 Point Complex FFT (Radix 4, with reversal) 23.2 μs FIR Filter (per tap)1 1.25 ns 1 IIR Filter (per biquad) 5.0 ns Matrix Multiply (pipelined) [3×3] × [3×1] 11.25 ns [4×4] × [4×1] 20.0 ns Divide (y/x) 8.75 ns Inverse Square Root 13.5 ns 128 dB 256 BallBGA, 208-Lead LQFP_EP 256 BallBGA 256 BallBGA, 208-Lead LQFP_EP 1 W = Automotive grade product. See Automotive Products on Page 58 for more information. 2 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay, speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. The diagram on Page 1 shows the two clock domains that make up the ADSP-21367/ADSP-21368/ADSP-21369 processors. The core clock domain contains the following features. Assumes two files in multichannel SIMD mode. ADSP-21368 ADSP-21369/ ADSP-21369W Table 2. ADSP-2136x Family Features1 ADSP-21367 Yes S/PDIF Transceiver Table 1. Processor Benchmarks (at 400 MHz) 1 2 • Two processing elements (PEx, PEy), each of which comprises an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache Frequency 400 MHz • PM and DM buses capable of supporting 2x64-bit data transfers between memory and the core at every core processor cycle RAM 2M bits • One periodic interval timer with pinout ROM2 6M bits • On-chip SRAM (2M bit) Feature Audio Decoders in ROM Yes Pulse-Width Modulation Yes S/PDIF Yes SDRAM Memory Bus Width • On-chip mask-programmable ROM (6M bit) • JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user breakpoints which allows flexible exception handling. 32/16 bits Rev. E | Page 3 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 • Digital peripheral interface that includes three timers, a 2wire interface, two UARTs, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG) and a flexible signal routing unit (DPI SRU). The block diagram of the ADSP-21368 on Page 1 also shows the peripheral clock domain (also known as the I/O processor) and contains the following features: • IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers SHARC FAMILY CORE ARCHITECTURE • Peripheral and external port buses for core connection The ADSP-21367/ADSP-21368/ADSP-21369 are code compatible at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21367/ADSP-21368/ ADSP-21369 processors share architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the following sections. • External port with an AMI and SDRAM controller • 4 units for PWM control • 1 MTM unit for internal-to-internal memory transfers • Digital applications interface that includes four precision clock generators (PCG), a input data port (IDP) for serial and parallel interconnect, an S/PDIF receiver/transmitter, four asynchronous sample rate converters, eight serial ports, a flexible signal routing unit (DAI SRU). S FLAG JTAG TIMER INTERRUPT CACHE SIMD Core PM DATA 48 DMD/PMD 64 5 STAGE PROGRAM SEQUENCER PM ADDRESS 24 DAG1 16x32 DAG2 16x32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 USTAT 4x32-BIT PM DATA 64 PX 64-BIT DM DATA 64 MULTIPLIER MRF 80-BIT MRB 80-BIT SHIFTER ALU RF Rx/Fx PEx 16x40-BIT DATA SWAP RF Sx/SFx PEy 16x40-BIT ASTATx ASTATy STYKx STYKy Figure 2. SHARC Core Block Diadram Rev. E | Page 4 of 60 | July 2009 ALU SHIFTER MULTIPLIER MSB 80-BIT MSF 80-BIT ADSP-21367/ADSP-21368/ADSP-21369 SIMD Computational Engine The processors contain two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM data bus. These registers contain hardware to handle the data width difference. Timer A core timer that can generate periodic software Interrupts. The core timer can be configured to use FLAG3 as a timer expired signal Single-Cycle Fetch of Instruction and Four Operands The ADSP-21367/ADSP-21368/ADSP-21369 feature an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 2 on Page 4). With separate program and data memory buses and on-chip instruction cache, the processors can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats. Data Register File A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Context Switch The processors include an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The ADSP-21367/ADSP-21368/ADSP-21369 have two data address generators (DAGs). The DAGs are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result registers all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. Universal Registers The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the ADSP-21367/ADSP-21368/ADSP-21369 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. On-Chip Memory These registers can be used for general-purpose tasks. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all system registers (control/status) of the core. Rev. E The processors contain two megabits of internal RAM and six megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data storage (see Table 3 on Page 6). Each memory block supports single-cycle, independent accesses by the core processor and I/O | Page 5 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 processor. The memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a single cycle. Table 3. Internal Memory Space 1 IOP Registers 0x0000 0000–0x0003 FFFF 1 Long Word (64 Bits) Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits) Block 0 ROM (Reserved) 0x0004 0000–0x0004 BFFF Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF Block 0 ROM (Reserved) 0x0008 0000–0x0009 7FFF Block 0 ROM (Reserved) 0x0010 0000–0x0012 FFFF Reserved 0x0004 F000–0x0004 FFFF Reserved 0x0009 4000–0x0009 FFFF Reserved 0x0009 E000–0x0009 FFFF Reserved 0x0013 C000–0x0013 FFFF Block 0 SRAM 0x0004 C000–0x0004 EFFF Block 0 SRAM 0x0009 0000–0x0009 3FFF Block 0 SRAM 0x0009 8000–0x0009 DFFF Block 0 SRAM 0x0013 0000–0x0013 BFFF Block 1 ROM (Reserved) 0x0005 0000–0x0005 BFFF Block 1 ROM (Reserved) 0x000A 0000–0x000A FFFF Block 1 ROM (Reserved) 0x000A 0000–0x000B 7FFF Block 1 ROM (Reserved) 0x0014 0000–0x0016 FFFF Reserved 0x0005 F000–0x0005 FFFF Reserved 0x000B 4000–0x000B FFFF Reserved 0x000B E000–0x000B FFFF Reserved 0x0017 C000–0x0017 FFFF Block 1 SRAM 0x0005 C000–0x0005 EFFF Block 1 SRAM 0x000B 0000–0x000B 3FFF Block 1 SRAM 0x000B 8000–0x000B DFFF Block 1 SRAM 0x0017 0000–0x0017 BFFF Block 2 SRAM 0x0006 0000–0x0006 0FFF Block 2 SRAM 0x000C 0000–0x000C 1554 Block 2 SRAM 0x000C 0000–0x000C 1FFF Block 2 SRAM 0x0018 0000–0x0018 3FFF Reserved 0x0006 1000– 0x0006 FFFF Reserved 0x000C 1555–0x000C 3FFF Reserved 0x000C 2000–0x000D FFFF Reserved 0x0018 4000–0x001B FFFF Block 3 SRAM 0x0007 0000–0x0007 0FFF Block 3 SRAM 0x000E 0000–0x000E 1554 Block 3 SRAM 0x000E 0000–0x000E 1FFF Block 3 SRAM 0x001C 0000–0x001C 3FFF Reserved 0x0007 1000–0x0007 FFFF Reserved 0x000E 1555–0x000F FFFF Reserved 0x000E 2000–0x000F FFFF Reserved 0x001C 4000–0x001F FFFF The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details. The SRAM can be configured as a maximum of 64k words of 32-bit data, 128k words of 16-bit data, 42k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that can be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. Rev. E On-Chip Memory Bandwidth The internal memory architecture allows programs to have four accesses at the same time to any of the four blocks (assuming there are no block conflicts). The total bandwidth is realized using the DMD and PMD buses (2x64-bits, core CLK) and the IOD0/1 buses (2x32-bit, PCLK). ROM-Based Security The ADSP-21367/ADSP-21368/ADSP-21369 have a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the processor does not boot-load any external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or test access port will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned. | Page 6 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 FAMILY PERIPHERAL ARCHITECTURE Table 4. External Memory for SDRAM Addresses The ADSP-21367/ADSP-21368/ADSP-21369 family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. Bank Size in Words Address Range Bank 0 62M 0x0020 0000–0x03FF FFFF Bank 1 64M 0x0400 0000–0x07FF FFFF External Port Bank 2 64M 0x0800 0000–0x0BFF FFFF The external port interface supports access to the external memory through core and DMA accesses. The external memory address space is divided into four banks. Any bank can be programmed as either asynchronous or synchronous memory. The external ports of the ADSP-21367/8/9 processors are comprised of the following modules. Bank 3 64M 0x0C00 0000–0x0FFF FFFF • An Asynchronous Memory Interface which communicates with SRAM, FLASH, and other devices that meet the standard asynchronous SRAM access protocol. The AMI supports 14M words of external memory in bank 0 and 16M words of external memory in bank 1, bank 2, and bank 3. • An SDRAM controller that supports a glueless interface with any of the standard SDRAMs. The SDC supports 62M words of external memory in bank 0, and 64M words of external memory in bank 1, bank 2, and bank 3. • Arbitration Logic to coordinate core and DMA transfers between internal and external memory over the external port. • A Shared Memory Interface that allows the connection of up to four ADSP-21368 processors to create shared external bus systems (ADSP-21368 only). SDRAM Controller The SDRAM controller provides an interface of up to four separate banks of industry-standard SDRAM devices or DIMMs, at speeds up to fSCLK. Fully compliant with the SDRAM standard, each bank has its own memory select line (MS0–MS3), and can be configured to contain between 16M bytes and 128M bytes of memory. SDRAM external memory address space is shown in Table 4. A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. The memory banks can be configured as either 32 bits wide for maximum performance and bandwidth or 16 bits wide for minimum device count and lower system cost. The SDRAM controller address, data, clock, and control pins can drive loads up to distributed 30 pF loads. For larger memory systems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF. External Memory The external port provides a high performance, glueless interface to a wide variety of industry-standard memory devices. The 32-bit wide bus can be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller Rev. E for connection of industry-standard synchronous DRAM devices and DIMMs (dual inline memory module), while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. Non-SDRAM external memory address space is shown in Table 5. Table 5. External Memory for Non-SDRAM Addresses Bank Size in Words Address Range Bank 0 14M 0x0020 0000–0x00FF FFFF Bank 1 16M 0x0400 0000–0x04FF FFFF Bank 2 16M 0x0800 0000–0x08FF FFFF Bank 3 16M 0x0C00 0000–0x0CFF FFFF Shared External Memory The ADSP-21368 processor supports connecting to common shared external memory with other ADSP-21368 processors to create shared external bus processor systems. This support includes: • Distributed, on-chip arbitration for the shared external bus • Fixed and rotating priority bus arbitration • Bus time-out logic • Bus lock Multiple processors can share the external bus with no additional arbitration logic. Arbitration logic is included on-chip to allow the connection of up to four processors. Bus arbitration is accomplished through the BR1–4 signals and the priority scheme for bus arbitration is determined by the setting of the RPBA pin. Table 8 on Page 13 provides descriptions of the pins used in multiprocessor systems. External Port Throughput The throughput for the external port, based on 166 MHz clock and 32-bit data bus, is 221M bytes/s for the AMI and 664M bytes/s for SDRAM. | Page 7 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 Asynchronous Memory Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety of memory devices including SRAM, ROM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 14M word window and Banks 1, 2, and 3 occupy a 16M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. The banks can also be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of interfacing to a range of memories and I/O devices tailored either to high performance or to low cost and power. Pulse-Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode, the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in 2-phase PWM inverters. Digital Applications Interface (DAI) The digital applications interface (DAI ) provide the ability to connect various peripherals to any of the DSP’s DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU1), shown in Figure 1. The SRU is amatrix routing unit (or group of multiplexers) that enable the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. The DAI include eight serial ports, an S/PDIF receiver/transmitter, four precision clock generators (PCG), eight channels of synchronous sample rate converters, and an input data port (IDP). The IDP provides an additional input path to the Rev. E processor core, configurable as either eight channels of I2S serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports. For complete information on using the DAI, see the ADSP-21368 SHARC Processor Hardware Reference. Serial Ports The processors feature eight synchronous serial ports (SPORTs) that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports are enabled via 16 programmable and simultaneous receive or transmit pins that support up to 32 transmit or 32 receive channels of audio data when all eight SPORTs are enabled, or eight full duplex TDM streams of 128 channels per frame. The serial ports operate at a maximum data rate of 50 Mbps. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in five modes: • Standard DSP serial mode • Multichannel (TDM) mode with support for packed I2S mode • I2S mode • Packed I2S mode • Left-justified sample pair mode Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over various attributes of this mode. Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry-standard interface commonly used by audio codecs, ADCs, and DACs such as the Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 32 I2S channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated. | Page 8 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 The serial ports also contain frame sync error detection logic where the serial ports detect frame syncs that arrive early (for example, frame syncs that arrive while the transmission/reception of the previous word is occurring). All the serial ports also share one dedicated error interrupt. S/PDIF-Compatible Digital Audio Receiver/Transmitter The S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers. Synchronous/Asynchronous Sample Rate Converter The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Input Data Port The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive audio channels in I2S, left-justified sample pair, or right-justified mode. One frame sync cycle indicates one 64-bit left/right pair, but data is sent to the FIFO as 32-bit words (that is, onehalf of a frame at a time). The processor supports 24- and 32-bit I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justified formats. Precision Clock Generators The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D, are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. Digital Peripheral Interface (DPI) The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), two universal asynchronous receiver-transmitters (UARTs), a 2-wire interface (TWI), 12 flags, and three general-purpose timers. Rev. E Serial Peripheral (Compatible) Interface The processors contain two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21367/ ADSP-21368/ADSP-21369 SPI-compatible peripheral implementation also features programmable baud rate and clock phase and polarities. The SPI-compatible port uses open-drain drivers to support a multimaster configuration and to avoid data contention. UART Port The processors provide a full-duplex universal asynchronous receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface standard. The UART port also includes support for five data bits to eight data bits, one stop bit or two stop bits, and none, even, or odd parity. The UART port supports two modes of operation: • PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive. • DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. The UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable: • Supporting bit rates ranging from (fSCLK/1,048,576) to (fSCLK/16) bits per second. • Supporting data formats from 7 bits to 12 bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. Where the 16-bit UART_Divisor comes from the DLH register (most significant eight bits) and DLL register (least significant eight bits). In conjunction with the general-purpose timer functions, autobaud detection is supported. | Page 9 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 Peripheral Timers Delay Line DMA Three general-purpose timers can generate periodic interrupts and be independently set to operate in one of three modes: The ADSP-21367/ADSP-21368/ADSP-21369 processors provide delay line DMA functionality. This allows processor reads and writes to external delay line buffers (in external memory, SRAM, or SDRAM) with limited core interaction. • Pulse waveform generation mode • Pulse width count/capture mode SYSTEM DESIGN • External event watchdog mode Each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers independently. 2-Wire Interface Port (TWI) The TWI is a bidirectional 2-wire serial bus used to move 8-bit data while maintaining compliance with the I2C bus protocol. The TWI master incorporates the following features: • Simultaneous master and slave operation on multiple device systems with support for multimaster data arbitration The following sections provide an introduction to system design options and power supply issues. Program Booting The internal memory of the processors can be booted up at system power-up from an 8-bit EPROM via the external port, an SPI master or slave, or an internal boot. Booting is determined by the boot configuration (BOOT_CFG1–0) pins (see Table 7 and the processor hardware reference). Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM. Table 7. Boot Mode Selection BOOT_CFG1–0 00 01 10 11 • Digital filtering and timed event processing • 7-bit and 10-bit addressing • 100 kbps and 400 kbps data rates • Low interrupt rate Booting Mode SPI Slave Boot SPI Master Boot EPROM/FLASH Boot Reserved I/O PROCESSOR FEATURES Power Supplies The I/O processor provides many channels of DMA, and controls the extensive set of peripherals described in the previous sections. The processors have separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.3 V requirement for the 400 MHz device and 1.2 V for the 333 MHz and 266 MHz devices. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. DMA Controller The processor’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the UART. Thirty four channels of DMA are available on the ADSP-2136x processors as shown in Table 6. Table 6. DMA Channels Peripheral SPORTs PDAP SPI UART External Port Memory-to-Memory DMA Channels 16 8 2 4 2 2 Rev. E Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure 3. (A recommended ferrite chip is the muRata BLM18AG102SN1D). To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure 3 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip. | Page 10 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 100nF 10nF 1nF ADSP-213xx AVDD VDDINT HI-Z FERRITE BEAD CHIP developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: AVSS • View mixed C/C++ and assembly code (interleaved source and object information) LOCATE ALL COMPONENTS CLOSE TO AVDD AND AVSS PINS • Insert breakpoints • Set conditional breakpoints on registers, memory, and stacks Figure 3. Analog Power (AVDD) Filter Circuit Target Board JTAG Emulator Connector • Perform linear or statistical profiling of program execution Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21367/ ADSP-21368/ADSP-21369 processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing. • Fill, dump, and graphically plot the contents of memory For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate “Emulator Hardware User’s Guide.” DEVELOPMENT TOOLS The processors are supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21367/ ADSP-21368/ADSP-21369. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the Rev. E • Perform source level debugging • Create custom debugger windows The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: • Control how the development tools process inputs and generate outputs • Maintain a one-to-one correspondence with the tool’s command line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK. Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a drag of the mouse and examine runtime stack and heap usage. The expert linker is fully compatible with the existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments. | Page 11 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Thirdparty software tools include DSP libraries, real-time operating systems, and block diagram design tools. Designing an Emulator-Compatible DSP Board (Target) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. Nonintrusive in-circuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. Rev. E Evaluation Kit Analog Devices offers a range of EZ-KIT Lite® evaluation platforms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom-defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21367/ADSP-21368/ADSP-21369 architecture and functionality. For detailed information on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-21368 SHARC Processor Hardware Reference and the SHARC Processor Programming Reference. | Page 12 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 PIN FUNCTION DESCRIPTIONS The following symbols appear in the Type column of Table 8: A = asynchronous, G = ground, I = input, O = output, O/T = output three-state, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open-drain, (pd) = pull-down resistor, (pu) = pull-up resistor. The ADSP-21367/ADSP-21368/ADSP-21369 SHARC processors use extensive pin multiplexing to achieve a lower pin count. For complete information on the multiplexing scheme, see the ADSP-21368 SHARC Processor Hardware Reference, “System Design” chapter. Table 8. Pin Descriptions State During/ After Reset (ID = 00x) Description Name Type ADDR23–0 O/T (pu)1 Pulled high/ driven low External Address. The processors output addresses for external memory and peripherals on these pins. DATA31–0 I/O (pu)1 Pulled high/ pulled high External Data. Data pins can be multiplexed to support external memory interface data (I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF mode and FLAG(0-3) pins are in FLAGS mode (default). When configured using the IDP_PDAP_CTL register, IDP Channel 0 scans the external port data pins for parallel input data. ACK I (pu)1 MS0–1 O/T (pu)1 Pulled high/ driven high Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corresponding banks of external memory. The MS3-0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring, the MS3-0 lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether or not the condition is true. The MS1 pin can be used in EPORT/FLASH boot mode. See the processor hardware reference for more information. RD O/T (pu)1 Pulled high/ driven high External Port Read Enable. RD is asserted whenever the processors read a word from external memory. WR O/T (pu)1 Pulled high/ driven high External Port Write Enable. WR is asserted when the processors write a word to external memory. FLAG[0]/IRQ0 I/O FLAG[0] INPUT FLAG0/Interrupt Request 0. FLAG[1]/IRQ1 I/O FLAG[1] INPUT FLAG1/Interrupt Request 1. FLAG[2]/IRQ2/ MS2 I/O with programmable pu (for MS mode) FLAG[2] INPUT FLAG2/Interrupt Request 2/Memory Select 2. FLAG[3]/ TMREXP/MS3 I/O with programmable pu (for MS mode) FLAG[3] INPUT FLAG3/Timer Expired/Memory Select 3. Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. Rev. E | Page 13 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 Table 8. Pin Descriptions (Continued) State During/ After Reset (ID = 00x) Description Name Type SDRAS O/T (pu)1 Pulled high/ driven high SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDCAS O/T (pu)1 Pulled high/ driven high SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform. SDWE O/T (pu)1 Pulled high/ driven high SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. SDCKE O/T (pu)1 Pulled high/ driven high SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal. For details, see the data sheet supplied with the SDRAM device. SDA10 O/T (pu)1 Pulled high/ driven low SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with nonSDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses. SDCLK0 O/T High-Z/driving SDRAM Clock Output 0. Clock driver for this pin differs from all other clock drivers. See Figure 39 on Page 48. SDCLK1 O/T DAI _P20–1 I/O with programmable pu2 Pulled high/ pulled high Digital Applications Interface. These pins provide the physical interface to the DAI SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric peripheral inputs or outputs connected to the pin, and to the pin’s output enable. The configuration registers then determines the exact behavior of the pin. Any input or output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU provides the connection from the serial ports (8), the SRC module, the S/PDIF module, input data ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. Pullups can be disabled via the DAI_PIN_PULLUP register. DPI _P14–1 I/O with programmable pu2 Pulled high/ pulled high Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU. The DPI SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) TWI (1), and general-purpose I/O (9) to the DPI_P14–1 pins. The TWI output is an open-drain output— so the pins used for I2C data and clock should be connected to logic level 0. Pull-ups can be disabled via the DPI_PIN_PULLUP register. TDI I (pu) Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDO O/T Test Data Output (JTAG). Serial scan output of the boundary scan path. TMS I (pu) Test Mode Select (JTAG). Used to control the test state machine. TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up, or held low for proper operation of the processor TRST I (pu) Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the processor. SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices, handles the increased clock load requirements, eliminating need of offchip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. Clock driver for this pin differs from all other clock drivers. See Figure 39 on Page 48. The SDCLK1 signal is only available on the SBGA package. SDCLK1 is not available on the LQFP_EP package. Rev. E | Page 14 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 Table 8. Pin Descriptions (Continued) 1 2 State During/ After Reset (ID = 00x) Name Type EMU O/T (pu) Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/ ADSP-21369 Analog Devices DSP Tools product line of JTAG emulator target board connectors only. CLK_CFG1–0 I Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See the processor hardware reference for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. CLKIN I Local Clock In. Used with XTAL. CLKIN is the processor’s clock input. It configures the processors to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processor to use an external clock such as an external clock oscillator. CLKIN may not be halted, changed, or operated below the specified frequency. XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. RESET I Processor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at powerup. RESETOUT O BOOT_CFG1–0 I BR4–1 I/O (pu)1 ID2–0 I (pd) Processor ID. Determines which bus request (BR4–1) is used by the ADSP-21368 processor. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000 or 001 in single-processor systems. These lines are a system configuration selection that should be hardwired or only changed at reset. ID = 101,110, and 111 are reserved. RPBA I (pu)1 Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for the ADSP-21368 external bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every processor in the system. Driven low/ driven high Description Reset Out. Drives out the core reset signal to an external device. Boot Configuration Select. These pins select the boot mode for the processor. The BOOT_CFG pins must be valid before reset is asserted. See the processor hardware reference for a description of the boot modes. Pulled high/ pulled high External Bus Request. Used by the ADSP-21368 processor to arbitrate for bus mastership. A processor only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a system with less than four processors, the unused BRx pins should be tied high; the processor’s own BRx line must not be tied high or low because it is an output. The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID2–0 = 00x Pull-up can be enabled/disabled, value of pull-up cannot be programmed. Rev. E | Page 15 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 SPECIFICATIONS OPERATING CONDITIONS 366 MHz 350 MHz 400 MHz Parameter1 Description 333 MHz 266 MHz Min Max Min Max Min Max Unit 1.25 1.35 1.235 1.365 1.14 1.26 V VDDINT Internal (Core) Supply Voltage AVDD Analog (PLL) Supply Voltage 1.25 1.35 1.235 1.365 1.14 1.26 V VDDEXT External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 V High Level Input Voltage @ VDDEXT = Max 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 V Low Level Input Voltage @ VDDEXT = Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V 2 VIH 2 VIL 3 VIH_CLKIN High Level Input Voltage @ VDDEXT = Max 1.74 VDDEXT + 0.5 1.74 VDDEXT + 0.5 1.74 VDDEXT + 0.5 V VIL_CLKIN3 Low Level Input Voltage @ VDDEXT = Min –0.5 +1.1 –0.5 +1.1 –0.5 +1.1 V TJ Junction Temperature 208-Lead LQFP_EP @ TAMBIENT 0°C to 70°C N/A N/A 0 110 0 110 °C Junction Temperature 208-Lead LQFP_EP @ TAMBIENT –40°C to +85°C N/A N/A N/A N/A –40 +120 °C TJ Junction Temperature 256-Ball BGA_ED @ TAMBIENT 0°C to 70°C 0 95 N/A N/A 0 105 °C TJ Junction Temperature 256-Ball BGA_ED @ TAMBIENT –40°C to +85°C N/A N/A N/A N/A 0 105 °C TJ 1 Specifications subject to change without notice. Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST. 3 Applies to input pin CLKIN. 2 Rev. E | Page 16 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 ELECTRICAL CHARACTERISTICS Parameter Description Test Conditions Min VOH1 Max Unit High Level Output Voltage @ VDDEXT = Min, IOH = –1.0 mA2 2.4 VOL Low Level Output Voltage @ VDDEXT = Min, IOL = 1.0 mA2 0.4 V IIH3, 4 High Level Input Current @ VDDEXT = Max, VIN = VDDEXT Max 10 μA Low Level Input Current @ VDDEXT = Max, VIN = 0 V 10 μA High Level Input Current Pull-Down @ VDDEXT = Max, VIN = 0 V 250 μA Low Level Input Current Pull-Up @ VDDEXT = Max, VIN = 0 V 200 μA 7, 8 Three-State Leakage Current @ VDDEXT = Max, VIN = VDDEXT Max 10 μA 7, 9 Three-State Leakage Current @ VDDEXT = Max, VIN = 0 V 10 μA 1 3, 5, 6 IIL IIHPD 5 IILPU4 IOZH IOZL 8 Typ V IOZLPU Three-State Leakage Current Pull-Up @ VDDEXT = Max, VIN = 0 V IDD-INTYP10 Supply Current (Internal) tCCLK = 3.75 ns, VDDINT = 1.2 V, 25°C tCCLK = 3.00 ns, VDDINT = 1.2 V, 25°C tCCLK = 2.85 ns, VDDINT = 1.3 V, 25°C tCCLK = 2.73 ns, VDDINT = 1.3 V, 25°C tCCLK = 2.50 ns, VDDINT = 1.3 V, 25°C AIDD11 Supply Current (Analog) AVDD = Max 11 mA Input Capacitance fIN = 1 MHz, TCASE = 25°C, VIN = 1.3 V 4.7 pF 12, 13 CIN 1 200 μA mA mA mA mA mA 700 900 1050 1080 1100 Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO. See Output Drive Currents on Page 48 for typical drive current capabilities. 3 Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK. 4 Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST. 5 Applies to input pins with internal pull-downs: IDx. 6 Applies to input pins with internal pull-ups disabled: ACK, RPBA. 7 Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO. 8 Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU. 9 Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10 10 See Estimating Power Dissipation for ADSP-21368 SHARC Processors (EE-299) for further information. 11 Characterized, but not tested. 12 Applies to all signal pins. 13 Guaranteed, but not tested. 2 Rev. E | Page 17 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 PACKAGE INFORMATION Table 10. Absolute Maximum Ratings The information presented in Figure 4 provides details about the package branding for the ADSP-21367/ADSP-21368/ ADSP-21369 processors. For a complete listing of product availability, see Ordering Guide on Page 58. a ADSP-2136x tppZ-cc Parameter Internal (Core) Supply Voltage (VDDINT) Analog (PLL) Supply Voltage (AVDD) External (I/O) Supply Voltage (VDDEXT) Input Voltage Output Voltage Swing Load Capacitance Storage Temperature Range Junction Temperature Under Bias Rating –0.3 V to +1.5 V –0.3 V to +1.5 V –0.3 V to +4.6 V –0.5 V to +3.8 V –0.5 V to VDDEXT + 0.5 V 200 pF –65°C to +150°C 125°C vvvvvv.x n.n #yyww country_of_origin TIMING SPECIFICATIONS S Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 40 on Page 48 under Test Conditions for voltage reference levels. Figure 4. Typical Package Brand Table 9. Package Brand Information Brand Key t pp Z cc vvvvvv.x n.n # yyww Field Description Temperature Range Package Type RoHS Compliant Option See Ordering Guide Assembly Lot Code Silicon Revision RoHS Compliant Designation Date Code Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. MAXIMUM POWER DISSIPATION See Estimating Power Dissipation for ADSP-21368 SHARC Processors (EE-299) for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 50. ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 10 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. E Core Clock Requirements The processor’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins. The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL, see Figure 5). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock. Voltage Controlled Oscillator In application designs, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds fVCO specified in Table 13. • The product of CLKIN and PLLM must never exceed 1/2 of fVCO (max) in Table 13 if the input divider is not enabled (INDIV = 0). | Page 18 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 • The product of CLKIN and PLLM must never exceed fVCO (max) in Table 13 if the input divider is enabled (INDIV = 1). Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in and Table 11. All of the timing specifications for the ADSP-2136x peripherals are defined in relation to tPCLK. See the peripheral specific timing section for each peripheral’s timing information. The VCO frequency is calculated as follows: fVCO = 2 × PLLM × fINPUT fCCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLD) Table 11. Clock Periods where: Timing Requirements tCK tCCLK tPCLK fVCO = VCO output PLLM = Multiplier value programmed in the PMCTL register. During reset, the PLLM value is derived from the ratio selected using the CLK_CFG pins in hardware. PLLD = Divider value 1, 2, 4, or 8 based on the PLLD value programmed on the PMCTL register. During reset this value is 1. Description CLKIN Clock Period Processor Core Clock Period Peripheral Clock Period = 2 × tCCLK Figure 5 shows core to CLKIN relationships with external oscillator or crystal. The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, see the processor hardware reference. fINPUT = Input frequency to the PLL. fINPUT = CLKIN when the input divider is disabled or fINPUT = CLKIN ÷ 2 when the input divider is enabled PMCTL (SDCKR) PMCTL (PLLBP) CLKIN DIVIDER fINPUT LOOP FILTER fVCO VCO PLL DIVIDER fCCLK XTAL CCLK SDRAM DIVIDER BYPASS MUX CLKIN BYPASS MUX PLL PMCTL (2xPLLD) BUF PMCTL (INDIV) PLL MULTIPLIER DIVIDE BY 2 PMCTL (PLLBP) SDCLK PCLK PCLK CLK_CFGx/PMCTL (2xPLLM) CCLK PIN MUX CLKOUT (TEST ONLY) DELAY OF 4096 CLKIN CYCLES Figure 5. Core Clock and System Clock Relationship to CLKIN Rev. E | Page 19 of 60 | July 2009 BUF ADSP-21367/ADSP-21368/ADSP-21369 Power-Up Sequencing driven low before power up is complete. This leakage current results from the weak internal pull-up resistor on this pin being enabled during power-up. The timing requirements for processor start-up are given in Table 12. Note that during power-up, a leakage current of approximately 200μA may be observed on the RESET pin if it is Table 12. Power-Up Sequencing Timing Requirements (Processor Start-up) Parameter Timing Requirements tRSTVDD tIVDDEVDD tCLKVDD1 tCLKRST tPLLRST Switching Characteristic tCORERST Min RESET Low Before VDDINT/VDDEXT On VDDINT On Before VDDEXT CLKIN Valid After VDDINT/VDDEXT Valid CLKIN Valid Before RESET Deasserted PLL Control Setup Before RESET Deasserted 0 –50 0 102 20 Core Reset Deasserted After RESET Deasserted 4096tCK + 2 tCCLK 3, 4 1 Max +200 200 Unit ns ms ms μs μs Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. 2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate default states at all I/O pins. 4 The 4096 cycle count depends on tsrst specification in Table 14. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum. RESET VDDINT tRSTVDD tIVDDEVDD VDDEXT tCLKVDD CLKIN tCLKRST CLK_CFG1–0 tPLLRST RESETOUT Figure 6. Power-Up Sequencing Rev. E | Page 20 of 60 | July 2009 tCORERST ADSP-21367/ADSP-21368/ADSP-21369 Clock Input Table 13. Clock Input Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK7 CCLK Period VCO Frequency fVCO8 tCKJ9, 10 CLKIN Jitter Tolerance 400 MHz1 Min Max 366 MHz2 Min Max 350 MHz3 Min Max 333 MHz4 Min Max 266 MHz5 Min Max 156 7.51 7.51 16.396 8.11 8.11 17.146 8.51 8.51 186 91 91 22.56 11.251 11.251 2.56 100 –250 100 45 45 3 10 800 +250 2.736 100 –250 100 45 45 3 10 800 +250 100 45 45 3 10 800 +250 2.856 100 –250 1 Applies to all 400 MHz models. See Ordering Guide on Page 58. Applies to all 366 MHz models. See Ordering Guide on Page 58. 3 Applies to all 350 MHz models. See Ordering Guide on Page 58. 4 Applies to all 333 MHz models. See Ordering Guide on Page 58. 5 Applies to all 266 MHz models. See Ordering Guide on Page 58. 6 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL. 7 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK. 8 See Figure 5 on Page 19 for VCO diagram. 9 Actual input jitter should be combined with ac specifications for accurate timing analysis. 10 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. 2 tCKJ tCK CLKIN tCKH tCKL Figure 7. Clock Input Rev. E | Page 21 of 60 | July 2009 3.06 100 –250 100 45 45 3 10 800 +250 3.756 100 –250 100 45 45 3 10 600 +250 Unit ns ns ns ns ns MHz ps ADSP-21367/ADSP-21368/ADSP-21369 Clock Signals The processors can use an external clock or a crystal. See the CLKIN pin description in Table 8 on Page 13. Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 8 shows the component connections used for a crystal operating in fundamental mode. Note that the clock rate is achieved using a 25 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 400 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. ADSP-2136x CLKIN R1 1M⍀* XTAL R2 47⍀* C1 22pF Y1 C2 22pF 25.00 MHz R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS Figure 8. 400 MHz Operation (Fundamental Mode Crystal) Rev. E | Page 22 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 Reset Table 14. Reset Parameter Timing Requirements tWRST1 RESET Pulse Width Low tSRST RESET Setup Before CLKIN Low 1 Min Max Unit 4tCK 8 ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST tSRST RESET Figure 9. Reset Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Table 15. Interrupts Parameter Timing Requirement tIPW IRQx Pulse Width Min 2 × tPCLK +2 DAI_P20–1 DPI_P14–1 FLAG2–0 (IRQ2–0) tIPW Figure 10. Interrupts Rev. E | Page 23 of 60 | July 2009 Max Unit ns ADSP-21367/ADSP-21368/ADSP-21369 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP). Table 16. Core Timer Parameter Switching Characteristic tWCTIM TMREXP Pulse Width Min Max 4 × tPCLK – 1 FLAG3 (TMREXP) Unit ns tWCTIM Figure 11. Core Timer Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins. Table 17. Timer PWM_OUT Timing Parameter Switching Characteristic tPWMO Timer Pulse Width Output Min Max Unit 2 × tPCLK – 1.2 2 × (231 – 1) × tPCLK ns tPWMO DPI_P14–1 (TIMER2–0) Figure 12. Timer PWM_OUT Timing Rev. E | Page 24 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 Timer WDTH_CAP Timing The following specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the DPI SRU. Therefore, the specification provided in Table 18 is valid at the DPI_P14–1 pins. Table 18. Timer Width Capture Timing Parameter Switching Characteristic tPWI Timer Pulse Width Min Max Unit 2 × tPCLK 2 × (231 – 1) × tPCLK ns tPWI DPI_P14–1 (TIMER2–0) Figure 13. Timer Width Capture Timing Pin to Pin Direct Routing (DAI and DPI) For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 19. DAI/DPI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid Min Max Unit 1.5 12 ns DAI_Pn DPI_Pn DAI_Pm DPI_Pm tDPIO Figure 14. DAI/DPI Pin to Pin Direct Routing Rev. E | Page 25 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P01–20). Table 20. Precision Clock Generator (Direct Pin Routing) Parameter Min Max Unit Timing Requirements tPCGIP Input Clock Period tPCLK × 4 ns tSTRIG PCG Trigger Setup Before Falling 4.5 ns Edge of PCG Input Clock tHTRIG PCG Trigger Hold After Falling 3 ns Edge of PCG Input Clock Switching Characteristics tDPCGIO PCG Output Clock and Frame Sync Active Edge 2.5 10 ns Delay After PCG Input Clock tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2.5 + (2.5 × tPCGIP) 10 + (2.5 × tPCGIP) ns tDTRIGFS PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × tPCGIP) 10 + ((2.5 + D – PH) × tPCGIP) ns tPCGOW1 Output Clock Period 2 × tPCGIP – 1 ns D = FSxDIV, and PH = FSxPHASE. For more information, see the processor hardware reference, “Precision Clock Generators” chapter. 1 In normal mode. tSTRIG tHTRIG DAI_Pn DPI_Pn PCG_TRIGx_I tPCGIW DAI_Pm DPI_Pm PCG_EXTx_I (CLKIN) tDPCGIO DAI_Py DPI_Py PCK_CLKx_O tDTRIGCLK tDPCGIO DAI_Pz DPI_Pz PCG_FSx_O tDTRIGFS Figure 15. Precision Clock Generator (Direct Pin Routing) Rev. E | Page 26 of 60 | July 2009 tPCGOW ADSP-21367/ADSP-21368/ADSP-21369 Flags The timing specifications provided below apply to the FLAG3–0 and DPI_P14–1 pins, and the serial peripheral interface (SPI). See Table 8 on Page 13 for more information on flag use. Table 21. Flags Parameter Timing Requirement FLAG3–0 IN Pulse Width tFIPW Switching Characteristic tFOPW FLAG3–0 OUT Pulse Width Min Unit 2 × tPCLK + 3 ns 2 × tPCLK – 1.5 ns DPI_P14–1 (FLAG3–0IN) (AMI_DATA7–0) (AMI_ADDR23–0) tFIPW DPI_P14-1 (FLAG3–0OUT) (AMI_DATA7–0) (AMI_ADDR23–0) tFOPW Figure 16. Flags Rev. E Max | Page 27 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 SDRAM Interface Timing (166 MHz SDCLK) The 166 MHz access speed is for a single processor. When multiple ADSP-21368 processors are connected in a shared memory system, the access speed is 100 MHz. Table 22. SDRAM Interface Timing1 Parameter Timing Requirements tSSDAT DATA Setup Before SDCLK DATA Hold After SDCLK tHSDAT Switching Characteristics tSDCLK SDCLK Period tSDCLKH SDCLK Width High tSDCLKL SDCLK Width Low tDCAD Command, ADDR, Data Delay After SDCLK2 Command, ADDR, Data Hold After SDCLK2 tHCAD tDSDAT Data Disable After SDCLK tENSDAT Data Enable After SDCLK 366 MHz Min Max 350 MHz Min Max All Other Speed Grades Min Max Unit 500 1.23 500 1.23 500 1.23 ps ns 6.83 3 3 7.14 3 3 6.0 2.6 2.6 ns ns ns ns ns ns ns 4.8 1.2 4.8 1.2 5.3 1.3 5.3 1.3 tSDCLKH tSDCLK SDCLK tSDCLKL tHSDAT DATA (IN) tDCAD tENSDAT tDCAD CMND ADDR (OUT) tHCAD Figure 17. SDRAM Interface Timing Rev. E tDSDAT tHCAD DATA (OUT) | Page 28 of 60 | July 2009 5.3 1.3 The processor needs to be programmed in tSDCLK = 2.5 × tCCLK mode when operated at 350MHz, 366MHz and 400MHz. 2 Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE. 1 tSSDAT 4.8 1.2 ADSP-21367/ADSP-21368/ADSP-21369 SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Table 23. SDRAM Interface Enable/Disable Timing1 Parameter Switching Characteristics tDSDC Command Disable After CLKIN Rise tENSDC Command Enable After CLKIN Rise tDSDCC SDCLK Disable After CLKIN Rise tENSDCC SDCLK Enable After CLKIN Rise tDSDCA Address Disable After CLKIN Rise tENSDCA Address Enable After CLKIN Rise 1 Min Max Unit 2 × tPCLK + 3 ns ns ns ns ns ns 4.0 8.5 3.8 2 × tPCLK – 4 For fCCLK = 400 MHz (SDCLK ratio = 1:2.5). CLKIN tDSDC tDSDCC tDSDCA COMMAND SDCLK ADDR tENSDC tENSDCA tENSDCC COMMAND SDCLK ADDR Figure 18. SDRAM Interface Enable/Disable Timing Rev. E | Page 29 of 60 | July 2009 9.2 4 × tPCLK ADSP-21367/ADSP-21368/ADSP-21369 Memory Read Use these specifications for asynchronous interfacing to memories. These specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 24. Memory Read Parameter Timing Requirements tDAD Address, Selects Delay to Data Valid1 tDRLD RD Low to Data Valid tSDS Data Setup to RD High tHDRH Data Hold from RD High2, 3 tDAAK ACK Delay from Address, Selects1, 4 tDSAK ACK Delay from RD Low4 Min Max Unit W + tSDCLK –5.12 W – 3.2 tSDCLK –9.5 + W ns ns ns ns ns W – 7.0 ns 2.5 0 Switching Characteristics tDRHA Address Selects Hold After RD High RH + 0.20 tDARL Address Selects to RD Low1 tSDCLK – 3.3 tRW RD Pulse Width W – 1.4 tRWR RD High to WR, RD Low HI + tSDCLK – 0.8 W = (number of wait states specified in AMICTLx register) × tSDCLK. HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × tSDCLK IC = (number of idle cycles specified in AMICTLx register) × tSDCLK. H = (number of hold cycles specified in AMICTLx register) × tSDCLK. ns ns ns ns 1 The falling edge of MSx is referenced. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. 3 Data hold: User must meet tHDA or tHDRH in asynchronous access mode. See Test Conditions on Page 48 for the calculation of hold times given capacitive and dc loads. 4 ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet tDAAK or tDSAK. 2 ADDR MSx tDARL tRW tDRHA RD tDRLD tSDS tDAD tHDRH DATA tRWR tDSAK tDAAK ACK WR Figure 19. Memory Read Rev. E | Page 30 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 access mode. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode. Memory Write Use these specifications for asynchronous interfacing to memories. These specifications apply when the processors are the bus masters, accessing external memory space in asynchronous Table 25. Memory Write Parameter Timing Requirements ACK Delay from Address, Selects1, 2 tDAAK tDSAK ACK Delay from WR Low 1, 3 Switching Characteristics tDAWH Address, Selects to WR Deasserted2 tDAWL Address, Selects to WR Low2 tWW WR Pulse Width Data Setup Before WR High tDDWH tDWHA Address Hold After WR Deasserted tDWHD Data Hold After WR Deasserted tWWR WR High to WR, RD Low tDDWR Data Disable Before RD Low tWDE WR Low to Data Enabled W = (number of wait states specified in AMICTLx register) × tSDCLK. H = (number of hold cycles specified in AMICTLx register) × tSDCLK. Min Max Unit tSDCLK – 9.7 + W W – 4.9 ns ns tSDCLK – 3.1+ W tSDCLK – 2.7 W – 1.3 tSDCLK – 3.0+ W H + 0.15 H + 0.02 tSDCLK – 1.5+ H 2tSDCLK – 4.11 tSDCLK – 3.5 ns ns ns ns ns ns ns ns ns 1 ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high), user must meet tDAAK or tDSAK. The falling edge of MSx is referenced. 3 Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode. 2 ADDR MSx tDWHA tDAWH tDAWL tWW WR tWWR tWDE tDDWH tDATRWH DATA tDSAK tDWHD tDAAK ACK RD Figure 20. Memory Write Rev. E | Page 31 of 60 | July 2009 tDDWR ADSP-21367/ADSP-21368/ADSP-21369 Asynchronous Memory Interface (AMI) Enable/Disable Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 26. AMI Enable/Disable Parameter Switching Characteristics tENAMIAC Address/Control Enable After Clock Rise tENAMID Data Enable After Clock Rise tDISAMIAC Address/Control Disable After Clock Rise tDISAMID Data Disable After Clock Rise CLKIN Min Unit 8.7 0 ns ns ns ns 4 tSDCLK + 4 tDISAMIAC tDISAMID ADDR, WR , RD, MS1–0, DATA tENAMIAC tENAMID ADDR , WR , RD, MS1–0, DATA Figure 21. AMI Enable/Disable Rev. E Max | Page 32 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 Shared Memory Bus Request Use these specifications for passing bus mastership between ADSP-21368 processors (BRx). Table 27. Multiprocessor Bus Request Parameter Timing Requirements tSBRI BRx, Setup Before CLKIN High tHBRI BRx, Hold After CLKIN High Switching Characteristics tDBRO BRx Delay After CLKIN High BRx Hold After CLKIN High tHBRO Min Max 9 0.5 ns ns 9 1.0 CLKIN tDBRO tHBRO BRX(OUT) tSBRI BRX(IN) Figure 22. Shared Memory Bus Request Rev. E | Page 33 of 60 | July 2009 Unit tHBRI ns ns ADSP-21367/ADSP-21368/ADSP-21369 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Serial port signals SCLK, frame sync (FS), data channel A, data channel B are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 28. Serial Ports—External Clock 400 MHz 366 MHz 350 MHz Parameter Timing Requirements tSFSE1 FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode) FS Hold After SCLK tHFSE1 (Externally Generated FS in Either Transmit or Receive Mode) tSDRE1 Receive Data Setup Before Receive SCLK tHDRE1 Receive Data Hold After SCLK tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE2 FS Delay After SCLK (Internally Generated FS in Either Transmit or Receive Mode) tHOFSE2 FS Hold After SCLK (Internally Generated FS in Either Transmit or Receive Mode) tDDTE2 Transmit Data Delay After Transmit SCLK tHDTE2 Transmit Data Hold After Transmit SCLK 1 2 Min 333 MHz Max Min 266 MHz Max Min Max Unit 2.5 2.5 2.5 ns 2.5 2.5 2.5 ns 1.9 2.0 2.5 ns 2.5 (tPCLK × 4) ÷ 2 – 0.5 tPCLK × 4 2.5 (tPCLK × 4) ÷ 2 – 0.5 tPCLK × 4 2.5 (tPCLK × 4) ÷ 2 – 0.5 tPCLK × 4 ns ns ns 10.25 2 10.25 2 7.8 2 2 9.6 2 Referenced to sample edge. Referenced to drive edge. Rev. E 10.25 | Page 34 of 60 | July 2009 ns 9.8 2 ns ns ns ADSP-21367/ADSP-21368/ADSP-21369 Table 29. Serial Ports—Internal Clock Parameter Timing Requirements tSFSI1 FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode) tHFSI1 FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive Mode) tSDRI1 Receive Data Setup Before SCLK tHDRI1 Receive Data Hold After SCLK Switching Characteristics tDFSI2 FS Delay After SCLK (Internally Generated FS in Transmit Mode) FS Hold After SCLK (Internally Generated FS in Transmit Mode) tHOFSI2 tDFSIR2 FS Delay After SCLK (Internally Generated FS in Receive Mode) 2 tHOFSIR FS Hold After SCLK (Internally Generated FS in Receive Mode) tDDTI2 Transmit Data Delay After SCLK tHDTI2 Transmit Data Hold After SCLK 3 tSCLKIW Transmit or Receive SCLK Width Min Max Unit 7 ns 2.5 ns 7 2.5 ns ns 4 –1.0 9.75 –1.0 3.25 –1.0 2 × tPCLK – 1.5 2 × tPCLK + 1.5 ns ns ns ns ns ns ns 1 Referenced to the sample edge. 2 Referenced to drive edge. 3 Minimum SPORT divisor register value. Table 30. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK tDDTTE1 Data Disable from External Transmit SCLK 1 tDDTIN Data Enable from Internal Transmit SCLK 1 Min Max Unit 10 ns ns ns Max Unit 7.75 ns 2 –1 Referenced to drive edge. Table 31. Serial Ports—External Late Frame Sync Parameter Switching Characteristics Data Delay from Late External Transmit FS or External Receive tDDTLFSE1 FS with MCE = 1, MFD = 0 1 tDDTENFS Data Enable for MCE = 1, MFD = 0 1 Min 0.5 The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0. Rev. E | Page 35 of 60 | July 2009 ns ADSP-21367/ADSP-21368/ADSP-21369 EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) tSFSE/I tHFSE/I DAI_P20–1 (FS) tDDTE/I tDDTENFS tHDTE/I DAI_P20–1 (DATA CHANNEL A/B) 2ND BIT 1ST BIT tDDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) tSFSE/I tHFSE/I DAI_P20–1 (FS) tDDTE/I tDDTENFS tHDTE/I DAI_P20–1 (DATA CHANNEL A/B) 1ST BIT 2ND BIT tDDTLFSE NOTES 1. SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20–1 PINS USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20–1 PINS. THE CHARACTERIZED SPORT AC TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH THE SRU. Figure 23. External Late Frame Sync1 1 This figure reflects changes made to support left-justified sample pair mode. Rev. E | Page 36 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK) tDFSIR tDFSE tSFSI tHOFSIR tHFSI DAI_P20–1 (FS) tSFSE tHFSE tSDRE tHDRE tHOFSE DAI_P20–1 (FS) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) NOTES 1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) tSCLKW SAMPLE EDGE DAI_P20–1 (SCLK) tDFSI tDFSE tHOFSI tSFSI tHFSI DAI_P20–1 (SCLK) tHOFSE tSFSE tHFSE DAI_P20–1 (FS) tDDTI tHDTI tHDTE DAI_P20–1 (DATA CHANNEL A/B) tDDTE DAI_P20–1 (DATA CHANNEL A/B) NOTES 1. EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE DRIVE EDGE DAI_P20–1 (SCLK, EXT) SCLK tDDTEN tDDTTE DAI_P20–1 (FS) DRIVE EDGE DAI_P20–1 (DATA CHANNEL A/B) tDDTIN Figure 24. Serial Ports Rev. E | Page 37 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 Input Data Port The timing requirements for the IDP are given in Table 32. IDP signals SCLK, frame sync (FS), and SDATA are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 32. IDP Parameter Timing Requirements tSISFS1 FS Setup Before SCLK Rising Edge 1 tSIHFS FS Hold After SCLK Rising Edge SDATA Setup Before SCLK Rising Edge tSISD1 tSIHD1 SDATA Hold After SCLK Rising Edge tIDPCLKW Clock Width tIDPCLK Clock Period 1 Min 4 2.5 2.5 2.5 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 Max Unit ns ns ns ns ns ns DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE DAI_P20–1 (SCLK) tIPDCLK tIPDCLKW tSISFS tSIHFS DAI_P20–1 (FS) tSISD tSIHD DAI_P20–1 (SDATA) Figure 25. IDP Master Timing Rev. E | Page 38 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 chapter of the ADSP-21368 SHARC Processor Hardware Reference. Note that the 20 bits of external PDAP data can be provided through the external port DATA31–12 pins or the DAI pins. Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 33. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP Table 33. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements PDAP_CLKEN Setup Before PDAP_CLK Sample Edge tSPCLKEN1 tHPCLKEN1 PDAP_CLKEN Hold After PDAP_CLK Sample Edge tPDSD1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 1 tPDHD PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge tPDCLKW Clock Width tPDCLK Clock Period Switching Characteristics tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word tPDSTRB PDAP Strobe Pulse Width 1 Min ns ns ns ns ns ns 2 × tPCLK + 3 2 × tPCLK – 1 ns ns tPDCLK tPDCLKW DAI_P20–1 (PDAP_CLK) tSPCLKEN tHPCLKEN DAI_P20–1 (PDAP_CLKEN) tPDSD tPDHD DATA DAI_P20–1 (PDAP_STROBE) tPDHLDD Figure 26. PDAP Timing Rev. E | Page 39 of 60 | July 2009 Unit 2.5 2.5 3.85 2.5 (tPCLK × 4) ÷ 2 – 3 tPCLK × 4 Data Source pins are DATA31–12, or DAI pins. Source pins for SCLK and FS are: 1) DATA11–10 pins, 2) DAI pins. SAMPLE EDGE Max tPDSTRB ADSP-21367/ADSP-21368/ADSP-21369 Pulse-Width Modulation Generators Table 34. PWM Timing Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period Min Max Unit tPCLK – 2 2 × tPCLK – 1.5 (216 – 2) × tPCLK – 2 (216 – 1) × tPCLK – 1.5 ns ns tPWMW PWM OUTPUTS tPWMP Figure 27. PWM Timing Sample Rate Converter—Serial Input Port The SRC input signals SCLK, frame sync (FS), and SDATA are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 35 are valid at the DAI_P20–1 pins. Table 35. SRC, Serial Input Port Parameter Timing Requirements tSRCSFS1 FS Setup Before SCLK Rising Edge 1 FS Hold After SCLK Rising Edge tSRCHFS tSRCSD1 SDATA Setup Before SCLK Rising Edge tSRCHD1 SDATA Hold After SCLK Rising Edge tSRCCLKW Clock Width tSRCCLK Clock Period 1 Min 4 5.5 4 5.5 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 Max Unit ns ns ns ns ns ns DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE DAI_P20–1 (SCLK) tSRCCLK tSRCCLKW tSRCSFS tSRCHFS DAI_P20–1 (FS) tSRCSD tSRCHD DAI_P20–1 (SDATA) Figure 28. SRC Serial Input Port Timing Rev. E | Page 40 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 and delay specification with regard to SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the drive edge. Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold time Table 36. SRC, Serial Output Port Parameter Timing Requirements FS Setup Before SCLK Rising Edge tSRCSFS1 tSRCHFS1 FS Hold After SCLK Rising Edge tSRCCLKW Clock Width tSRCCLK Clock Period Switching Characteristics tSRCTDD1 Transmit Data Delay After SCLK Falling Edge 1 Transmit Data Hold After SCLK Falling Edge tSRCTDH 1 Min Max 4 5.5 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 ns ns ns ns 9.9 1 Unit ns ns DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK tSRCCLKW DAI_P20–1 (SCLK) tSRCSFS tSRCHFS DAI_P20–1 (FS) tSRCTDD DAI_P20–1 (SDATA) tSRCTDH Figure 29. SRC Serial Output Port Timing Rev. E | Page 41 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter. Figure 30 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel. Data is valid on the rising edge of SCLK. The MSB is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output mode) from an LRCLK transition, so that when there are 64 SCLK periods per LRCLK period, the LSB of the data is rightjustified to the next LRCLK transition. DAI_P20–1 LRCLK RIGHT CHANNEL LEFT CHANNEL DAI_P20–1 SCLK DAI_P20–1 SDATA LSB + 1 MSB – 2 LSB MSB – 1 LSB + 1 MSB – 2 LSB MSB MSB LSB + 2 LSB MSB – 1 LSB + 2 Figure 30. Right-Justified Mode Figure 31 shows the default I2S-justified mode. LRCLK is low for the left channel and high for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition but with a single SCLK period delay. RIGHT CHANNEL DAI_P20–1 LRCLK LEFT CHANNEL DAI_P20–1 SCLK MSB – 2 DAI_P20–1 SDATA MSB – 2 LSB + 1 LSB + 2 MSB – 1 LSB + 1 MSB LSB MSB LSB MSB LSB + 2 MSB – 1 Figure 31. I2S-Justified Mode Figure 32 shows the left-justified mode. LRCLK is high for the left channel and low for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition with no MSB delay. DAI_P20–1 LRCLK RIGHT CHANNEL LEFT CHANNEL DAI_P20–1 SCLK DAI_P20–1 SDATA MSB – 2 MSB – 1 MSB – 2 LSB + 1 MSB LSB LSB + 1 MSB LSB + 2 MSB – 1 Figure 32. Left-Justified Mode Rev. E | Page 42 of 60 | July 2009 LSB LSB + 2 MSB MSB + 1 ADSP-21367/ADSP-21368/ADSP-21369 S/PDIF Transmitter Input Data Timing The timing requirements for the input port are given in Table 37. Input signals SCLK, frame sync (FS), and SDATA are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 37. S/PDIF Transmitter Input Data Timing Parameter Timing Requirements FS Setup Before SCLK Rising Edge tSISFS1 tSIHFS1 FS Hold After SCLK Rising Edge 1 tSISD SDATA Setup Before SCLK Rising Edge tSIHD1 SDATA Hold After SCLK Rising Edge tSISCLKW Clock Width tSISCLK Clock Period Transmit Clock Width tSITXCLKW tSITXCLK Transmit Clock Period 1 Min Max 3 3 3 3 36 80 9 20 Unit ns ns ns ns ns ns ns ns DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSITXCLKW tSITXCLK DAI_P20–1 (TxCLK) tSISCLKW DAI_P20–1 (SCLK) tSISCLK tSISFS tSIHFS tSISD tSIHD DAI_P20–1 (FS) DAI_P20–1 (SDATA) Figure 33. S/PDIF Transmitter Input Timing Oversampling Clock (TxCLK) Switching Characteristics The S/PDIF transmitter has an oversampling clock. This TxCLK input is divided down to generate the biphase clock. Table 38. Oversampling Clock (TxCLK) Switching Characteristics Parameter TxCLK Frequency for TxCLK = 384 × FS TxCLK Frequency for TxCLK = 256 × FS Frame Rate (FS) Min Rev. E Max Oversampling Ratio × FS <= 1/tSITXCLK 49.2 192.0 | Page 43 of 60 | July 2009 Unit MHz MHz kHz ADSP-21367/ADSP-21368/ADSP-21369 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 39. S/PDIF Receiver Internal Digital PLL Mode Timing Parameter Switching Characteristics LRCLK Delay After SCLK tDFSI tHOFSI LRCLK Hold After SCLK tDDTI Transmit Data Delay After SCLK tHDTI Transmit Data Hold After SCLK tSCLKIW1 Transmit SCLK Width 1 Min Max Unit 5 ns ns ns ns ns –2 5 –2 40 SCLK frequency is 64 × FS where FS = the frequency of LRCLK. SAMPLE EDGE DRIVE EDGE tSCLKIW DAI_P20–1 (SCLK) tDFSI tHOFSI DAI_P20–1 (FS) tDDTI tHDTI DAI_P20–1 (DATA CHANNEL A/B) Figure 34. S/PDIF Receiver Internal Digital PLL Mode Timing Rev. E | Page 44 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 SPI Interface—Master The processors contain two SPI ports. The primary has dedicated pins and the secondary is available through the DPI. The timing provided in Table 40 and Table 41 on Page 46 applies to both. Table 40. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) tHSPIDM SPICLK Last Sampling Edge to Data Input Not Valid Switching Characteristics tSPICLKM Serial Clock Cycle tSPICHM Serial Clock High Period tSPICLM Serial Clock Low Period tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge tSDSCIM tHDSM Last SPICLK Edge to FLAG3–0IN High tSPITDM Sequential Transfer Delay Min Max 8.2 2 ns ns 8 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 ns ns ns ns ns ns ns ns 2.5 4 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 1 FLAG3–0 (OUTPUT) tSDSCIM tSPICHM tSPICLM tSPICLM tSPICHM tSPICLKM tSPITDM tHDSM SPICLK (CP = 0) (OUTPUT) SPICLK (CP = 1) (OUTPUT) tHDSPIDM tDDSPIDM MOSI (OUTPUT) LSB MSB tSSPIDM tSSPIDM tHSPIDM CPHASE = 1 MISO (INPUT) tHSPIDM MSB VALID LSB VALID tHDSPIDM tDDSPIDM MOSI (OUTPUT) CPHASE = 0 MISO (INPUT) MSB tSSPIDM LSB tHSPIDM MSB VALID LSB VALID Figure 35. SPI Master Timing Rev. E | Page 45 of 60 | July 2009 Unit ADSP-21367/ADSP-21368/ADSP-21369 SPI Interface—Slave Table 41. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements tSPICLKS Serial Clock Cycle tSPICHS Serial Clock High Period tSPICLS Serial Clock Low Period tSDSCO SPIDS Assertion to First SPICLK Edge, CPHASE = 0 or CPHASE = 1 tHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 tSSPIDS Data Input Valid to SPICLK Edge (Data Input Setup Time) SPICLK Last Sampling Edge to Data Input Not Valid tHSPIDS tSDPPW SPIDS Deassertion Pulse Width (CPHASE = 0) Switching Characteristics tDSOE SPIDS Assertion to Data Out Active tDSOE1 SPIDS Assertion to Data Out Active (SPI2) tDSDHI SPIDS Deassertion to Data High Impedance SPIDS Deassertion to Data High Impedance (SPI2) tDSDHI1 tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) 1 Min Max 4 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK 2 × tPCLK 2 2 2 × tPCLK 0 0 0 0 Unit ns ns ns ns ns ns ns ns 6.8 8 6.8 8.6 9.5 2 × tPCLK 5 × tPCLK ns ns ns ns ns ns ns The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral Interface Port” chapter. SPIDS (INPUT) tSPICHS tSPICLS tSPICLKS tHDS tSDPPW SPICLK (CP = 0) (INPUT) tSPICLS tSDSCO SPICLK (CP = 1) (INPUT) tSPICHS tDSDHI tDDSPIDS tDSOE tDDSPIDS MISO (OUTPUT) MSB LSB tSSPIDS tHSPIDS tSSPIDS CPHASE = 1 MOSI (INPUT) MSB VALID LSB VALID tHDSPIDS tDDSPIDS MISO (OUTPUT) MSB LSB tDSOV CPHASE = 0 MOSI (INPUT) tHDSPIDS tHSPIDS tSSPIDS MSB VALID LSB VALID Figure 36. SPI Slave Timing Rev. E | Page 46 of 60 | July 2009 tDSDHI ADSP-21367/ADSP-21368/ADSP-21369 JTAG Test Access Port and Emulation Table 42. JTAG Test Access Port and Emulation Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS1 System Inputs Setup Before TCK High 1 tHSYS System Inputs Hold After TCK High tTRSTW TRST Pulse Width Switching Characteristics tDTDO TDO Delay from TCK Low 2 tDSYS System Outputs Delay After TCK Low 1 2 Min tCK 5 6 7 18 4tCK tTCK TCK tHTAP TMS TDI tDTDO TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 37. IEEE 1149.1 JTAG Test Access Port Rev. E | Page 47 of 60 | July 2009 Unit ns ns ns ns ns ns 7 tCK ÷ 2 + 7 System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0. System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, EMU. tSTAP Max ns ns ADSP-21367/ADSP-21368/ADSP-21369 OUTPUT DRIVE CURRENTS TEST CONDITIONS Figure 38 shows typical I-V characteristics for the output drivers and Figure 39 shows typical I-V characteristics for the SDCLK output drivers. The curves represent the current drive capability of the output drivers as a function of output voltage. The ac signal specifications (timing parameters) appear in Table 14 on Page 23 through Table 42 on Page 47. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 40. Timing is measured on signals when they cross the 1.5 V level as described in Figure 40. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V. 40 VOH SOURCE (VDDEXT) CURRENT (mA) 30 3.3V, 25°C 20 3.47V, -45°C 10 3.11V, 125°C 0 -10 1.5V 1.5V 3.11V, 125°C 3.11V, 105°C -20 Figure 40. Voltage Reference Levels for AC Measurements 3.3V, 25°C VOL -30 CAPACITIVE LOADING 3.47V, -45°C -40 0 0.5 1.0 1.5 2.0 2.5 SWEEP (VDDEXT) VOLTAGE (V) 3.0 3.5 Output delays and holds are based on standard capacitive loads of an average of 6 pF on all pins (see Figure 41). Figure 46 and Figure 47 show graphically how output delays and holds vary with load capacitance. The graphs of Figure 42 through Figure 47 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) vs. Load Capacitance. Figure 38. Typical Drive at Junction Temperature 75 VOH 60 SOURCE (VDDEXT) CURRENT (mA) INPUT OR OUTPUT 3.11V, 105°C 3 .47 V, - 45 °C 45 3.3 V, 25 °C 30 TESTER PIN ELECTRONICS 3 .1 3 V, 12 5 °C 15 3.1 3V, 1 05 °C 0 1.5V T1 - 15 3.1 3V, 1 25 °C - 30 DUT OUTPUT 70: 3 .1 3 V, 10 5° C - 45 - 60 3.3 V, 2 5°C - 75 3 .47 V, - 4 5°C ZO = 50:(impedance) TD = 4.04 r 1.18 ns 50: 0.5pF 4pF 2pF VOL - 90 -105 0 45: 400: 0.5 1.0 1.5 2.0 2.5 3.0 3.5 S W EE P (V D D EX T ) VOL TAG E (V ) Figure 39. SDCLK1–0 Drive at Junction Temperature NOTES: THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES. Figure 41. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Rev. E | Page 48 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 12 10 RISE RISE 8 RISE AND FALL TIMES (ns) RISE AND FALL TIMES (ns) 10 FALL y = 0.049x + 1.5105 8 6 y = 0.0482x + 1.4604 4 2 0 y = 0.0372x + 0.228 6 FALL y = 0.0277x + 0.369 4 2 0 0 50 100 150 200 250 0 50 LOAD CAPACITANCE (pF) 100 150 200 250 LOAD CAPACITANCE (pF) Figure 42. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min) Figure 44. SDCLK Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min) 12 10 RISE y = 0.0467x + 1.6323 8 RISE RISE AND FALL TIMES (ns) RISE AND FALL TIMES (ns) 10 FALL 8 6 y = 0.045x + 1.524 4 y = 0.0364x + 0.197 6 FALL 4 y = 0.0259x + 0.311 2 2 0 0 0 50 100 150 200 250 0 LOAD CAPACITANCE (pF) 50 100 150 200 LOAD CAPACITANCE (pF) Figure 43. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Max) Figure 45. SDCLK Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Max) Rev. E | Page 49 of 60 | July 2009 250 ADSP-21367/ADSP-21368/ADSP-21369 To determine the junction temperature of the device while on the application PCB, use: 10 T J = T TOP + ( Ψ JT × P D ) OUTPUT DELAY OR HOLD (ns) 8 where: 6 y = 0.0488x - 1.5923 TJ = junction temperature (°C) 4 TTOP = case temperature (°C) measured at the top center of the package 2 ΨJT = junction-to-top (of package) characterization parameter is 0 the typical value from Table 43 and Table 44. -2 PD = power dissipation (see EE Note EE-299) -4 0 50 100 150 200 LOAD CAPACITANCE (pF) Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approximation of TJ by the equation: T J = T A + ( θ JA × P D ) Figure 46. Typical Output Delay or Hold vs. Load Capacitance (at Junction Temperature) where: TA = ambient temperature (°C) Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required. This is only applicable when a heat sink is used. 8 RISE AND FALL TIMES (ns) 6 y = 0.0256x - 0.021 Values of θJB are provided for package comparison and PCB design considerations. The thermal characteristics values provided in Table 43 and Table 44 are modeled values @ 2 W. 4 Table 43. Thermal Characteristics for 256-Ball BGA_ED 2 0 -2 0 50 100 150 200 LOAD CAPACITANCE (pF) Figure 47. SDCLK Typical Output Delay or Hold vs. Load Capacitance (at Junction Temperature) Parameter θJA θJMA θJMA θJC θJB ΨJT ΨJMT ΨJMT Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 12.5 10.6 9.9 0.7 5.3 0.3 0.3 0.3 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W THERMAL CHARACTERISTICS The ADSP-21367/ADSP-21368/ADSP-21369 processors are rated for performance over the temperature range specified in Operating Conditions on Page 16. Table 43 and Table 44 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-toboard measurement complies with JESD51-8. Test board design complies with JEDEC standards JESD51-9 (BGA_ED) and JESD51-8 (LQFP_EP). The junction-to-case measurement complies with MIL-STD-883. All measurements use a 2S2P JEDEC test board. The LQFP-EP package requires thermal trace squares and thermal vias, to an embedded ground plane, in the PCB. Refer to JEDEC standard JESD51-5 for more information. Rev. E Table 44. Thermal Characteristics for 208-Lead LQFP EPAD (With Exposed Pad Soldered to PCB) Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT ΨJB ΨJMB ΨJMB | Page 50 of 60 | July 2009 Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 17.1 14.7 14.0 9.6 0.23 0.39 0.45 11.5 11.2 11.0 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W ADSP-21367/ADSP-21368/ADSP-21369 256-BALL BGA_ED PINOUT The following table shows the ADSP-2136x’s pin names and their default function after reset (in parentheses). Table 45. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 E01 E02 E03 E04 E17 E18 E19 E20 J01 J02 J03 J04 J17 J18 J19 J20 Signal NC TDI TMS CLK_CFG0 CLK_CFG1 EMU DAI_P04 (SFS0) DAI_P01 (SD0A) DPI_P14 (TIMER1) DPI_P12 (TWI_CLK) DPI_P10 (UART0RX) DPI_P09 (UART0TX) DPI_P07 (SPIFLG2) DPI_P06 (SPIFLG1) DPI_P03 (SPICLK) DPI_P02 (SPIMISO) RESETOUT DATA31 NC NC DAI_P11 (SD3A) DAI_P08 (SFS1) VDDINT VDDINT GND GND DATA25 DATA23 DAI_P19 (SCLK5) DAI_P18 (SD5B) GND GND GND GND GND/ID12 DATA17 Ball No. B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 F01 F02 F03 F04 F17 F18 F19 F20 K01 K02 K03 K04 K17 K18 K19 K20 Signal DAI_P05 (SD1A) SDCLK11 TRST TCK BOOT_CFG0 BOOT_CFG1 TDO DAI_P03 (SCLK0) DAI_P02 (SD0B) DPI_P13 (TIMER0) DPI_P11 (TWI_DATA) DPI_P08 (SPIFLG3) DPI_P05 (SPIFLG0) DPI_P04 (SPIDS) DPI_P01 (SPIMOSI) RESET DATA30 DATA29 DATA28 NC DAI_P14 (SFS3) DAI_P12 (SD3B) GND GND VDDEXT GND GND/ID22 DATA21 FLAG0 DAI_P20 (SFS5) GND VDDEXT VDDINT VDDINT GND/ID02 DATA16 Rev. E Ball No. C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 G01 G02 G03 G04 G17 G18 G19 G20 L01 L02 L03 L04 L17 L18 L19 L20 | Page 51 of 60 | July 2009 Signal DAI_P09 (SD2A) DAI_P07 (SCLK1) GND VDDEXT GND GND VDDINT GND GND VDDINT GND GND VDDINT GND GND VDDINT VDDINT VDDINT DATA27 NC/RPBA2 DAI_P15 (SD4A) DAI_P13 (SCLK3) GND VDDEXT VDDINT VDDINT DATA22 DATA20 FLAG2 FLAG1 VDDINT VDDINT VDDINT VDDINT DATA15 DATA14 Ball No. D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 H01 H02 H03 H04 H17 H18 H19 H20 M01 M02 M03 M04 M17 M18 M19 M20 Signal DAI_P10 (SD2B) DAI_P06 (SD1B) GND VDDEXT GND VDDEXT VDDINT GND VDDEXT VDDINT GND VDDEXT VDDINT GND VDDEXT GND VDDEXT GND DATA26 DATA24 DAI_P17 (SD5A) DAI_P16 (SD4B) VDDINT VDDINT VDDEXT GND DATA19 DATA18 ACK FLAG3 GND GND VDDEXT GND DATA12 DATA13 ADSP-21367/ADSP-21368/ADSP-21369 Table 45. 256-Ball BGA_ED Pin Assignment (Numerically by Ball Number) (Continued) Ball No. N01 N02 N03 N04 N17 N18 N19 N20 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 1 2 Signal RD SDCLK0 GND VDDEXT GND GND DATA11 DATA10 MS0 MS1 VDDINT GND VDDEXT GND VDDEXT VDDINT VDDEXT GND VDDEXT VDDINT VDDEXT VDDEXT VDDINT VDDEXT VDDINT VDDINT DATA0 DATA2 Ball No. P01 P02 P03 P04 P17 P18 P19 P20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 Signal SDA10 WR VDDINT VDDINT VDDINT VDDINT DATA8 DATA9 ADDR22 ADDR23 VDDINT GND GND GND GND VDDINT GND GND GND VDDINT VDDEXT GND VDDINT GND GND GND DATA1 DATA3 Ball No. R01 R02 R03 R04 R17 R18 R19 R20 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Signal SDWE SDRAS GND GND VDDEXT GND DATA6 DATA7 GND ADDR21 ADDR19 ADDR20 ADDR17 ADDR16 ADDR15 ADDR14 AVDD AVSS ADDR13 ADDR12 ADDR10 ADDR8 ADDR5 ADDR4 ADDR1 ADDR2 ADDR0 NC The SDCLK1 signal is only available on the SBGA package. SDCLK1 is not available on the LQFP_EP package. Applies to ADSP-21368 models only. Rev. E | Page 52 of 60 | July 2009 Ball No. T01 T02 T03 T04 T17 T18 T19 T20 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal SDCKE SDCAS GND VDDEXT GND GND DATA5 DATA4 GND NC NC ADDR18 NC/BR12 NC/BR22 XTAL CLKIN NC NC NC/BR32 NC/BR42 ADDR11 ADDR9 ADDR7 ADDR6 ADDR3 GND GND NC ADSP-21367/ADSP-21368/ADSP-21369 Figure 48 shows the bottom view of the BGA_ED ball configuration. Figure 49 shows the top view of the BGA_ED ball configuration. 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 2 1 1 KEY I/O SIGNALS 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 A A B C D E F G H J K L M N P R T U V W Y BOTTOM VIEW VDDINT 4 3 B C D E F G H J TOP VIEW K L M N P R T U V W Y KEY VDDEXT GND AVDD AVSS VDDINT NO CONNECT I/O SIGNALS Figure 48. 256-Ball BGA_ED Ball Configuration (Bottom View) Rev. E VDDEXT GND AVDD AVSS NO CONNECT Figure 49. 256-Ball BGA_ED Ball Configuration (Top View) | Page 53 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 208-LEAD LQFP_EP PINOUT The following table shows the ADSP-2136x’s pin names and their default function after reset (in parentheses). Table 46. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) Lead No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Signal Lead No. Signal VDDINT DATA28 DATA27 GND VDDEXT DATA26 DATA25 DATA24 DATA23 GND VDDINT DATA22 DATA21 DATA20 VDDEXT GND DATA19 DATA18 VDDINT GND DATA17 VDDINT GND VDDINT GND DATA16 DATA15 DATA14 DATA13 DATA12 VDDEXT GND VDDINT GND DATA11 DATA10 DATA9 DATA8 DATA7 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 VDDINT DATA4 DATA5 DATA2 DATA3 DATA0 DATA1 VDDEXT GND VDDINT VDDINT GND VDDEXT ADDR0 ADDR2 ADDR1 ADDR4 ADDR3 ADDR5 GND VDDINT GND VDDEXT ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 GND VDDINT GND VDDEXT ADDR11 ADDR12 ADDR13 GND VDDINT AVSS AVDD Lead No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Rev. E Signal VDDEXT GND VDDINT ADDR14 GND VDDEXT ADDR15 ADDR16 ADDR17 ADDR18 GND VDDEXT ADDR19 ADDR20 ADDR21 ADDR23 ADDR22 MS1 MS0 VDDINT VDDINT GND VDDEXT SDCAS SDRAS SDCKE SDWE WR SDA10 GND VDDEXT SDCLK0 GND VDDINT RD ACK FLAG3 FLAG2 FLAG1 Lead No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 Signal VDDINT GND VDDEXT DAI_P19 (SCLK5) DAI_P18 (SD5B) DAI_P17 (SD5A) DAI_P16 (SD4B) DAI_P15 (SD4A) DAI_P14 (SFS3) DAI_P13 (SCLK3) DAI_P12 (SD3B) VDDINT VDDEXT GND VDDINT GND DAI_P11 (SD3A) DAI_P10 (SD2B) DAI_P08 (SFS1) DAI_P09 (SD2A) DAI_P06 (SD1B) DAI_P07 (SCLK1) DAI_P05 (SD1A) VDDEXT GND VDDINT GND VDDINT GND VDDINT VDDINT VDDINT GND VDDINT VDDINT VDDINT TDI TRST TCK | Page 54 of 60 | July 2009 Lead No. 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 Signal CLK_CFG0 BOOT_CFG0 CLK_CFG1 EMU BOOT_CFG1 TDO DAI_P04 (SFS0) DAI_P02 (SD0B) DAI_P03 (SCLK0) DAI_P01 (SD0A) VDDEXT GND VDDINT GND DPI_P14 (TIMER1) DPI_P13 (TIMER0) DPI_P12 (TWI_CLK) DPI_P11 (TWI_DATA) DPI_P10 (UART0RX) DPI_P09 (UART0TX) DPI_P08 (SPIFLG3) DPI_P07 (SPIFLG2) VDDEXT GND VDDINT GND DPI_P06 (SPIFLG1) DPI_P05 (SPIFLG0) DPI_P04 (SPIDS) DPI_P03 (SPICLK) DPI_P01 (SPIMOSI) DPI_P02 (SPIMISO) RESETOUT RESET VDDEXT GND DATA30 DATA31 DATA29 ADSP-21367/ADSP-21368/ADSP-21369 Table 46. 208-Lead LQFP_EP Pin Assignment (Numerically by Lead Number) (Continued) Lead No. 40 41 42 Signal Lead No. Signal DATA6 VDDEXT GND 82 83 84 GND CLKIN XTAL Lead No. 124 125 126 Rev. E Signal Lead No. FLAG0 166 DAI_P20 (SFS5) 167 GND 168 Signal GND VDDINT TMS | Page 55 of 60 | July 2009 Lead No. 208 Signal VDDINT ADSP-21367/ADSP-21368/ADSP-21369 PACKAGE DIMENSIONS The ADSP-21367/ADSP-21368/ADSP-21369 processors are available in 256-ball RoHS compliant and leaded BGA_ED, and 208-lead RoHS compliant LQFP_EP packages. 0.75 0.60 0.45 1.00 REF 30.20 30.00 SQ 29.80 1.60 MAX 25.50 REF 28.10 28.00 SQ 27.90 8.712 REF 157 208 156 1 157 208 156 1 PIN 1 SEATING PLANE TOP VIEW 1.45 1.40 1.35 8.890 REF EXPOSED PAD (PINS DOWN) 0.20 0.15 0.09 7° 3.5° 0° BOTTOM VIEW 105 104 52 53 VIEW A ROTATED 90° CCW (PINS UP) 105 104 VIEW A 52 53 0.50 BSC LEAD PITCH 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BJB-HD NOTE: THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO VSS. THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A VSS PCB LAND THAT IS THE SAME SIZE AS THE EXPOSED PAD. THE VSS PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE VSS PLANE IN THE PCB WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE. Figure 50. 208-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] (SW-208-1) Dimensions shown in millimeters Rev. E | Page 56 of 60 | July 2009 100907 A 0.15 0.10 0.05 0.08 COPLANARITY ADSP-21367/ADSP-21368/ADSP-21369 A1 CORNER INDEX AREA 27.00 BSC SQ 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y BALL A1 INDICATOR 24.13 BSC SQ TOP VIEW BOTTOM VIEW 1.27 BSC DETAIL A 1.00 0.80 0.60 DETAIL A 1.70 MAX 0.70 0.60 0.50 0.10 MIN 0.90 0.75 0.60 BALL DIAMETER 0.25 MIN (4 ) COPLANARITY 0.20 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-192-BAL-2 Figure 51. 256-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] (BP-256) Dimension shown in millimeters SURFACE-MOUNT DESIGN Table 47 is provided as an aide to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 47. BGA_ED Data for Use with Surface-Mount Design Package 256-Lead Ball Grid Array BGA_ED (BP-256) Ball Attach Type Solder Mask Defined (SMD) Rev. E Solder Mask Opening 0.63 mm | Page 57 of 60 | July 2009 Ball Pad Size 0.73 mm ADSP-21367/ADSP-21368/ADSP-21369 AUTOMOTIVE PRODUCTS An ADSP-21369 model is available for automotive applications with controlled manufacturing. Note that this special model may have specifications that differ from the general release models. The automotive grade product shown in Table 48 is available for use in automotive applications. Contact your local ADI account representative or authorized ADI product distributor for specific product ordering information. Note that all automotive products are RoHS compliant. Table 48. Automotive Products 1 Model Temperature Range1 Instruction Rate On-Chip SRAM ROM Package Description Package Option AD21369WBSWZ1xx –40°C to +85°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 Temperature Range1 Instruction Rate On-Chip SRAM ROM Package Description Package Option 0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 Referenced temperature is ambient temperature. ORDERING GUIDE Model ADSP-21367KBP-2A2 2, 3 0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21367BBP-2A2 –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21367BBPZ-2A2, 3 –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21367KBPZ-3A2, 3 0°C to +70°C 400 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21367KSWZ-1A 2, 3 0°C to +70°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21367KSWZ-2A 2, 3 0°C to +70°C 333 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21367KSWZ-4A2, 3 0°C to +70°C 350 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 2, 3 0°C to +70°C 366 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 –40°C to +85°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21367KBPZ-2A ADSP-21367KSWZ-5A ADSP-21367BSWZ-1A2, 3 ADSP-21368KBP-2A 0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21368KBPZ-2A3 0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21368BBP-2A –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 0°C to +70°C 400 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21368BBPZ-2A 3 ADSP-21368KBPZ-3A3 ADSP-21369KBP-2A 0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21369KBPZ-2A3 0°C to +70°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21369BBP-2A –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21369BBPZ-2A2 –40°C to +85°C 333 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21369KBPZ-3A3 0°C to +70°C 400 MHz 2M bit 6M bit 256-Ball BGA_ED BP-256 ADSP-21369KSWZ-1A3 0°C to +70°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21369KSWZ-2A 3 0°C to +70°C 333 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21369KSWZ-4A 3 0°C to +70°C 350 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21369KSWZ-5A3 0°C to +70°C 366 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 3 –40°C to +85°C 266 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21369BSWZ-2A3 –40°C to +85°C 333 MHz 2M bit 6M bit 208-Lead LQFP_EP SW-208-1 ADSP-21369BSWZ-1A 1 Referenced temperature is ambient temperature. Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC. 3 Z = RoHS Compliant Part. 2 Rev. E | Page 58 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 Rev. E | Page 59 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05267-0-7/09(E) Rev. E | Page 60 of 60 | July 2009