Cypress CY62146EV30LL-45BVXI 4-mbit (256k x 16) static ram Datasheet

CY62146EV30 MoBL®
4-Mbit (256 K × 16) Static RAM
4-Mbit (256 K × 16) Static RAM
Features
advanced circuit design designed to provide an ultra low active
current. Ultra low active current is ideal for providing More
Battery Life (MoBL®) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that significantly reduces power consumption by 80
percent when addresses are not toggling.The device can also be
put into standby mode reducing power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
■
Very high speed: 45 ns
■
Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
■
Wide voltage range: 2.20 V to 3.60 V
■
Pin compatible with CY62146DV30
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
■
Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in a Pb-free 48-ball very fine ball grid array (VFBGA)
and 44-pin TSOP II Packages
To write to the device, take Chip Enable (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from the I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
Functional Description
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features an
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
Cypress Semiconductor Corporation
Document Number: 38-05567 Rev. *H
•
BHE
WE
CE
OE
BLE
A17
A16
A15
A13
A14
A12
A11
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 10, 2013
CY62146EV30 MoBL®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document Number: 38-05567 Rev. *H
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC Solutions ......................................................... 18
Page 2 of 18
CY62146EV30 MoBL®
Pin Configurations
Figure 1. 48-ball VFBGA pinout [1, 2]
Figure 2. 44-pin TSOP II pinout [1]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS I/O11
A17
A7
VCC
D
VCC
NC
A16
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O12
I/O3
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
Product Portfolio
Product
CY62146EV30LL
Range
Industrial /
Automotive-A
VCC Range (V)
Min
Typ [3]
Max
2.2
3.0
3.6
Speed
(ns)
45
Power Dissipation
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2 (A)
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
2
2.5
15
20
1
7
Notes
1. NC pins are not connected on the die.
2. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 38-05567 Rev. *H
Page 3 of 18
CY62146EV30 MoBL®
DC input voltage [4, 5] ....... –0.3 V to 3.9 V (VCC max + 0.3 V)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage to ground
potential .......................... –0.3 V to + 3.9 V (VCCmax + 0.3 V)
DC voltage applied to outputs
in High-Z state [4, 5] ............ –0.3 V to 3.9 V (VCCmax + 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... >2001 V
Latch-up Current .................................................... >200 mA
Operating Range
Device
CY62146EV30
Range
Ambient
Temperature
VCC [6]
Industrial / –40 °C to +85 °C 2.2 V to 3.6 V
Automotive-A
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output high voltage
Output low voltage
Input high voltage
Input LOW Voltage
Test Conditions
45 ns (Ind’l/Auto-A)
Min
Typ [7]
Max
Unit
IOH = –0.1 mA
2.0
–
–
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
–
–
V
IOL = 0.1 mA
–
–
0.4
V
IOL = 2.1 mA, VCC > 2.70 V
–
–
0.4
V
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3
V
VCC= 2.7 V to 3.6 V
2.2
–
VCC + 0.3
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
VCC= 2.7 V to 3.6 V
–0.3
–
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC, Output disabled
–1
–
+1
A
ICC
VCC operating supply current
f = fmax = 1/tRC
mA
f = 1 MHz
VCC = VCC(max),
IOUT = 0 mA
CMOS levels
–
15
20
–
2
2.5
ISB1
Automatic CE power down
current – CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (Address and data only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60 V
–
1
7
A
ISB2 [8]
Automatic CE power down
current – CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–
1
7
A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 38-05567 Rev. *H
Page 4 of 18
CY62146EV30 MoBL®
Capacitance
Parameter [9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
10
pF
10
pF
VFBGA
TSOP II
Unit
75
77
C/W
10
13
C/W
TA = 25 C, f = 1 MHz, VCC = VCC(typ)
Thermal Resistance
Parameter [9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
VCC
Output
R2
Including
JIG and
Scope
90%
10%
90%
10%
30 pF
GND
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: Thevenin Equivalent
Output
Parameters
All Input Pulses
VCC
2.50 V
RTH
V
3.0 V
Unit
R1
16667
1103

R2
15385
1554

RTH
8000
645

VTH
1.20
1.75
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05567 Rev. *H
Page 5 of 18
CY62146EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Typ [10]
Min
Max
Unit
VDR
VCC for data retention
1.5
–
–
V
ICCDR [11]
Data retention current
VCC = 1.5 V,
Industrial /
CE > VCC – 0.2 V,
Automotive-A
VIN > VCC – 0.2 V or
VIN < 0.2 V
–
0.8
7
A
tCDR [12]
Chip deselect to data retention
time
–
0
–
–
ns
tR [13]
Operation recovery time
–
45
–
–
ns
Data Retention Waveform
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1/ ISB2 / ICCDR spec. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 38-05567 Rev. *H
Page 6 of 18
CY62146EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter
[14, 15]
Description
45 ns
(Industrial /
Automotive-A)
Min
Unit
Max
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
[16]
5
–
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z
tLZCE
CE LOW to Low-Z
tHZCE
[16, 17]
[16]
CE HIGH to High-Z
[16, 17]
–
18
ns
10
–
ns
–
18
ns
–
ns
tPU
CE LOW to power up
0
tPD
CE HIGH to power down
–
45
ns
BLE / BHE LOW to data valid
–
22
ns
[16]
5
–
ns
–
18
ns
tDBE
tLZBE
BLE / BHE LOW to Low-Z
tHZBE
Write Cycle
BLE / BHE HIGH to High-Z
[16, 17]
[18]
tWC
Write cycle time
45
–
ns
tSCE
CE LOW to write end
Address setup to write end
35
–
ns
tAW
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
–
ns
tSD
BLE / BHE LOW to write end
Data setup to write end
35
25
–
ns
tHD
Data hold from write end
0
–
ns
–
18
ns
10
–
ns
tBW
tHZWE
tLZWE
WE LOW to High-Z
[16, 17]
WE HIGH to Low-Z
[16]
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 3 on page 5.
15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
18. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document Number: 38-05567 Rev. *H
Page 7 of 18
CY62146EV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle 1 (Address Transition Controlled) [19, 20]
tRC
ADDRESS
tOHA
DATA I/O
tAA
PREVIOUS DATA VALID
DATAOUT VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [20, 21]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA I/O
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATAOUT VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes
19. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 38-05567 Rev. *H
Page 8 of 18
CY62146EV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [22, 23, 24]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 25
tHD
DATAIN
tHZOE
Figure 8. Write Cycle No. 2 (CE Controlled) [22, 23, 24]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 25
tHZOE
Notes
22. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
23. Data I/O is high impedance if OE = VIH.
24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
25. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05567 Rev. *H
Page 9 of 18
CY62146EV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [26]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA I/O
NOTE 27
tHD
DATAIN
tLZWE
tHZWE
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [26]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 27
tSD
tHD
DATAIN
tLZWE
Notes
26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
27. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05567 Rev. *H
Page 10 of 18
CY62146EV30 MoBL®
Truth Table
CE [28]
WE
OE
BHE
BLE
H
X
X
X
X
Inputs/Outputs
High-Z
Mode
Deselect/power-down
Power
Standby (ISB)
L
X
X
H
H
High-Z
Output disabled
Active (ICC)
L
H
L
L
L
Data out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High-Z
Output disabled
Active (ICC)
L
H
H
H
L
High-Z
Output disabled
Active (ICC)
L
H
H
L
H
High-Z
Output disabled
Active (ICC)
L
L
X
L
L
Data in (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data in (I/O0–I/O7);
I/O8–I/O15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
Note
28. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 38-05567 Rev. *H
Page 11 of 18
CY62146EV30 MoBL®
Ordering Information
Speed
(ns)
45
Ordering Code
Package
Diagram
Package Type
CY62146EV30LL-45BVXI
51-85150 48-ball VFBGA (Pb-free)
CY62146EV30LL-45ZSXI
51-85087 44-pin TSOP II (Pb-free)
CY62146EV30LL-45ZSXA
51-85087 44-pin TSOP II (Pb-free)
Operating
Range
Industrial
Automotive-A
Please contact your local Cypress sales representative for availability of other parts
Ordering Code Definitions
CY 621 4
6
E V30 LL - 45 XX
X
X
Temperature Grade: X = I or A
I = Industrial; A = Automotive
Pb-free
Package Type: XX = BV or ZS
BV = VFBGA; ZS = TSOP II
Speed Grade: 45 ns
LL = Low Power
Voltage Range = 3 V typical
Process Technology: E = 90 nm
Buswidth: 6 = × 16
Density: 4 = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05567 Rev. *H
Page 12 of 18
CY62146EV30 MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 38-05567 Rev. *H
Page 13 of 18
CY62146EV30 MoBL®
Package Diagrams (continued)
Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05567 Rev. *H
Page 14 of 18
CY62146EV30 MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CMOS
Complementary Metal Oxide Semiconductor
MHz
megahertz
CE
Chip Enable
A
microampere
I/O
Input/Output
mA
milliampere
OE
Output Enable
ns
nanosecond
SRAM
Static Random Access Memory

ohm
TSOP
Thin Small Outline Package
pF
picofarad
VFBGA
Very Fine-Pitch Ball Gird Array
V
volt
WE
Write Enable
W
watt
Document Number: 38-05567 Rev. *H
Symbol
Unit of Measure
Page 15 of 18
CY62146EV30 MoBL®
Document History Page
Document Title: CY62146EV30 MoBL®, 4-Mbit (256 K × 16) Static RAM
Document Number: 38-05567
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
223225
AJU
See ECN
New data sheet.
*A
247373
SYT
See ECN
Changed Advance Information to Preliminary
Moved Product Portfolio to Page 2
Changed VCC stabilization time in footnote #8 from 100 s to 200 s
Removed Footnote #14(tLZBE) from Previous revision
Changed ICCDR from 2.0 A to 2.5 A
Changed typo in Data Retention Characteristics (tR) from 100 s to tRC ns
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to
18 ns for 45 ns Speed Bin
Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns
for 45 ns Speed Bin
Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns
Speed Bin
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns
Speed Bin
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Changed tDBE from 15 to 18 ns for 35 ns Speed Bin
Changed Ordering Information to include Pb-Free Packages
*B
414807
ZSD
See ECN
Changed from Preliminary information to Final
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62146EV30
Changed ball E3 from DNU to NC
Removed the redundant foot note on DNU.
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA
to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ values from 0.7 A to 1 A and Max values from
2.5 A to 7 A.
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed ICCDR from 2.5 A to 7 A.
Added ICCDR typical value.
Changed tLZOE from 3 ns to 5 ns
Changed tLZCE and tLZWE from 6 ns to 10 ns
Changed tLZBE from 6 ns to 5 ns
Changed tHZCE from 22 ns to 18 ns
Changed tPWE from 30 ns to 35 ns.
Changed tSD from 22 ns to 25 ns.
Updated the package diagram 48-ball VFBGA from *B to *D
Updated the ordering information table and replaced the Package Name
column with Package Diagram.
*C
925501
VKN
See ECN
Added footnote #8 related to ISB2 and ICCDR
Added footnote #12 related AC timing parameters
*D
2678796
VKN/PYRS
03/25/2009
*E
2944332
06/04/2010
VKN
Document Number: 38-05567 Rev. *H
Description of Change
Added Automotive-A information
Added Contents
Removed byte enable from footnote #2 in Electrical Characteristics
Added footnote related to chip enable in Truth Table
Updated Package Diagrams
Updated links in Sales, Solutions, and Legal Information
Page 16 of 18
CY62146EV30 MoBL®
Document History Page (continued)
Document Title: CY62146EV30 MoBL®, 4-Mbit (256 K × 16) Static RAM
Document Number: 38-05567
Rev.
ECN No.
Orig. of
Change
Submission
Date
*F
3109050
12/13/2010
PRAS
Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
*G
3302915
07/14/2011
RAME
Updated as per template. Added Units of Measure table.
Updated all the notes.
Ordering Code Definition updated.
Removed the references of AN1064 SRAM system guidelines from the
datasheet.
*H
3961126
04/10/2013
TAVA
Updated Package Diagrams:
spec 51-85150 – Changed revision from *F to *H.
spec 51-85087 – Changed revision from *C to *E.
Description of Change
Completing Sunset Review.
Document Number: 38-05567 Rev. *H
Page 17 of 18
CY62146EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004–2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05567 Rev. *H
Revised April 10, 2013
Page 18 of 18
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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