ATMEL ATMEGA165P 8-bit microcontroller with 16k bytes in-system programmable flash Datasheet

Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
•
•
•
•
•
•
•
•
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
Non-volatile Program and Data Memories
– 16K bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 512 bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 1K byte Internal SRAM
– Programming Lock for Software Security
JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
I/O and Packages
– 54 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
Speed Grade:
– ATmega165PV: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V
– ATmega165P: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V
Temperature range:
– -40°C to 85°C Industrial
Ultra-Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 330 µA
32 kHz, 1.8V: 10 µA (including Oscillator)
– Power-down Mode:
0.1 µA at 1.8V
– Power-save Mode:
0.6 µA at 1.8V(including 32 kHz RTC)
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega165P
ATmega165PV
Preliminary
Summary
8019HS–AVR–11/06
1. Pin Configurations
DNC
1
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC
PA0
PA1
PA2
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Pinout ATmega165P
64
Figure 1-1.
48 PA3
(RXD/PCINT0) PE0
2
(TXD/PCINT1) PE1
3
46 PA5
(XCK/AIN0/PCINT2) PE2
4
45 PA6
(AIN1/PCINT3) PE3
5
44 PA7
(USCK/SCL/PCINT4) PE4
6
43 PG2
(DI/SDA/PCINT5) PE5
7
42 PC7
(DO/PCINT6) PE6
8
41 PC6
(CLKO/PCINT7) PE7
9
40 PC5
(SS/PCINT8) PB0
10
39 PC4
(SCK/PCINT9) PB1
11
38 PC3
(MOSI/PCINT10) PB2
12
37 PC2
47 PA4
INDEX CORNER
Note:
1.1
26
27
28
29
(INT0) PD1
PD2
PD3
PD4
PD7 32
25
(ICP1) PD0
PD6 31
24
(TOSC1) XTAL1
PD5 30
23
(TOSC2) XTAL2
33 PG0
22
34 PG1
16
VCC 21
15
(OC1B/PCINT14) PB6
GND
(OC1A/PCINT13) PB5
(T0) PG4 19
35 PC0
RESET/PG5 20
36 PC1
(T1) PG3 18
13
14
(OC2A/PCINT15) PB7 17
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If
the center pad is left unconnected, the package might loosen from the board.
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
2
ATmega165P
8019HS–AVR–11/06
ATmega165P
2. Overview
The ATmega165P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega165P achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.
Block Diagram
Block Diagram
PF0 - PF7
PA0 - PA7
XTAL2
Figure 2-1.
XTAL1
2.1
PC0 - PC7
VCC
GND
PORTA DRIVERS
PORTF DRIVERS
DATA DIR.
REG. PORTF
DATA REGISTER
PORTF
PORTC DRIVERS
DATA DIR.
REG. PORTA
DATA REGISTER
PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
CALIB. OSC
INTERNAL
OSCILLATOR
ADC
AREF
OSCILLATOR
JTAG TAP
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
ON-CHIP DEBUG
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
BOUNDARYSCAN
INSTRUCTION
REGISTER
TIMING AND
CONTROL
TIMER/
COUNTERS
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
DECODER
CONTROL
LINES
+
-
INTERRUPT
UNIT
ALU
EEPROM
STATUS
REGISTER
AVR CPU
ANALOG
COMPARATOR
Z
Y
RESET
X
PROGRAMMING
LOGIC
USART
UNIVERSAL
SERIAL INTERFACE
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
PORTE DRIVERS
PE0 - PE7
SPI
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
PORTB DRIVERS
PB0 - PB7
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
DATA REG.
PORTG
DATA DIR.
REG. PORTG
PORTD DRIVERS
PORTG DRIVERS
PD0 - PD7
PG0 - PG4
3
8019HS–AVR–11/06
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega165P provides the following features: 16K bytes of In-System Programmable Flash
with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 53 general purpose I/O
lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip
Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start
Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal
Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator,
disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode,
the asynchronous timer continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions.
In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega165P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega165P AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
4
ATmega165P
8019HS–AVR–11/06
ATmega165P
2.2
2.2.1
Pin Descriptions
VCC
Digital supply voltage.
2.2.2
GND
Ground.
2.2.3
Port A (PA7:PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
2.2.4
Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the ATmega165P as listed on
”Alternate Functions of Port B” on page 72.
2.2.5
Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
2.2.6
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega165P as listed on
”Alternate Functions of Port D” on page 75.
2.2.7
Port E (PE7:PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
5
8019HS–AVR–11/06
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the ATmega165P as listed on
”Alternate Functions of Port E” on page 76.
2.2.8
Port F (PF7:PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface, see ”Alternate Functions of Port F” on
page 79
2.2.9
Port G (PG5:PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port G also serves the functions of various special features of the ATmega165P as listed on
page 81.
2.2.10
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page
46. Shorter pulses are not guaranteed to generate a reset.
2.2.11
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.2.12
XTAL2
Output from the inverting Oscillator amplifier.
2.2.13
AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
2.2.14
AREF
This is the analog reference pin for the A/D Converter.
6
ATmega165P
8019HS–AVR–11/06
ATmega165P
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
7
8019HS–AVR–11/06
4. Register Summary
8
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0xFF)
Reserved
–
–
–
–
–
–
–
–
(0xFE)
Reserved
–
–
–
–
–
–
–
–
(0xFD)
Reserved
–
–
–
–
–
–
–
–
(0xFC)
Reserved
–
–
–
–
–
–
–
–
(0xFB)
Reserved
–
–
–
–
–
–
–
–
(0xFA)
Reserved
–
–
–
–
–
–
–
–
(0xF9)
Reserved
–
–
–
–
–
–
–
–
(0xF8)
Reserved
–
–
–
–
–
–
–
–
(0xF7)
Reserved
–
–
–
–
–
–
–
–
(0xF6)
Reserved
–
–
–
–
–
–
–
–
(0xF5)
Reserved
–
–
–
–
–
–
–
–
(0xF4)
Reserved
–
–
–
–
–
–
–
–
(0xF3)
Reserved
–
–
–
–
–
–
–
–
(0xF2)
Reserved
–
–
–
–
–
–
–
–
(0xF1)
Reserved
–
–
–
–
–
–
–
–
(0xF0)
Reserved
–
–
–
–
–
–
–
–
(0xEF)
Reserved
–
–
–
–
–
–
–
–
(0xEE)
Reserved
–
–
–
–
–
–
–
–
(0xED)
Reserved
–
–
–
–
–
–
–
–
(0xEC)
Reserved
–
–
–
–
–
–
–
–
(0xEB)
Reserved
–
–
–
–
–
–
–
–
(0xEA)
Reserved
–
–
–
–
–
–
–
–
(0xE9)
Reserved
–
–
–
–
–
–
–
–
(0xE8)
Reserved
–
–
–
–
–
–
–
–
(0xE7)
Reserved
–
–
–
–
–
–
–
–
(0xE6)
Reserved
–
–
–
–
–
–
–
–
(0xE5)
Reserved
–
–
–
–
–
–
–
–
(0xE4)
Reserved
–
–
–
–
–
–
–
–
(0xE3)
Reserved
–
–
–
–
–
–
–
–
(0xE2)
Reserved
–
–
–
–
–
–
–
–
(0xE1)
Reserved
–
–
–
–
–
–
–
–
(0xE0)
Reserved
–
–
–
–
–
–
–
–
(0xDF)
Reserved
–
–
–
–
–
–
–
–
(0xDE)
Reserved
–
–
–
–
–
–
–
–
(0xDD)
Reserved
–
–
–
–
–
–
–
–
(0xDC)
Reserved
–
–
–
–
–
–
–
–
(0xDB)
Reserved
–
–
–
–
–
–
–
–
(0xDA)
Reserved
–
–
–
–
–
–
–
–
(0xD9)
Reserved
–
–
–
–
–
–
–
–
(0xD8)
Reserved
–
–
–
–
–
–
–
–
(0xD7)
Reserved
–
–
–
–
–
–
–
–
(0xD6)
Reserved
–
–
–
–
–
–
–
–
(0xD5)
Reserved
–
–
–
–
–
–
–
–
(0xD4)
Reserved
–
–
–
–
–
–
–
–
(0xD3)
Reserved
–
–
–
–
–
–
–
–
(0xD2)
Reserved
–
–
–
–
–
–
–
–
(0xD1)
Reserved
–
–
–
–
–
–
–
–
(0xD0)
Reserved
–
–
–
–
–
–
–
–
(0xCF)
Reserved
–
–
–
–
–
–
–
–
(0xCE)
Reserved
–
–
–
–
–
–
–
–
(0xCD)
Reserved
–
–
–
–
–
–
–
–
(0xCC)
Reserved
–
–
–
–
–
–
–
–
(0xCB)
Reserved
–
–
–
–
–
–
–
–
(0xCA)
Reserved
–
–
–
–
–
–
–
–
(0xC9)
Reserved
–
–
–
–
–
–
–
–
(0xC8)
Reserved
–
–
–
–
–
–
–
–
(0xC7)
Reserved
–
–
–
–
–
–
–
–
(0xC6)
UDR0
(0xC5)
UBRR0H
(0xC4)
UBRR0L
(0xC3)
Reserved
USART0 I/O Data Register
185
USART0 Baud Rate Register High
189
USART0 Baud Rate Register Low
–
–
–
–
–
Page
189
–
–
–
(0xC2)
UCSR0C
–
UMSEL0
UPM01
UPM00
USBS0
UCSZ01
UCSZ00
UCPOL0
185
(0xC1)
UCSR0B
RXCIE0
TXCIE0
UDRIE0
RXEN0
TXEN0
UCSZ02
RXB80
TXB80
185
(0xC0)
UCSR0A
RXC0
TXC0
UDRE0
FE0
DOR0
UPE0
U2X0
MPCM0
185
ATmega165P
8019HS–AVR–11/06
ATmega165P
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0xBF)
Reserved
–
–
–
–
–
–
–
–
Page
(0xBE)
Reserved
–
–
–
–
–
–
–
–
(0xBD)
Reserved
–
–
–
–
–
–
–
–
(0xBC)
Reserved
–
–
–
–
–
–
–
–
(0xBB)
Reserved
–
–
–
–
–
–
–
–
(0xBA)
USIDR
(0xB9)
USISR
USISIF
USIOIF
USIPF
USIDC
USICNT3
USICNT2
USICNT1
USICNT0
202
(0xB8)
USICR
USISIE
USIOIE
USIWM1
USIWM0
USICS1
USICS0
USICLK
USITC
203
(0xB7)
Reserved
–
–
–
–
–
–
–
(0xB6)
ASSR
–
–
–
EXCLK
AS2
TCN2UB
OCR2UB
TCR2UB
(0xB5)
Reserved
–
–
–
–
–
–
–
–
(0xB4)
Reserved
–
–
–
–
–
–
–
–
(0xB3)
OCR2A
Timer/Counter2 Output Compare Register A
150
(0xB2)
TCNT2
Timer/Counter2 (8-bit)
150
(0xB1)
Reserved
–
–
–
–
–
–
–
–
(0xB0)
TCCR2A
FOC2A
WGM20
COM2A1
COM2A0
WGM21
CS22
CS21
CS20
(0xAF)
Reserved
–
–
–
–
–
–
–
–
USI Data Register
202
151
148
(0xAE)
Reserved
–
–
–
–
–
–
–
–
(0xAD)
Reserved
–
–
–
–
–
–
–
–
(0xAC)
Reserved
–
–
–
–
–
–
–
–
(0xAB)
Reserved
–
–
–
–
–
–
–
–
(0xAA)
Reserved
–
–
–
–
–
–
–
–
(0xA9)
Reserved
–
–
–
–
–
–
–
–
(0xA8)
Reserved
–
–
–
–
–
–
–
–
(0xA7)
Reserved
–
–
–
–
–
–
–
–
(0xA6)
Reserved
–
–
–
–
–
–
–
–
(0xA5)
Reserved
–
–
–
–
–
–
–
–
(0xA4)
Reserved
–
–
–
–
–
–
–
–
(0xA3)
Reserved
–
–
–
–
–
–
–
–
(0xA2)
Reserved
–
–
–
–
–
–
–
–
(0xA1)
Reserved
–
–
–
–
–
–
–
–
(0xA0)
Reserved
–
–
–
–
–
–
–
–
(0x9F)
Reserved
–
–
–
–
–
–
–
–
(0x9E)
Reserved
–
–
–
–
–
–
–
–
(0x9D)
Reserved
–
–
–
–
–
–
–
–
(0x9C)
Reserved
–
–
–
–
–
–
–
–
(0x9B)
Reserved
–
–
–
–
–
–
–
–
(0x9A)
Reserved
–
–
–
–
–
–
–
–
(0x99)
Reserved
–
–
–
–
–
–
–
–
(0x98)
Reserved
–
–
–
–
–
–
–
–
(0x97)
Reserved
–
–
–
–
–
–
–
–
(0x96)
Reserved
–
–
–
–
–
–
–
–
(0x95)
Reserved
–
–
–
–
–
–
–
–
(0x94)
Reserved
–
–
–
–
–
–
–
–
(0x93)
Reserved
–
–
–
–
–
–
–
–
(0x92)
Reserved
–
–
–
–
–
–
–
–
(0x91)
Reserved
–
–
–
–
–
–
–
–
(0x90)
Reserved
–
–
–
–
–
–
–
–
(0x8F)
Reserved
–
–
–
–
–
–
–
–
(0x8E)
Reserved
–
–
–
–
–
–
–
–
(0x8D)
Reserved
–
–
–
–
–
–
–
–
(0x8C)
Reserved
–
–
–
–
–
–
–
–
(0x8B)
OCR1BH
Timer/Counter1 - Output Compare Register B High Byte
127
(0x8A)
OCR1BL
Timer/Counter1 - Output Compare Register B Low Byte
127
(0x89)
OCR1AH
Timer/Counter1 - Output Compare Register A High Byte
127
(0x88)
OCR1AL
Timer/Counter1 - Output Compare Register A Low Byte
127
(0x87)
ICR1H
Timer/Counter1 - Input Capture Register High Byte
128
(0x86)
ICR1L
Timer/Counter1 - Input Capture Register Low Byte
128
(0x85)
TCNT1H
Timer/Counter1 - Counter Register High Byte
127
(0x84)
TCNT1L
(0x83)
Reserved
–
–
–
Timer/Counter1 - Counter Register Low Byte
(0x82)
TCCR1C
FOC1A
FOC1B
–
–
–
–
–
–
126
(0x81)
TCCR1B
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
125
123
–
–
127
–
–
–
(0x80)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
–
–
WGM11
WGM10
(0x7F)
DIDR1
–
–
–
–
–
–
AIN1D
AIN0D
209
(0x7E)
DIDR0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
227
9
8019HS–AVR–11/06
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0x7D)
Reserved
–
–
–
–
–
–
–
–
(0x7C)
ADMUX
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
223
(0x7B)
ADCSRB
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
208, 227
(0x7A)
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
(0x79)
ADCH
ADC Data Register High byte
Page
225
226
(0x78)
ADCL
(0x77)
Reserved
–
–
–
ADC Data Register Low byte
–
–
–
–
–
226
(0x76)
Reserved
–
–
–
–
–
–
–
–
(0x75)
Reserved
–
–
–
–
–
–
–
–
(0x74)
Reserved
–
–
–
–
–
–
–
–
(0x73)
Reserved
–
–
–
–
–
–
–
–
(0x72)
Reserved
–
–
–
–
–
–
–
–
(0x71)
Reserved
–
–
–
–
–
–
–
–
(0x70)
TIMSK2
–
–
–
–
–
–
OCIE2A
TOIE2
151
(0x6F)
TIMSK1
–
–
ICIE1
–
–
OCIE1B
OCIE1A
TOIE1
128
(0x6E)
TIMSK0
–
–
–
–
–
–
OCIE0A
TOIE0
99
(0x6D)
Reserved
–
–
–
–
–
–
–
–
(0x6C)
PCMSK1
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
62
(0x6B)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
63
(0x6A)
Reserved
–
–
–
–
–
–
–
–
(0x69)
EICRA
–
–
–
–
–
–
ISC01
ISC00
(0x68)
Reserved
–
–
–
–
–
–
–
–
(0x67)
Reserved
–
–
–
–
–
–
–
–
(0x66)
OSCCAL
(0x65)
Reserved
–
–
–
–
–
–
–
–
(0x64)
PRR
–
–
–
–
PRTIM1
PRSPI
PRUSART0
PRADC
(0x63)
Reserved
–
–
–
–
–
–
–
–
(0x62)
Reserved
–
–
–
–
–
–
–
–
(0x61)
CLKPR
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
36
(0x60)
WDTCR
–
–
–
WDCE
WDE
WDP2
WDP1
WDP0
53
0x3F (0x5F)
SREG
I
T
H
S
V
N
Z
C
11
0x3E (0x5E)
SPH
–
–
–
–
–
SP10
SP9
SP8
13
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
13
0x3C (0x5C)
Reserved
0x3B (0x5B)
Reserved
0x3A (0x5A)
Reserved
0x39 (0x59)
Reserved
271
Oscillator Calibration Register
61
35
43
0x38 (0x58)
Reserved
0x37 (0x57)
SPMCSR
SPMIE
RWWSB
–
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
0x36 (0x56)
Reserved
–
–
–
–
–
–
–
–
0x35 (0x55)
MCUCR
JTD
–
–
PUD
–
–
IVSEL
IVCE
59, 83, 256
0x34 (0x54)
MCUSR
–
–
–
JTRF
WDRF
BORF
EXTRF
PORF
256
0x33 (0x53)
SMCR
–
–
–
–
SM2
SM1
SM0
SE
43
0x32 (0x52)
Reserved
–
–
–
–
–
–
–
0x31 (0x51)
OCDR
–
IDRD/OCD
OCDR6
OCDR5
OCDR4
OCDR3
OCDR2
OCDR1
OCDR0
234
0x30 (0x50)
ACSR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
208
–
–
–
–
–
–
–
–
0x2F (0x4F)
Reserved
0x2E (0x4E)
SPDR
0x2D (0x4D)
SPSR
SPIF
WCOL
–
0x2C (0x4C)
SPCR
SPIE
SPE
DORD
0x2B (0x4B)
GPIOR2
General Purpose I/O Register 2
0x2A (0x4A)
GPIOR1
General Purpose I/O Register 1
0x29 (0x49)
Reserved
–
–
–
0x28 (0x48)
Reserved
–
–
–
0x27 (0x47)
OCR0A
Timer/Counter0 Output Compare Register A
99
0x26 (0x46)
TCNT0
Timer/Counter0 (8 Bit)
99
0x25 (0x45)
Reserved
–
–
–
–
–
–
–
–
0x24 (0x44)
TCCR0A
FOC0A
WGM00
COM0A1
COM0A0
WGM01
CS02
CS01
CS00
97
0x23 (0x43)
GTCCR
TSM
–
–
–
–
–
PSR2
PSR10
132, 152
0x22 (0x42)
EEARH
–
–
–
–
–
–
–
EEAR8
25
0x21 (0x41)
EEARL
EEPROM Address Register Low Byte
0x20 (0x40)
EEDR
EEPROM Data Register
0x1F (0x3F)
EECR
SPI Data Register
–
–
–
162
–
–
–
–
SPI2X
161
MSTR
CPOL
CPHA
SPR1
SPR0
160
27
27
–
–
–
–
–
–
–
–
–
–
–
EERIE
25
25
EEMWE
EEWE
EERE
25
0x1E (0x3E)
GPIOR0
0x1D (0x3D)
EIMSK
PCIE1
PCIE0
–
–
–
–
–
INT0
61
0x1C (0x3C)
EIFR
PCIF1
PCIF0
–
–
–
–
–
INTF0
62
10
General Purpose I/O Register 0
27
ATmega165P
8019HS–AVR–11/06
ATmega165P
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x1B (0x3B)
Reserved
–
–
–
–
–
–
–
–
Page
0x1A (0x3A)
Reserved
–
–
–
–
–
–
–
–
0x19 (0x39)
Reserved
–
–
–
–
–
–
–
–
0x18 (0x38)
Reserved
–
–
–
–
–
–
–
–
0x17 (0x37)
TIFR2
–
–
–
–
–
–
OCF2A
TOV2
0x16 (0x36)
TIFR1
–
–
ICF1
–
–
OCF1B
OCF1A
TOV1
129
0x15 (0x35)
TIFR0
–
–
–
–
–
–
OCF0A
TOV0
100
0x14 (0x34)
PORTG
–
–
PORTG5
PORTG4
PORTG3
PORTG2
PORTG1
PORTG0
85
0x13 (0x33)
DDRG
–
–
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
85
151
0x12 (0x32)
PING
–
–
PING5
PING4
PING3
PING2
PING1
PING0
85
0x11 (0x31)
PORTF
PORTF7
PORTF6
PORTF5
PORTF4
PORTF3
PORTF2
PORTF1
PORTF0
85
0x10 (0x30)
DDRF
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
85
0x0F (0x2F)
PINF
PINF7
PINF6
PINF5
PINF4
PINF3
PINF2
PINF1
PINF0
85
0x0E (0x2E)
PORTE
PORTE7
PORTE6
PORTE5
PORTE4
PORTE3
PORTE2
PORTE1
PORTE0
84
0x0D (0x2D)
DDRE
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
DDE1
DDE0
84
0x0C (0x2C)
PINE
PINE7
PINE6
PINE5
PINE4
PINE3
PINE2
PINE1
PINE0
85
0x0B (0x2B)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
84
0x0A (0x2A)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
84
0x09 (0x29)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
84
0x08 (0x28)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
84
0x07 (0x27)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
84
0x06 (0x26)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
84
0x05 (0x25)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
83
0x04 (0x24)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
83
0x03 (0x23)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
83
0x02 (0x22)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
83
0x01 (0x21)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
83
0x00 (0x20)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
83
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega165P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
11
8019HS–AVR–11/06
5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd ← Rd • Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
1
COM
Rd
One’s Complement
Rd ← 0xFF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ← 0x00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← 0xFF
None
1
MUL
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
Z,C
2
MULS
Rd, Rr
Multiply Signed
R1:R0 ← Rd x Rr
Z,C
2
MULSU
Rd, Rr
Multiply Signed with Unsigned
R1:R0 ← Rd x Rr
Z,C
2
FMUL
Rd, Rr
Fractional Multiply Unsigned
R1:R0 ← (Rd x Rr) <<
1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Z,C
2
Z,C
2
Z,C
2
2
FMULS
Rd, Rr
Fractional Multiply Signed
FMULSU
Rd, Rr
Fractional Multiply Signed with Unsigned
BRANCH INSTRUCTIONS
RJMP
k
IJMP
Relative Jump
PC ← PC + k + 1
None
Indirect Jump to (Z)
PC ← Z
None
2
JMP
k
Direct Jump
PC ← k
None
3
RCALL
k
Relative Subroutine Call
PC ← PC + k + 1
None
3
Indirect Call to (Z)
PC ← Z
None
3
Direct Subroutine Call
PC ← k
None
4
RET
Subroutine Return
PC ← STACK
None
4
RETI
Interrupt Return
PC ← STACK
I
4
ICALL
CALL
k
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd − Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd − K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
1/2/3
1
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
12
ATmega165P
8019HS–AVR–11/06
ATmega165P
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
SEC
Set Carry
C←1
C
1
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I←0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Twos Complement Overflow.
V←1
V
1
CLV
Clear Twos Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H←1
H←0
H
H
1
1
Rd ← Rr
Rd+1:Rd ← Rr+1:Rr
None
1
None
1
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
LDI
Rd, K
Load Immediate
Rd ← K
None
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ← (X), X ← X + 1
None
2
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)
None
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
2
ST
X, Rr
Store Indirect
(X) ← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ← Rr, Y ← Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ← Y - 1, (Y) ← Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program Memory
R0 ← (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd ← (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd ← (Z), Z ← Z+1
None
3
Store Program Memory
(Z) ← R1:R0
None
-
IN
Rd, P
In Port
Rd ← P
None
1
OUT
P, Rr
Out Port
P ← Rr
None
1
SPM
13
8019HS–AVR–11/06
Mnemonics
Operands
Description
Operation
Flags
#Clocks
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
MCU CONTROL INSTRUCTIONS
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/timer)
For On-chip Debug Only
None
None
1
N/A
14
ATmega165P
8019HS–AVR–11/06
ATmega165P
6. Ordering Information
Speed (MHz)(3)
Power Supply
8
16
Notes:
Ordering Code(2)
Package(1)
Operation Range
1.8 - 5.5V
ATmega165PV-8AU
ATmega165PV-8MU
64A
64M1
Industrial
(-40°C to 85°C)
2.7 - 5.5V
ATmega165P-16AU
ATmega165P-16MU
64A
64M1
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC, see Figure 26-2 on page 308 and Figure 26-3 on page 308.
Package Type
64A
64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1
64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
15
8019HS–AVR–11/06
7. Packaging Information
7.1
64A
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
15.75
16.00
16.25
D1
13.90
14.00
14.10
E
15.75
16.00
16.25
E1
13.90
14.00
14.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
SYMBOL
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
64A
B
ATmega165P
8019HS–AVR–11/06
ATmega165P
7.2
64M1
D
Marked Pin# 1 ID
E
C
SEATING PLANE
A1
TOP VIEW
A
K
0.08 C
L
Pin #1 Corner
D2
1
2
3
Option A
SIDE VIEW
Pin #1
Triangle
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
Option B
K
Option C
b
e
Pin #1
Chamfer
(C 0.30)
Pin #1
Notch
(0.20 R)
BOTTOM VIEW
Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
2. Dimension and tolerance conform to ASMEY14.5M-1994.
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
–
0.02
0.05
b
0.18
0.25
0.30
D
8.90
9.00
9.10
D2
5.20
5.40
5.60
E
8.90
9.00
9.10
E2
5.20
5.40
5.60
e
NOTE
0.50 BSC
L
0.35
0.40
0.45
K
1.25
1.40
1.55
5/25/06
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
64M1
REV.
G
17
8019HS–AVR–11/06
8. Errata
8.1
ATmega165P Rev. G
No known errata.
8.2
ATmega165P Rev. A to F
Not sampled.
18
ATmega165P
8019HS–AVR–11/06
ATmega165P
9. Datasheet Revision History
Please note that the referring page numbers in this section are referring to this document. The
referring revision in this section are referring to the document revision.
9.1
9.2
9.3
9.4
9.5
Rev. H 11/06
1.
2.
3.
Updated ”Low-frequency Crystal Oscillator” on page 31.
Updated Table 26-6 on page 307.
Updated note in Table 26-6 on page 307.
1.
2.
3.
4.
5.
6.
Updated ”Calibrated Internal RC Oscillator” on page 29.
Updated ”System Control and Reset” on page 44.
Updated Table 7-9 on page 32 and Table 7-10 on page 32.
Added note for Table 25-15 on page 286
Updated ”Parallel Programming Characteristics” on page 282.
Updated ”Electrical Characteristics” on page 301.
1.
2.
Updated Table 1s2-12 on page 80.
Updated ”DC Characteristics” on page 304.
1.
2.
3.
4.
Updated ”Low-frequency Crystal Oscillator” on page 32.
Updated ”Device Identification Register” on page 236.
Updated ”Signature Bytes” on page 275.
Added Table 25-6 on page 275.
1.
2.
3.
4.
5.
Updated ”Register Description for I/O-Ports” on page 83.
Updated ”Fast PWM Mode” on page 92.
Updated ”Fast PWM Mode” on page 115.
Updated Features in ”USI – Universal Serial Interface” on page 194.
Added ”Clock speed considerations.” on page 201.
Rev. G 09/06
Rev. F 08/06
Rev. E 08/06
Rev. D 07/06
19
8019HS–AVR–11/06
6.
9.6
9.7
9.8
20
7.
8.
Updated Table 13-2 on page 97, Table 13-4 on page 98, Table 14-2 on page 123,Table
14-3 on page 124, Table 14-4 on page 125, Table 16-2 on page 148 and Table 16-4 on
page 149.
Updated ”UCSRnC – USART Control and Status Register n C” on page 187.
Updated ”Register Summary” on page 348.
1.
2.
3.
4.
Updated typos.
Updated ”Calibrated Internal RC Oscillator” on page 30.
Updated ”OSCCAL – Oscillator Calibration Register” on page 36.
Added Table 26-5 on page 312.
1.
2.
Updated ”Calibrated Internal RC Oscillator” on page 30
Updated ”Sleep Modes” on page 38.
1.
Initial revision.
Rev. C 06/06
Rev. B 04/06
Rev. A 03/06
ATmega165P
8019HS–AVR–11/06
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8019HS–AVR–11/06