Cypress CY7B992 Programmable skew clock buffer Datasheet

CY7B991
CY7B992
Programmable Skew Clock Buffer
Features
Functional Description
■
All output pair skew <100 ps typical (250 maximum)
■
3.75 to 80 MHz output operation
■
User selectable output functions
❐ Selectable skew to 18 ns
❐ Inverted and non-inverted
❐ Operation at 1⁄2 and 1⁄4 input frequency
❐ Operation at 2x and 4x input frequency (input as low as 3.75
MHz)
The CY7B991 and CY7B992 Programmable Skew Clock Buffers
(PSCB) offer user selectable control over system clock functions.
These multiple output clock drivers provide the system integrator
with functions necessary to optimize the timing of high performance computer systems. Each of the eight individual drivers,
arranged in four pairs of user controllable outputs, can drive
terminated transmission lines with impedances as low as 50Ω.
They can deliver minimal and specified output skews and full
swing logic levels (CY7B991 TTL or CY7B992 CMOS).
■
Zero input to output delay
■
50% duty cycle outputs
■
Outputs drive 50Ω terminated lines
■
Low operating current
■
32-pin PLCC/LCC package
■
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Each output is hardwired to one of the nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined
by the operating frequency with outputs that skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows cancellation of external load and transmission line delay effects. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions,
you can create output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that are multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty, allowing maximum system clock speed and
flexibility.
Logic Block Diagram
TEST
PHASE
FREQ
DET
FB
REF
FILTER
VCO AND
TIME UNIT
GENERATOR
FS
4F0
4F1
3F0
3F1
4Q0
SELECT
INPUTS
(THREE
LEVEL)
4Q1
SKEW
3Q0
3Q1
SELECT
2Q0
2F0
2F1
MATRIX
2Q1
1Q0
1F0
1F1
Cypress Semiconductor Corporation
Document Number: 38-07138 Rev. *B
1Q1
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 22, 2007
CY7B991
CY7B992
Pin Configuration
FS
VCCQ
REF
GND
4
3
2
1
32 31 30
29
2F1
3F0
TEST
PLCC/LCC
2F0
5
4F0
6
28
GND
4F1
7
27
1F1
VCCQ
8
26
1F0
VCCN
9
25
VCCN
4Q1
10
24
1Q0
4Q0
11
23
1Q1
GND
12
22
GND
GND
13
21
14 15 16 17 18 19 20
GND
2Q1
VCCN
FB
VCCN
3Q0
3Q1
CY7B991
CY7B992
2Q0
3F1
Pin Definitions
IO
Description
REF
Signal Name
I
Reference frequency input. This input supplies the frequency and timing against which all functional
variations are measured.
FB
I
PLL feedback input (typically connected to one of the eight outputs).
FS
I
Three level frequency range select. See Table 1.
1F0, 1F1
I
Three level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
2F0, 2F1
I
Three level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
3F0, 3F1
I
Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
4F0, 4F1
I
Three level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
TEST
I
Three level select. See “Test Mode” on page 4 under the “Block Diagram Description” on page 3.
1Q0, 1Q1
O
Output pair 1. See Table 2.
2Q0, 2Q1
O
Output pair 2. See Table 2.
3Q0, 3Q1
O
Output pair 3. See Table 2.
4Q0, 4Q1
O
Output pair 4. See Table 2.
VCCN
PWR
Power supply for output drivers.
VCCQ
PWR
Power supply for internal circuitry.
GND
PWR
Ground.
Document Number: 38-07138 Rev. *B
Page 2 of 19
CY7B991
CY7B992
Block Diagram Description
Skew Select Matrix
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
VCO and Time Unit Generator
Table 1. Frequency Range Select and tU Calculation[1]
FS[2, 3]
where N =
Approximate
Frequency (MHz) At
Which tU = 1.0 ns
30
44
22.7
25
50
26
38.5
40
80
16
62.5
Min
Max
LOW
15
MID
HIGH
1
t U = -----------------------f NOM × N
Table 2. Programmable Skew Configurations[1]
Function Selects
The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency used by the time unit generator to
create discrete time units that are selected in the skew select
matrix. The operational range of the VCO is determined by the
FS control pin. The time unit (tU) is determined by the operating
frequency of the device and the level of the FS pin as shown in
Table 1.
fNOM (MHz)
The skew select matrix contains four independent sections. Each
section has two low skew, high fanout drivers (xQ0, xQ1), and
two corresponding three level function select (xF0, xF1) inputs.
Table 2 shows the nine possible output functions for each section
as determined by the function select inputs. All times are
measured with respect to the REF input assuming that the output
connected to the FB input has 0tU selected.
Output Functions
1F1, 2F1,
3F1, 4F1
1F0, 2F0,
3F0, 4F0
1Q0, 1Q1,
2Q0, 2Q1
LOW
LOW
–4tU
LOW
MID
–3tU
–6tU
–6tU
LOW
HIGH
–2tU
–4tU
–4tU
MID
LOW
–1tU
–2tU
–2tU
MID
MID
0tU
0tU
0tU
MID
HIGH
+1tU
+2tU
+2tU
HIGH
LOW
+2tU
+4tU
+4tU
HIGH
MID
+3tU
+6tU
+6tU
HIGH
HIGH
+4tU
Divide by 4
Inverted
3Q0, 3Q1
4Q0, 4Q1
Divide by 2 Divide by 2
Notes
1. For all tri-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
holds an unconnected input to VCC/2.
2. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB
inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 4.3V.
Document Number: 38-07138 Rev. *B
Page 3 of 19
CY7B991
CY7B992
Figure 1 shows the typical outputs with FB connected to a zero skew output.[4]
U
U
U
U
U
U
t 0 +1t
t 0 +2t
t 0 +3t
t 0 +4t
t 0 +5t
t 0 +6t
t0
t 0 – 1t U
t 0 – 2t U
t 0 – 3t U
t 0 – 4t U
t 0 – 5t U
t 0 – 6t U
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
FBInput
REFInput
1Fx
2Fx
3Fx
4Fx
(N/A)
LM
– 6t U
LL
LH
– 4t U
LM
(N/A)
– 3t U
LH
ML
– 2t U
ML
(N/A)
– 1t U
MM
MM
MH
(N/A)
+1t U
HL
MH
+2t U
HM
(N/A)
+3t U
HH
HL
+4t U
0tU
(N/A)
HM
(N/A)
LL/HH
DIVIDED
(N/A)
HH
INVERT
+6t U
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, enabling the
CY7B991 or CY7B992 to operate as explained in “Skew Select
Matrix” on page 3. For testing purposes, any of the three level
inputs can have a removable jumper to ground, or be tied LOW
through a 100Ω resistor. This enables an external tester to
change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
selects inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
Note
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).
Document Number: 38-07138 Rev. *B
Page 4 of 19
CY7B991
CY7B992
Maximum Ratings
Operating outside these boundaries affects the performance and
life of the device. These user guidelines are not tested.
Operating Range
Range
Ambient
Temperature
Storage Temperature ................................. –65°C to +150°C
VCC
Commercial
0°C to +70°C
5V ± 10%
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Industrial
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
–40°C to +85°C
5V ± 10%
Military
[5]
–55°C to +125°C
5V ± 10%
Military
[5]
–55°C to +125°C
5V ± 10%
Output Current into Outputs (LOW) ............................. 64 mA
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Latch Up Current ..................................................... >200 mA
Note
5. Indicates case temperature.
Document Number: 38-07138 Rev. *B
Page 5 of 19
CY7B991
CY7B992
Electrical Characteristics
Over the Operating Range[6]
CY7B991
Parameter
Description
Test Conditions
VCC = Min IOH = –16 mA
Min
Max
CY7B992
Min
Max
2.4
Unit
VOH
Output HIGH Voltage
V
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
(REF and FB inputs only)
2.0
VCC
VCC –
1.35
VCC
V
VIL
Input LOW Voltage
(REF and FB inputs only)
–0.5
0.8
–0.5
1.35
V
VIHH
Three Level Input HIGH
Voltage (Test, FS, xFn)[10]
Min ≤ VCC ≤ Max
VCC – 0.85
VCC
VCC – 0.85
VCC
V
VIMM
Three Level Input MID
Voltage (Test, FS, xFn)[10]
Min ≤ VCC ≤ Max
VCC/2 –
500 mV
VCC/2 +
500 mV
VCC/2 –
500 mV
VCC/2 +
500 mV
V
VILL
Three Level Input LOW
Voltage (Test, FS, xFn)[10]
Min ≤ VCC ≤
Maximum
0.0
0.85
0.0
0.85
V
IIH
Input HIGH Leakage Current
(REF and FB inputs only)
VCC = Max, VIN = Max.
10
μA
IIL
Input LOW Leakage Current
(REF and FB inputs only)
VCC = Max, VIN = 0.4V
IIHH
Input HIGH Current
(Test, FS, xFn)
VIN = VCC
IIMM
Input MID Current
(Test, FS, xFn)
VIN = VCC/2
IILL
Input LOW Current
(Test, FS, xFn)
VIN = GND
IOS
Output Short Circuit
Current[8]
VCC = Max, VOUT
= GND (25°C only)
ICCQ
Operating Current Used by
Internal Circuitry
VCCN = VCCQ = Max,
All Input
Selects Open
ICCN
Output Buffer Current per
Output Pair[9]
PD
Power Dissipation per
Output Pair[10]
VCC = Min, IOH =–40 mA
VCC –0.75
VCC = Min, IOL = 46 mA
0.45
V
VCC = Min, IOL = 46 mA
0.45
10
–500
μA
–500
200
μA
50
μA
–200
–200
μA
–250
N/A
mA
Com’l
85
85
mA
Mil/Ind
90
90
VCCN = VCCQ = Max,
IOUT = 0 mA
Input Selects Open, fMAX
14
19
mA
VCCN = VCCQ = Max,
IOUT = 0 mA
Input Selects Open, fMAX
78
104[11]
mW
200
–50
50
–50
Notes
6. For more information see “Group A Subgroup Testing” on page 17.
7. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before
all datasheet limits are achieved.
8. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must
not be shorted to GND. Doing so may cause permanent damage.
9. Total output current per output pairis approximated by the following expression that includes device current plus load current:
CY7B991: ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B992: ICCN = [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz; C = capacitive load in pF; Z = line impedance in ohms; N = number of loaded outputs; 0, 1, or 2; FC = F < C.
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load
circuit:
CY7B991:PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B992:PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 9 for variable definition.
11. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-07138 Rev. *B
Page 6 of 19
CY7B991
CY7B992
Capacitance
CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
Parameter
CIN
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 5.0V
Max
Unit
10
pF
AC Test Loads and Waveforms
5V
R1
CL
R2
3.0V
R1=130
R2=91
CL = 50 pF (CL =30 pF for –2 and –5 devices)
(Includes fixture and probe capacitance)
2.0V
Vth =1.5V
0.8V
0.0V
TTL Input Test Waveform (CY7B991)
VCC
CL
≤1ns
≤1ns
TTL AC Test Load (CY7B991)
R1
2.0V
Vth =1.5V
0.8V
R1=100
R2=100
CL = 50 pF (CL =30 pF for –2 and –5 devices)
(Includes fixture and probe capacitance)
R2
CMOS AC Test Load (CY7B992)
Document Number: 38-07138 Rev. *B
VCC
80%
Vth = VCC/2
20%
0.0V
≤3ns
80%
Vth = VCC/2
20%
≤3ns
CMOS Input Test Waveform (CY7B992)
Page 7 of 19
CY7B991
CY7B992
Switching Characteristics Over the Operating Range[2, 13]
CY7B991–2[14]
Parameter
fNOM
Description
Min
[1, 2]
Operating Clock
Frequency in MHz
Typ
CY7B992–2[14]
Max
Min
Typ
Max
Unit
MHz
FS = LOW
15
30
15
30
FS = MID[1, 2]
25
50
25
50
FS = HIGH[1, 2 , 3]
40
80
40
80[15]
tRPWH
REF Pulse Width HIGH
5.0
5.0
ns
tRPWL
REF Pulse Width LOW
5.0
tU
Programmable Skew Unit
5.0
ns
tSKEWPR
Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17]
0.05
0.20
0.05
0.20
ns
tSKEW0
Zero Output Skew (All Outputs)[16, 18,19]
0.1
0.25
0.1
0.25
ns
tSKEW1
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[16, 19]
0.25
0.5
0.25
0.5
ns
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 19]
0.3
0.5
0.3
0.5
ns
tSKEW3
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 19]
0.25
0.5
0.25
0.5
ns
tSKEW4
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 19]
0.5
0.9
0.5
0.7
ns
tDEV
Device-to-Device Skew[14, 21]
0.75
ns
tPD
Propagation Delay, REF Rise to FB Rise
See Table 1
0.75
Variation[22]
–0.25
0.0
+0.25
–0.25
0.0
+0.25
ns
–0.65
0.0
+0.65
–0.5
0.0
tODCV
Output Duty Cycle
+0.5
ns
tPWH
Output HIGH Time Deviation from 50%[23, 24]
2.0
3.0
ns
tPWL
50%[23, 24]
1.5
3.0
ns
ns
tORISE
Output LOW Time Deviation from
Output Rise
Time[23, 25]
Time[23, 25]
tOFALL
Output Fall
tLOCK
PLL Lock Time[26]
tJR
Cycle-to-Cycle Output
Jitter
0.15
1.0
1.2
0.5
2.0
2.5
0.15
1.0
1.2
0.5
2.0
2.5
ns
0.5
0.5
ms
RMS[14]
25
25
ps
Peak-to-Peak[14]
200
200
ps
Notes
12. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
13. Test measurement levels for the CY7B991 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B992 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters.
15. Except as noted, all CY7B992–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load.
16. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay is selected when all are loaded
with 50 pF and terminated with 50Ω to 2.06V (CY7B991) or VCC/2 (CY7B992).
17. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
18. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
19. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns.
20. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in
Divide-by-2 or Divide-by-4 mode).
21. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, and so on.)
22. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
23. Specified with outputs loaded with 30 pF for the CY7B99X–2 and –5 devices and 50 pF for the CY7B99X–7 devices. Devices are terminated through 50Ω to
2.06V (CY7B991) or VCC/2 (CY7B992).
24. tPWH is measured at 2.0V for the CY7B991 and 0.8 VCC for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 VCC for the CY7B992.
25. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B991 or 0.8VCC and 0.2VCC for the CY7B992.
26. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits.
This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07138 Rev. *B
Page 8 of 19
CY7B991
CY7B992
Switching Characteristics
Over the Operating Range[2, 13] (continued)
CY7B991–5
Parameter
fNOM
Description
Operating Clock
Frequency in MHz
Min
FS = LOW
[1, 2]
[1, 2]
FS = MID
[1, 2 , 3]
FS = HIGH
Typ
CY7B992–5
Max
Min
15
30
25
40
Typ
Max
Unit
15
30
MHz
50
25
50
80
40
80[15]
tRPWH
REF Pulse Width HIGH
5.0
5.0
ns
tRPWL
REF Pulse Width LOW
5.0
5.0
ns
tU
Programmable Skew Unit
tSKEWPR
Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17]
0.1
0.25
0.1
0.25
ns
tSKEW0
Zero Output Skew (All Outputs)[16, 18]
0.25
0.5
0.25
0.5
ns
tSKEW1
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[16, 19]
0.6
0.7
0.6
0.7
ns
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 19]
0.5
1.0
0.6
1.5
ns
tSKEW3
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 19]
0.5
0.7
0.5
0.7
ns
tSKEW4
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 19]
0.5
1.0
0.6
1.7
ns
tDEV
Device-to-Device Skew[14, 21]
1.25
ns
tPD
Propagation Delay, REF Rise to FB Rise
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
Output Duty Cycle
See Table 1
1.25
Variation[22]
–0.5
0.0
+0.5
–0.5
0.0
+0.5
ns
–1.0
0.0
+1.0
–1.2
0.0
+1.2
ns
Output HIGH Time Deviation from
50%[23, 24]
2.5
4.0
ns
Output LOW Time Deviation from
50%[23, 24]
3
4.0
ns
[23, 25]
Output Rise Time
Output Fall
0.15
1.0
1.5
0.5
2.0
3.5
ns
0.15
1.0
1.5
0.5
2.0
3.5
ns
0.5
0.5
ms
RMS
25
25
ps
Peak-to-Peak[14]
200
200
ps
Time[23, 25]
[26]
PLL Lock Time
Cycle-to-Cycle Output
Jitter
Document Number: 38-07138 Rev. *B
[14]
Page 9 of 19
CY7B991
CY7B992
Switching Characteristics
Over the Operating Range[2, 13] (continued)
CY7B991–7
Parameter
fNOM
Description
Min
Max
Min
15
30
15
FS = MID
25
50
25
50
FS = HIGH[1, 2]
40
80
40
80[15]
[1, 2]
Operating Clock
Frequency in MHz
FS = LOW
[1, 2]
Typ
CY7B992–7
Typ
Max
Unit
30
MHz
tRPWH
REF Pulse Width HIGH
5.0
5.0
ns
tRPWL
REF Pulse Width LOW
5.0
5.0
ns
tU
Programmable Skew Unit
tSKEWPR
Zero Output Matched-Pair Skew
(XQ0, XQ1)[16, 17]
0.1
0.25
0.1
0.25
ns
tSKEW0
Zero Output Skew (All Outputs)[16, 18]
0.3
0.75
0.3
0.75
ns
tSKEW1
Output Skew (Rise-Rise, Fall-Fall, Same
Class Outputs)[16, 19]
0.6
1.0
0.6
1.0
ns
tSKEW2
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided)[16, 19]
1.0
1.5
1.0
1.5
ns
tSKEW3
Output Skew (Rise-Rise, Fall-Fall, Different
Class Outputs)[16, 19]
0.7
1.2
0.7
1.2
ns
tSKEW4
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted)[16, 19]
1.2
1.7
1.2
1.7
ns
tDEV
Device-to-Device Skew[14, 22]
1.65
ns
tPD
Propagation Delay, REF Rise to FB Rise
See Table 1
Variation[22]
1.65
–0.7
0.0
+0.7
–0.7
0.0
+0.7
ns
–1.2
0.0
+1.2
–1.5
0.0
+1.5
ns
tODCV
Output Duty Cycle
tPWH
Output HIGH Time Deviation from 50%[23, 24]
3
5.5
ns
tPWL
Output LOW Time Deviation from 50%[23, 24]
3.5
5.5
ns
tORISE
tOFALL
Output Rise
Output Fall
Time[23, 25]
Time[23, 25]
Time[26]
tLOCK
PLL Lock
tJR
Cycle-to-Cycle Output
Jitter
Document Number: 38-07138 Rev. *B
0.15
1.5
2.5
0.5
3.0
5.0
ns
0.15
1.5
2.5
0.5
3.0
5.0
ns
0.5
0.5
ms
RMS[14]
25
25
ps
Peak-to-Peak[14]
200
200
ps
Page 10 of 19
CY7B991
CY7B992
AC Timing Diagrams
tREF
tRPWL
tRPWH
REF
tODCV
tPD
tODCV
FB
tJR
Q
tSKEWPR,
tSKEW0,1
tSKEWPR,
tSKEW0,1
OTHER Q
tSKEW2
tSKEW2
INVERTED Q
tSKEW3,4
tSKEW3,4
tSKEW3,4
REF DIVIDED BY 2
tSKEW1,3, 4
tSKEW2,4
REF DIVIDED BY 4
Document Number: 38-07138 Rev. *B
Page 11 of 19
CY7B991
CY7B992
Operational Mode Descriptions
Figure 2. Zero Skew and Zero Delay Clock Driver
REF
SYSTEM
CLOCK
LOAD
Z0
L1
FB
REF
FS
4F0
4F1
4Q0
4Q1
3F0
3F1
3Q0
3Q1
2F0
2F1
2Q0
2Q1
1F0
1F1
1Q0
1Q1
LOAD
L2
Z0
LOAD
L3
Z0
L4
LOAD
TEST
Z0
LENGTH L1 = L2 = L3 = L4
Figure 2 shows the PSCB configured as a zero skew clock buffer. In this mode the 7B991/992 is used as the basis for a low-skew
clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and each drives a
terminated transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency
range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission lines (with
impedances as low as 50 ohms), enables efficient printed circuit board design.
Figure 3. Programmable Skew Clock Driver
REF
SYSTEM
CLOCK
FB
REF
FS
4F0
4F1
LOAD
L1
LOAD
4Q0
4Q1
3F0
3F1
2F0
2F1
3Q0
3Q1
1F0
1F1
1Q0
1Q1
Z0
L2
Z0
LOAD
L3
2Q0
2Q1
Z0
L4
LOAD
TEST
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
Figure 3 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between
outputs, the PSCB is programmed to stagger the timing of its
outputs. Each of the four groups of output pairs are programmed
to different output timing. Skew timing is adjusted over a wide
range in small increments with the appropriate strapping of the
function select pins. In this configuration the 4Q0 output is fed
Document Number: 38-07138 Rev. *B
Z0
back to FB and configured for zero skew. The other three pairs
of outputs are programmed to yield different skews relative to the
feedback. By advancing the clock signal on the longer traces or
retarding the clock signal on shorter traces, all loads can receive
the clock pulse at the same time.
In this illustration the FB input is connected to an output with 0-ns
skew (xF1, xF0 = MID) selected. The internal PLL synchronizes
Page 12 of 19
CY7B991
CY7B992
the FB and REF inputs and aligns their rising edges to ensure
that all outputs have precise phase alignment.
Clock skews are advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +tU, and –tU are defined relative to output
groups, and since the PLL aligns the rising edges of REF and
FB, you can create wider output skews by proper selection of the
xFn inputs. For example, a +10 tU between REF and 3Qx is
achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND,
3F0 = MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qx
skews to +6 tU, a total of +10 tU skew is realized.) Many other
configurations are realized by skewing both the outputs used as
the FB input and skewing the other outputs.
F
Figure 5. Frequency Multiplier with Skew Connectrions
REF
20 MHz
Figure 4. Inverted Output Connections
REF
FB
REF
FS
4F0
4F1
4Q0
4Q1
3F0
3F1
3Q0
3Q1
2F0
2F1
2Q0
2Q1
1F0
1F1
1Q0
1Q1
TEST
Figure 4 shows an example of the invert function of the PSCB.
In this example the 4Q0 output used as the FB input is
programmed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew. When 4F0 and
4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising edge of the FB input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs
to become the “inverted” outputs with respect to the REF input.
It is possible to have 2 inverted and 6 non-inverted outputs or 6
inverted and 2 non-inverted outputs by selecting the output
connected to FB. The correct configuration is determined by the
need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q
outputs can also be skewed to compensate for varying trace
delays independent of inversion on 4Q.
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
40 MHz
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
20 MHz
80 MHz
Figure 5 shows the PSCB configured as a clock multiplier. The
3Q0 output is programmed to divide by four and is sent to FB.
This causes the PLL to increase its frequency until the 3Q0 and
3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx
outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two, that results in a 40 MHz waveform
at these outputs. Note that the 20 and 40 MHz clocks fall simultaneously and are out of phase on their rising edge. This enables
the designer to use the rising edges of the 1⁄2 frequency and 1⁄4
frequency outputs without concern for rising edge skew. The
2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed
by programming their select inputs accordingly. Note that the FS
pin is wired for 80 MHz operation because that is the frequency
of the fastest output.
Figure 6. Frequency Divider Connections
REF
20 MHz
FB
REF
FS
4F0
4F1
4Q0
4Q1
10 MHz
3F0
3F1
2F0
2F1
3Q0
3Q1
5 MHz
1F0
1F1
TEST
1Q0
1Q1
2Q0
2Q1
20 MHz
Figure 6 demonstrates the PSCB in a clock divider application.
2Q0 is fed back to the FB input and programmed for zero skew.
3Qx is programmed to divide by four. 4Qx is programmed to
divide by two. Note that the falling edges of the 4Qx and 3Qx
outputs are aligned. This enables the use of rising edges of the
1⁄ frequency and 1⁄ frequency without concern for skew
2
4
mismatch. The 1Qx outputs are programmed to zero skew and
are aligned with the 2Qx outputs. In this example, the FS input
is grounded to configure the device in the 15 MHz to 30 MHz
Document Number: 38-07138 Rev. *B
Page 13 of 19
CY7B991
CY7B992
range since the highest frequency output is running at 20 MHz.
Figure 7 shows some of the functions that are selectable on the
3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output enables the system designer to clock different
subsystems on opposite edges, without suffering from the pulse
asymmetry typical of non-ideal loading. This function enables
each of the two subsystems to clock 180 degrees out of phase
and align within the skew specifications.
The divided outputs offer a zero delay divider for portions of the
system that need the clock divided by either two or four, and still
remain within a narrow skew of the “1X” clock. Without this
feature, an external divider is added, and the propagation delay
of the divider adds to the skew between the different clock
signals.
These divided outputs, coupled with the Phase Locked Loop,
enables the PSCB to multiply the clock rate at the REF input by
either two or four. This mode enables the designer to distribute
a low frequency clock between various portions of the system,
and then locally multiply the clock rate to a more suitable
frequency, still maintaining the low skew characteristics of the
clock driver. The PSCB performs all of the functions described in
this section at the same time. It multiplies by two and four or
divides by two (and four) at the same time. In other words, it is
shifting its outputs over a wide range or maintaining zero skew
between selected outputs.
Figure 7. Multi-Function Clock Driver
REF
LOAD
Z0
20 MHz
DISTRIBUTION
CLOCK
80 MHz
INVERTED
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Document Number: 38-07138 Rev. *B
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
20 MHz
Z0
LOAD
80 MHz
ZERO SKEW
80 MHz
SKEWED –3.125 ns (–4tU)
Z0
LOAD
Z0
Page 14 of 19
CY7B991
CY7B992
Figure 8. Board-to-Board Clock Distribution
LOAD
REF
Z0
L1
FB
SYSTEM
CLOCK
REF
FS
4F0
4F1
LOAD
L2
4Q0
4Q1
3F0
3F1
2F0
2F1
3Q0
3Q1
1F0
1F1
1Q0
1Q1
Z0
LOAD
L3
2Q0
2Q1
Z0
L4
TEST
Z0
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
Figure 8 shows the CY7B991 and 992 connected in series to construct a zero skew clock distribution tree between boards. Delays
of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire
delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers
in series.
Document Number: 38-07138 Rev. *B
Page 15 of 19
CY7B991
CY7B992
Ordering Information
Accuracy
(ps)
250
500
750
250
500
750
Ordering Code
Package Type
Operating
Range
CY7B991–2JC
32-Pb Plastic Leaded Chip Carrier
Commercial
CY7B991–2JCT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Commercial
CY7B991–5JC
32-Pb Plastic Leaded Chip Carrier
Commercial
CY7B991–5JCT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Commercial
CY7B991–5JI
32-Pb Plastic Leaded Chip Carrier
Industrial
CY7B991–5JIT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Industrial
CY7B991–7JC
32-Pb Plastic Leaded Chip Carrier
Commercial
CY7B991–7JCT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Commercial
CY7B991–7JI
32-Pb Plastic Leaded Chip Carrier
Industrial
CY7B991–7LMB[27]
32-Pin Rectangular Leadless Chip Carrier
Military
CY7B992–2JC
32-Pb Plastic Leaded Chip Carrier
Commercial
CY7B992–2JCT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Commercial
CY7B992–5JC
32-Pb Plastic Leaded Chip Carrier
Commercial
CY7B992–5JCT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Commercial
CY7B992–5JI[27]
32-Pb Plastic Leaded Chip Carrier
Industrial
CY7B992–5JIT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Industrial
CY7B992–7JC
32-Pb Plastic Leaded Chip Carrier
Commercial
CY7B992–7JCT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Commercial
CY7B992–7JI
32-Pb Plastic Leaded Chip Carrier
Industrial
CY7B992–7LMB[27]
32-Pin Rectangular Leadless Chip Carrier
Military
CY7B991–2JXC
32-Pb Plastic Leaded Chip Carrier
Commercial
CY7B991–2JXCT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Commercial
CY7B991–5JXC
32-Pb Plastic Leaded Chip Carrier
Commercial
CY7B991–5JXCT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Commercial
CY7B991–5JXI
32-Pb Plastic Leaded Chip Carrier
Industrial
CY7B991–5JXIT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Industrial
CY7B991–7JXC
32-Pb Plastic Leaded Chip Carrier
Commercial
CY7B991–7JXCT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Commercial
CY7B992–5JXI
32-Pb Plastic Leaded Chip Carrier
Industrial
CY7B992–5JXIT
32-Pb Plastic Leaded Chip Carrier - Tape and Reel
Industrial
Pb-Free
250
500
750
500
Note
27. Not recommended for the new design.
Document Number: 38-07138 Rev. *B
Page 16 of 19
CY7B991
CY7B992
Military Specifications
Group A Subgroup Testing
DC Characteristics
Parameter
Subgroups
VOH
1, 2, 3
VOL
1, 2, 3
VIH
1, 2, 3
VIL
1, 2, 3
VIHH
1, 2, 3
VIMM
1, 2, 3
VILL
1, 2, 3
IIH
1, 2, 3
IIL
1, 2, 3
IIHH
1, 2, 3
IIMM
1, 2, 3
IILL
1, 2, 3
ICCQ
1, 2, 3
ICCN
1, 2, 3
Package Diagrams
Figure 9. 32-Pin Plastic Leaded Chip Carrier
51-85002-*B
Document Number: 38-07138 Rev. *B
Page 17 of 19
CY7B991
CY7B992
Package Diagrams (continued)
Figure 10. 32-Pin Rectangular Leadless Chip Carrier
MIL-STD-1835 C-12
51-85002-*B
Document Number: 38-07138 Rev. *B
Page 18 of 19
CY7B991
CY7B992
Document History
Document Title: CY7B991/CY7B992 Programmable Skew Clock Buffer
Document Number: 38-07138
REV.
ECN NO.
Issue Date
Orig. of
Change
**
110247
12/19/01
SZV
*A
1199925
See ECN KVM/AESA Add Pb-free part numbers. Update package names in Ordering Information
table. Remove Pentium reference on page 1.
*B
1286064
See ECN
AESA
Description of Change
Change from Specification number: 38-00513 to 38-07138
Change status to final
© Cypress Semiconductor Corporation, 2001-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07138 Rev. *B
Revised June 22, 2007
Page 19 of 19
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