TI1 BUF16821 Programmable gamma-voltage generator Datasheet

Product
Folder
Sample &
Buy
Technical
Documents
Support &
Community
Tools &
Software
BUF16821-Q1
SBOS712 – MAY 2014
BUF16821-Q1 Programmable Gamma-Voltage Generator and
VCOM Calibrator with Integrated Two-Bank Memory
1 Features
3 Description
•
The BUF16821-Q1 offers 16 programmable gamma
channels and two programmable VCOM channels.
The final gamma and VCOM values can be stored in
the on-chip, nonvolatile memory. To allow for
programming errors or liquid crystal display (LCD)
panel rework, the device supports up to 16 write
operations to the on-chip memory.
1
•
•
•
•
•
•
•
AEC-Q100 Qualified with:
– Temperature Grade 3: –40°C to 85°C
– HBM ESD Classification 2
– CDM ESD Classification C4B
16-Channel P-Gamma, 2-Channel P-VCOM, 10Bit Resolution
16x Rewritable Nonvolatile Memory
Two Independent Pin-Selectable Memory Banks
Rail-to-Rail Output:
– 300-mV (Min) Swing-to-Rail (10 mA)
– > 300-mA (Max) IOUT
Supply Voltage: 9 V to 20 V
Digital Supply: 2 V to 5.5 V
I2C™ Interface: Supports 400 kHz and 2.7 MHz
2 Application
TFT-LCD Reference Drivers
Functional Block Diagram
The device has two separate memory banks, allowing
simultaneous storage of two different gamma curves
to facilitate switching between gamma curves. All
gamma and VCOM channels offer a rail-to-rail output
that typically swings to within 150 mV of either supply
rail with a 10-mA load. All channels are programmed
using an I2C interface that supports standard
operations up to 400 kHz and high-speed data
transfers up to 2.7 MHz.
The device is manufactured using Texas Instruments’
proprietary, state-of-the-art, high-voltage CMOS
process. This process offers very dense logic and
high supply voltage operation of up to 20 V. The
device is offered in an HTSSOP-28 PowerPAD™
package, and is specified from –40°C to +85°C.
Digital
Analog
BKSEL (2.0 V to 5.5 V) (9 V to 20 V)
Device Information(1)
PART NUMBER
BUF16821-Q1
1
PACKAGE
HTSSOP (28)
BODY SIZE (NOM)
9.70 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
DAC Registers
DAC Registers
¼
¼
¼
¼
¼
OUT2
16x Nonvolatile Memory BANK1
16x Nonvolatile Memory BANK0
OUT1
OUT15
OUT16
BUF16821-Q1
VCOM1
VCOM2
SDA
SCL
Control IF
A0
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Application .............................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 19
7.5 Programming .......................................................... 20
7.6 Register Maps ......................................................... 24
8
Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Application .................................................. 25
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
2
DATE
REVISION
NOTES
May 2014
*
Initial release.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
Related Products
FEATURES
DEVICE
22-channel gamma correction buffer
BUF22821
12-channel gamma correction buffer
BUF12800
18-, 20-channel programmable buffer, 10-bit, VCOM
BUF20800
18-, 20-channel programmable buffer with memory
BUF20820
Programmable VCOM driver
BUF01900
18-V supply, traditional gamma buffers
BUF11704
22-V supply, traditional gamma buffers
BUF11705
5 Pin Configuration and Functions
PWP Package
HTSSOP-28
(Top View)
VCOM2
1
28
VCOM1
OUT1
2
27
OUT16
OUT2
3
26
OUT15
OUT3
4
25
OUT14
OUT4
5
24
GNDA
OUT5
6
23
VS
OUT6
7
22
OUT13
21
OUT12
20
OUT11
OUT7 10
19
OUT10
OUT8 11
18
GNDD
OUT9 12
17
BKSEL
VSD 13
16
A0
SCL 14
15
SDA
(1)
8
VS
9
GNDA
PowerPAD
Lead-Frame
Die Pad
Exposed on
Underside
(must connect to
GNDA and GNDD)
(1)
(1)
(1) GNDA and GNDD must be connected together.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
3
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
Pin Functions
PIN
4
DESCRIPTION
NO.
NAME
1
VCOM2
2
OUT1
DAC output 1
3
OUT2
DAC output 2
4
OUT3
DAC output 3
5
OUT4
DAC output 4
6
OUT5
DAC output 5
7
OUT6
DAC output 6
8
GNDA
Analog ground; must be connected to digital ground (GNDD).
9
VS
10
OUT7
DAC output 7
11
OUT8
DAC output 8
12
OUT9
DAC output 9
13
VSD
Digital supply; connect to logic supply
14
SCL
Serial clock input; open-drain, connect to pull-up resistor.
15
SDA
Serial data I/O; open-drain, connect to pull-up resistor.
16
A0
17
BKSEL
Selects memory bank 0 or 1; connect to either logic 1 to select bank 1 or logic 0 to select bank 0.
18
GNDD
Digital ground; must be connected to analog ground at the BUF16821-Q1.
19
OUT10
DAC output 10
20
OUT11
DAC output 11
21
OUT12
DAC output 12
22
OUT13
DAC output 13
VCOM channel 2
VS connected to analog supply
A0 address pin for I2C address; connect to either logic 1 or logic 0; refer to Table 2.
23
VS
24
GNDA
VS connected to analog supply
Analog ground; must be connected to digital ground (GNDD).
25
OUT14
DAC output 14
26
OUT15
DAC output 15
27
OUT16
DAC output 16
28
VCOM1
VCOM channel 1
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
Supply voltage
DVDD
Digital power supply (VSD pin)
Digital input pins
SCL, SDA, AO, BKSEL: voltage
–0.5
(V–) – 0.5
Output short-circuit (3)
(1)
(2)
(3)
V
6
V
V
±10
mA
(V+) + 0.5
V
Continuous
Ambient operating temperature
TJ
UNIT
22
6
SCL, SDA, AO, BKSEL: current
Output pins, OUT1 through OUT16, VCOM1 and VCOM2 (2)
MAX
–40
Junction temperature
95
°C
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See the Output Protection section.
Short-circuit to ground, one amplifier per package.
6.2 Handling Ratings
Tstg
MIN
MAX
UNIT
–65
150
°C
–2000
2000
Corner pins (1, 14, 15,
and 28)
–750
750
Other pins
–500
500
Storage temperature range
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VS
Supply voltage
9.0
18.0
20.0
V
DVDD
Digital power supply (VSD pin)
2.0
3.3
5.5
V
6.4 Thermal Information
BUF16821-Q1
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
34.3
RθJC(top)
Junction-to-case (top) thermal resistance
19.9
RθJB
Junction-to-board thermal resistance
17.4
ψJT
Junction-to-top characterization parameter
0.7
ψJB
Junction-to-board characterization parameter
17.2
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.0
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
5
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
6.5 Electrical Characteristics
At TA = 25°C, VS = 18 V, VSD = 2 V, RL = 1.5 kΩ connected to ground, and CL = 200 pF, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
17.7
17.85
MAX
UNIT
ANALOG GAMMA BUFFER CHANNELS
Reset value
Code 512
OUT 1–16 output swing: high
Code = 1023, sourcing 10 mA, TA = –40°C to 85°C
OUT 1–16 output swing: low
Code = 0, sinking 10 mA, TA = –40°C to 85°C
VCOM1, 2 output swing: high
Code = 1023, sourcing 100 mA, TA = –40°C to 85°C
VCOM1, 2 output swing: low
Code = 0, sinking 100 mA, TA = –40°C to 85°C
9
0.07
13
INL
Integral nonlinearity
DNL
Differential nonlinearity
ΔVO(ΔIO)
Load regulation, 10 mA
±20
Code 512, TA = –40°C to 85°C
V
mA
±50
mV
±25
μV/°C
0.3
LSB
0.3
Code 512 or VCC / 2, IOUT = 5-mA to –5-mA step
V
V
2
30
Output accuracy
Output accuracy over temperature
V
0.3
16.2
0.6
Continuous output current (1)
V
0.5
LSB
1.5
mV/mA
16
Cycles
OTP MEMORY
Number of OTP write cycles
Memory retention
100
Years
ANALOG POWER SUPPLY
Operating range
ICC(tot)
9
Total analog supply current
Outputs at reset values, no load
ICC(tot) over temperature
TA = –40°C to 85°C
12
20
V
14
mA
18
mA
DIGITAL
VIH
Logic 1 high input voltage
VIL
Logic 0 low input voltage
VOL
Logic 0 low output voltage
0.7 × VSD
ISINK = 3 mA
Input leakage
fCLK
Clock frequency
V
0.3 × VSD
V
0.15
0.4
V
±0.01
±10
μA
Standard, fast mode, TA = –40°C to 85°C
400
kHz
High-speed mode, TA = –40°C to 85°C
2.7
MHz
DIGITAL POWER SUPPLY
DVDD
Digital power supply (VSD pin)
ISD
Digital supply current (1)
Outputs at reset values, no load, two-wire bus inactive
2.0
115
ISD over temperature
TA = –40°C to 85°C
115
5.5
V
150
μA
μA
TEMPERATURE RANGE
Specified range
Operating range
Junction temperature < 125°C
Storage range
RθJA
(1)
(2)
6
–40
85
°C
–40
95
°C
–65
150
°C
Thermal resistance,
HTSSOP-28 (1) (2)
40
°C/W
Observe maximum power dissipation.
Thermal pad is attached to the printed circuit board (PCB), 0-lfm airflow, and 76-mm × 76-mm copper area.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
6.6 Timing Requirements
FAST MODE
PARAMETER
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
UNIT
0.4
0.001
2.7
MHz
f(SCL)
SCL operating frequency
0.001
t(BUF)
Bus free time between stop and start conditions
1300
230
ns
t(HDSTA)
Hold time after repeated start condition. After this period,
the first clock is generated.
600
230
ns
t(SUSTA)
Repeated start condition setup time
600
230
ns
t(SUSTO)
Stop condition setup time
600
t(HDDAT)
Data hold time
20
t(SUDAT)
Data setup time
100
20
ns
t(LOW)
SCL clock low period
1300
230
ns
t(HIGH)
SCL clock high period
600
60
ns
tR(SDA),
tF(SDA)
Data rise and fall time
300
80
ns
tR(SCL),
tF(SCL)
Clock rise and fall time
300
40
ns
tR
Clock and data rise time for SCLK ≤ 100 kHz
1000
t(LOW)
230
900
tF
tR
20
ns
130
ns
ns
t(HDSTA)
SCL
t(HDSTA)
t(HIGH)
t(HDDAT)
t(SUSTO)
t(SUSTA)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 1. Timing Requirements Diagram
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
7
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
6.7 Typical Characteristics
18
17.5
17
16.5
16
15.5
15
VCOM1
3
2.5
2
1.5
1
0.5
0
Output Voltage (V)
Output Voltage (V)
At TA = 25°C, VS = 18 V, VSD = 2 V, RL = 1.5 kΩ connected to ground, and CL = 200 pF, unless otherwise noted.
VCOM2
0
25
50
75
100
125
18
17.5
17
16.5
16
15.5
15
Output Swing High
3
2.5
2
1.5
1
0.5
0
Output Swing Low
0
150
25
50
Output Current (mA)
Figure 2. Output Voltage vs Output Current
(VCOM1 and VCOM2)
125
100
150
Figure 3. Output Voltage vs Output Current
(Channels 1–16)
120
11
118
10.5
Analog Supply Current (mA)
Digital Supply Current (mA)
75
Output Current (mA)
116
114
112
110
108
106
104
10
9.5
9
8.5
8
7.5
7
102
6.5
100
-50
-25
0
25
50
75
100
–50
125
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 4. Digital Supply Current vs Temperature
Figure 5. Analog Supply Current vs Temperature
0.15
9.02
9.015
0.1
Error (LSB)
Initial Voltage (V)
9.01
9.005
9
8.995
0.05
0
–0.05
8.99
–0.1
8.985
–0.15
8.98
–50
–25
0
25
50
75
100
125
0
Temperature (°C)
256
512
768
1024
Input Code
10 Typical Units Shown
Figure 6. Output Voltage vs Temperature
8
Submit Documentation Feedback
Figure 7. Differential Linearity Error
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
Typical Characteristics (continued)
At TA = 25°C, VS = 18 V, VSD = 2 V, RL = 1.5 kΩ connected to ground, and CL = 200 pF, unless otherwise noted.
0.15
0.1
Error (LSB)
BKSEL (2 V/div)
0.05
780 ms
0
9V
–0.05
DAC Channel
(2 V/div)
–0.1
5V
–0.15
0
256
768
512
1 ms/div
1024
Input Code
Figure 9. BKSEL Switching Time Delay
Output Voltage (2 V/div)
Figure 8. Integral Linearity Error
Time (1 ms/div)
Figure 10. Large-Signal Step Response
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
9
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
7 Detailed Description
7.1 Overview
The BUF16821-Q1 programmable voltage reference allows fast and easy adjustment of 16 programmable
gamma reference outputs and two VCOM outputs, each with 10-bit resolution. The device is programmed
through a high-speed, I2C interface. The final gamma and VCOM values can be stored in the onboard,
nonvolatile memory. To allow for programming errors or liquid crystal display (LCD) panel rework, the device
supports up to 16 write operations to the onboard memory. The device has two separate memory banks, allowing
simultaneous storage of two different gamma curves to facilitate dynamic switching between gamma curves.
Figure 19 illustrates a typical configuration of the device.
7.2 Functional Block Diagram
Digital
Analog
BKSEL (2.0 V to 5.5 V) (9 V to 20 V)
1
DAC Registers
DAC Registers
¼
¼
¼
¼
¼
OUT2
16x Nonvolatile Memory BANK1
16x Nonvolatile Memory BANK0
OUT1
OUT15
OUT16
VCOM1
VCOM2
SDA
SCL
Control IF
Device
A0
7.3 Feature Description
7.3.1 Two-Wire Bus Overview
The device communicates over an industry-standard, two-wire interface to receive data in slave mode. This
standard uses a two-wire, open-drain interface that supports multiple devices on a single bus. Bus lines are
driven to a logic low level only. The device that initiates the communication is called a master, and the devices
controlled by the master are slaves. The master generates the serial clock on the clock signal line (SCL),
controls the bus access, and generates the start and stop conditions.
To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a
high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the SCL rising
edge, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the
slave being addressed responds to the master by generating an acknowledge and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a
start or stop condition.
10
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
Feature Description (continued)
When all data are transferred, the master generates a stop condition, indicated by pulling SDA from low to high
while SCL is high. The device can act only as a slave device and therefore never drives SCL. SCL is an input
only for the BUF16821-Q1.
7.3.2 Data Rates
The two-wire bus operates in one of three speed modes:
• Standard: allows a clock frequency of up to 100 kHz;
• Fast: allows a clock frequency of up to 400 kHz; and
• High-speed mode (also called Hs mode): allows a clock frequency of up to 2.7 MHz.
The device is fully compatible with all three modes. No special action is required to use the device in standard or
fast modes, but high-speed mode must be activated. To activate high-speed mode, send a special address byte
of 00001 xxx, with SCL ≤ 400 kHz, following the start condition; where xxx are bits unique to the Hs-capable
master, which can be any value. This byte is called the Hs master code. Table 1 provides a reference for the
high-speed mode command code. (Note that this configuration is different from normal address bytes—the low
bit does not indicate read or write status.) The device responds to the high-speed command regardless of the
value of these last three bits. The device does not acknowledge this byte; the communication protocol prohibits
acknowledgment of the Hs master code. Upon receiving a master code, the device switches on its Hs mode
filters, and communicates at up to 2.7 MHz. Additional high-speed transfers may be initiated without resending
the Hs mode byte by generating a repeat start without a stop. The device switches out of Hs mode with the next
stop condition.
Table 1. Quick-Reference of Command Codes
COMMAND
CODE
General-call reset
Address byte of 00h followed by a data byte of 06h.
High-speed mode
00001xxx, with SCL ≤ 400 kHz; where xxx are bits unique to the Hs-capable master. This
byte is called the Hs master code.
7.3.3 General-Call Reset and Power-Up
The device responds to a general-call reset, which is an address byte of 00h (0000 0000) followed by a data byte
of 06h (0000 0110). The device acknowledges both bytes. Table 1 provides a reference for the general-call reset
command code. Upon receiving a general-call reset, the device performs a full internal reset, as though it was
powered off and then on. The device always acknowledges the general-call address byte of 00h (0000 0000), but
does not acknowledge any general-call data bytes other than 06h (0000 0110).
The device automatically performs a reset when powered up. As part of the reset, the device is configured for all
outputs to change to the last programmed nonvolatile memory values, or 1000000000 if the nonvolatile memory
values are not programmed.
7.3.4 Output Voltage
The buffer output values are determined by the analog supply voltage (VS) and the decimal value of the binary
input code used to program that buffer. The value is calculated using Equation 1:
CODE10
VOUT = VS ´
1024
(1)
The device outputs are capable of a full-scale voltage output change in typically 5 μs; no intermediate steps are
required.
7.3.5 Updating the DAC Output Voltages
Updating the digital-to-analog converter (DAC) and the VCOM register is not the same as updating the DAC and
VCOM output voltage because the device features a double-buffered register structure. There are two methods
for updating the DAC and VCOM output voltages.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
11
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
Method 1: Method 1 is used when the DAC and VCOM output voltage are desired to change immediately after
writing to a DAC register. For each write transaction, the master sets data bit 15 to a 1. The DAC and VCOM
output voltage update occurs after receiving the 16th data bit for the currently-written register.
Method 2: Method 2 is used when all DAC and VCOM output voltages are desired to change at the same time.
First, the master writes to the desired DAC and VCOM channels with data bit 15 a 0. Then, when writing the last
desired DAC and VCOM channel, the master sets data bit 15 to a 1. All DAC and VCOM channels are updated
at the same time after receiving the 16th data bit.
7.3.6 DIE_ID and DIE_REV Registers
The user can verify the presence of the BUF16821-Q1 in the system by reading from address 111101. When
read at this address, the BUF16821-Q1A returns 0101100100100111 and the BUF16821-Q1B returns
0101100100100100.
The user can also determine the die revision of the device by reading from register 111100. The device returns
0000000000000000 when a RevA die is present. RevB is designated by 0000000000000001, and so on.
7.3.7 Read and Write Operations
Read and write operations can be done for a single DAC and VCOM or for multiple DACs and VCOMs. Writing
to a DAC and VCOM register differs from writing to the nonvolatile memory. Bits D15–D14 of the most significant
byte of data determine if data are written to the DAC and VCOM register or the nonvolatile memory.
7.3.7.1 Read and Write: DAC and VCOM Register (Volatile Memory)
The device is able to read from a single DAC and VCOM, or multiple DACs and VCOMs, or write to the register
of a single DAC and VCOM, or multiple DACs and VCOMs in a single communication transaction. The DAC
pointer addresses begin with 000000 (which corresponds to OUT1) through 001111 (which corresponds to
OUT16). Addresses 010010 and 010011 are VCOM1 and VCOM2, respectively.
Write commands are performed by setting the read and write bit low. Setting the read or write bit high performs a
read transaction.
7.3.7.2 Writing: DAC and VCOM Register (Volatile Memory)
To
1.
2.
3.
write to a single DAC and VCOM register:
Send a start condition on the bus.
Send the device address and read and write bit = low. The device acknowledges this byte.
Send a DAC and VCOM pointer address byte. Set bit D7 = 0 and D6 = 0. Bits D5–D0 are the DAC and
VCOM address. Although the device acknowledges 000000 through 010111, data are stored and returned
only from these addresses:
– 000000 through 001111
– 010010 through 010011
The device returns 0000 for reads from 010000 through 010001, and 010100 through 010111. See Table 4
for valid DAC and VCOM addresses.
4. Send two bytes of data for the specified register. Begin by sending the most significant byte first (bits
D15–D8, of which only bits D9 and D8 are used, and bits D15–D14 must not be 01), followed by the least
significant byte (bits D7–D0). The register is updated after receiving the second byte.
5. Send a stop or start condition on the bus.
The device acknowledges each data byte. If the master terminates communication early by sending a stop or
start condition on the bus, the specified register is not updated. Updating the DAC and VCOM register is not the
same as updating the DAC and VCOM output voltage; see the Updating the DAC Output Voltages section.
The process of updating multiple DAC and VCOM registers begins the same as when updating a single register.
However, instead of sending a stop condition after writing the addressed register, the master continues to send
data for the next register. The device automatically and sequentially steps through subsequent registers as
additional data are sent. The process continues until all desired registers are updated or a stop or start condition
is sent.
12
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
To
1.
2.
3.
write to multiple DAC and VCOM registers:
Send a start condition on the bus.
Send the device address and read or write bit = low. The device acknowledges this byte.
Send either the OUT1 pointer address byte to start at the first DAC, or send the pointer address byte for
whichever DAC and VCOM is the first in the sequence of DACs and VCOMs to be updated. The device
begins with this DAC and VCOM and steps through subsequent DACs and VCOMs in sequential order.
4. Send the bytes of data; begin by sending the most significant byte (bits D15–D8, of which only bits D9 and
D8 have meaning, and bits D15–D14 must not be 01), followed by the least significant byte (bits D7–D0).
The first two bytes are for the DAC and VCOM addressed in the previous step. The DAC and VCOM register
is automatically updated after receiving the second byte. The next two bytes are for the following DAC and
VCOM. That DAC and VCOM register is updated after receiving the fourth byte. This process continues until
the registers of all following DACs and VCOMs are updated. The device continues to accept data for a total
of 18 DACs; however, the two data sets following the 16th data set are meaningless. The 19th and 20th data
sets apply to VCOM1 and VCOM2. The write disable bit cannot be accessed using this method. This bit must
be written to using the write to a single DAC register procedure.
5. Send a stop or start condition on the bus.
The device acknowledges each byte. To terminate communication, send a stop or start condition on the bus.
Only DAC registers that have received both bytes of data are updated.
7.3.7.3 Reading: DAC, VCOM, Other Register (Volatile Memory)
Reading a register returns the data stored in that DAC, VCOM, other register.
To
1.
2.
3.
4.
5.
6.
7.
8.
read a single DAC, VCOM, other register:
Send a start condition on the bus.
Send the device address and read or write bit = low. The device acknowledges this byte.
Send the DAC, VCOM, other pointer address byte. Set bit D7 = 0 and D6 = 0; bits D5–D0 are the DAC,
VCOM, other address. Note that the device stores and returns data only from these addresses:
– 000000 through 001111
– 010010
– 010011
– 111100 through 111111
The device returns 0000 for reads from 010000 and 010001, and 010100 through 010111. See Table 4 for
valid DAC, VCOM, other addresses.
Send a start or stop and start condition.
Send the correct device address and read or write bit = high. The device acknowledges this byte.
Receive two bytes of data. These bytes are for the specified register. The most significant byte (bits D15–D8)
is received first; next is the least significant byte (bits D7–D0). In the case of DAC and VCOM channels, bits
D15–D10 have no meaning.
Acknowledge after receiving the first byte.
Send a stop or start condition on the bus or do not acknowledge the second byte to end the read transaction.
Communication may be terminated by sending a premature stop or start condition on the bus, or by not
acknowledging.
To
1.
2.
3.
read multiple registers:
Send a start condition on the bus.
Send the device address and read or write bit = low. The device acknowledges this byte.
Send either the OUT1 pointer address byte to start at the first DAC, or send the pointer address byte for
whichever register is the first in the sequence of DACs and VCOMs to be read. The device begins with this
DAC and VCOM and steps through subsequent DACs and VCOMs in sequential order.
4. Send a start or stop and start condition on the bus.
5. Send the correct device address and read or write bit = high. The device acknowledges this byte.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
13
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
6. Receive two bytes of data. These bytes are for the specified DAC and VCOM. The first received byte is the
most significant byte (bits D15–D8; only bits D9 and D8 have meaning), next is the least significant byte (bits
D7–D0).
7. Acknowledge after receiving each byte of data.
8. When all desired DACs are read, send a stop or start condition on the bus.
Communication may be terminated by sending a premature stop or start condition on the bus, or by not sending
the acknowledge bit. Reading the DieID, DieRev, and MaxBank registers is not supported in this mode of
operation (these values must be read using the single register read method).
7.3.7.4 Write: Nonvolatile Memory for the DAC Register
The device is able to write to the nonvolatile memory of a single DAC and VCOM in a single communication
transaction. In contrast to the BUF20820, writing to multiple nonvolatile memory words in a single transaction is
not supported. Valid DAC and VCOM pointer addresses begin with 000000 (which corresponds to OUT1)
through 001111 (which corresponds to OUT16). Addresses 010010 and 010011 are VCOM1 and VCOM2,
respectively.
When programming the nonvolatile memory, the analog supply voltage must be between 9 V and 20 V. Write
commands are performed by setting the read or write bit low.
To write to a single nonvolatile register:
1. Send a start condition on the bus.
2. Send the device address and read or write bit = low. The device acknowledges this byte. Although the device
acknowledges 000000 through 010111, data are stored and returned only from these addresses:
– 000000 through 001111
– 010010 and 010011
The device returns 0000 for reads from 010000 through 010001, and 010100 through 010111. See Table 4
for DAC and VCOM addresses.
3. Send a DAC and VCOM pointer address byte. Set bit D7 = 0 and D6 = 0. Bits D5–D0 are the DAC and
VCOM address.
4. Send two bytes of data for the nonvolatile register of the specified DAC and VCOM. Begin by sending the
most significant byte first (bits D15–D8, of which only bits D9 and D8 are data bits, and bits D15–D14 must
be 01), followed by the least significant byte (bits D7–D0). The register is updated after receiving the second
byte.
5. Send a stop condition on the bus.
The device acknowledges each data byte. If the master terminates communication early by sending a stop or
start condition on the bus, the specified nonvolatile register is not updated. Writing a nonvolatile register also
updates the DAC and VCOM register and output voltage.
The DAC and VCOM register and DAC and VCOM output voltage are updated immediately, while the
programming of the nonvolatile memory takes up to 250 μs. When a nonvolatile register write command is
issued, no communication with the device should take place for at least 250 μs. Writing or reading over the serial
interface while the nonvolatile memory is being written jeopardizes the integrity of the data being stored.
7.3.7.5 Read: Nonvolatile Memory for the DAC Register
To read the data present in nonvolatile register for a particular DAC and VCOM channel, the master must first
issue a general acquire command, or a single acquire command with the appropriate DAC and VCOM channel
chosen. This action updates both the DAC and VCOM registers and DAC and VCOM output voltages. The
master may then read from the appropriate DAC and VCOM register as described earlier.
14
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
A6
Figure 11. Write DAC Register Timing
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
A4
A4
A6
A6
SDA_In
Device_Out
Start
A3
A3
A5
A5
A4
A4
A5
A5
A4
A4
A3
A3
Device Address
A2
A2
A5
A5
A4
A4
A3
A3
Device Address
A2
A2
A1
A1
A1
A1
A3
A3
Device Address
Read multiple DAC registers. P4-P0 specify DAC address.
A6
SCL
A6
SDA_In
Start
Device_Out
SCL
A5
A5
Read single DAC register. P4-P0 specify DAC address.
A6
SDA_In
Start
Device_Out
SCL
A6
Device Address
A2
A2
A1
A1
A0
A0
A0
A0
A2
A2
W
W
Write
W
W
Write
A1
A1
A0
A0
A0
A0
D7
D7
Ackn
Ackn
Ackn
D7
D7
Read operation.
Ackn
Ackn
Ackn
W
W
Write
W
W
Write
Read operation.
Write multiple DAC registers. P4-P0 specify DAC address.
A6
SDA_In
Device_Out
SCL
Start
Write single DAC register. P4-P0 specify DAC address.
D7
D7
D7
D7
D5
D5
D6
D6
D6
D5
D5
D5
D5
P4
P4
P3
P3
P2
P2
D6
D6
D5
D5
P4
P4
P3
P3
P2
P2
P1
P1
P1
P1
P4
P4
Start DAC address pointer. D7-D5 must be 000.
D6
P4
P4
P3
P3
P2
P2
P0
P0
P0
P0
P3
P3
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
P2
P2
P1
P1
P1
P1
Start
Start
DAC address pointer. D7-D5 must be 000.
D6
D6
DAC address pointer. D7-D5 must be 000.
DAC address pointer. D7-D5 must be 000.
Ackn
Ackn
Ackn
Write Operation
Ackn
Ackn
Ackn
Write Operation
D14
D14
D14
D14
A3
A3
A4
A3
A3
Device Address
A4
D14
D14
D15
D13
D13
D11
D11
D10
D10
D13
D13
D12
D12
D11
D11
D10
D10
DAC (pointer) MSbyte. D14 must be 0.
Device Address
A4
D12
D12
D9
D9
D8
D8
Ackn
Ackn
D7
D7
D9
D9
D8
D8
Ackn
Ackn
Ackn
D7
D7
A2
A2
A2
A2
A1
A1
A1
A1
A0
A0
A0
A0
D12
D12
D11
D11
D9
D9
D10
D10
D8
D8
R
R
Read
R
R
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
D7
D7
D15
D15
D15
D11
D11
D10
D10
D9
D9
D6
D6
D6
D6
D8
D8
D13
D12
D12
D11
D11
D10
D10
D6
D6
D14
D14
D5
D5
D13
D13
D11
D11
D4
D4
D3
D3
DAC 20 LSbyte.
D12
D12
D2
D2
D10
D10
D4
D4
D3
D3
DAC LSbyte
D9
D9
Ackn
Ackn
Ackn
D5
D5
D1
D1
D9
D9
D0
D0
D8
D8
D8
D8
D4
D4
Ackn
D1
D1
D0
D0
Ackn
Ackn
Ackn
D1
D1
D0
D0
Ackn
Ackn
D7
D7
D6
D6
D5
D5
D5
D5
D4
D4
D2
D2
D4
D4
D3
D3
DAC LSbyte.
D3
D3
DAC 20 LSbyte
is updated at this moment.
Stop
D2
D2
D1
D1
D15
D15
D1
D1
D14
D14
D0
D0
D0
D0
Stop
Stop
No Ackn
No Ackn
Ackn
Ackn
Ackn
D13
D13
DAC (pointer + 1) MSbyte. D14 must be 0.
The entire DAC register D9-D0
D2
D2
Ackn
is updated at this moment.
The entire DAC register D9-D0
D2
D2
Stop
D6
D6
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
D7
D7
D3
D3
DAC (pointer) LSbyte
D5
D5
DAC (pointer) MSbyte. D15-D10 have no meaning.
D14
D13
DAC MSbyte. D15-D10 have no meaning.
D14
D12
D13
D15
D12
D13
Ackn
Ackn
D14
D15
Read
D14
D15
DAC 20 (VCOM OUT2) MSbyte. D14 must be 0.
If D15 = 1, all DACs are updated when the current DAC register is updated.
D15
D15
A4
D13
D13
Ackn
If D15 = 1, all DACs are updated when the current DAC register is updated.
D15
D15
DAC MSbyte. D14 must be 0.
DAC 20 (VCOM OUT2) MSbyte. D15-D10 have no meaning.
A5
A5
A5
A5
Ackn
Ackn
Ackn
Ackn
Ackn
D15
A6
A6
A6
A6
P0
P0
P0
P0
Ackn
www.ti.com
SBOS712 – MAY 2014
BUF16821-Q1
Figure 12. Read Register Timing
Submit Documentation Feedback
15
16
A6
A6
SDA_In
Device_Out
SCL
Start
A5
A5
A4
A4
A3
A3
Device Address
Figure 13. Write Nonvolatile Register Timing
Submit Documentation Feedback
Product Folder Links: BUF16821-Q1
A1
A0
W
W
Ackn
Ackn
D6
D6
D5
D5
P4
P4
P3
P3
P2
P2
A5
A5
A4
A4
A3
A3
Device address.
A2
A2
A1
A1
P1
A0
A0
P1
A6
A6
SDA_In
Device_Out
Start
A5
A5
A4
A4
A3
A3
Device address.
A2
A2
A1
A1
A0
A0
P0
P0
W
W
Write
W
W
Write
Single channel acquire command. P4-P0 must specify and valid DAC address.
A6
Start
A6
SCL
D7
D7
DAC address pointer. D7-D0 must be 000.
General acquire command. P4-P0 must specify and valid DAC address.
A0
Ackn
Write operation.
SDA_In
SCL
A1
Write
Device_Out
A2
A2
Write single OTP register. P4-P0 specify DAC address.
D15
D15
D7
D7
Ackn
Ackn
Ackn
D7
D7
Write Operation
Ackn
Ackn
Ackn
Write Operation
Ackn
Ackn
Ackn
D14
D14
D12
D12
D11
D11
D10
D10
D9
D9
D8
D8
D5
D5
P4
P4
P3
P3
P2
P2
D6
D6
D5
D5
P4
P4
P3
P3
P2
P2
DAC address pointer. D7-D5 must be 010.
D6
D6
DAC address pointer. D7-D5 must be 100.
D13
D13
DAC MSbyte. D15-D14 must be 01.
P1
P1
P1
P1
Ackn
Ackn
Ackn
P0
P0
P0
P0
D7
D6
D6
Ackn
Ackn
Ackn
Ackn
Ackn
Ackn
D7
D5
Stop
Stop
D5
D4
D4
D2
D2
D1
D1
D0
D0
Ackn
Ackn
Ackn
t2
Stop
t2: minimum 100ms, maximum 2ms.
The OTP register (D9-D0) is updated at this moment.
t1: > 20ms before falling edge of clock.
D3
D3
DAC LSbyte.
Write supply active.
Write signal active.
t1
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
Figure 14. Acquire Operation Timing
Copyright © 2014, Texas Instruments Incorporated
Figure 15. General-Call Reset Timing
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
SDA
SCL
SDA
SCL
Start
High-Speed Command
Start
General-Call Reset Command
Address Byte = 00h
Address Byte = 00001xxx (HS Master Code)
Ackn
Ackn
Device enters high-speed mode at ACK clock pulse.
Device exits high-speed mode with stop condition.
No Ackn
Device begins reset at arrow and is in reset until ACK clock pulse.
Then the device acquires memory, etc., as it does at power-up.
Address Byte = 06h
www.ti.com
SBOS712 – MAY 2014
BUF16821-Q1
Figure 16. High-Speed Mode Timing
Submit Documentation Feedback
17
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
7.3.8 Output Protection
The device output stages can safely source and sink the current levels indicated in Figure 2 and Figure 3.
However, there are other modes where precautions must be taken to prevent the output stages from being
damaged by excessive current flow. The outputs (OUT1 through OUT16, VCOM1 and VCOM2) include
electrostatic discharge (ESD) protection diodes, as shown in Figure 17. Normally, these diodes do not conduct
and are passive during typical device operation. Unusual operating conditions can occur where the diodes may
conduct, potentially subjecting them to high, even damaging current levels. These conditions are most likely to
occur when a voltage applied to an output exceeds (VS) + 0.5 V, or drops below GND – 0.5 V.
One common scenario where this condition can occur is when the output pin is connected to a sufficiently large
capacitor and the device power-supply source (VS) is suddenly removed. Removing the power-supply source
allows the capacitor to discharge through the current-steering diodes. The energy released during the high
current flow period causes the power dissipation limits of the diode to be exceeded. Protection against the high
current flow may be provided by placing current-limiting resistors in series with the output; see Figure 19. Select
a resistor value that restricts the current level to the maximum rating for the particular pin.
VS
Device
ESD Current-Steering
Diodes
OUTx or VCOMx
Figure 17. Output Pins ESD Protection Current-Steering Diodes
18
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
7.4 Device Functional Modes
7.4.1 End-User Selected Gamma Control
The device is well-suited for providing two levels of gamma control by using the BKSEL pin because the device
has two banks of nonvolatile memory, as shown in Figure 18. When the state of the BKSEL pin changes, the
device updates all 18 programmable buffer outputs simultaneously after 750 μs (±80 μs).
To update all 18 programmable output voltages simultaneously via hardware, toggle the BKSEL pin to switch
between gamma curve 0 (stored in Bank0) and gamma curve 1 (stored in Bank1).
All DAC and VCOM registers and output voltages are updated simultaneously after approximately 750 μs.
5V
Device
BKSEL
OUT1
Change in
Output Voltages
Bank0
Bank1
Switch
OUT16
2
IC
Figure 18. Gamma Control
7.4.2 Dynamic Gamma Control
Dynamic gamma control is a technique used to improve the picture quality in LCD television applications. This
technique typically requires switching gamma curves between frames. Using the BKSEL pin to switch between
two gamma curves does not often provide good results because of the 750 μs required to transfer the data from
the nonvolatile memory to the DAC register. However, dynamic gamma control can still be accomplished by
storing two gamma curves in an external electrically erasable programmable read-only memory (EEPROM) and
writing directly to the DAC register (volatile).
The double register input structure saves programming time by allowing updated DAC values to be pre-stored
into the first register bank. Storage of this data can occur while a picture is still being displayed. Because the
data are only stored into the first register bank, the DAC and VCOM output values remain unchanged—the
display is unaffected. At the beginning or the end of a picture frame, the DAC and VCOM outputs (and therefore,
the gamma voltages) can be quickly updated by writing a 1 in bit 15 of any DAC and VCOM register. For details
on the operation of the double register input structure, see the Updating the DAC Output Voltages section.
To update all 18 programmable output voltages simultaneously via software, perform the following actions:
STEP 1: Write to registers 1–18 with bit 15 always 0.
STEP 2: Write any DAC and VCOM register a second time with identical data. Make sure that bit 15 is set to 1.
All DAC and VCOM channels are updated simultaneously after receiving the last bit of data.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
19
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
7.5 Programming
7.5.1 Addressing the Device
The device address 111010x, where x is the state of the A0 pin. When the A0 pin is low, the device
acknowledges on address 74h (1110100). If the A0 pin is high, the device acknowledges on address 75h
(1110101). Table 2 shows the A0 pin settings and device address options.
Other valid addresses are possible through a simple mask change. Contact your TI representative for
information.
Table 2. Quick-Reference of Device Addresses
20
DEVICE, COMPONENT
(Device Address)
ADDRESS
A0 pin is low
(device acknowledges on address 74h)
1110100
A0 pin is high
(device acknowledges on address 75h)
1110101
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
Device
(1)
(1)
VCOM2
1
VCOM2
VCOM1
28
2
OUT1
OUT16
27
3
OUT2
OUT15
26
4
OUT3
OUT14
25
5
OUT4
6
OUT5
7
OUT6
8
GNDA
VCOM1
(1)
(1)
(1)
(1)
(1)
(1)
Source
Driver
(1)
(1)
GNDA
(2)
VS
24
23
VS
100 nF
10 mF
(1)
(1)
(2)
OUT13
22
OUT12
21
(1)
Source
Driver
(1)
9
VS
OUT11
20
10
OUT7
OUT10
19
11
OUT8
12
OUT9
VS
100 nF
10 mF
(1)
(1)
(1)
Source
Driver
Source
Driver
GNDD
(2)
18
(1)
3.3 V
1 mF
BKSEL
17
13 VSD
A0
16
SCL
SDA
15
100 nF
14
Timing
Controller
(1) RC combination optional; see the Output Protection section.
(2) GNDA and GNDD must be connected together.
Figure 19. Typical Application Configuration
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
21
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
7.5.2 Nonvolatile Memory
7.5.2.1 BKSEL Pin
The device has 16x rewrite capability of the nonvolatile memory. Additionally, the device is capable of storing two
distinct gamma curves in two different nonvolatile memory banks, each of which has 16x rewrite capability. One
of the two available banks is selected using the external input pin, BKSEL. When this pin is low, Bank0 is
selected; when this pin is high, Bank1 is selected.
When the BKSEL pin changes state, the device acquires the last programmed DAC and VCOM values from the
nonvolatile memory associated with this newly chosen bank. At power-up, the state of the BKSEL pin determines
which memory bank is selected.
The I2C master can also update (acquire) the DAC registers with the last programmed nonvolatile memory
values using software control. The bank to be acquired depends on the state of BKSEL.
7.5.2.2 General Acquire Command
A general acquire command is used to update all registers and DAC and VCOM outputs to the last programmed
values stored in nonvolatile memory. A single-channel acquire command updates only the register and DAC and
VCOM output of the DAC and VCOM corresponding to the DAC and VCOM address used in the single-channel
acquire command.
These are the steps of the sequence to initiate a general channel acquire:
1. Be sure BKSEL is in its desired state and is stable for at least 1 ms.
2. Send a start condition on the bus.
3. Send the appropriate device address (based on A0) and the read or write bit = low. The device
acknowledges this byte.
4. Send a DAC and VCOM pointer address byte. Set bit D7 = 1 and D6 = 0. Bits D5–D0 are any valid DAC and
VCOM address. Although the device acknowledges 000000 through 010111, data are stored and returned
only from these addresses:
– 000000 through 001111
– 010010 and 010011
The device returns 0000 for reads from 010000 and 010001, and 010100 through 010111. See Table 4 for
valid DAC and VCOM addresses.
5. Send a stop condition on the bus.
Approximately 750 μs (±80 μs) after issuing this command, all DAC and VCOM registers and DAC and VCOM
output voltages change to the respective, appropriate nonvolatile memory values.
7.5.2.3 Single-Channel Acquire Command
These are the steps to initiate a single-channel acquire:
1. Be sure BKSEL is in its desired state and is stable for at least 1 ms.
2. Send a start condition on the bus.
3. Send the device address (based on A0) and read or write bit = low. The device acknowledges this byte.
4. Send a DAC and VCOM pointer address byte using the DAC and VCOM address corresponding to the
output and register to update with the OTP memory value. Set bit D7 = 0 and D6 = 1. Bits D5–D0 are the
DAC and VCOM address. Although the device acknowledges 000000 through 010111, data are stored and
returned only from these addresses:
– 000000 through 001111
– 010010 and 010011
The device returns 0000 reads from 010000 and 010001, and 010100 through 010111. See Table 4 for valid
DAC and VCOM addresses.
5. Send a stop condition on the bus.
Approximately 36 μs (±4 μs) after issuing this command, the specified DAC and VCOM register and DAC and
VCOM output voltage change to the appropriate OTP memory value.
22
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
7.5.2.4 MaxBank
The device can provide the user with the number of times the nonvolatile memory of a particular DAC and VCOM
channel nonvolatile memory is written to for the current memory bank. This information is provided by reading the
register at pointer address 111111.
There are two ways to update the MaxBank register:
1. After initiating a single acquire command, the device updates the MaxBank register with a code
corresponding to how many times that particular channel memory is written to.
2. Following a general acquire command, the device updates the MaxBank register with a code corresponding
to the maximum number of times the most used channel (OUT1–16 and VCOMs) is written to.
MaxBank is a read-only register and is only updated by performing a general- or single-channel acquire.
Table 3 shows the relationship between the number of times the nonvolatile memory is programmed and the
corresponding state of the MaxBank Register.
Table 3. MaxBank Details
NUMBER OF TIMES WRITTEN TO
RETURNS CODE
0
0000
1
0000
2
0001
3
0010
4
0011
5
0100
6
0101
7
0110
8
0111
9
1000
10
1001
11
1010
12
1011
13
1100
14
1101
15
1110
16
1111
7.5.2.5 Parity Error Correction
The device provides single-bit parity error correction for data stored in the nonvolatile memory to provide
increased reliability of the nonvolatile memory. If a single bit of nonvolatile memory for a channel fails, the device
corrects for the failure and updates the appropriate DAC with the intended value when its memory is acquired.
If more than one bit of nonvolatile memory for a channel fails, the device does not correct for it, and updates the
appropriate DAC and VCOM with the default value of 1000000000.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
23
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
7.6 Register Maps
Table 4. DAC Register Pointer Addresses
24
DAC REGISTER
POINTER ADDRESS
OUT1
000000
OUT2
000001
OUT3
000010
OUT4
000011
OUT5
000100
OUT6
000101
OUT7
000110
OUT8
000111
OUT9
001000
OUT10
001001
OUT11
001010
OUT12
001011
OUT13
001100
OUT14
001101
OUT15
001110
OUT16
001111
VCOM1
010010
VCOM2
010011
OTHER REGISTER
POINTER ADDRESS
Die_Rev
111100
Die_ID
111101
MaxBank
111111
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
8 Application and Implementation
8.1 Application Information
The BUF16821-Q1 is a multichannel programmable voltage reference. Featuring 16 programmable gamma
reference outputs and two programmable VCOM outputs, the device is designed to interface between timing
controllers and source drivers commonly used in LCD displays.
8.2 Typical Application
I/O
BKSEL
Timing Controller
SCL
SDA
SCL
SDA
OUT1
.
BUF16821 .
.
OUT16
Source Driver
Figure 20. Gamma Control Block Diagram
8.2.1 Design Requirements
If the nonvolatile memory has never been programmed, the BUF16821-Q1 outputs defaults to VS / 2 following
power-up. Refer to the Power Supply Recommendations section for proper power-supply sequencing
requirements. Figure 21 shows the typical output response when the analog power supply (VS) ramps to its
desired value. When the analog supply is below 2 V, the outputs follow the analog supply voltage. After the
analog supply voltage (VS) exceeds approximately 2 V, the outputs begin to track at VS / 2. This sequence is
illustrated in Figure 21.
If the nonvolatile memory is pre-programmed, the device outputs ramp to their pre-programmed values.
Figure 22 and Figure 23 illustrate the power-up behavior of the device pre-programmed to a 4-V and 8-V output
voltage, respectively. Note that when the analog power supply voltage (VS) exceeds approximately 5 V, the
device performs an automatic read of the nonvolatile memory, acquiring the pre-programmed values to ensure
the proper output value when the analog supply voltage ramps to its final value. During the nonvolatile memory
acquire operation, the output tracks at VS / 2 for approximately 1 ms. This sequence is illustrated in Figure 22
and Figure 23 . Note that the minimum valid analog supply voltage, VS, is specified as 9 V. Below this value the
outputs should not be considered valid.
Figure 24 illustrates the device output response to a general-call reset. During the internal reset, the output
momentarily tracks at VS / 2 while the nonvolatile memory values are acquired. Following the reset, the output
returns to the pre-programmed value.
8.2.2 Detailed Design Procedure
Proper power-supply bypassing is required when using the BUF16821-Q1. TI recommends connecting a 10-μF
capacitor in parallel with a 100-nF capacitor at each analog supply pin (pins 9 and 23), as illustrated in Figure 19.
Similarly, connecting a 1-μF capacitor in parallel with a 100-nF capacitor at the digital supply pin (pin 13) is also
recommended. However, adding more than 200-pF capacitance at any gamma or VCOM output is not
recommended; see the Output Protection section.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
25
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
Typical Application (continued)
8.2.3 Application Curves
Output Volatge
Analog Supply Voltage
Voltage (2 V/div)
Voltage (2 V/div)
Output Voltage
Analog Supply Voltage
Time (2 ms/div)
Time (2 ms/div)
Figure 21. Power-On Response Prior to Programming the
Nonvolatile Memory
Figure 22. Power-On Response with Nonvolatile Memory
Programmed for 4-V Output
Output Voltage
Analog Supply Voltage
Voltage (2 V/div)
Voltage (2 V/div)
Output Voltage
Analog Supply Voltage
Time (2 ms/div)
Time (2 ms/div)
Figure 23. Power-On Response with Nonvolatile Memory
Programmed for 8-V Output
Figure 24. Output Response to a General-Call Reset
9 Power Supply Recommendations
The device can be powered using an analog supply voltage from 9 V to 20 V, and a digital supply from 2 V to
5.5 V. The digital supply must be applied before the analog supply to avoid excessive current and power
consumption, or possibly even damage to the device if left connected only to the analog supply for extended
periods of time.
26
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
10 Layout
10.1 Layout Guidelines
10.1.1 General PowerPAD Design Considerations
The device is available in a thermally-enhanced PowerPAD package. This package is constructed using a
downset leadframe upon which the die is mounted; see Figure 25(a) and Figure 25(b). This arrangement results
in the lead frame being exposed as a thermal pad on the underside of the package; see Figure 25(c). This
thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by providing
a good thermal path away from the thermal pad.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
Figure 25. Views of a Thermally-Enhanced PWP Package
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications that have
low power dissipation. This technique provides the necessary thermal and mechanical connection between the
lead frame die pad and the PCB.
The PowerPAD must be connected to the most negative supply voltage on the device, GNDA and GNDD.
1. Prepare the PCB with a top-side etch pattern. There should be etching for the leads as well as etch for the
thermal pad.
2. Place recommended holes in the area of the thermal pad. Ideal thermal land size and thermal via patterns for
the HTSSOP-28 PWP package can be seen in the technical brief, PowerPAD Thermally-Enhanced Package
(SLMA002), available for download at www.ti.com. These holes should be 13 mils (0.33 mm) in diameter.
Keep these holes small, so that solder wicking through the holes is not a problem during reflow. An example
thermal land pattern mechanical drawing is attached to the end of this data sheet.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area to help
dissipate the heat generated by the device. These additional vias may be larger than the 13-mil diameter
vias directly under the thermal pad. These vias can be larger because they are not in the thermal pad area to
be soldered; thus, wicking is not a problem.
4. Connect all holes to the internal plane that is at the same voltage potential as the GND pins.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
27
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
Layout Guidelines (continued)
5. When connecting these holes to the internal plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This configuration makes the soldering of vias that have plane
connections easier. In this application, however, low thermal resistance is desired for the most efficient heat
transfer. Therefore, the holes under the device PowerPAD package should make their connection to the
internal plane with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the pins of the package and the thermal pad area with its twelve
holes exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This masking
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all device pins.
8. With these preparatory steps in place, simply place the device in position and run the chip through the solder
reflow operation as any standard surface-mount component. This preparation results in a properly installed
part.
For a given RθJA (listed in the Electrical Characteristics), the maximum power dissipation is shown in Figure 26
and calculated by Equation 2:
TMAX - TA
PD =
qJA
(
)
where
•
•
•
PD = maximum power dissipation (W),
TMAX = absolute maximum junction temperature (125°C), and
TA = free-ambient air temperature (°C).
(2)
Maximum Power Dissipation (W)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100
TA, Free-Air Temperature (°C)
Figure 26. Maximum Power Dissipation
vs Free-Air Temperature
(With PowerPAD Soldered Down)
28
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
BUF16821-Q1
www.ti.com
SBOS712 – MAY 2014
10.2 Layout Example
To Source
Drivers
GND
VS
SCL
VSD BKSEL SDA
To Timing Controller
Figure 27. PCB Layout Example
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
29
BUF16821-Q1
SBOS712 – MAY 2014
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• BUF16821EVM-USB User's Guide, SBOU106
• BUF20820 Data Sheet, SBOS330
• PowerPAD Thermally-Enhanced Package, SLMA002
• Driving Capacitive Loads with Gamma Buffers, SBOA134
11.2 Trademarks
PowerPAD is a trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: BUF16821-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
BUF16821AIPWPRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
PWP
28
2000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
B16821Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
OTHER QUALIFIED VERSIONS OF BUF16821-Q1 :
• Catalog: BUF16821
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BUF16821AIPWPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BUF16821AIPWPRQ1
HTSSOP
PWP
28
2000
367.0
367.0
38.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated