IRFR320, IRFU320, SiHFR320, SiHFU320 Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Dynamic dV/dt Rating 400 RDS(on) (Ω) VGS = 10 V Qg (Max.) (nC) 1.8 Available • Repetitive Avalanche Rated • Surface Mount (IRFR320/SiHFR320) 20 Qgs (nC) 3.3 • Straight Lead (IRFU320/SiHFU320) Qgd (nC) 11 • Available in Tape and Reel Configuration RoHS* COMPLIANT • Fast Switching Single • Ease of Paralleling D DPAK (TO-252) • Lead (Pb)-free Available IPAK (TO-251) DESCRIPTION G S N-Channel MOSFET Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU/SiHFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. ORDERING INFORMATION Package Lead (Pb)-free SnPb DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251) IRFR320PbF IRFR320TRLPbFa IRFR320TRPbFa IRFR320TRRPbFa IRFU320PbF SiHFR320-E3 SiHFR320TL-E3a SiHFR320T-E3a SiHFR320TR-E3a SiHFU320-E3 IRFR320 IRFR320TRLa IRFR320TRa IRFR320TRRa IRFU320 SiHFR320 SiHFR320TLa SiHFR320Ta SiHFR320TRa SiHFU320 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Currenta VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL LIMIT VDS VGS 400 ± 20 3.1 2.0 12 0.33 0.020 160 3.1 4.2 42 2.5 4.0 - 55 to + 150 260d ID IDM Pulsed Drain Linear Derating Factor Linear Derating Factor (PCB Mount)e EAS Single Pulse Avalanche Energyb Repetitive Avalanche Currenta IAR EAR Repetitive Avalanche Energya Maximum Power Dissipation TC = 25 °C PD TA = 25 °C Maximum Power Dissipation (PCB Mount)e Peak Diode Recovery dV/dtc dV/dt Operating Junction and Storage Temperature Range TJ, Tstg Soldering Recommendations (Peak Temperature) for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 °C, L = 29 mH, RG = 25 Ω, IAS = 3.1 A (see fig. 12). c. ISD ≤ 3.1 A, dI/dt ≤ 65 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). UNIT V A W/°C mJ A mJ W V/ns °C www.kersemi.com 1 IRFR320, IRFU320, SiHFR320, SiHFU320 THERMAL RESISTANCE RATINGS SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient PARAMETER RthJA - - 110 Maximum Junction-to-Ambient (PCB Mount)a RthJA - - 50 Maximum Junction-to-Case (Drain) RthJC - - 3.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance VDS VGS = 0 V, ID = 250 µA 400 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.51 - V/°C VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V nA IGSS IDSS RDS(on) gfs VGS = ± 20 V - - ± 100 VDS = 400 V, VGS = 0 V - - 25 VDS = 320 V, VGS = 0 V, TJ = 125 °C - - 250 - - 1.8 Ω VDS = 50 V, ID = 1.9 A 1.7 - - S VGS = 0 V, VDS = - 25 V, f = 1.0 MHz, see fig. 5 - 350 - - 120 - - 47 - - - 20 - - 3.3 ID = 1.9 Ab VGS = 10 V µA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs VGS = 10 V ID = 3.3 A, VDS = 320 V, see fig. 6 and 13b pF nC Gate-Drain Charge Qgd - - 11 Turn-On Delay Time td(on) - 10 - - 14 - - 30 - - 13 - - 4.5 - - 7.5 - - - 3.1 - - 12 - - 1.6 V - 270 600 ns - 1.4 3.0 µC Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 200 V, ID = 3.3 A, RG = 18 Ω, RD = 56 Ω, see fig. 10b tf Internal Drain Inductance LD Internal Source Inductance LS Between lead, 6 mm (0.25") from package and center of die contact ns D nH G S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode A G S TJ = 25 °C, IS = 3.1 A, VGS = 0 Vb TJ = 25 °C, IF = 3.3 A, dI/dt = 100 A/µsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. www.kersemi.com 2 D IRFR320, IRFU320, SiHFR320, SiHFU320 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.kersemi.com 3 IRFR320, IRFU320, SiHFR320, SiHFU320 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.kersemi.com 4 Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area IRFR320, IRFU320, SiHFR320, SiHFU320 RD VDS VGS D.U.T. RG + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case www.kersemi.com 5 IRFR320, IRFU320, SiHFR320, SiHFU320 L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T RG + - I AS V DD VDS 10 V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.kersemi.com 6 Fig. 13b - Gate Charge Test Circuit IRFR320, IRFU320, SiHFR320, SiHFU320 Peak Diode Recovery dV/dt Test Circuit + D.U.T Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test Driver gate drive P.W. + Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel www.kersemi.com 7