[AK7770] AK7770EQ Audio DSP with Multi-Channel Audio CODEC GENERAL DESCRIPTION The AK7770 is a digital signal processor with an integrated 4-channel audio ADC and a 6-channel audio DAC, as well as an S/PDIF transmitter. It utilizes an enhanced dual bit architecture that results in wide dynamic range for the ADC, and the advanced multi-bit architecture of the DAC enables wide dynamic range and low out-of-band noise. Two sample-rate converters are integrated, allowing for operation at 48kHz sampling rate with input rates of 32kHz, 44.1kHz, or 48kHz. Volume control, compression, EQ and sound processing are performed by the DSP. In addition, delay adjustment up to 70ms is possible for four output channels through the integrated delay RAM. The AK7770 is packaged in a space-saving 80-pin LQFP package. FEATURES ■ DSP - Data Width: 24-bit (Data RAM F20.4 floating Point) - Processing Speed: 13.5 ns (1536step/fs; fs = 48kHz) - Multiplication: 20 x 16 → 36-bit Double precision arithmetic available - Program RAM: 1536 x 36-bit - Coefficient RAM: 1536 x 16-bit - Offset RAM: 64 x 14-bit - DRAM: 14kword (1word = F16.4 floating point) - Sample Rate: fs = 48kHz - Master / Slave operation ■ 4:2 Selector with Input Pre-amp ■ 4ch 24-bit ADC ■ - 64-times oversampling - Sample Rate: 48kHz - S/(N+D): 84dB (fs = 48kHz) - DR, S/N: 96dB (fs = 48kHz) - Digital HPF for offset DC cancellation - Channel independent Digital Volume control (+24/-103dB, 0.5dB step) - Soft Mute 6ch 24-bit DAC - 128-times oversampling - Sample Rate: 48kHz - S/(N+D): 88dB (fs = 48kHz ) - DR, S/N: 100dB - Channel independent Digital Volume control (+12/-115dB, 0.5dBstep) - Soft Mute - Digital de-emphasis MS0699-E-01-PB -1- 2008/06 [AK7770] ■ Stereo Headphone Amplifier with Volume Control - DAC3 direct connection - S/(N+D): 73dB (fs=48kHz) - S/N: 86dB (fs=48kHz) - Analog volume control (+0/-50dB,1.0/2.0/4.0dB per step) - Output power: 22.5mW@16Ω - No click noise at power ON/OFF Headphone Detection Circuit (denounce circuit) ■ ■ High Tolerance to Clock Jitter ■ Sample Rate Converter - Dual 2ch SRC - Input sample rate: 32kHz~48kHz - Output sample rate: 48kHz fixed ■ DIT - S/PDIF, IEC958, AES/EBU, EIAJ CP1201 - Output Selector (DIT or Through) - 24 bit interface format - 16 bit interface format CMOS Level Digital I/F (for 3.3V) ■ ■ Master Clock Input: 256fs (fs=48kHz) ■ Master Clock Output: 128fs, 192fs, 256fs, 384fs ■ Three Digital Audio Inputs ■ I²C µP I/F ■ Power Supply: +3.3V ±0.3V, +1.8V ±0.1V ■ Temperature Range: -10°C~70°C ■ Package: 80pin LQFP (0.5mm pitch) MS0699-E-01-PB -2- 2008/06 [AK7770] ■ Block Diagram AOUTL1,AOUTR1 AOUTL2,AOUTR2 VCOM 2 FROL2,FROR2 FRIL2,FRIR2 2 HMUTEN 2 2 VREF HPA DAC1 DAC2 DAC3 SDINDA1 SDINDA2 SDINDA3 2 HPL,HPR HVCOM HDT ADC2 ASEL2[1:0] AINL1,AINR1 2 AINL2,AINR2 2 SDOUTAD2 AINL3,AINR3 2 SDOUTAD1 AINL4,AINR4 2 HVDD VSS2 3 AVDD 3 VSS1 ADC1 ASEL1[1:0] 4 DVDD 3 4 DVDD18 4 VSS3 FRIL1,FRIR1 FROL1,FROR1 2 2 LFLT pull down XTO Hi-z Open Drain CLKGEN XTI External system clock 0 internal system clock 0 CLKOE CLKO SELCLK BITCLKO BITCLKO MCLKO MBITCLKO Internal system clock 3 LRCLKOE LRCLKO MLRCLK O SELCKDIT 1 0 SELDITI[1:0] SDIN3 3 2 1 0 CLK3 DIV BITCLK3 DIT DIT SELTX[1:0] DITO MCLK3 DIN4 DOUT5 DIN3 DOUT4 0 1 2 3 TX LRCLK3 External system clock 3 SELO3[1:0] 3 2 1 0 DOUT3 OUT3 SDOUT3 SELO2[1:0] SDIN2 SRCO2 SRCI2 DOUT2 SRC DIV CLK2 MCLK2 BITCLK2 LRCLK2 3 2 1 0 DIN2 SRCO2 3 2 1 0 DOUT1 UNLOCK2 External system clock 2 SDIN1 SRCI1 SRCO1 SRC External system clock 1 DIV CLK1 BITCLK1 LRCLK1 MCLK1 MICIF SRCO1 CONT SDOUT1 SO TESTI3 CAD1 SCL CAD0 SDA * CLK0 SRCMCK1 DSP SRCBICK1 SRCLRCK1 UNLOCK1 2 OUT1 DIN1 HPEN WDT HPEN HP Detect "L" WDTEN CRC STATUS STO CRCE INITRSTN TESTI2 CKM[1:0] TESTI SDOUT2 SELO1[1:0] SRCMCK2 SRCBICK2 SRCLRCK2 OUT2 LOCK2E ROM LOCK1E Figure 1. Block Diagram Figure 1shows a simplified diagram of the AK7770, which is not the perfect same as the actual circuit diagram. MS0699-E-01-PB -3- 2008/06 [AK7770] CP0,CP1 DLP0,DLP1 DP0,DP1 DLRAM DRAM 1536w × 24bit CRAM 1536w × 16bit OFREG 64w X 14bit 14kw × 20bit CBUS(16bit) DBUS(24bit) MPX16 Micon I/F MPX20 Control X Y Serial I/F PRAM DEC 1536w × 36bit Multiply 16bit×20bit→ 36bit PC Stack : 5level(max) TMP 8×24bit 24bit 36bit PTMP(LIFO) 6×24bit MUL DBUS SHIFT 40bit 40bit A B ALU 40bit Overflow Margin: 4bit 2×24bit DIN4 2×24bit DIN3 2×24bit DIN2 2×24bit DIN1 40bit DR0 ~ 3 40bit Over Flow Data Generator Division 20÷20→20 2×24/20/16bit DOUT5 2×24/20/16bit DOUT4 2×24bit DOUT3 2×24bit DOUT2 2×24bit DOUT1 Peak Detector Figure 2. AK7770 DSP Block Diagram MS0699-E-01-PB -4- 2008/06 [AK7770] ■ Ordering Information -10 ∼ +70°C Evaluation board AK7770EQ AKD7770 80pin LQFP (0.5mm pitch) HPEN TX STO DVDD VSS3 SDIN3 DVDD18 BITCLK3 CLK3 LRCLK3 TESTI3 CKM[1] HDT HVDD HPR HVCOM VSS2 HPL AOUTR2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AOUTL2 ■ Pin Assignment AOUTR1 AOUTL1 61 40 SDA 62 39 DVDD18 VSS1 63 38 VSS3 AVDD 64 37 DVDD FRIR2 FROR2 65 36 SCL 66 35 CAD0 FROL2 67 34 CAD1 FRIL2 68 33 SDIN2 AINR1 AINL1 69 32 BITCLK2 31 CLK2 AINR2 71 30 LRCLK2 AINL2 72 AINR3 73 AINL3 80 pin LQFP 70 29 SDIN1 28 BITCLK1 74 27 CLK1 AINR4 75 26 LRCLK1 AINL4 76 25 DVDD18 VSS1 77 24 VSS3 VCOM 78 23 DVDD AVDD 79 22 XTI FROR1 80 21 XTO SDOUT3 SDOUT1 SDOUT2 CLKO BITCLKO LRCLKO VSS3 DVDD DVDD18 TESTI2 INITRSTN HMUTEN TESTI CKM[0] VSS1 AVDD FROL1 LFLT FRIL1 FRIR1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (TOP VIEW) pin Input Output I/O Power MS0699-E-01-PB -5- 2008/06 [AK7770] PIN FUNCTION No. 1 2 3 Pin name FRIR1 FRIL1 FROL1 4 LFLT 5 6 7 AVDD VSS1 TESTI 8 CKM [0] 9 10 HMUTEN INITRSTN 11 TEST2 12 13 14 15 DVDD18 VSS3 DVDD LRCLKO 16 CLKO 17 BITCLKO 18 SDOUT1 19 SDOUT2 20 SDOUT3 21 XTO 22 XTI 23 24 25 DVDD VSS3 DVDD18 MS0699-E-01-PB I/O Function Classification I Rch Feedback Resistance Input Pin for ADC1 Analog I Lch Feedback Resistance Input Pin for ADC1 O Lch Feedback Resistance Output Pin for ADC1 At initial reset, this pin goes Hi-Z. O Loop Filter Pin. Connect a 10nF cap to AVDD. The output is AVDD at initial reset - Analog Power Supply Pin 3.3V (typ) Analog power supply - Analog Ground Pin 0V (connected to silicon substrate) I Test Pin (Internal pull-down) Test Connect to GND. Mode choice I Clock Mode Selection Pin Connect to GND. I Headphone Amplifier Mute Pin Headphones I Reset Pin (for initialization) Reset Use to initialize the AK7770. I Test Pin Test Connect to GND. Digital power - Digital Power Supply Pin 1.8V(typ) supply - Digital Ground Pin 0V - Digital Power Supply Pin 3.3V(typ) O Left/right Clock Output Pin System clock The output in initial reset is “L”. O Clock Output Pin The output in initial reset is “L”. O Bit Clock Output Pin The output in initial reset is “L”. Serial data O Serial Data Output 1 Pin The output in initial reset is “L”. O Serial Data Output 2 Pin The output in initial reset is “L”. O Serial Data Output 3 Pin The output in initial reset is “L”. O Crystal Oscillator Output Pin A system clock Connect a crystal oscillator between the XTI pin and XTO pin. Leave open when using an external clock source. The output in initial reset is undetermined. I Crystal Oscillator Input Pin Connect a crystal oscillator between the XTI pin and XTO pin. Input an external clock into the XTI pin when not using a crystal oscillator. Digital power - Digital Power Supply Pin 3.3V(typ) supply - Digital Ground Pin 0V - Digital Power Supply Pin 1.8V(typ) -6- 2008/06 [AK7770] No. Pin name I/O 26 LRCLK1 I Left/Right Clock Input 1 Pin System clock 27 28 29 30 CLK1 BITCLK1 SDIN1 LRCLK2 I I I I Master Clock 1 Pin Bit Clock 1 Pin Serial Data Input 1 Pin Left/Right Clock Input 2 Pin Serial data System clock 31 32 33 34 35 36 CLK2 BITCLK2 SDIN2 CAD1 CAD0 SCL I I I I I I Master Clock 2 Pin Bit Clock 2 Pin Serial Data Input 2 Pin I2C Bus Address Pin 1 I2C Bus Address Pin 0 I2C Clock Pin I2C interface I2C interface I2C interface 37 DVDD - Digital Power Supply Pin 3.3V(typ) 38 VSS3 - Digital Ground Pin 0V 39 40 DVDD18 SDA 41 HPEN 42 STO 43 TX 44 DVDD 45 VSS3 46 DVDD18 47 SDIN3 I Serial Data Input 3 Pin 48 BITCLK3 I Bit Clock 3 Pin 49 CLK3 I Master Clock 3 Pin 50 LRCLK3 I 51 CKM [1] I 52 TESTI3 I Left/Right Clock 3 Pin Clock Mode Selection Pin Connect to GND. Test Pin This pin must be connected to DVDD. MS0699-E-01-PB Function Classification Digital power supply - Digital Power Supply Pin 1.8V(typ) I/O I2C Bus Data Clock Pin I2C interface SDA goes to “Hi-Z” during initial reset. O Headphone Detect Output Pin Headphones Initial reset for headphone search is determined by the state of HDT O Status Output Pin Status When HDT = “H”, STO = “L” When HDT = “L”, STO = “H” The output in initial reset is “H” S/PDIF transmitter Output Pin O TX S/PDIF data is output when SELTX [1:0] bit= “00”. “L” during initial rest. - Digital Power Supply Pin 3.3V(typ) Digital power - Digital Ground Pin 0V supply - Digital Power Supply Pin 1.8V(typ) Serial data System clock -7- Mode selection Test 2008/06 [AK7770] No. Pin name I/O Function 53 HDT I Headphone Detection Pin Headphone Rch Output Pin 54 HPR O Output is VSS2 at initial reset Headphone Power Supply Pin 3.3V(typ) Classification Headphones Headphones Analog power supply 55 HVDD - 56 HVCOM O 57 VSS2 - 58 HPL O 59 AOUTR2 O 60 AOUTL2 O 61 AOUTR1 O 62 AOUTL1 O 63 VSS1 - 64 AVDD - 65 FROR2 O 66 FRIR2 I ADC2 Rch Feedback Resistance Input Pin Analog input 67 FRIL2 I ADC2 Lch Feedback Resistance Input Pin Analog input 68 FROL2 O 69 70 71 72 73 74 75 76 AINR1 AINL1 AINR2 AINL2 AINR3 AINL3 AINR4 AINL4 I I I I I I I I 77 VSS1 Headphone Common Voltage Output Pin Connect a of 1μF cap to VSS2. Do not use for an outside circuits. Output at Headphones initial reset is VSS2 Analog power Headphone Ground Pin 0V supply Headphone Lch Output Pin Headphone Output is VSS2 at initial reset output DAC2 Rch Output Pin Output at initial reset is VSS1 DAC2 Lch Output Pin Output at initial reset is VSS1 Analog output DAC1 Rch Output Pin Output at initial reset is VSS1 DAC1 Lch Output Pin Output at initial reset is VSS1 Analog power Analog Ground Pin 0V (connected to silicon substrate) supply Analog power Analog Power Supply Pin 3.3V (typ) supply ADC2 Rch Feedback Resistance Output Pin Analog output The output at initial reset is Hi-Z ADC2 Lch Feedback Resistance Input Pin The output at initial reset is Hi-Z. ADC Rch Single-ended Input 1 Pin ADC Lch Single-ended Input 1 Pin ADC Rch Single-ended Input 2 Pin ADC Lch Single-ended Input 2 Pin ADC Rch Single-ended Input 3 Pin ADC Lch Single-ended Input 3 Pin ADC Rch Single-ended Input 4 Pin ADC Lch Single-ended Input 4 Pin Analog output Analog input - Analog Power Supply Pin 0.0V Analog power supply Analog output Analog power supply 78 VCOM Analog Common Voltage Output Pin Output at initial reset is VSS1. Connect capacitors of 0.1uF and 2.2uF O between this pin and VSS1. No external circuits should be connected to this pin. 79 AVDD - Analog Power Supply Pin 3.3V (typ) 80 FROR1 O Rch Feedback Resistance Output Pin for ADC1 The output in initial reset is Hi-Z Analog output Note 1. Do not leave digital input pins floating. Note 2. When analog input pins (AINL1-4 pins, AINR1-4) are not used, leave them open. MS0699-E-01-PB -8- 2008/06 [AK7770] ■ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name FRIR1-2, FRIL1-2, FROL1-2, FROR1-2, XTO, AOUTL1-2, AOUTR1-2, AINL1-4, AINR1-4 LRCLKO,CLKO, BITCLKO, SDOUT1-3, HPEN, HPR, HPL TESTI2, CLK1-3, BITCLK1-3, LRCLK1-3 SDIN1-3, HDT HMUTEN Setting These pins should be open. These pins should be open. These pins should be connected to VSS3. This pin should be connected to DVDD. ABSOLUTE MAXIMUM RATINGS (VSS1 = VSS2 = VSS3=0V: Note 3) Parameter Symbol min max Power supply voltage Analog AVDD -0.3 4.3 Analog HVDD -0.3 4.3 Digital DVDD -0.3 4.3 Digital DVDD18 -0.3 2.5 Input current (except power supply pins) IIN ±10 Analog input voltage VINA AINL1~AINL4, AINR1~AINR4 -0.3 AVDD+0.3 FRIL1, FRIL2, FRIR1, FRIL2 Digital input voltage VIND -0.3 DVDD+0.3 Ambient operating temperature Ta -10 70 Storage temperature Tstg -65 150 Note 3. All voltages referred to ground. Connect VSS1, VSS2, VSS3 to the same ground plane. Units V V V V mA V V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OERATING CONDITIONS (VSS1 = VSS2 = VSS3=0V: Note 3) Parameter Symbol min typ max Supply Analog AVDD 3.0 3.3 3.6 voltage Analog HVDD 3.0 3.3 3.6 Digital DVDD 3.0 3.3 3.6 Digital DVDD18 1.7 1.8 1.9 Difference HVDD-AVDD -0.3 0 +0.3 Difference HVDD-DVDD -0.3 0 +0.3 Difference AVDD-DVDD -0.3 0 +0.3 Units V V V V V V V Note 4. The power supply sequence for AVDD HVDD, DVDD, DVDD18 is not critical but all power supplies must be On before start operating the AK7770. Note 5. Do not turn off the power supply of the AK7770 with the power supply of the surrounding device turned on. DVDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for DVDD in the SDA and SCL pins.) *AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. MS0699-E-01-PB -9- 2008/06 [AK7770] ANALOG CHARACTERISTICS ■ ADC1/2 (Ta=25 °C; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=0V; Signal frequency = 1kHz; Measurement bandwidth =20Hz~20kHz , fs=48kHz fs; SRC reset; unless otherwise specified) Parameter min typ max Units Feedback Resistance 10 30 kΩ (Note 6) 99 dB Pre-AMP S/(N+D) S/N (A-weighted) (Note 6) 105 dB Load Capacitance 20 pF Resolution 24 Bits Pre-AMP Dynamic characteristics S/(N+D) fs = 48kHz (-1dBFS) 74 84 dB + Dynamic range fs = 48kHz (A-weighted) ADC1 88 96 dB (Note 7, Note 8) ADC2 S/N fs = 48kHz (A-weighted) (Note 7) 85 96 dB Interchannel Isolation( (f=1kHz) (Note 9) 85 100 dB DC Accuracy Gain mis-match between channels 0.1 0.3 dB ADC1 ADC2 Analog input Input voltage 2.05 2.2 2.35 Vp-p Note 6. Value measured with an input resistance of 47kΩ and a feedback resistance of 16kΩ with a 2Vrms input voltage. Note 7. The value measured through the pre-amp and ADC with an input resistance of 47kΩ and a feedback resistance of 16kΩ with a 2Vrms input voltage. Note 8. S/(N+D) with an input signal of -60dBFS Note 9. Isolation between AINL1-4, AINR1-4 with a -1dBFS input signal. Note 10. When the SRC on DIT operate asynchronously, the performance may be degraded. ■ DAC1/2 (Ta= 25°C; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=0V; Signal frequency = 1kHz; Measurement bandwidth =20Hz~20kHz, fs=48kHz fs; SRC reset; unless otherwise specified) Parameter min typ max Units Resolution 24 Bits DAC1 DAC2 Dynamic characteristics S/(N+D) (0 dBFS) 78 88 dB Dynamic range (A-weighted) (Note 11) 92 100 dB S/N (A-weighted) 92 100 dB Interchannel Isolation (f=1kHz) (Note 12) 90 100 dB DC Accuracy Gain mis-match between channels 0.2 0.5 dB Analog output Output voltage (Note 13) 2.02 2.18 2.34 Vp-p Load resistance 5 kΩ Load capacitance 30 pF Note 11. S/(N+D) with a -60dBFS input signal Note 12. Isolation between Lch-Rch between each DAC Note 13. Full scale output voltage MS0699-E-01-PB - 10 - 2008/06 [AK7770] ■ DAC3 + HP Amp (Ta=25°C; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=0V; Signal frequency = 1kHz; Measurement bandwidth =20Hz~20kHz , fs=48kHz fs; SRC reset; fs=48kHzs) Parameter min typ max Units Maximum (OPGA[4:0] bits= “1FH”) Minimum (OPGA[4:0] bits= “01H”) Step size 0.1 +0dB ∼ -16dB -16dB ∼ -38dB 0.1 -38dB ∼ -50dB Headphone-Amp Characteristics: DAC → HPL/HPR pins, RL=16Ω Output Voltage 1.53 63 S/(N+D) (−3dBFS) S/N (A-weighted) 80 Inter channel Isolation 60 Inter channel Gain Mismatch Load Resistance (RL, Figure 3) 16 Load Capacitance (C1, Figure 3) Load Capacitance (C2, Figure 3) - +0 -50 1 2 4 - dB dB dB dB dB 1.7 73 86 80 0.1 - 1.87 0.5 30 300 Vpp dB dB dB dB Ω pF pF Analog Volume Control Characteristics OPGA): Gain Measurement Point HP-Amp HPL pin HPR pin 47μF − + + C1 0.22μF C2 RL 10Ω Figure 3. Headphone amplifier output circuit MS0699-E-01-PB - 11 - 2008/06 [AK7770] ■ SRC (SRC1, SRC2) (Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=0V; Input signal frequency = 1kHz; measurement bandwidth = 20Hz to FSO/2, fs=48kHz) Parameter Symbol min typ Resolution Input Sample Rate FSI 32 Output Sample Rate FSO 48 THD+N (Input= 1kHz, 0dBFS) FSO/FSI=48kHz/44.1kHz -112 FSO/FSI=48kHz/32kHz -112 Dynamic Range (Input= 1kHz, -60dBFS) FSO/FSI=48kHz/44.1kHz 113 FSO/FSI=48kHz/32kHz 113 Dynamic Range (Input= 1kHz, -60dBFS, A-weighted) FSO/FSI=48kHz/32kHz 115 Ratio between Input and Output Sample Rate FSO/FSI 0.98 max 24 48 - Units Bits kHz kHz dB dB dB dB dB - 1.5 DC CHARACTERISTICS (Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, VSS1 = VSS2 = VSS3=0V) Parameter Symbol min typ max High level input voltage (Note 14) VIH 80%DVDD Low level input voltage (Note 14) VIL 20%DVDD SCL, SDA high level input voltage VIH 70%DVDD SCL, SDA low level input voltage VIL 30%DVDD HDT high level input voltage VIH 85%HVDD HDT low level input voltage VIL 45%HVDD VOH DVDD-0.5 High level output voltage Iout=-100μA VOL 0.5 Low level output voltage Iout=100μA (Note 15) SDA low level output voltage Iout=3mA VOL 0.4 Input leakage current (Note 16) Iin ±10 Input leakage current pull-down pin (Note 17) Iid 22 Input leakage current XTI pin Iix 26 Units V V V V V V V V V μA μA μA Note 14. SCL, SDA and HDT pins are not included. Note 15. The SDA pin is not included Note 16. Pull-down pins and the XTI pin are not included. Note 17. Pull-down pins (Typ 150k) and TESTI [Description rule] Regarding the input/output levels in the text, the low level will be represented as “L”, and the high level as “H”. In principle, “0” and “1” will be used to represent the bus (serial/parallel) such as registers. ##h means hexadecimal code. (#=0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F) MS0699-E-01-PB - 12 - 2008/06 [AK7770] POWER CONSUMPTION (Ta=25°C; AVDD=HVDD=DVDD=3.0~3.6V(typ=3.3V, max=3.6V); DVDD18=1.7~1.9V(typ=1.8V, max=1.9V); VSS1= VSS2 = VSS3=0V) Parameter min typ max Units Power Supply Power supply electric current Normal Operation AVDD 75 mA HVDD 6 mA DVDD 5 mA DVDD18 (Note 18) 58 85 mA AVDD+HVDD+DVDD 120 mA Reset (INITRSTN pin = “L” reference data) AVDD+HVDD+DVDD+DVDD18 (Note 19) 2 mA Note 18. DVDD18 value varies with use frequency and DSP program contents. Note 19. This is a reference value when using a crystal oscillator. Since most of the supply current at the initial reset state is in the oscillator section, the value may vary slightly according to the crystal type and the external circuit. This is a “reference data” only. DIGITAL FILTER CHARACTERISTICS ■ ADC1/2 (Ta=-10°C ~70°C; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V; fs=48kHz; Parameter Symbol min typ max PassBand (±0.1dB) (Note 21) PB 0 18.9 (-0.2dB) 20.0 (-3.0dB) 23.0 Stopband SB 28 Passband Ripple (Note 21) PR ±0.04 Stop band attenuation SA 68 (Note 22, Note 23) Group Delay deviation ∆GD 0 Group Delay (Ts=1/fs) GD 16 Digital filter + analog filter ±0.5 Amplitude characteristic 20Hz~20.0kHz (Note 24) Note 20) Units kHz kHz kHz kHz dB dB μs Ts dB Note 20. Frequency of each amplitude characteristic is in proportion to fs (sampling rate). The characteristic of the high pass filter is not included. Note 21. The passband is from DC to 18.9kHz when fs=48kHz. Note 22. Attenuation frequency is 48kHz to 3.044MHz when fs=48kHz. Note 23. When fs = 48kHz, the analog modulator samples the input signal at 3.072MHz. There is no attenuation of an input signal in band (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3…) of integer times the sampling frequency of the digital filter. Note 24. Value through Pre-Amp and ADC. External input resistance is 47kΩ, and feedback resistance is 16kΩ. MS0699-E-01-PB - 13 - 2008/06 [AK7770] ■ DAC1-3 (Ta=-10°C ~70°C; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V; fs=48kHz; DEM=OFF) Parameter Symbol min typ max Units Passband (±0.05dB) (Note 25) PB 0 21.7 kHz (-6.0dB) 24 kHz Stopband (Note 25) SB 26.2 kHz Passband ripple PR ±0.01 dB Stopband Attenuation SA 64 dB Group delay (Ts=1/fs) (Note 26) GD 24 Ts Digital filter + analog filter Amplitude characteristic ±0.5 dB 20Hz~20.0kHz Note 25. The pass band and stop band frequencies are proportional to “fs” (system sampling rate), and represents PB=0.4535 * fs (@ -0.05dB), and SB=0.5465 * fs, respectively. Note 26. The digital filter’s delay is calculated as the time from setting data into the input register until an analog signal is output. ■ SRC1/2 (Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V) Parameter Symbol min typ max Units PB 0 0.4583FSI kHz Passband -0.01dB (0.980≤FSO/FSI≤1.500) SB 0.5417FSI kHz Stop Band (0.980≤FSO/FSI≤1.500) Passband ripple PR dB ± 0.01 Stop band attenuation SA 102.2 dB Group Delay (Ts=1/fs) (Note 27) GD 56 Ts Note 27. SRC delay time is calculated from the start of SRCLRCK just after data input to the start of LRCLKO just after data output, when there is no phase difference between SRCLRCK and LRCLKO. MS0699-E-01-PB - 14 - 2008/06 [AK7770] SWITCHING CHARACTERISTICS ■ System Clock (Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V) Parameter Sysmbol Min typ max XTI a) with a crystal oscillator fXTI 12.288 b) with an external clock Duty cycle ratio 40 11.0 2.0 Duty cycle ratio 40 Clock speed 256 CLK1, CLK2 Frequency (Note 28) LRCLK1, LRCLK2 Frequency (Note 29) BITCLK1, BITCLK2 Frequency High level width Low level width CLK3 Frequency Duty cycle ratio (Note 28) fXTI fCK fs 8 tBCLKH tBCLKL 150 150 fCK 11.0 40 Clock speed LRCLK3 Frequency 50 fs 43 MHz 12.288 60 12.4 50 % MHz MHz 50 60 % 1024 fs 48.4 kHz 48 ns ns 12.288 50 256 (Note 29) Units 48 50 60 MHz % 1024 fs 48.4 kHz BITCLK3 Frequency High level width tBCLKH 150 Low level width tBCLKL 150 Note 28. CLKn and LRCLKn must occur in the same period, but phase matching is not critical. Note 29. The sample rate must match LRCLK. ns ns ■ Reset (Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V) Parameter Symbol Min typ max INITRSTN (Note 30) tRST 600 Note 30. Power supply must be up and a master clock must be present before initializing reset. MS0699-E-01-PB - 15 - Units ns 2008/06 [AK7770] ■ Audio System Interface 1. SDIN1~SDIN3, SDOUT1~SDOUT3 (Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1 = VSS2 = VSS3=0V; CL=20pF) Parameter Symbol min typ max Units Input Delay time from BITCLKn “↑”to LRCLK (Note 31) tBLRD 20 ns Delay time from LRCLKn to BITCLKn “↑” (Note 31) tLRBD 20 ns Serial data entry latch setup time tBSIDS 80 ns Serial data entry latch hold time tBSIDH 80 ns Output BITCLKO frequency fBCLK 64 fs BITCLKO duty cycle ratio 50 % Delay time from BITCLKO “↓” to LRCLKO tMBL -20 40 ns Delay time from LRCLKO to SDOUTn (Only MSB) tLRD 80 ns Delay time from BITCLKO to SDOUTn tBSOD 80 ns SDINn → SDOUTn (Note 32) Delay time from SDINn to SDOUTn tIOD 50 ns Note 31. BITCLKn “↑” must not occur at the same time as LRCKn edge Note 32. SDIN1 → SDOUT1: control register setting SELO1[1:0]= “11”, OUT1E=1 SDIN2 → SDOUT2: control register setting SELO2[1:0]= “11”, OUT2E=1 SDIN3 → SDOUT3: control register setting SELO3[1:0]= “11”, OUT3E=1 MS0699-E-01-PB - 16 - 2008/06 [AK7770] ■ Microcontroller Interface (I2CBUS Interface) (Ta=-10°C ~70°C; AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1= VSS2 = VSS3=0V) Parameter Symbol min typ max Unit I2C Timing SCL clock frequency fSCL 400 kHz Bus Free Time Between Transmissions tBUF 1.3 μs Start Condition Hold Time tHD:STA 0.6 μs (prior to first Clock pulse) Clock Low Time tLOW 1.3 μs Clock High Time tHIGH 0.6 μs Setup Time for Repeated Start Condition tSU:STA 0.6 μs SDA Hold Time from SCL Falling tHD:DAT 0 0.9 μs SDA Setup Time from SCL Rising tSU:DAT 0.1 μs Rise Time of Both SDA and SCL Lines tR 0.3 μs Fall Time of Both SDA and SCL Lines tF 0.3 μs Setup Time for Stop Condition tSU:STO 0.6 μs Pulse Width of Spike Noise Suppress By Input Filter tSP 0 50 ns Capacitive load on bus Cb 400 pF Note 33. I2C is a registered trademark of Philips Semiconductors. MS0699-E-01-PB - 17 - 2008/06 [AK7770] ■ Timing Diagram 1/fXTI 1/fXTI tXTI=1/fXTI XTI VIH VIL 1/fs ts=1/fs 1/fs LRCLKn VIH n = 1, 2, 3 VIL 1/fBCLK 1/fBCLK tBCLK=1/fBCLK BITCLKn VIH n = 1, 2, 3 VIL tBCLKH tBCLKL Figure 4. System Clock INITRSTN tRST VIL Figure 5. Reset MS0699-E-01-PB - 18 - 2008/06 [AK7770] LRCLKn 50%DVDD LRCLKO tMBL tMBL tLRBD tBLRD BITCLKn 50%DVDD BITCLKO tLRD tBSOD SDOUT* 50%DVDD tBSIDS tBSIDH 50%DVDD SDIN* SDIN*=SDIN1, SDIN2, SDIN3 SDOUT*=SDOUT1, SDOUT2, SDOUT3 Figure 6. Audio System Interface VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA Start tSU:STO Stop Figure 7. Microcontroller Interface (I2C bus) MS0699-E-01-PB - 19 - 2008/06 [AK7770] PACKAGE 80-pin LQFP (Unit: mm ) 14.0±0.2 12.0±0.2 41 61 40 80 21 12.0±0.2 1 0.125+0.10 -0.05 0.50±0.2 0.08 0.10 M 1.85MAX 0.50 0° ~ 10° 1.40±0.2 1.25TYP 20 0.20±0.1 +0.15 0.10 -0.10 14.0±0.2 60 ■ Materials and lead Specification Package: Lead frame: Lead-finish: MS0699-E-01-PB Epoxy Copper Soldering plate (Pb free) - 20 - 2008/06 [AK7770] MARKING AKM AK7770EQ XXXXXXX 1) 2) 3) 4) Pin #1 indication Date Code: XXXXXXX(7digits) Marking Code: AK7770EQ Asahi Kasei Logo REVISION HISTORY Date (YY/MM/DD) 08/01/08 Revision 00 Reason First Edition Page Contents 08/06/24 01 Error Correct 15 SWITCHING CHARACTERISTICS ■System Clock CLK1, CLK2 Frequency; 11.0 → 2.0 MS0699-E-01-PB - 21 - 2008/06 [AK7770] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. Thank you for your access to AKEMD products information. More detail product information is available, please contact our sales office or authorized distributors. MS0699-E-01-PB - 22 - 2008/06