NXP K40P100M72SF1 K40 sub-family Datasheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: K40P100M72SF1
Rev. 3, 11/2012
K40P100M72SF1
K40 Sub-Family
Supports: MK40DX128VLL7,
MK40DX256VLL7, MK40DX64VMC7,
MK40DX128VMC7, MK40DX256VMC7
Features
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– Multiple low-power modes to provide power
optimization based on application requirements
– 16-channel DMA controller, supporting up to 63
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
• Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– 128-bit unique identification (ID) number per chip
• Human-machine interface
– Segment LCD controller supporting up to 36
frontplanes and 8 backplanes, or 40 frontplanes and
4 backplanes, depending on the package size
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
• Analog modules
– Two 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– 12-bit DAC
– Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
• Timers
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Two 2-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
• Communication interfaces
– USB full-/low-speed On-the-Go controller with onchip transceiver
– Controller Area Network (CAN) module
– Two SPI modules
– Two I2C modules
– Five UART modules
– I2S module
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................3
6 Peripheral operating requirements and behaviors....................22
1.1 Determining valid orderable parts......................................3
6.1 Core modules....................................................................22
2 Part identification......................................................................3
6.1.1
Debug trace timing specifications.........................22
2.1 Description.........................................................................3
6.1.2
JTAG electricals....................................................22
2.2 Format...............................................................................3
6.2 System modules................................................................25
2.3 Fields.................................................................................3
6.3 Clock modules...................................................................25
2.4 Example............................................................................4
6.3.1
MCG specifications...............................................25
3 Terminology and guidelines......................................................4
6.3.2
Oscillator electrical specifications.........................27
3.1 Definition: Operating requirement......................................4
6.3.3
32 kHz Oscillator Electrical Characteristics...........30
3.2 Definition: Operating behavior...........................................5
6.4 Memories and memory interfaces.....................................30
3.3 Definition: Attribute............................................................5
6.4.1
Flash electrical specifications................................30
3.4 Definition: Rating...............................................................6
6.4.2
EzPort Switching Specifications............................35
3.5 Result of exceeding a rating..............................................6
6.5 Security and integrity modules..........................................36
3.6 Relationship between ratings and operating
6.6 Analog...............................................................................36
requirements......................................................................6
6.6.1
ADC electrical specifications.................................36
3.7 Guidelines for ratings and operating requirements............7
6.6.2
CMP and 6-bit DAC electrical specifications.........43
3.8 Definition: Typical value.....................................................7
6.6.3
12-bit DAC electrical characteristics.....................46
3.9 Typical value conditions....................................................8
6.6.4
Voltage reference electrical specifications............49
4 Ratings......................................................................................9
6.7 Timers................................................................................50
4.1 Thermal handling ratings...................................................9
6.8 Communication interfaces.................................................50
4.2 Moisture handling ratings..................................................9
6.8.1
USB electrical specifications.................................50
4.3 ESD handling ratings.........................................................9
6.8.2
USB DCD electrical specifications........................51
4.4 Voltage and current operating ratings...............................9
6.8.3
USB VREG electrical specifications......................51
5 General.....................................................................................10
6.8.4
CAN switching specifications................................52
5.1 AC electrical characteristics..............................................10
6.8.5
DSPI switching specifications (limited voltage
5.2 Nonswitching electrical specifications...............................10
range)....................................................................52
5.2.1
Voltage and current operating requirements.........11
6.8.6
DSPI switching specifications (full voltage range).53
5.2.2
LVD and POR operating requirements.................11
6.8.7
I2C switching specifications..................................55
5.2.3
Voltage and current operating behaviors..............12
6.8.8
UART switching specifications..............................55
5.2.4
Power mode transition operating behaviors..........13
6.8.9
I2S/SAI Switching Specifications..........................55
5.2.5
Power consumption operating behaviors..............14
5.2.6
Designing with radiated emissions in mind...........18
6.9.1
TSI electrical specifications...................................60
5.2.7
Capacitance attributes..........................................18
6.9.2
LCD electrical characteristics................................61
5.3 Switching specifications.....................................................19
6.9 Human-machine interfaces (HMI)......................................60
7 Dimensions...............................................................................62
5.3.1
Device clock specifications...................................19
7.1 Obtaining package dimensions.........................................62
5.3.2
General switching specifications...........................19
8 Pinout........................................................................................62
5.4 Thermal specifications.......................................................20
8.1 K40 Signal Multiplexing and Pin Assignments..................62
5.4.1
Thermal operating requirements...........................20
8.2 K40 Pinouts.......................................................................67
5.4.2
Thermal attributes.................................................21
9 Revision History........................................................................69
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
2
Freescale Semiconductor, Inc.
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to www.freescale.com and perform a part number search for
the following device numbers: PK40 and MK40 .
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K40
A
Key attribute
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
3
Terminology and guidelines
Field
Description
Values
FFF
Program flash memory size
•
•
•
•
•
•
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
•
•
•
•
•
•
•
•
•
•
•
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
MJ = 256 MAPBGA (17 mm x 17 mm)
CC
Maximum CPU frequency (MHz)
•
•
•
•
•
5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK40DN512ZVMD10
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
4
Freescale Semiconductor, Inc.
Terminology and guidelines
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
5
Terminology and guidelines
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
–0.3
Max.
1.2
Unit
V
3.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
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Freescale Semiconductor, Inc.
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
e
Op
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rat
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mi
rat
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Op
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)
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.)
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Op
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(m
.)
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Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
g
lin
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Ha
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rat
n.)
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Ha
g
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ing
rat
ax
(m
.)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
Handling (power off)
∞
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
7
Terminology and guidelines
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
IWP
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
8
Freescale Semiconductor, Inc.
Ratings
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
VDD
Description
Min.
Max.
Unit
Digital supply voltage
–0.3
3.8
V
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
9
General
Symbol
IDD
Description
Max.
Unit
—
185
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
5.5
V
VAIO
Analog1, RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Maximum current single pin limit (applies to all digital pins)
–25
25
mA
ID
Digital supply current
Min.
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
VUSB_DP
USB_DP input voltage
–0.3
3.63
V
VUSB_DM
USB_DM input voltage
–0.3
3.63
V
VREGIN
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
VBAT
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
5.2 Nonswitching electrical specifications
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
10
Freescale Semiconductor, Inc.
General
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
-5
—
mA
VBAT
VIH
VIL
RTC battery supply voltage
Input high voltage
Input low voltage
VHYS
Input hysteresis
IICDIO
Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V
IICAIO
IICcont
3
mA
• VIN < VSS-0.3V (Negative current injection)
-5
—
• VIN > VDD+0.3V (Positive current injection)
—
+5
-25
—
—
+25
1.2
—
V
VPOR_VBAT
—
V
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Positive current injection
VRFVBAT
1
Analog2, EXTAL, and XTAL pin DC injection current —
single pin
• Negative current injection
VRAM
Notes
VDD voltage required to retain RAM
VBAT voltage required to retain the VBAT register file
mA
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection
to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at
the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current
limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN
(=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is
calculated as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
11
General
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
±80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
±60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
12
Freescale Semiconductor, Inc.
General
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
0.5
V
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
Output low current total for all ports
—
100
mA
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
1
IIN
Input leakage current (per pin) at 25°C
—
0.025
μA
1
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pullup resistors
20
50
kΩ
2
RPD
Internal pulldown resistors
20
50
kΩ
3
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 72 MHz
• Bus clock = 36 MHz
• Flash clock = 24 MHz
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
13
General
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
Min.
Max.
Unit
Notes
—
300
μs
1
—
112
μs
—
74
μs
—
73
μs
—
5.9
μs
—
5.8
μs
—
4.2
μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
• @ 1.8V
• @ 3.0V
IDD_RUN
Min.
2
—
21.5
25
mA
—
21.5
30
mA
Run mode current — all peripheral clocks
enabled, code executing from flash
• @ 1.8V
3, 4
—
31
34
mA
—
31
34
mA
—
32
39
mA
• @ 3.0V
• @ 25°C
• @ 125°C
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
12.5
—
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V —
all peripheral clocks disabled
—
7.2
—
mA
5
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
0.996
—
mA
6
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
1.46
—
mA
7
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
14
Freescale Semiconductor, Inc.
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
IDD_VLPW
Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
IDD_STOP
Stop mode current at 3.0 V
IDD_VLPS
IDD_LLS
IDD_VLLS3
IDD_VLLS2
IDD_VLLS1
IDD_VBAT
Min.
Typ.
Max.
Unit
Notes
—
0.61
—
mA
8
• @ –40 to 25°C
—
0.35
0.567
mA
• @ 70°C
—
0.384
0.793
mA
• @ 105°C
—
0.628
1.2
mA
• @ –40 to 25°C
—
5.9
32.7
μA
• @ 70°C
—
26.1
59.8
μA
• @ 105°C
—
98.1
188
μA
Very-low-power stop mode current at 3.0 V
Low leakage stop mode current at 3.0 V
9
• @ –40 to 25°C
—
2.6
8.6
μA
• @ 70°C
—
10.3
29.1
μA
• @ 105°C
—
42.5
92.5
μA
Very low-leakage stop mode 3 current at 3.0 V
9
• @ –40 to 25°C
—
1.9
5.8
μA
• @ 70°C
—
6.9
12.1
μA
• @ 105°C
—
28.1
41.9
μA
• @ –40 to 25°C
—
1.59
5.5
μA
• @ 70°C
—
4.3
9.5
μA
• @ 105°C
—
17.5
34
μA
• @ –40 to 25°C
—
1.47
5.4
μA
• @ 70°C
—
2.97
8.1
μA
• @ 105°C
—
12.41
32
μA
—
0.19
0.22
μA
—
0.49
0.64
μA
—
2.2
3.2
μA
Very low-leakage stop mode 2 current at 3.0 V
Very low-leakage stop mode 1 current at 3.0 V
Average current with RTC and 32kHz disabled at
3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
15
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
IDD_VBAT
Average current when CPU is not accessing RTC
registers
Typ.
Max.
Unit
Notes
10
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
0.57
0.67
μA
—
0.90
1.2
μA
—
2.4
3.5
μA
—
0.67
0.94
μA
—
1.0
1.4
μA
—
2.7
3.9
μA
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEE mode. All peripheral
clocks disabled.
3. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEE mode. All peripheral
clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25MHz core, system, bus and flash clock. MCG configured for FEI mode.
6. 4 MHz core and system clock, 4 MHz and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled. Code executing from flash.
7. 4 MHz core and system clock, 4 MHz and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core and system clock, 4 MHz and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
9. Data reflects devices with 128 KB of RAM.
10. Includes 32kHz oscillator current and RTC operation.
5.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
16
Freescale Semiconductor, Inc.
General
Figure 2. Run mode supply current vs. core frequency
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
17
General
Figure 3. VLPR mode supply current vs. core frequency
5.2.6 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.7 Capacitance attributes
Table 7. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
18
Freescale Semiconductor, Inc.
General
5.3 Switching specifications
5.3.1 Device clock specifications
Table 8. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
72
MHz
System and core clock when Full Speed USB in
operation
20
—
MHz
Bus clock
—
50
MHz
fFLASH
Flash clock
—
25
MHz
fLPTMR
LPTMR clock
—
25
MHz
Notes
Normal run mode
fSYS
fSYS_USB
fBUS
VLPR
mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
fFLASH
Flash clock
—
0.5
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
25
MHz
LPTMR external reference clock
—
16
MHz
—
8
MHz
fLPTMR_pin
fLPTMR_ERCLK
fFlexCAN_ERCLK FlexCAN external reference clock
fI2S_MCLK
I2S master clock
—
12.5
MHz
fI2S_BCLK
I2S bit clock
—
4
MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I2C signals.
Table 9. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
3
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
19
General
Table 9. General switching specifications (continued)
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16
—
ns
3
External reset pulse width (digital glitch filter disabled)
100
—
ns
3
2
—
Bus clock
cycles
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
4
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
Port rise and fall time (low drive strength)
5
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
—
12
ns
• 2.7 ≤ VDD ≤ 3.6V
—
6
ns
• 1.71 ≤ VDD ≤ 2.7V
—
36
ns
• 2.7 ≤ VDD ≤ 3.6V
—
24
ns
• Slew enabled
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75pF load
5. 15pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 10. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
20
Freescale Semiconductor, Inc.
General
5.4.2 Thermal attributes
Board type
Symbol
Description
Single-layer
(1s)
RθJA
Four-layer
(2s2p)
100 LQFP
Unit
Notes
Thermal
74
resistance,
junction to
ambient (natural
convection)
52
°C/W
1, 2
RθJA
Thermal
42
resistance,
junction to
ambient (natural
convection)
40
°C/W
1, 3
Single-layer
(1s)
RθJMA
Thermal
62
resistance,
junction to
ambient (200 ft./
min. air speed)
42
°C/W
1,3
Four-layer
(2s2p)
RθJMA
Thermal
38
resistance,
junction to
ambient (200 ft./
min. air speed)
34
°C/W
1,3
—
RθJB
Thermal
resistance,
junction to
board
23
25
°C/W
4
—
RθJC
Thermal
resistance,
junction to case
19
12
°C/W
5
—
ΨJT
Thermal
4
characterization
parameter,
junction to
package top
outside center
(natural
convection)
2
°C/W
6
1.
2.
3.
4.
121
MAPBGA
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the
JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.
Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal. For the LQFP, the board meets the JESD51-7
specification.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
5.
6.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 11. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
3
—
ns
Th
Data hold
2
—
ns
Figure 4. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Figure 5. Trace data specifications
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.1.2 JTAG electricals
Table 12. JTAG limited voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• Boundary Scan
0
10
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
20
—
ns
• Serial Wire Debug
10
—
ns
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
17
ns
J12
TCLK low to TDO high-Z
—
17
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
Table 13. JTAG full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
TCLK frequency of operation
• Boundary Scan
0
10
• JTAG and CJTAG
0
20
• Serial Wire Debug
0
40
1/J1
—
ns
• Boundary Scan
50
—
ns
• JTAG and CJTAG
25
—
ns
• Serial Wire Debug
12.5
—
ns
—
3
ns
J2
TCLK cycle period
J3
TCLK clock pulse width
J4
MHz
TCLK rise and fall times
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
Table 13. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
25
ns
J8
TCLK low to boundary scan output high-Z
—
25
ns
J9
TMS, TDI input data setup time to TCLK rise
8
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1.4
—
ns
J11
TCLK low to TDO data valid
—
22.1
ns
J12
TCLK low to TDO high-Z
J13
TRST assert time
J14
TRST setup time (negation) to TCLK high
—
22.1
ns
100
—
ns
8
—
ns
J2
J3
J3
TCLK (input)
J4
J4
Figure 6. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 7. Boundary scan (JTAG) timing
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 8. Test Access Port timing
TCLK
J14
J13
TRST
Figure 9. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
6.3.1 MCG specifications
Table 14. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
—
32.768
—
kHz
31.25
—
39.0625
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
Notes
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+0.5/-0.7
—
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.3
± 0.3
%fdco
1
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
4
—
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
2, 3
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
4, 5
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol
Jcyc_fll
Description
FLL period jitter
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire
FLL target frequency acquisition time
Min.
Typ.
Max.
Unit
—
180
—
—
150
—
—
—
1
ms
48.0
—
100
MHz
—
1060
—
µA
—
600
—
µA
2.0
—
4.0
MHz
Notes
ps
6
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter (RMS)
Jacc_pll
7
8
• fvco = 48 MHz
—
120
—
ps
• fvco = 100 MHz
—
50
—
ps
PLL accumulated jitter over 1µs (RMS)
8
• fvco = 48 MHz
—
1350
—
ps
• fvco = 100 MHz
—
600
—
ps
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
7
Lock detector detection time
—
—
10-6
150 ×
+ 1075(1/
fpll_ref)
s
9
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
6.3.2.1
Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 15. Oscillator DC electrical specifications (continued)
Symbol
Vpp5
1.
2.
3.
4.
5.
Description
Min.
Typ.
Max.
Unit
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx,Cy can be provided by using either the integrated capacitors or by using external components.
When low power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2
Symbol
Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.3.3 32 kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1
32 kHz oscillator DC electrical specifications
Table 17. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
RF
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
6.3.3.2
Symbol
fosc_lo
tstart
32kHz oscillator frequency specifications
Table 18. 32kHz oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32.768
—
kHz
Crystal start-up time
—
1000
—
ms
1
700
—
VBAT
mV
2, 3
vec_extal32 Externally provided input clock amplitude
Notes
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 19. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm4
thversscr
Notes
Longword Program high-voltage time
—
7.5
18
μs
Sector Erase high-voltage time
—
13
113
ms
1
thversblk32k Erase Block high-voltage time for 32 KB
—
52
452
ms
1
thversblk256k Erase Block high-voltage time for 256 KB
—
104
904
ms
1
Notes
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2
Symbol
Flash timing specifications — commands
Table 20. Flash command timing specifications
Description
Min.
Typ.
Max.
Unit
Read 1s Block execution time
trd1blk32k
• 32 KB data flash
—
—
0.5
ms
trd1blk256k
• 256 KB program flash
—
—
1.7
ms
trd1sec1k
Read 1s Section execution time (data flash
sector)
—
—
60
μs
1
trd1sec2k
Read 1s Section execution time (program flash
sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
Erase Flash Block execution time
2
tersblk32k
• 32 KB data flash
—
55
465
ms
tersblk256k
• 256 KB program flash
—
122
985
ms
—
14
114
ms
tersscr
Erase Flash Sector execution time
2
Program Section execution time
tpgmsec512p
• 512 B program flash
—
2.4
—
ms
tpgmsec512d
• 512 B data flash
—
4.7
—
ms
tpgmsec1kp
• 1 KB program flash
—
4.7
—
ms
tpgmsec1kd
• 1 KB data flash
—
9.3
—
ms
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
trdonce
Read Once execution time
—
—
25
μs
Program Once execution time
—
65
—
μs
Erase All Blocks execution time
—
175
1500
ms
tpgmonce
tersall
1
2
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
Table 20. Flash command timing specifications (continued)
Symbol
tvfykey
Description
Verify Backdoor Access Key execution time
Min.
Typ.
Max.
Unit
Notes
—
—
30
μs
1
Swap Control execution time
tswapx01
• control code 0x01
—
200
—
μs
tswapx02
• control code 0x02
—
70
150
μs
tswapx04
• control code 0x04
—
70
150
μs
tswapx08
• control code 0x08
—
—
30
μs
—
70
—
ms
Program Partition for EEPROM execution time
tpgmpart32k
• 32 KB FlexNVM
Set FlexRAM Function execution time:
tsetramff
• Control Code 0xFF
—
50
—
μs
tsetram8k
• 8 KB EEPROM backup
—
0.3
0.5
ms
tsetram32k
• 32 KB EEPROM backup
—
0.7
1.0
ms
Byte-write to FlexRAM for EEPROM operation
teewr8bers
Byte-write to erased FlexRAM location execution
time
—
175
260
μs
3
Byte-write to FlexRAM execution time:
teewr8b8k
• 8 KB EEPROM backup
—
340
1700
μs
teewr8b16k
• 16 KB EEPROM backup
—
385
1800
μs
teewr8b32k
• 32 KB EEPROM backup
—
475
2000
μs
Word-write to FlexRAM for EEPROM operation
teewr16bers Word-write to erased FlexRAM location
execution time
—
175
260
μs
Word-write to FlexRAM execution time:
teewr16b8k
• 8 KB EEPROM backup
—
340
1700
μs
teewr16b16k
• 16 KB EEPROM backup
—
385
1800
μs
teewr16b32k
• 32 KB EEPROM backup
—
475
2000
μs
Longword-write to FlexRAM for EEPROM operation
teewr32bers Longword-write to erased FlexRAM location
execution time
—
360
540
μs
Longword-write to FlexRAM execution time:
teewr32b8k
• 8 KB EEPROM backup
—
545
1950
μs
teewr32b16k
• 16 KB EEPROM backup
—
630
2050
μs
teewr32b32k
• 32 KB EEPROM backup
—
810
2250
μs
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
32
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.4.1.3
Flash high voltage current behaviors
Table 21. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
6.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 22. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
5
50
—
years
tnvmretd1k
Data retention after up to 1 K cycles
20
100
—
years
nnvmcycd
Cycling endurance
10 K
50 K
—
cycles
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
50
—
years
tnvmretee10 Data retention up to 10% of write endurance
20
100
—
years
Write endurance
3
nnvmwree16
• EEPROM backup to FlexRAM ratio = 16
35 K
175 K
—
writes
nnvmwree128
• EEPROM backup to FlexRAM ratio = 128
315 K
1.6 M
—
writes
nnvmwree512
• EEPROM backup to FlexRAM ratio = 512
1.27 M
6.4 M
—
writes
nnvmwree4k
• EEPROM backup to FlexRAM ratio = 4096
10 M
50 M
—
writes
nnvmwree8k
• EEPROM backup to FlexRAM ratio = 8192
20 M
100 M
—
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
6.4.1.5
Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
33
Peripheral operating requirements and behaviors
The bytes not assigned to data flash via the FlexNVM partition code are used by the flash
memory module to obtain an effective endurance increase for the EEPROM data. The
built-in EEPROM record management system raises the number of program/erase cycles
that can be attained prior to device wear-out by cycling the EEPROM data through a
larger EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
Writes_subsystem =
EEPROM – 2 × EEESPLIT × EEESIZE
EEESPLIT × EEESIZE
× Write_efficiency × nnvmcycd
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycd — data flash cycling endurance (the following graph assumes 10,000
cycles)
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
34
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 10. EEPROM backup writes to FlexRAM
6.4.2 EzPort Switching Specifications
Table 23. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid
—
16
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 11. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 24 and Table 25 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 26 and
Table 27.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.1.1
16-bit ADC operating conditions
Table 24. 16-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD - VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS - VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
• 16-bit differential mode
VREFL
—
31/32 *
VREFH
V
• All other modes
VREFL
—
• 16-bit mode
—
8
10
• 8-/10-/12-bit modes
—
4
5
—
2
5
CADIN
RADIN
RAS
Input capacitance
Input resistance
Notes
VREFH
pF
kΩ
Analog source
resistance
13-/12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 13-bit mode
1.0
—
18.0
MHz
4
fADCK
ADC conversion
clock frequency
16-bit mode
2.0
—
12.0
MHz
4
Crate
ADC conversion
rate
≤ 13 bit modes
No ADC hardware averaging
3
5
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion
rate
16-bit mode
No ADC hardware averaging
5
37.037
—
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best
results. The results in this data sheet were derived from a system which has < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
Z AS
R AS
ADC SAR
ENGINE
R ADIN
V ADIN
C AS
V AS
R ADIN
INPUT PIN
R ADIN
INPUT PIN
R ADIN
INPUT PIN
C ADIN
Figure 12. ADC input impedance equivalency diagram
6.6.1.2
16-bit ADC electrical characteristics
Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
fADACK
ADC
asynchronous
clock source
Sample Time
TUE
DNL
INL
EFS
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
LSB4
VADIN =
VDDA
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
• <12-bit modes
—
±1.4
±2.1
Differential nonlinearity
• 12-bit modes
—
±0.7
-1.1 to +1.9
Integral nonlinearity
Full-scale error
-0.3 to 0.5
• <12-bit modes
—
±0.2
• 12-bit modes
—
±1.0
-2.7 to +1.9
-0.7 to +0.5
• <12-bit modes
—
±0.5
• 12-bit modes
—
-4
-5.4
• <12-bit modes
—
-1.4
-1.8
5
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 25. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
Description
EQ
Quantization
error
ENOB
Conditions1
Min.
Typ.2
Max.
Unit
• 16-bit modes
—
-1 to 0
—
LSB4
• ≤13-bit modes
—
—
±0.5
Effective number 16-bit differential mode
of bits
• Avg = 32
• Avg = 4
Notes
6
12.8
14.5
—
bits
11.9
13.8
—
bits
12.2
13.9
—
bits
11.4
13.1
—
bits
16-bit single-ended mode
• Avg = 32
• Avg = 4
SINAD
THD
Signal-to-noise
plus distortion
See ENOB
Total harmonic
distortion
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
dB
7
—
–94
—
dB
—
-85
—
dB
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
EIL
6.02 × ENOB + 1.76
7
82
95
—
dB
78
90
—
dB
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and current
operating
ratings)
VTEMP25
Temp sensor
slope
Across the full temperature
range of the device
—
1.715
—
mV/°C
Temp sensor
voltage
25 °C
—
719
—
mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
Figure 13. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Figure 14. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.1.3
16-bit ADC with PGA operating conditions
Table 26. 16-bit ADC with PGA operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
VREFPGA
PGA ref voltage
VADIN
VCM
RPGAD
VREF_OU VREF_OU VREF_OU
T
T
T
V
Notes
2, 3
Input voltage
VSSA
—
VDDA
V
Input Common
Mode range
VSSA
—
VDDA
V
Gain = 1, 2, 4, 8
—
128
—
kΩ
IN+ to IN-4
Gain = 16, 32
—
64
—
Gain = 64
—
32
—
Differential input
impedance
RAS
Analog source
resistance
—
100
—
Ω
5
TS
ADC sampling
time
1.25
—
—
µs
6
18.484
—
450
Ksps
7
37.037
—
250
Ksps
8
Crate
ADC conversion
rate
≤ 13 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
16 bit modes
No ADC hardware
averaging
Continuous conversions
enabled
Peripheral clock = 50
MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
41
Peripheral operating requirements and behaviors
6.6.1.4
16-bit ADC with PGA characteristics with Chop enabled
(ADC_PGA[PGACHPb] =0)
Table 27. 16-bit ADC with PGA characteristics
Symbol
Description
Conditions
IDDA_PGA
Supply current
Low power
(ADC_PGA[PGALPb]=0)
IDC_PGA
Input DC current
G
BW
Gain4
Input signal
bandwidth
PSRR
Power supply
rejection ratio
CMRR
Common mode
rejection ratio
Min.
Typ.1
Max.
Unit
Notes
—
420
644
μA
2
A
3
Gain =1, VREFPGA=1.2V,
VCM=0.5V
—
1.54
—
μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
—
0.57
—
μA
• PGAG=0
0.95
1
1.05
• PGAG=1
1.9
2
2.1
• PGAG=2
3.8
4
4.2
• PGAG=3
7.6
8
8.4
• PGAG=4
15.2
16
16.6
• PGAG=5
30.0
31.6
33.2
• PGAG=6
58.8
63.3
67.8
—
—
4
kHz
—
—
40
kHz
—
-84
—
dB
VDDA= 3V
±100mV,
fVDDA= 50Hz,
60Hz
• Gain=1
—
-84
—
dB
• Gain=64
—
-85
—
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
• 16-bit modes
• < 16-bit modes
Gain=1
RAS < 100Ω
VOFS
Input offset
voltage
—
0.2
—
mV
Output offset =
VOFS*(Gain+1)
TGSW
Gain switching
settling time
—
—
10
µs
5
dG/dT
Gain drift over full
temperature range
• Gain=1
• Gain=64
—
6
10
ppm/°C
—
31
42
ppm/°C
• Gain=1
• Gain=64
—
0.07
0.21
%/V
—
0.14
0.31
%/V
dG/dVDDA Gain drift over
supply voltage
EIL
Input leakage
error
All modes
IIn × RAS
mV
VDDA from 1.71
to 3.6V
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
42
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 27. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
VPP,DIFF
Maximum
differential input
signal swing
SNR
THD
SFDR
ENOB
SINAD
Conditions
Typ.1
Min.
Max.
Unit
Notes
V
6
16-bit
differential
mode,
Average=32
where VX = VREFPGA × 0.583
Signal-to-noise
ratio
• Gain=1
80
90
—
dB
• Gain=64
52
66
—
dB
Total harmonic
distortion
• Gain=1
85
100
—
dB
• Gain=64
49
95
—
dB
Spurious free
dynamic range
• Gain=1
85
105
—
dB
• Gain=64
53
88
—
dB
Effective number
of bits
• Gain=1, Average=4
11.6
13.4
—
bits
• Gain=64, Average=4
7.2
9.6
—
bits
• Gain=1, Average=32
12.8
14.5
—
bits
• Gain=2, Average=32
11.0
14.3
—
bits
• Gain=4, Average=32
7.9
13.8
—
bits
• Gain=8, Average=32
7.3
13.1
—
bits
• Gain=16, Average=32
6.8
12.5
—
bits
• Gain=32, Average=32
6.8
11.5
—
bits
• Gain=64, Average=32
7.5
10.6
—
bits
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
16-bit
differential
mode,
Average=32,
fin=100Hz
16-bit
differential
mode,
Average=32,
fin=100Hz
16-bit
differential
mode,fin=100Hz
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
4. Gain = 2PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 28. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
43
Peripheral operating requirements and behaviors
Table 28. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VH
Analog comparator
hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
—
—
40
μs
6-bit DAC current adder (enabled)
—
7
—
μA
IDAC6b
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
44
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0.08
0.07
0.06
HYSTCTR
Setting
CM P Hystereris (V)
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 15. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
45
Peripheral operating requirements and behaviors
0.18
0.16
0.14
CMP
P Hystereris (V)
0.12
HYSTCTR
Setting
0.1
00
01
0
08
0.08
10
11
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
Vin level (V)
1.9
2.2
2.5
2.8
3.1
Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1
Symbol
12-bit DAC operating requirements
Table 29. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
1.13
3.6
V
TA
Temperature
Operating temperature
range of the device
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
Notes
1
°C
2
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
46
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.3.2
Symbol
12-bit DAC operating behaviors
Table 30. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
150
μA
—
—
700
μA
Notes
P
IDDA_DACH Supply current — high-speed mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
—
0.7
1
μs
1
—
—
100
mV
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
—
±0.4
±0.8
%FSR
5
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
Rop
Output resistance load = 3 kΩ
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
VOFFSET Offset error
EG
PSRR
1.
2.
3.
4.
5.
6.
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
—
—
-80
CT
Channel to channel cross talk
BW
3dB bandwidth
6
dB
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
47
Peripheral operating requirements and behaviors
Figure 17. Typical INL error vs. digital code
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
48
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 18. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 31. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
TA
Temperature
CL
Output load capacitance
Operating temperature
range of the device
°C
100
nF
Notes
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
49
Peripheral operating requirements and behaviors
Table 32. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1915
1.195
1.1977
V
Vout
Voltage reference output — factory trim
1.1584
—
1.2376
V
Vout
Voltage reference output — user trim
1.193
—
1.197
V
Vstep
Voltage reference trim step
—
0.5
—
mV
Vtdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
—
80
mV
Ibg
Bandgap only current
—
—
80
µA
1
Ilp
Low-power buffer current
—
—
360
uA
1
Ihp
High-power buffer current
—
—
1
mA
1
µV
1, 2
ΔVLOAD
Load regulation
• current = ± 1.0 mA
—
200
—
Tstup
Buffer startup time
—
—
100
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 33. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
TA
Temperature
0
50
°C
Notes
Table 34. VREF limited-range operating behaviors
Symbol
Vout
Description
Voltage reference output with factory trim
Min.
Max.
Unit
1.173
1.225
V
Notes
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
50
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
6.8.2 USB DCD electrical specifications
Table 35. USB DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
0.5
—
0.7
V
Threshold voltage for logic high
0.8
—
2.0
V
VLGC
IDP_SRC
USB_DP source current
7
10
13
μA
IDM_SINK
USB_DM sink current
50
100
150
μA
RDM_DWN
D- pulldown resistance for data pin contact detect
14.25
—
24.8
kΩ
VDAT_REF
Data detect voltage
0.25
0.33
0.4
V
6.8.3 USB VREG electrical specifications
Table 36. USB VREG electrical specifications
Symbol
Description
Min.
VREGIN
Typ.1
Max.
Unit
Input supply voltage
2.7
—
5.5
V
IDDon
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
—
120
186
μA
IDDstby
Quiescent current — Standby mode, load current
equal zero
—
1.1
10
μA
IDDoff
Quiescent current — Shutdown mode
—
650
—
nA
—
—
4
μA
• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature
ILOADrun
Maximum load current — Run mode
—
—
120
mA
ILOADstby
Maximum load current — Standby mode
—
—
1
mA
VReg33out
Regulator output voltage — Input supply
(VREGIN) > 3.6 V
3
3.3
3.6
V
2.1
2.8
3.6
V
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1
—
3.6
V
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
• Run mode
• Standby mode
VReg33out
Notes
2
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
51
Peripheral operating requirements and behaviors
Table 36. USB VREG electrical specifications
(continued)
Symbol
ILIM
Description
Short circuit current
Min.
Typ.1
Max.
Unit
—
290
—
mA
Notes
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
6.8.4 CAN switching specifications
See General switching specifications.
6.8.5 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 37. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
25
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
52
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
DSPI_PCSn
DS3
DS1
DS2
DS4
DSPI_SCK
DS8
DS7
(CPOL=0)
DSPI_SIN
Data
First data
Last data
DS5
DSPI_SOUT
DS6
First data
Data
Last data
Figure 19. DSPI classic SPI timing — master mode
Table 38. Slave mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
12.5
MHz
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
Frequency of operation
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 20. DSPI classic SPI timing — slave mode
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
53
Peripheral operating requirements and behaviors
6.8.6 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 39. Master mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
12.5
MHz
4 x tBUS
—
ns
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-4.5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
20.5
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
DS1
DSPI_SCK output cycle time
DS2
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DS1
DS2
DS4
DSPI_SCK
DS7
(CPOL=0)
DSPI_SIN
DS8
Data
First data
Last data
DS5
DSPI_SOUT
First data
DS6
Data
Last data
Figure 21. DSPI classic SPI timing — master mode
Table 40. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
6.25
MHz
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
54
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 40. Slave mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
8 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
19
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
19
ns
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 22. DSPI classic SPI timing — slave mode
6.8.7 I2C switching specifications
See General switching specifications.
6.8.8 UART switching specifications
See General switching specifications.
6.8.9 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
55
Peripheral operating requirements and behaviors
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
6.8.9.1
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 41. I2S/SAI master mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
40
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
80
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1.0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
20.5
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
56
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 23. I2S/SAI timing — master modes
Table 42. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
80
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
5.8
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
—
25
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
57
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 24. I2S/SAI timing — slave modes
6.8.9.2
VLPR, VLPW, and VLPS mode performance over the full operating
voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 43. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
I2S_MCLK cycle time
62.5
—
ns
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
250
—
ns
S4
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
45
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
53
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
58
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 25. I2S/SAI timing — master modes
Table 44. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
250
—
ns
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
7.6
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
67
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
30
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
6.5
—
ns
—
72
ns
S19
I2S_TX_FS input assertion to I2S_TXD output
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
59
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 26. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 45. TSI electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDDTSI
Operating voltage
1.71
—
3.6
V
Target electrode capacitance range
1
20
500
pF
1
fREFmax
Reference oscillator frequency
—
8
15
MHz
2, 3
fELEmax
Electrode oscillator frequency
—
1
1.8
MHz
2, 4
Internal reference capacitor
—
1
—
pF
Oscillator delta voltage
—
500
—
mV
2, 5
μA
2, 6
μA
2, 7
CELE
CREF
VDELTA
IREF
IELE
Reference oscillator current source base current
• 2 μA setting (REFCHRG = 0)
• 32 μA setting (REFCHRG = 15)
Electrode oscillator current source base current
• 2 μA setting (EXTCHRG = 0)
• 32 μA setting (EXTCHRG = 15)
—
2
3
—
36
50
—
2
3
—
36
50
Notes
Pres5
Electrode capacitance measurement precision
—
8.3333
38400
fF/count
8
Pres20
Electrode capacitance measurement precision
—
8.3333
38400
fF/count
9
Pres100
Electrode capacitance measurement precision
—
8.3333
38400
fF/count
10
0.008
1.46
—
fF/count
11
—
—
16
bits
Response time @ 20 pF
8
15
25
μs
Current added in run mode
—
55
—
μA
Low power mode current adder
—
1.3
2.5
μA
MaxSens Maximum sensitivity
Res
TCon20
ITSI_RUN
ITSI_LP
Resolution
12
13
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
60
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. Fixed external capacitance of 20 pF.
3. REFCHRG = 2, EXTCHRG=0.
4. REFCHRG = 0, EXTCHRG = 10.
5. VDD = 3.0 V.
6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity
depends on the configuration used. The documented values are provided as examples calculated for a specific
configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN)
The typical value is calculated with the following configuration:
Iext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF
The minimum value is calculated with the following configuration:
Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF
The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be
measured by a single count.
12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, EXTCHRG = 7.
13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of
20 pF. Data is captured with an average of 7 periods window.
6.9.2 LCD electrical characteristics
Table 46. LCD electricals
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fFrame
LCD frame frequency
28
30
58
Hz
CLCD
LCD charge pump capacitance — nominal value
—
100
—
nF
1
CBYLCD
LCD bypass capacitance — nominal value
—
100
—
nF
1
CGlass
LCD glass capacitance
—
2000
8000
pF
2
VIREG
VIREG
ΔRTRIM
VIREG TRIM resolution
—
3
—
—
3.0
% VIREG
—
1
—
µA
—
10
—
µA
—
1
—
µA
VIREG ripple
IVIREG
VIREG current adder — RVEN = 1
IRBIAS
RBIAS current adder
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
4
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
61
Dimensions
Table 46. LCD electricals (continued)
Symbol
Description
RRBIAS
RBIAS resistor values
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
VLL2
VLL2 voltage
VLL3
VLL3 voltage
Min.
Typ.
Max.
Unit
—
0.28
—
MΩ
—
2.98
—
MΩ
Notes
1. The actual value used could vary with tolerance.
2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter
within the device's reference manual.
3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V
4. 2000 pF load LCD, 32 Hz frame frequency
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.freescale.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
Then use this document number
100-pin LQFP
98ASS23308W
121-pin MAPBGA
98ASA00344D
8 Pinout
8.1 K40 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
62
Freescale Semiconductor, Inc.
Pinout
121 100
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
E4
1
PTE0
ADC1_SE4a
ADC1_SE4a
PTE0
SPI1_PCS1
UART1_TX
I2C1_SDA
RTC_CLKOUT
E3
2
PTE1/
LLWU_P0
ADC1_SE5a
ADC1_SE5a
PTE1/
LLWU_P0
SPI1_SOUT
UART1_RX
I2C1_SCL
SPI1_SIN
E2
3
PTE2/
LLWU_P1
ADC1_SE6a
ADC1_SE6a
PTE2/
LLWU_P1
SPI1_SCK
UART1_CTS_
b
F4
4
PTE3
ADC1_SE7a
ADC1_SE7a
PTE3
SPI1_SIN
UART1_RTS_
b
E7
—
VDD
VDD
VDD
VSS
F7
—
VSS
VSS
H7
5
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
UART3_TX
G4
6
PTE5
DISABLED
PTE5
SPI1_PCS2
UART3_RX
F3
7
PTE6
DISABLED
PTE6
SPI1_PCS3
UART3_CTS_ I2S0_MCLK
b
E6
8
VDD
VDD
VDD
G7
9
VSS
VSS
VSS
L6
—
VSS
VSS
VSS
F1
10
USB0_DP
USB0_DP
USB0_DP
F2
11
USB0_DM
USB0_DM
USB0_DM
G1
12
VOUT33
VOUT33
VOUT33
G2
13
VREGIN
VREGIN
VREGIN
H1
14
ADC0_DP1
ADC0_DP1
ADC0_DP1
H2
15
ADC0_DM1
ADC0_DM1
ADC0_DM1
J1
16
ADC1_DP1
ADC1_DP1
ADC1_DP1
J2
17
ADC1_DM1
ADC1_DM1
ADC1_DM1
K1
18
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
K2
19
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
L1
20
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
L2
21
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
F5
22
VDDA
VDDA
VDDA
G5
23
VREFH
VREFH
VREFH
G6
24
VREFL
VREFL
VREFL
F6
25
VSSA
VSSA
VSSA
L3
26
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
EzPort
SPI1_SOUT
USB_SOF_
OUT
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
63
Pinout
121 100
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
K5
27
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
L7
—
RTC_
WAKEUP_B
RTC_
WAKEUP_B
RTC_
WAKEUP_B
L4
28
XTAL32
XTAL32
XTAL32
L5
29
EXTAL32
EXTAL32
EXTAL32
K6
30
VBAT
VBAT
VBAT
H5
31
PTE24
ADC0_SE17
ADC0_SE17
PTE24
UART4_TX
EWM_OUT_b
J5
32
PTE25
ADC0_SE18
ADC0_SE18
PTE25
UART4_RX
EWM_IN
H6
33
PTE26
DISABLED
PTE26
UART4_CTS_
b
RTC_CLKOUT USB_CLKIN
J6
34
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1
PTA0
UART0_CTS_ FTM0_CH5
b/
UART0_COL_
b
JTAG_TCLK/
SWD_CLK
EZP_CLK
H8
35
PTA1
JTAG_TDI/
EZP_DI
TSI0_CH2
PTA1
UART0_RX
FTM0_CH6
JTAG_TDI
EZP_DI
J7
36
PTA2
JTAG_TDO/ TSI0_CH3
TRACE_SWO/
EZP_DO
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/ EZP_DO
TRACE_SWO
H9
37
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
PTA3
UART0_RTS_ FTM0_CH0
b
J8
38
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5
PTA4/
LLWU_P3
K7
39
PTA5
DISABLED
E5
40
VDD
VDD
VDD
G3
41
VSS
VSS
VSS
K8
42
PTA12
CMP2_IN0
L8
43
PTA13/
LLWU_P4
CMP2_IN1
K9
44
PTA14
JTAG_TMS/
SWD_DIO
FTM0_CH1
PTA5
USB_CLKIN
FTM0_CH2
CMP2_IN0
PTA12
CAN0_TX
CMP2_IN1
PTA13/
LLWU_P4
DISABLED
NMI_b
CMP2_OUT
I2S0_TX_
BCLK
JTAG_TRST_
b
FTM1_CH0
I2S0_TXD0
FTM1_QD_
PHA
CAN0_RX
FTM1_CH1
I2S0_TX_FS
FTM1_QD_
PHB
PTA14
SPI0_PCS0
UART0_TX
I2S0_RX_
BCLK
I2S0_TXD1
L9
45
PTA15
DISABLED
PTA15
SPI0_SCK
UART0_RX
I2S0_RXD0
J10
46
PTA16
DISABLED
PTA16
SPI0_SOUT
UART0_CTS_
b/
UART0_COL_
b
I2S0_RX_FS
H10
47
PTA17
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_RTS_
b
I2S0_MCLK
L10
48
VDD
VDD
VDD
K10
49
VSS
VSS
VSS
L11
50
PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
EZP_CS_b
I2S0_RXD1
FTM_CLKIN0
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
64
Freescale Semiconductor, Inc.
Pinout
121 100
MAP LQFP
BGA
Pin Name
Default
ALT0
K11
51
PTA19
XTAL0
XTAL0
ALT1
ALT2
PTA19
ALT3
FTM1_FLT0
ALT4
ALT5
FTM_CLKIN1
ALT6
ALT7
EzPort
LPTMR0_
ALT1
J11
52
RESET_b
RESET_b
RESET_b
G11
53
PTB0/
LLWU_P5
LCD_P0/
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
LCD_P0/
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
FTM1_QD_
PHA
LCD_P0
G10
54
PTB1
LCD_P1/
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
LCD_P1/
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_
PHB
LCD_P1
G9
55
PTB2
LCD_P2/
ADC0_SE12/
TSI0_CH7
LCD_P2/
ADC0_SE12/
TSI0_CH7
PTB2
I2C0_SCL
UART0_RTS_
b
FTM0_FLT3
LCD_P2
G8
56
PTB3
LCD_P3/
ADC0_SE13/
TSI0_CH8
LCD_P3/
ADC0_SE13/
TSI0_CH8
PTB3
I2C0_SDA
UART0_CTS_
b/
UART0_COL_
b
FTM0_FLT0
LCD_P3
E11
57
PTB7
LCD_P7/
ADC1_SE13
LCD_P7/
ADC1_SE13
PTB7
D11
58
PTB8
LCD_P8
LCD_P8
PTB8
E10
59
PTB9
LCD_P9
LCD_P9
PTB9
D10
60
PTB10
LCD_P10/
ADC1_SE14
LCD_P10/
ADC1_SE14
C10
61
PTB11
LCD_P11/
ADC1_SE15
B10
62
PTB16
E9
63
D9
LCD_P7
UART3_RTS_
b
LCD_P8
SPI1_PCS1
UART3_CTS_
b
LCD_P9
PTB10
SPI1_PCS0
UART3_RX
FTM0_FLT1
LCD_P10
LCD_P11/
ADC1_SE15
PTB11
SPI1_SCK
UART3_TX
FTM0_FLT2
LCD_P11
LCD_P12/
TSI0_CH9
LCD_P12/
TSI0_CH9
PTB16
SPI1_SOUT
UART0_RX
EWM_IN
LCD_P12
PTB17
LCD_P13/
TSI0_CH10
LCD_P13/
TSI0_CH10
PTB17
SPI1_SIN
UART0_TX
EWM_OUT_b
LCD_P13
64
PTB18
LCD_P14/
TSI0_CH11
LCD_P14/
TSI0_CH11
PTB18
CAN0_TX
FTM2_CH0
I2S0_TX_
BCLK
FTM2_QD_
PHA
LCD_P14
C9
65
PTB19
LCD_P15/
TSI0_CH12
LCD_P15/
TSI0_CH12
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS
FTM2_QD_
PHB
LCD_P15
F10
66
PTB20
LCD_P16
LCD_P16
PTB20
CMP0_OUT
LCD_P16
F9
67
PTB21
LCD_P17
LCD_P17
PTB21
CMP1_OUT
LCD_P17
CMP2_OUT
LCD_P18
F8
68
PTB22
LCD_P18
LCD_P18
PTB22
E8
69
PTB23
LCD_P19
LCD_P19
PTB23
B9
70
PTC0
LCD_P20/
ADC0_SE14/
TSI0_CH13
LCD_P20/
ADC0_SE14/
TSI0_CH13
PTC0
SPI0_PCS4
PDB0_EXTRG
I2S0_TXD1
LCD_P20
D8
71
PTC1/
LLWU_P6
LCD_P21/
ADC0_SE15/
TSI0_CH14
LCD_P21/
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3
UART1_RTS_ FTM0_CH0
b
I2S0_TXD0
LCD_P21
SPI0_PCS5
LCD_P19
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
65
Pinout
121 100
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
C8
72
PTC2
LCD_P22/
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
LCD_P22/
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2
SPI0_PCS2
UART1_CTS_ FTM0_CH1
b
B8
73
PTC3/
LLWU_P7
LCD_P23/
CMP1_IN1
LCD_P23/
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
—
74
VSS
VSS
VSS
A11
75
VLL3
VLL3
VLL3
A10
76
VLL2
VLL2
VLL2
A9
77
VLL1
VLL1
VLL1
B11
78
VCAP2
VCAP2
VCAP2
C11
79
VCAP1
VCAP1
VCAP1
A8
80
PTC4/
LLWU_P8
LCD_P24
LCD_P24
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
D7
81
PTC5/
LLWU_P9
LCD_P25
LCD_P25
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
C7
82
PTC6/
LLWU_P10
LCD_P26/
CMP0_IN0
LCD_P26/
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_EXTRG I2S0_RX_
BCLK
B7
83
PTC7
LCD_P27/
CMP0_IN1
LCD_P27/
CMP0_IN1
PTC7
SPI0_SIN
USB_SOF_
OUT
A7
84
PTC8
LCD_P28/
ADC1_SE4b/
CMP0_IN2
LCD_P28/
ADC1_SE4b/
CMP0_IN2
D6
85
PTC9
LCD_P29/
ADC1_SE5b/
CMP0_IN3
C6
86
PTC10
C5
87
B6
ALT5
ALT6
ALT7
I2S0_TX_FS
LCD_P22
I2S0_TX_
BCLK
LCD_P23
FTM0_CH3
CMP1_OUT
LCD_P24
I2S0_RXD0
CMP0_OUT
LCD_P25
I2S0_MCLK
LCD_P26
CLKOUT
I2S0_RX_FS
LCD_P27
PTC8
I2S0_MCLK
LCD_P28
LCD_P29/
ADC1_SE5b/
CMP0_IN3
PTC9
I2S0_RX_
BCLK
LCD_P30/
ADC1_SE6b
LCD_P30/
ADC1_SE6b
PTC10
I2C1_SCL
I2S0_RX_FS
LCD_P30
PTC11/
LLWU_P11
LCD_P31/
ADC1_SE7b
LCD_P31/
ADC1_SE7b
PTC11/
LLWU_P11
I2C1_SDA
I2S0_RXD1
LCD_P31
—
PTC12
LCD_P32
LCD_P32
PTC12
UART4_RTS_
b
LCD_P32
A6
—
PTC13
LCD_P33
LCD_P33
PTC13
UART4_CTS_
b
LCD_P33
A5
—
PTC14
LCD_P34
LCD_P34
PTC14
UART4_RX
LCD_P34
—
88
VSS
VSS
VSS
—
89
VDD
VDD
VDD
D5
90
PTC16
LCD_P36
LCD_P36
PTC16
UART3_RX
LCD_P36
C4
91
PTC17
LCD_P37
LCD_P37
PTC17
UART3_TX
LCD_P37
B4
92
PTC18
LCD_P38
LCD_P38
PTC18
UART3_RTS_
b
LCD_P38
A4
—
PTC19
LCD_P39
LCD_P39
PTC19
UART3_CTS_
b
LCD_P39
D4
93
PTD0/
LLWU_P12
LCD_P40
LCD_P40
PTD0/
LLWU_P12
UART2_RTS_
b
LCD_P40
SPI0_PCS0
FTM2_FLT0
EzPort
LCD_P29
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
66
Freescale Semiconductor, Inc.
Pinout
121 100
MAP LQFP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
D3
94
PTD1
LCD_P41/
ADC0_SE5b
LCD_P41/
ADC0_SE5b
PTD1
SPI0_SCK
UART2_CTS_
b
LCD_P41
C3
95
PTD2/
LLWU_P13
LCD_P42
LCD_P42
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
LCD_P42
B3
96
PTD3
LCD_P43
LCD_P43
PTD3
SPI0_SIN
UART2_TX
LCD_P43
A3
97
PTD4/
LLWU_P14
LCD_P44
LCD_P44
PTD4/
LLWU_P14
SPI0_PCS1
UART0_RTS_ FTM0_CH4
b
EWM_IN
LCD_P44
A2
98
PTD5
LCD_P45/
ADC0_SE6b
LCD_P45/
ADC0_SE6b
PTD5
SPI0_PCS2
UART0_CTS_ FTM0_CH5
b/
UART0_COL_
b
EWM_OUT_b
LCD_P45
B2
99
PTD6/
LLWU_P15
LCD_P46/
ADC0_SE7b
LCD_P46/
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FTM0_FLT0
LCD_P46
A1
100
PTD7
LCD_P47
LCD_P47
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
FTM0_FLT1
LCD_P47
K3
—
NC
NC
NC
H4
—
NC
NC
NC
J3
—
NC
NC
NC
H3
—
NC
NC
NC
K4
—
NC
NC
NC
J9
—
NC
NC
NC
J4
—
NC
NC
NC
H11
—
NC
NC
NC
F11
—
NC
NC
NC
B1
—
NC
NC
NC
C2
—
NC
NC
NC
C1
—
NC
NC
NC
D2
—
NC
NC
NC
D1
—
NC
NC
NC
E1
—
NC
NC
NC
B5
—
NC
NC
NC
EzPort
8.2 K40 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
67
PTD0/LLWU_P12
PTC18
PTC17
PTC16
VDD
VSS
PTC11/LLWU_P11
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
VCAP1
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
VLL2
PTD1
94
76
PTD2/LLWU_P13
95
VCAP2
PTD3
96
VLL1
PTD4/LLWU_P14
97
78
PTD5
77
PTD6/LLWU_P15
98
PTD7
100
99
Pinout
PTE0
1
75
VLL3
PTE1/LLWU_P0
2
74
VSS
PTE2/LLWU_P1
3
73
PTC3/LLWU_P7
PTE3
4
72
PTC2
PTE4/LLWU_P2
5
71
PTC1/LLWU_P6
PTE5
6
70
PTC0
PTE6
7
69
PTB23
VDD
8
68
PTB22
VSS
9
67
PTB21
USB0_DP
10
66
PTB20
USB0_DM
11
65
PTB19
VOUT33
12
64
PTB18
VREGIN
13
63
PTB17
49
50
PTA18
46
PTA16
48
45
PTA15
VSS
44
PTA14
VDD
43
PTA13/LLWU_P4
PTA17
42
PTA12
47
41
PTA19
VSS
51
40
25
VDD
RESET_b
VSSA
39
PTB0/LLWU_P5
52
38
53
24
PTA5
23
VREFL
PTA4/LLWU_P3
VREFH
37
PTB1
PTA3
54
36
22
PTA2
PTB2
VDDA
35
55
PTA1
21
34
PTB3
PGA1_DM/ADC1_DM0/ADC0_DM3
33
PTB7
56
PTA0
57
20
PTE26
19
PGA1_DP/ADC1_DP0/ADC0_DP3
32
PGA0_DM/ADC0_DM0/ADC1_DM3
PTE25
PTB8
31
PGA0_DP/ADC0_DP0/ADC1_DP3
58
PTE24
PTB9
18
29
59
30
17
VBAT
PTB10
ADC1_DM1
EXTAL32
60
XTAL32
16
28
PTB11
ADC1_DP1
27
PTB16
61
26
62
15
DAC0_OUT/CMP1_IN3/ADC0_SE23
14
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
ADC0_DP1
ADC0_DM1
Figure 27. K40 100 LQFP Pinout Diagram
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
68
Freescale Semiconductor, Inc.
Revision History
1
2
3
4
5
6
7
8
9
10
A
PTD7
PTD5
PTD4/
LLWU_P14
PTC19
PTC14
PTC13
PTC8
PTC4/
LLWU_P8
VLL1
VLL2
B
NC
PTD6/
LLWU_P15
PTD3
PTC18
NC
PTC12
PTC7
PTC3/
LLWU_P7
PTC0
C
NC
NC
PTD2/
LLWU_P13
PTC17
PTC11/
LLWU_P11
PTC10
PTC6/
LLWU_P10
PTC2
D
NC
NC
PTD1
PTD0/
LLWU_P12
PTC16
PTC9
PTC5/
LLWU_P9
E
NC
PTE2/
LLWU_P1
PTE1/
LLWU_P0
PTE0
VDD
VDD
F
USB0_DP
USB0_DM
PTE6
PTE3
VDDA
G
VOUT33
VREGIN
VSS
PTE5
11
VLL3
A
PTB16
VCAP2
B
PTB19
PTB11
VCAP1
C
PTC1/
LLWU_P6
PTB18
PTB10
PTB8
D
VDD
PTB23
PTB17
PTB9
PTB7
E
VSSA
VSS
PTB22
PTB21
PTB20
NC
F
VREFH
VREFL
VSS
PTB3
PTB2
PTB1
PTB0/
LLWU_P5
G
H
ADC0_DP1 ADC0_DM1
NC
NC
PTE24
PTE26
PTE4/
LLWU_P2
PTA1
PTA3
PTA17
NC
H
J
ADC1_DP1 ADC1_DM1
NC
NC
PTE25
PTA0
PTA2
PTA4/
LLWU_P3
NC
PTA16
RESET_b
J
K
PGA0_DP/ PGA0_DM/
ADC0_DP0/ ADC0_DM0/
ADC1_DP3 ADC1_DM3
NC
NC
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
VBAT
PTA5
PTA12
PTA14
VSS
PTA19
K
L
VREF_OUT/
PGA1_DP/ PGA1_DM/ CMP1_IN5/
ADC1_DP0/ ADC1_DM0/ CMP0_IN5/
ADC0_DP3 ADC0_DM3 ADC1_SE18
XTAL32
EXTAL32
VSS
PTA15
VDD
PTA18
L
4
5
6
9
10
11
1
2
3
RTC_
PTA13/
WAKEUP_B LLWU_P4
7
8
Figure 28. K40 121 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Table 47. Revision History
Rev. No.
Date
1
3/2012
Substantial Changes
Initial public release
Table continues on the next page...
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc.
69
Revision History
Table 47. Revision History (continued)
Rev. No.
Date
Substantial Changes
2
4/2012
•
•
•
•
•
•
3
11/2012
• Updated orderable part numbers.
• Updated the maximum input voltage (VADIN) specification in the "16-bit ADC operating
conditions" section.
• Updated the maximum IDDstby specification in the "USB VREG electrical specifications"
section.
Replaced TBDs throughout.
Updated "Power consumption operating behaviors" table.
Updated "ADC electrical specifications" section.
Updated "VREF full-range operating behaviors" table.
Updated "I2S/SAI Switching Specifications" section.
Updated "TSI electrical specifications" table.
K40 Sub-Family Data Sheet, Rev. 3, 11/2012.
70
Freescale Semiconductor, Inc.
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