AD ADA4084-2ARMZ-R7 30 v, low noise, rail-to-rail Datasheet

FEATURES
PIN CONFIGURATIONS
Rail-to-rail input/output
Low power: 625 µA typical
Gain bandwidth product: 15.9 MHz at AV =100 typical
Unity-gain crossover: 9.9 MHz typical
−3 dB closed-loop bandwidth: 13.9 MHz typical at ±15 V
Low offset voltage: 100 μV maximum (SOIC)
Unity-gain stable
High slew rate: 4.6 V/μs typical
Low noise: 3.9 nV/√Hz typical at 1 kHz
ADA4084-2
OUT A
1
8
V+
–IN A
2
7
OUT B
+IN A
3
6
–IN B
V–
4
5
+IN B
TOP VIEW
(Not to Scale)
08237-001
Data Sheet
30 V, Low Noise, Rail-to-Rail
I/O, Low Power Operational Amplifier
ADA4084-2
Figure 1. 8-Lead MSOP (RM)
8-Lead SOIC (R)
APPLICATIONS
Battery-powered instrumentation
Power supply control and protection
Telecommunications
DAC output amplifier
ADC input buffer
GENERAL DESCRIPTION
The ADA4084-2 is a dual, single-supply, 10 MHz bandwidth
amplifier featuring rail-to-rail inputs and outputs. It is guaranteed to operate from 3 V to 30 V (or ±1.5 V to ±15 V).
These amplifiers are well suited for single-supply applications
requiring both ac and precision dc performance. The combination of wide bandwidth, low noise, and precision makes the
ADA4084-2 useful in a wide variety of applications, including
filters and instrumentation.
Other applications for these amplifiers include portable telecommunications equipment, power supply control and protection,
and use as amplifiers or buffers for transducers with wide output
ranges. Sensors requiring a rail-to-rail input amplifier include
Hall effect, piezoelectric, and resistive transducers.
The ability to swing rail-to-rail at both the input and output
enables designers to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios.
The ADA4084-2 is a member of a growing series of high voltage,
low noise op amps offered by Analog Devices, Inc., (see Table 1).
For a more complete selection table of low input voltage noise
amplifiers, see the AN-940 Application Note, Low Noise
Amplifier Selection Guide for Optimal Noise Performance,
available at www.analog.com.
Table 1. Low Noise Op Amps
Voltage Noise
1.1 nV/Hz
1.8 nV/Hz
2.8 nV/Hz RRO1
2.8 nV/Hz
3.2 nV/Hz
3.9 nV/Hz RRIO2
1
2
Single
AD8597
ADA4004-1
AD8675
AD8671
OP27/OP37
Dual
AD8599
ADA4004-2
AD8676
AD8672
Quad
ADA4004-4
AD8674
ADA4084-2
Rail-to-rail output.
Rail-to-rail input/output.
The ADA4084-2 is specified over the industrial temperature
range of −40°C to +125°C. The dual ADA4084-2 is available in
the 8-lead SOIC and MSOP surface-mount packages.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADA4084-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
±15 V Characteristics ................................................................ 15
Applications ....................................................................................... 1
Comparative Voltage and Variable Voltage Graphs ............... 19
General Description ......................................................................... 1
Applications Information .............................................................. 20
Pin Configurations ........................................................................... 1
Functional Description .............................................................. 20
Revision History ............................................................................... 2
Input Protection ......................................................................... 21
Specifications..................................................................................... 3
Output Phase Reversal ............................................................... 21
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 6
Designing Low Noise Circuits in Single-Supply
Applications ................................................................................ 21
Thermal Resistance ...................................................................... 6
Comparator Operation .............................................................. 22
ESD Caution .................................................................................. 6
Outline Dimensions ....................................................................... 23
Typical Performance Characteristics ............................................. 7
Ordering Guide .......................................................................... 23
±1.5 V Characteristics.................................................................. 7
±5 V Characteristics ................................................................... 11
REVISION HISTORY
2/12—Rev. 0 to Rev. A
Changes to Data Sheet Title ............................................................ 1
Changes to Voltage Range in General Description ...................... 1
Changes to Supply Current/Amplifier Parameter, Table 2.......... 3
Changes to Common-Mode Rejection Ratio Parameter, Table 3.. 4
Changes to Common-Mode Rejection Ratio Parameter, Table 4.. 5
Changes to Figure 2 .......................................................................... 6
Changes to Figure 24 ...................................................................... 10
Changes to Figure 32 ...................................................................... 12
Changes to Figure 47 ...................................................................... 14
Changes to Figure 55 ...................................................................... 16
Changes to Figure 62 ...................................................................... 17
Changes to Figure 73 ...................................................................... 20
10/11—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADA4084-2
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VSY = 3 V, VCM =1.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage 1
Offset Voltage Drift
Offset Voltage Matching
Input Bias Current
Symbol
Test Conditions/Comments
VOS
SOIC package
−40°C ≤ TA ≤ +125°C
MSOP package
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Channel A vs. Channel B, TA = 25°C
ΔVOS/ΔT
Min
Typ
0.5
IB
140
–40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
–40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Input Impedance, Differential
Input Impedance, Common-Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOH
VOL
ISC
Supply Current/Amplifier
ISY
1
0
64
60
100
97
Unit
100
200
130
250
1.75
150
300
450
25
50
3
μV
μV
μV
μV
µV/°C
μV
nA
nA
nA
nA
V
dB
dB
dB
dB
kΩ||pF
MΩ||pF
80
104
100||1.1
80||2.9
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
Phase Margin
−3 dB Closed-Loop Bandwidth
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
VCM = 0 V to 3 V
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ, 0.5 V ≤ VO ≤ 2.5 V
RL = 2 kΩ, −40°C ≤ TA ≤ +125°C
Max
PSRR
RL = 10 kΩ to VCM
–40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
–40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
–40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
–40°C ≤ TA ≤ +125°C
2.85
2.8
2.8
2.7
2.95
2.9
10
20
40
50
75
−17/+10
VSY = ±1.25 V to ±1.75 V
–40°C ≤ TA ≤ +125°C
IO = 0 mA
–40°C ≤ TA ≤ +125°C
100
90
SR
GBP
UGC
ΦM
−3 dB
RL = 2 kΩ
VIN = 5 mV p-p, RL = 10 kΩ, AV = 100
VIN = 5 mV p-p, RL = 10 kΩ, AV = 1
2.0
en p-p
en
in
110
565
650
950
V
V
V
V
mV
mV
mV
mV
mA
dB
dB
µA
µA
AV = 1, VIN = 5 mV p-p
2.6
15.4
8.08
86
12.3
V/µs
MHz
MHz
Degrees
MHz
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.14
3.9
0.55
μV p-p
nV/√Hz
pA/√Hz
Offset voltage does not include solder heat resistance.
Rev. A | Page 3 of 24
ADA4084-2
Data Sheet
VSY = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage 1
Offset Voltage Drift
Offset Voltage Matching
Input Bias Current
Symbol
Conditions
VOS
SOIC package
−40°C ≤ TA ≤ +125°C
MSOP package
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Channel A vs. Channel B, TA = 25°C
ΔVOS/ΔT
Min
Typ
0.5
IB
140
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Input Impedance, Differential
Input Impedance, Common-Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOH
VOL
ISC
Supply Current/Amplifier
ISY
1
−5
106
76
108
103
Unit
100
250
130
250
1.75
150
300
450
25
50
+5
μV
μV
μV
μV
μV/°C
μV
nA
nA
nA
nA
V
dB
dB
dB
dB
kΩ||pF
MΩ||pF
124
112
100||1.1
200||2.5
Short Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
Phase Margin
−3 dB Closed-Loop Bandwidth
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
VCM = ±4 V
VCM = ±5 V, −40°C ≤ TA ≤ +125°C
RL = 2 kΩ, −4 V ≤ VO ≤ 4 V
RL = 2 kΩ, −40°C ≤ TA ≤ +125°C
Max
PSRR
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
4.9
4.8
4.8
4.7
4.95
4.85
−4.95
−4.95
−4.9
−4.8
−4.8
−4.7
−24/+17
VSY = ±2 V to ±18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
−40°C ≤ TA ≤ +125°C
110
105
SR
GBP
UGC
ΦM
−3 dB
RL = 2 kΩ to VCM
VIN = 5 mV p-p, RL = 10 kΩ, AV = 100
VIN = 5 mV p-p, RL = 10 kΩ, AV = 1
2.4
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
AV = 1, VIN = 5 mV p-p
Offset Voltage does not include solder heat resistance.
Rev. A | Page 4 of 24
120
595
700
1000
V
V
V
V
V
V
V
V
mA
dB
dB
µA
µA
3.7
15.9
9.6
85
13.9
V/µs
MHz
MHz
Degrees
MHz
0.14
3.9
0.55
µV p-p
nV/√Hz
pA/√Hz
Data Sheet
ADA4084-2
VSY = ±15.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
INPUT CHARACTERISTICS
Offset Voltage 1
Offset Voltage Drift
Offset Voltage Matching
Input Bias Current
Symbol
Conditions
VOS
SOIC package
−40°C ≤ TA ≤ +125°C
MSOP package
−40°C ≤ TA ≤ +125°C
Min
ΔVOS/ΔT
Typ
0.5
Channel A vs. Channel B, TA = 25°C
IB
140
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Input Impedance, Differential
Input Impedance, Common-Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOH
VOL
ISC
Supply Current/Amplifier
ISY
1
−15
106
85
110
105
Unit
100
200
130
250
1.75
150
300
450
25
50
+15
μV
μV
μV
μV
μV/°C
μV
nA
nA
nA
nA
V
dB
dB
dB
dB
kΩ||pF
MΩ||pF
124
117
100||1.1
200||2.5
Short Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
Phase Margin
−3 dB Closed-Loop Bandwidth
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
VCM = ±14 V
VCM = ±15 V, −40°C ≤ TA ≤ +125°C
RL = 2 kΩ, −13.5 V ≤ VO ≤ +13.5 V
−40°C ≤ TA ≤ +125°C
Max
PSRR
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
14.8
14.8
14.5
14.3
14.9
14.6
−14.95
−14.9
−14.9
−14.8
−14.8
−14.7
±30
VSY = ±2 V to ±18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
−40°C ≤ TA ≤ +125°C
110
105
SR
GBP
UGC
ΦM
−3 dB
RL = 2 kΩ
VIN = 5 mV p-p, RL = 10 kΩ, AV = 100
VIN = 5 mV p-p, RL = 10 kΩ, AV = 1
2.4
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
AV = 1, VIN = 5 mV p-p
Offset Voltage does not include solder heat resistance.
Rev. A | Page 5 of 24
120
625
750
1050
V
V
V
V
V
V
V
V
mA
dB
dB
µA
µA
4.6
15.9
9.9
86
13.9
V/µs
MHz
MHz
Degrees
MHz
0.1
3.9
0.55
µV p-p
nV/√Hz
pA/√Hz
ADA4084-2
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage1
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering 60 sec)
1
THERMAL RESISTANCE
Rating
±18 V
V− ≤ VIN ≤ V+
±0.6 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
θJA is specified for the device soldered on a 4-layer JEDEC
standard printed circuit board (PCB) with zero airflow.
Table 6. Thermal Resistance
Package Type
8-Lead SOIC
8-Lead MSOP
θJA
121
142
θJC
43
45
ESD CAUTION
For input differential voltages greater than 0.6 V, the input current should be
limited to less than 5 mA to prevent degradation or destruction of the input
devices.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VCC
R4
R3
R6
Q24
D2
Q1
Q23
D1
Q2
MIRROR
D100
Q4
D101
FOLDED
CASCADE
Q3
VOUT
R7 C2
Q13
D5
VBIAS
D4
R5
Q18
C1
R1
R2
Q21
D20
Figure 2. Simplified Schematic
Rev. A | Page 6 of 24
VEE
08237-002
Q19
Unit
°C/W
°C/W
Data Sheet
ADA4084-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
±1.5 V CHARACTERISTICS
500
120
ADA4084-2
VSY = ±1.5V
TA = 25°C
RL = ∞
80
60
40
300
200
100
0
–100
–200
–300
ADA4084-2
VSY = ±1.5V
TA = 25°C
RL = ∞
20
–400
–75
–25
–50
0
25
75
50
100
VOS (µV)
–500
08237-003
0
–100
0
COMMON-MODE VOLTAGE (V)
Figure 3. Input Offset Voltage Distribution, SOIC
Figure 6. Input Offset Voltage vs. Common-Mode Voltage
–50
50
ADA4084-2
VSY = ±1.5V
TA = 25°C
RL = ∞
45
40
IB+
–100
35
INPUT BIAS (nA)
30
25
20
–150
IB–
15
–200
10
–75
–50
–25
0
25
50
75
100
VOS (µV)
–250
–40
08237-004
0
–100
400
40
200
INPUT BIAS (nA)
50
30
20
0.2
0.4
0.6
0.8
1.0
1.2
1.4
TCVOS (µV/°C)
1.6
1.8
20
35
50
65
80
95
110
125
TA = +125°C
0
TA = +85°C
–200
TA = +25°C
ADA4084-2
VSY = ±1.5V
TA = 25°C
RL = ∞
–40° ≤ TA ≤ +125°C
–400
TA = –40°C
ADA4084-2
VSY = ±1.5V
2.0
08237-005
NUMBER OF AMPLIFIERS
600
0
5
Figure 7. Input Bias Current vs. Temperature
60
0
–10
TEMPERATURE (°C)
Figure 4. Input Offset Voltage Distribution, MSOP
10
–25
08237-007
ADA4084-2
VSY = ±1.5V
VCM = 0V
RL = ∞
5
–600
–1.5
–1.0
–0.5
0
0.5
1.0
VCM (V)
Figure 8. Input Bias Current vs. VCM and Temperature
Figure 5. TCVOS Distribution, SOIC
Rev. A | Page 7 of 24
1.5
08237-008
NUMBER OF AMPLIFIERS
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00
08237-006
INPUT OFFSET VOLTAGE (µV)
NUMBER OF AMPLIFIERS
100
400
ADA4084-2
Data Sheet
60
1000
40
AV = +100
30
GAIN (dB)
100
VDO (mV)
ADA4084-2
VSY = ±1.5V
TA = 25°C
50
20
AV = +10
10
(V+) –VOH
0
ADA4084-2
VSY = ±1.5V
TA = 25°C
0.01
0.1
1
–10
–20
10
08237-009
1
0.001
10
LOAD CURRENT (mA)
AV = +1
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
08237-012
10
Figure 12. Closed-Loop Gain vs. Frequency
Figure 9. Dropout Voltage vs. Source Current
1000
1000
AV = +10
100
ZOUT (Ω)
10
10
1
0.10
0.1
1
10
0.01
10
LOAD CURRENT (mA)
270
140
225
120
180
100
135
40
90
20
45
0
0
PSRR (dB)
60
PHASE (Degrees)
ADA4084-2
VSY = ±1.5V
TA = 25°C
RL = 10kΩ
100
1k
10k
100k
1M
10M
100M
–90
100k
FREQUENCY (kHz)
ADA4084-2
VSY = ±1.5V
TA = 25°C
80
60
PSRR–
20
PSRR+
0
08237-011
10
10k
40
–45
–20
1
1k
Figure 13. Output Impedance vs. Frequency
120
80
100
FREQUENCY (Hz)
Figure 10. Dropout Voltage vs. Sink Current
100
ADA4084-2
VSY = ±1.5V
TA = 25°C
08237-013
0.01
08237-010
1
0.001
GAIN (dB)
AV = +1
VOL – (V–)
ADA4084-2
VSY = ±1.5V
TA = 25°C
–40
0.1
AV = +100
–20
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 14. PSRR vs. Frequency
Figure 11. Open-Loop Gain and Phase vs. Frequency
Rev. A | Page 8 of 24
10M
100M
08237-014
VDO (mV)
100
Data Sheet
ADA4084-2
2
ADA4084-2
VSY = ±1.5V
TA = 25°C
110
100
INPUT
0
90
0.06
0.04
–2
VOLTAGE (V)
CMRR (dB)
0.08
80
70
60
0.02
–4
OUTPUT
–6
VOLTAGE (V)
120
0
50
ADA4084-2
VSY = ±1.5V
TA = 25°C
–8
30
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–10
–1
08237-015
20
10
–0.04
0
1
4
5
6
7
8
9
TIME (µs)
Figure 18. Settling Time
1.5
10
0.5
0
–0.5
–1.0
–1.5
0
2
4
6
8
10
12
14
16
18
TIME (µs)
ADA4084-2
VSY = ±1.5V
TA = 25°C
1
08237-016
ADA4084-2
VSY = ±1.5V
TA = 25°C
RL = 2kΩ
CL = 100pF
4
1
10
100
1k
10k
FREQUENCY (Hz)
100k
08237-019
VOLTAGE NOISE DENSITY (nV/√Hz)
1.0
Figure 19. Voltage Noise Density
Figure 16. Large Signal Transient Response
60
80
60
ADA4084-2
VSY = ±1.5V
VIN = 100mV p-p
RL = 2kΩ
TA = 25°C
50
OVERSHOOT (%)
40
20
0
–20
ADA4084-2
VSY = ±1.5V
TA = 25°C
RL = 2kΩ
CL = 100pF
–60
–80
0
2
4
6
8
10
40
30
20
OS–
10
12
14
TIME (µs)
16
18
08237-017
–40
OS+
Figure 17. Small Signal Transient Response
0
1
10
100
CAPACITANCE (pF)
Figure 20. Overshoot vs. Capacitance
Rev. A | Page 9 of 24
1000
08237-020
VOLTAGE (V)
3
2
Figure 15. CMRR vs. Frequency
VOLTAGE (mV)
–0.02
08237-018
40
ADA4084-2
Data Sheet
0.01
80
60
20
THD + N (%)
0
–20
0.001
ADA4084-2
VSY = ±1.5V
TA = 25°C
–80
0
1
2
3
4
5
6
7
8
9
10
TIME (Seconds)
0.0001
10
08237-021
–60
100
Figure 21. Voltage Noise 0.1 Hz to 10 Hz
10k
100k
Figure 24. THD + N vs. Frequency
0
2.0
ADA4084-2
VSY = ±1.5V
TA = 25°C
VIN = 1V p-p
–20
–40
ADA4084-2
VSY = ±1.5V
TA = 25°C
1.5
1.0
VOLTAGE (V)
–60
–80
–100
0.5
OUTPUT
0
–0.5
INPUT
–120
–1.0
–140
–1.5
–160
100
1k
10k
100k
FREQUENCY (Hz)
08237-022
CHANNEL SEPARATION (dB)
1k
FREQUENCY (Hz)
08237-024
ADA4084-2
RL = 2kΩ
VIN = 0.4VRMS
VSY = ±1.5V
TA = 25°C
500kHz FILTER
–40
Figure 22. Channel Separation
THD + N (%)
0.1
0.01
0.1
AMPLITUDE (VRMS)
1
08237-023
ADA4084-2
VSY = ±1.5V
TA = 25°C
f = 1kHz
0.01
0
100
200
300
400
500
600
700
TIME (µs)
Figure 25. No Phase Reversal
1
0.001
0.001
–2.0
Figure 23. THD + N vs. Amplitude
Rev. A | Page 10 of 24
800
900
1000
08237-025
VOLTAGE NOISE (nV)
40
Data Sheet
ADA4084-2
±5 V CHARACTERISTICS
600
120
ADA4084-2
VSY = ±5V
TA = 25°C
RL = ∞
500
400
80
60
40
300
200
100
0
–100
–200
–300
ADA4084-2
VSY = ±5V
TA = 25°C
RL = ∞
–400
20
–500
–75
–50
–25
0
25
50
75
100
VOS (µV)
–600
–5
08237-026
0
–100
–3
–2
–1
0
1
2
4
5
Figure 29. Input Offset Voltage vs. Common-Mode Voltage
–50
60
ADA4084-2
VSY = ±5V
TA = 25°C
RL = ∞
–100
INPUT BIAS (nA)
40
30
20
IB+
–150
IB–
–200
ADA4084-2
VSY = ±5V
VCM = 0V
RL = ∞
10
–75
–50
–25
0
25
50
75
100
VOS (µV)
–250
–40
08237-027
0
–100
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
08237-030
50
Figure 30. Input Bias Current vs. Temperature
Figure 27. Input Offset Voltage Distribution MSOP
50
800
45
600
40
400
30
25
20
15
5
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
TCVOS (µV/°C)
1.6
1.8
TA = +85°C
0
TA = +125°C
–200
TA = +25°C
–400
ADA4084-2
VSY = ±5V
RL = ∞
–40° ≤ TA ≤ +125°C
10
200
ADA4084-2
VSY = ±5V
–600
2.0
TA = –40°C
–800
–5
–4
–3
–2
–1
0
1
2
3
4
VCM (V)
Figure 31. Input Bias Current vs. VCM and Temperature
Figure 28. TCVOS Distribution
Rev. A | Page 11 of 24
5
08237-031
INPUT BIAS (nA)
35
08237-028
NUMBER OF AMPLIFIERS
3
COMMON-MODE VOLTAGE (V)
Figure 26. Input Offset Voltage Distribution SOIC
NUMBER OF AMPLIFIERS
–4
08237-029
INPUT OFFSET VOLTAGE (µV)
NUMBER OF AMPLIFIERS
100
ADA4084-2
Data Sheet
60
ADA4084-2
VSY = ±5V
TA = 25°C
1000
50
40
30
100
GAIN (dB)
VDO (mV)
AV = +100
20
AV = +10
10
(V+) –VOH
0
ADA4084-2
VSY = ±5V
TA = 25°C
0.01
0.1
1
–10
–20
10
08237-032
1
0.001
AV = +1
10
LOAD CURRENT (mA)
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 32. Dropout Voltage vs. Source Current
08237-035
10
Figure 35. Closed-Loop Gain vs. Frequency
1000
1000
100
ZOUT (Ω)
10
1
VOL – (V–)
ADA4084-2
VSY = ±5V
TA = 25°C
0.01
0.1
1
0.01
10
08237-033
1
0.001
0.10
10
LOAD CURRENT (mA)
140
225
120
180
100
135
40
90
20
45
0
0
PSRR (dB)
60
100
1k
10k
100k
1M
10M
100M
–90
100k
FREQUENCY (kHz)
ADA4084-2
VSY = ±5V
TA = 25°C
80
60
PSRR–
20
PSRR+
0
–45
–20
10
10k
40
08237-034
GAIN (dB)
270
PHASE (Degrees)
ADA4084-2
VSY = ±5V
TA = 25°C
RL = 10kΩ
1
1k
Figure 36. Output Impedance vs. Frequency
120
80
100
FREQUENCY (Hz)
Figure 33. Dropout Voltage vs. Sink Current
100
ADA4084-2
VSY = ±5V
TA = 25°C
08237-036
10
–40
0.1
AV = +1
AV = +100
Figure 34. Open-Loop Gain and Phase vs. Frequency
–20
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 37. PSRR vs. Frequency
Rev. A | Page 12 of 24
10M
100M
08237-037
VDO (mV)
100
AV = +10
Data Sheet
ADA4084-2
120
10
0.16
5
0.12
ADA4084-2
VSY = ±5V
TA = 25°C
110
100
INPUT
70
60
50
0.04
–5
OUTPUT
0
–10
–15
–0.04
ADA4084-2
VSY = ±5V
TA = 25°C
40
–20
100
1k
10k
100k
1M
100M
10M
FREQUENCY (Hz)
08237-038
30
20
10
VOLTAGE (V)
80
–25
–2
–0.08
–0.12
0
4
2
6
8
10
12
14
16
08237-041
VOLTAGE (V)
CMRR (dB)
0.08
0
90
18
TIME (µs)
Figure 38. CMRR vs. Frequency
Figure 41. Settling Time
5
10
3
1
0
–1
–2
ADA4084-2
VSY = ±5V
TA = 25°C
RL = 2kΩ
CL = 100pF
–3
–4
–5
0
2
4
6
8
10
12
14
16
18
TIME (µs)
4
ADA4084-2
VSY = ±5V
TA = 25°C
1
08237-039
1
100
1k
10k
FREQUENCY (Hz)
100k
Figure 42. Voltage Noise Density
Figure 39. Large Signal Transient Response
60
80
ADA4084-2
VSY = ±5V
VIN = 100mV p-p
RL = 2kΩ
TA = 25°C
60
50
OVERSHOOT (%)
40
20
0
–20
ADA4084-2
VSY = ±5V
TA = 25°C
RL = 2kΩ
CL = 100pF
–40
–60
–80
0
1
2
3
4
5
OS+
40
30
20
OS–
10
6
7
8
TIME (µs)
9
10
08237-040
VOLTAGE (mV)
10
Figure 40. Small Signal Transient Response
0
1
10
100
1000
CAPACITANCE (pF)
Figure 43. Overshoot vs. Load Capacitance
Rev. A | Page 13 of 24
08237-043
VOLTAGE (V)
2
08237-042
VOLTAGE NOISE DENSITY (nV/√Hz)
4
ADA4084-2
Data Sheet
1
80
60
0.1
20
THD + N (%)
0
–20
0.001
–40
1
2
3
4
5
6
7
8
9
10
TIME (Seconds)
0.0001
10
08237-044
0
100
Figure 44. Volage Noise 0.1 Hz to 10 Hz
100k
6
ADA4084-2
VSY = ±5V
TA = 25°C
VIN = 5V p-p
–20
–40
ADA4084-2
VSY = ±5V
TA = 25°C
4
2
–60
VOLTAGE (V)
CHANNEL SEPARATION (dB)
10k
Figure 47. THD + N vs. Frequency
0
–80
–100
0
OUTPUT
–2
INPUT
–120
–4
–160
100
1k
10k
100k
FREQUENCY (Hz)
08237-045
–140
Figure 45. Channel Separation
0.1
0.01
ADA4084-2
VSY = ±5V
TA = 25°C
f = 1kHz
0.0001
0.001
0.01
0.1
AMPLITUDE (VRMS)
1
08237-046
0.001
–6
0
100
200
300
400
500
600
700
TIME (µs)
Figure 48. No Phase Reversal
1
THD + N (%)
1k
FREQUENCY (Hz)
08237-047
ADA4084-2
VSY = ±5V
TA = 25°C
–60
–80
0.01
Figure 46. THD + N vs. Amplitude
Rev. A | Page 14 of 24
800
900
1000
08237-048
VOLTAGE NOISE (nV)
40
ADA4084-2
RL = 2kΩ
VIN = 2.0VRMS
VSY = ±5V
TA = 25°C
500kHz FILTER
Data Sheet
ADA4084-2
±15 V CHARACTERISTICS
600
100
ADA4084-2
VSY = ±15V
TA = 25°C
RL = ∞
400
60
50
40
30
20
200
100
0
–100
–200
–300
ADA4084-2
VSY = ±15V
TA = 25°C
RL = ∞
–400
10
–500
–75
–50
–25
0
25
50
75
100
VOS (µV)
–600
–15
08237-049
0
–100
–10
0
–5
5
10
Figure 52. Input Offset Voltage vs. Common-Mode Voltage
–50
ADA4084-2
VSY = ±15V
TA = 25°C
RL = ∞
50
IB+
–100
INPUT BIAS (nA)
40
30
20
–150
IB–
–200
ADA4084-2
VSY = ±15V
VCM = 0V
RL = ∞
10
–75
–50
–25
0
25
50
75
100
VOS (µV)
–250
–40
08237-050
0
–100
800
40
400
INPUT BIAS (nA)
50
30
20
ADA4084-2
VSY = ±15V
RL = ∞
–40° ≤ TA ≤ +125°C
0.4
0.6
0.8
1.0
1.2
1.4
TCVOS (µV/°C)
1.6
1.8
20
35
50
65
80
95
110
125
TA = +125°C
TA = +85°C
0
TA = +25°C
–400
–800
2.0
08237-051
NUMBER OF AMPLIFIERS
1200
0.2
5
Figure 53. Input Bias Current vs. Temperature
60
0
–10
TEMPERATURE (°C)
Figure 50. Input Offset Voltage Distribution, MSOP
10
–25
08237-053
60
0
15
COMMON-MODE VOLTAGE (V)
Figure 49. Input Offset Voltage Distribution, SOIC
NUMBER OF AMPLIFIERS
300
08237-052
70
TA = –40°C
ADA4084-2
VSY = ±15V
–1200
–15
–10
–5
0
5
10
VCM (V)
Figure 54. Input Bias Current vs. VCM and Temperature
Figure 51. TCVOS Distribution
Rev. A | Page 15 of 24
15
08237-054
NUMBER OF AMPLIFIERS
80
INPUT OFFSET VOLTAGE (µV)
90
500
ADA4084-2
Data Sheet
60
10000
ADA4084-2
VSY = ±15V
TA = 25°C
50
40
1000
AV = +100
GAIN (dB)
VDO (mV)
30
100
20
AV = +10
10
ADA4084-2
VSY = ±15V
TA = 25°C
1
0.001
0.01
0.1
1
0
AV = +1
–10
–20
10
08237-055
10
10
LOAD CURRENT (mA)
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 55. Dropout Voltage vs. Source Current
08237-058
(V+) –VOH
Figure 58. Closed-Loop Gain vs. Frequency
1000
10000
100
AV = +10
ZOUT (Ω)
100
0.01
0.1
1
AV = +1
0.1
10
0.01
10
1
LOAD CURRENT (mA)
140
225
120
180
100
40
90
20
45
0
0
PSRR (dB)
135
10k
100k
1M
10M
100k
1M
10M
100M
–90
100M
FREQUENCY (Hz)
ADA4084-2
VSY = ±15V
TA = 25°C
80
60
PSRR–
20
–45
–20
1k
10k
40
PSRR+
0
08237-057
GAIN (dB)
270
PHASE (Degrees)
ADA4084-2
VSY = ±15V
TA = 25°C
RL = 10kΩ
60
–40
100
1k
Figure 59. Output Impedance vs. Frequency
120
80
100
FREQUENCY (Hz)
Figure 56. Dropout Voltage vs. Sink Current
100
ADA4084-2
VSY = ±15V
TA = 25°C
08237-059
1
0.001
AV = +100
ADA4084-2
VSY = ±15V
TA = 25°C
08237-056
VOL – (V–)
10
10
Figure 57. Open-Loop Gain and Phase vs. Frequency
–20
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 60. PSRR vs. Frequency
Rev. A | Page 16 of 24
10M
100M
08237-060
VDO (mV)
1000
Data Sheet
ADA4084-2
120
10
ADA4084-2
VSY = ±15V
TA = 25°C
INPUT
0.10
0
VOLTAGE (V)
90
80
70
60
50
0.05
–5
OUTPUT
0
–10
–15
–0.05
40
ADA4084-2
VSY = ±15V
TA = 25°C
–20
20
10
100
1k
10k
100k
1M
08237-061
30
100M
10M
FREQUENCY (Hz)
–25
–2
–0.15
0
4
2
8
10
12
14
16
18
TIME (µs)
15
5
0
–5
–10
–15
0
4
8
12
16
20
24
28
32
36
TIME (µs)
ADA4084-2
VSY = ±15V
TA = 25°C
1
08237-062
ADA4084-2
VSY = ±15V
TA = 25°C
RL = 2kΩ
CL = 100pF
4
1
70
60
60
40
ADA4084-2
VSY = ±15V
VIN = 100mV p-p
RL = 2kΩ
TA = 25°C
OVERSHOOT (%)
50
20
0
–20
3
4
5
6
7
8
TIME (µs)
9
10
08237-063
2
100k
OS+
30
OS–
10
–80
1
10k
40
20
ADA4084-2
VSY = ±15V
TA = 25°C
RL = 2kΩ
CL = 100pF
0
1k
Figure 65. Voltage Noise Density
80
–60
100
FREQUENCY (Hz)
Figure 62. Large Signal Transient Response
–40
10
08237-065
VOLTAGE NOISE DENSITY (nV/√Hz)
10
10
VOLTAGE (V)
6
Figure 64. Settling Time
Figure 61. CMRR vs. Frequency
VOLTAGE (mV)
–0.10
Figure 63. Small Signal Transient Response
0
1
10
100
1000
CAPACITANCE (pF)
Figure 66. Overshoot vs. Load Capacitance
Rev. A | Page 17 of 24
08237-066
CMRR (dB)
0.15
5
VOLTAGE (V)
100
08237-064
110
0.20
ADA4084-2
Data Sheet
1
60
ADA4084-2
VSY = ±15V
TA = 25°C
500kHz FILTER
40
THD + N (%)
VOLTAGE NOISE (nV)
0.1
20
0
0.01
–20
0.001
0
2
4
6
8
10
TIME (Seconds)
0.0001
10
08237-067
–60
100
100k
20
0
ADA4084-2
VSY = ±15V
TA = 25°C
VIN = 10V p-p
–20
–40
ADA4084-2
VSY = ±15V
TA = 25°C
15
10
–60
VOLTAGE (V)
–80
–100
5
0
OUTPUT
–5
INPUT
–120
–10
–140
–15
–180
100
1k
10k
100k
FREQUENCY (Hz)
08237-068
–160
1
0.1
0.01
0.001
0.1
1
AMPLITUDE (VRMS)
10
08237-069
ADA4084-2
VSY = ±15V
TA = 25°C
f = 1kHz
0.01
0
100
200
300
400
500
600
700
TIME (µs)
Figure 71. No Phase Reversal
Figure 68. Channel Sepatation
0.0001
0.001
–20
Figure 69. THD + N vs. Amplitude
Rev. A | Page 18 of 24
800
900
1000
08237-071
CHANNEL SEPARATION (dB)
10k
Figure 70. THD + N vs. Frequency
Figure 67. Voltage Noise 0.1 Hz to 10 Hz
THD + N (%)
1k
FREQUENCY (Hz)
08237-070
ADA4084-2
VSY = ±15V
TA = 25°C
–40
Data Sheet
ADA4084-2
COMPARATIVE VOLTAGE AND VARIABLE VOLTAGE GRAPH
1000
900
+125°C
+85°C
700
+25°C
600
–40°C
500
400
300
200
ADA4084-2
TA = 25°C
RL = ∞
100
0
0
4
8
12
16
20
24
28
VSY (V)
32
36
08237-072
ISY/AMPLIFIER (µA)
800
Figure 72. Supply Current vs. Supply Voltage
Rev. A | Page 19 of 24
ADA4084-2
Data Sheet
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
The ADA4084-2 is a precision single-supply, rail-to-rail operational amplifier. Intended for portable instrumentation, the
ADA4084-2 combines the attributes of precision, wide bandwidth, and low noise to make it an ideal choice in single-supply
applications that require both ac and precision dc performance.
Other low supply voltage applications for which the ADA4084-2
is well suited are active filters, audio microphone preamplifiers,
power supply control, and telecommunications. To combine all
of these attributes with rail-to-rail input/output operation, novel
circuit design techniques are used.
R4
R3
important that the effective source impedances connected to
the ADA4084-2 inputs be balanced for optimum dc and ac
performance.
To achieve rail-to-rail output, the ADA4084-2 output stage
design employs a unique topology for both sourcing and sinking
current. This circuit topology is illustrated in Figure 74. The
output stage is voltage-driven from the second gain stage. The
signal path through the output stage is inverting; that is, for
positive input signals, Q13 provides the base current drive to Q19
so that it conducts (sinks) current. For negative input signals, the
signal path via Q18 → mirror → Q24 provides the base current
drive for Q23 to conduct (source) current. Both transistors
provide output current until they are forced into saturation.
VCC
R6
D2
Q1
D1
Q2
Q24
Q23
D100
Q4
D101
Q3
MIRROR
VOUT
D5
D4
R7 C2
Q13
R1
R2
08237-073
VBIAS
R5
Q18
C1
Q19
For example, Figure 73 illustrates a simplified equivalent circuit
for the input stage of the ADA4084-2. It comprises a PNP
differential pair, Q1 and Q2, and an NPN differential pair, Q3
and Q4, operating concurrently. Diode D100 and Diode D101
serve to clamp the applied differential input voltage to the
ADA4084-2, thereby protecting the input transistors against
Zener breakdown of the emitter-base junctions. Input stage
voltage gains are kept low for input rail-to-rail operation. The
two pairs of differential output voltages are connected to the
second stage of the ADA4084-2, which is a modified compound
folded cascade gain stage. It is also in the second gain stage,
where the two pairs of differential output voltages are combined
into a single-ended output signal voltage used to drive the
output stage.
Q21
D20
VEE
08237-074
Figure 73. ADA4084-2 Equivalent Input Circuit
Figure 74. ADA4084-2 Equivalent Output Circuit
Thus, the saturation voltage of the output transistors sets the
limit on the ADA4084-2 maximum output voltage swing. Output
short-circuit current limiting is determined by the maximum
signal current into the base of Q13 from the second gain stage.
The output stage also exhibits voltage gain. This is accomplished
by the use of common-emitter amplifiers, and, as a result, the
voltage gain of the output stage (thus, the open-loop gain of the
device) exhibits a dependence on the total load resistance at the
output of the ADA4084-2.
A key issue in the input stage is the behavior of the input bias
currents over the input common-mode voltage range. Input bias
currents in the ADA4084-2 are the arithmetic sum of the base
currents in Q1 and Q4 and in Q2 and Q3. As a result of this
design approach, the input bias currents in the ADA4084-2 not
only exhibit different amplitudes; they also exhibit different
polarities. This effect is best illustrated by Figure 7, Figure 8,
Figure 30, Figure 31, Figure 53, and Figure 54. It is therefore
Rev. A | Page 20 of 24
Data Sheet
ADA4084-2
INPUT PROTECTION
OUTPUT PHASE REVERSAL
As with any semiconductor device, if conditions exist where the
applied input voltages to the device exceed either supply voltage,
the input overvoltage I-to-V characteristic of the device must be
considered. When an overvoltage occurs, the amplifier may be
damaged, depending on the magnitude of the applied voltage
and the magnitude of the fault current.
Some operational amplifiers designed for single-supply operation
exhibit an output voltage phase reversal when their inputs are
driven beyond their useful common-mode range. Typically, for
single-supply bipolar op amps, the negative supply determines
the lower limit of their common-mode range. With these devices,
external clamping diodes, with the anode connected to ground
and the cathode to the inputs, prevent input signal excursions
from exceeding the negative supply of the device (that is, GND),
preventing a condition that causes the output voltage to change
phase. JFET input amplifiers can also exhibit phase reversal,
and, if so, a series input resistor is usually required to prevent it.
This input current is not inherently damaging to the device,
provided that it is limited to 5 mA or less. If a fault condition
causes more than 5 mA to flow, an external series resistor
should be added at the expense of additional thermal noise.
Figure 75 illustrates a typical noninverting configuration for an
overvoltage-protected amplifier where the series resistance, RS,
is chosen, such that
RS =
VIN ( MAX ) − VSUPPLY
5 mA
For example, a 1 kΩ resistor protects the ADA4084-2 against
input signals up to 5 V above and below the supplies. Note that
the thermal noise of a 1 kΩ resistor at room temperature is
4 nV/√Hz, which exceeds the voltage noise of the ADA4084-2.
For other configurations where both inputs are used, each input
should be protected against abuse with a series resistor. Again,
to ensure optimum dc and ac performance, it is recommended
that source impedance levels be balanced.
R2
1/2
VIN
R1
VOUT
08237-075
ADA4084-2
Figure 75. Resistance in Series with Input
Limits Overvoltage Currents to Safe Values
To protect Q1-Q2 and Q3-Q4 from large differential voltages
that may result in Zener breakdown of the emitter-base junction,
D100 and D101 are connected between the two inputs. This
precludes operation as a comparator. For a more complete
description, see the MT-035 Tutorial, Op Amp Inputs, Outputs,
Single-Supply, and Rail-to-Rail Issues; the MT-083 Tutorial,
Comparators, the MT-084 Tutorial, Using Op Amps As
Comparators; and the AN-849 Application Note, Using Op
Amps as Comparators, at www.analog.com.
The ADA4084-2 is free from reasonable input voltage range
restrictions, provided that input voltages no greater than the
supply voltages are applied. Although device output does not
change phase, large currents can flow through the input
protection diodes. Therefore, the technique recommended in the
Input Protection section should be applied to those applications
where the likelihood of input voltages exceeding the supply
voltages is high.
DESIGNING LOW NOISE CIRCUITS IN SINGLESUPPLY APPLICATIONS
In single-supply applications, devices like the ADA4084-2
extend the dynamic range of the application through the use of
rail-to-rail operation. Referring to the op amp noise model
circuit configuration illustrated in Figure 76, the expression for
an amplifier’s total equivalent input noise voltage for a source
resistance level, RS, is given by
e nT = 2 [(e nR ) 2 + (inOA ×
R S )2 ] + (e nOA )2 , units in
V
Hz
where:
RS = 2R, the effective, or equivalent, circuit source resistance.
(enR)2 is the source resistance thermal noise voltage power (4kTR).
k is the Boltzmann’s constant, 1.38 × 10–23 J/K.
T is the ambient temperature in Kelvin of the circuit, 273.15 +
TA (°C).
(inOA)2 is the op amp equivalent input noise current spectral
power (1 Hz bandwidth).
(enOA)2 is the op amp equivalent input noise voltage spectral
power (1 Hz bandwidth).
R
enR
NOISELESS
R
NOISELESS
enOA
inOA
enR
inOA
IDEAL
NOISELESS
OP AMP
RS = 2R
08237-076
The D1, D2, D4, and D5 diodes conduct when the input commonmode voltage exceeds either supply pin by a diode drop. This
varies with temperature and is in the range of 0.3 V to 0.8 V. As
illustrated in the simplified equivalent circuit shown in Figure 73,
the ADA4084-2 does not have any internal current limiting resistors; thus, fault currents can quickly rise to damaging levels.
Figure 76. Op Amp Noise Circuit Model Used to Determine Total Circuit
Equivalent Input Noise Voltage and Noise Figure
Rev. A | Page 21 of 24
ADA4084-2
Data Sheet
ADA4084-2 TOTAL
EQUIVALENT NOISE
10
RESISTOR THERMAL
NOISE ONLY
1
100
1k
10k
100k
TOTAL SOURCE RESISTANCE, RS (Ω)
Figure 77. ADA4084-2 Equivalent Thermal Noise vs. Total Source Resistance
Because circuit SNR is the critical parameter in the final analysis,
the noise behavior of a circuit is sometimes expressed in terms
of its noise figure, NF. The noise figure is defined as the ratio of
a circuit’s output signal-to-noise to its input signal-to-noise.
Noise figure is generally used for RF and microwave circuit
analysis in a 50 Ω system. This is not very useful for op amp
circuits where the input and output impedances can vary
greatly. For a more complete description of noise figure, see the
MT-052 Tutorial, Op Amp Noise Figure: Don’t be Mislead,
available at www.analog.com.
COMPARATOR OPERATION
Although op amps are quite different from comparators,
occasionally an unused section of a dual or a quad op amp
can be used as a comparator; however, this is not recommended
for any rail-to-rail output op amps. For rail-to-rail output op
amps, the output stage is generally a ratioed current mirror with
bipolar or MOSFET transistors. With the part operating open
loop, the second stage increases the current drive to the ratioed
mirror to close the loop. However, it cannot, which results in an
increase in supply current. With the op amp configured as a
comparator, the supply current can be significantly higher (see
Figure 76). An unused section should be configured as a voltage
follower with the noninverting input connected to a voltage
within the input voltage range. The ADA4084-2 has unique
second stage and output stage designs that greatly reduce the
excess supply current when the op amp is operating open loop.
800
COMPARATOR
OUTPUT LOW
700
Signal levels in the application invariably increase to maximize
circuit SNR, which is not an option in low voltage, single-supply
applications.
Therefore, to achieve optimum circuit SNR in single-supply
applications, it is recommended that an operational amplifier
with the lowest equivalent input noise voltage be chosen, along
Rev. A | Page 22 of 24
600
BUFFER
COMPARATOR
OUTPUT HIGH
500
400
300
200
ADA4084-2
TA = 25°C
RL = ∞
100
0
0
4
8
12
16
20
24
28
VSY (V)
Figure 78. Supply Current vs. Supply Voltage
32
36
08237-078
FREQUENCY = 1kHz
TA = 25°C
08237-077
EQUIVALENT THERMAL NOISE (nV/ Hz)
100
with source resistance levels that are consistent with maintaining
low total circuit noise.
SUPPLY CURRENT (µA)
As a design aid, Figure 77 shows the total equivalent input noise
of the ADA4084-2 and the total thermal noise of a resistor for
comparison. Note that for source resistance less than 1 kΩ, the
equivalent input noise voltage of the ADA4084-2 is dominant.
Data Sheet
ADA4084-2
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.23
0.09
6°
0°
0.40
0.25
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 79. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 80. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
ADA4084-2ARMZ
ADA4084-2ARMZ-R7
ADA4084-2ARMZ-RL
ADA4084-2ARZ
ADA4084-2ARZ-R7
ADA4084-2ARZ-RL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
Z = RoHS Compliant Part.
Rev. A | Page 23 of 24
Package Option
RM-8
RM-8
RM-8
R-8
R-8
R-8
Branding
A2Q
A2Q
A2Q
ADA4084-2
Data Sheet
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08237-0-2/12(A)
Rev. A | Page 24 of 24