MC14569B Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter The MC14569B is a programmable divide−by−N dual 4−bit binary or BCD down counter constructed with MOS P−Channel and N−Channel enhancement mode devices (complementary MOS) in a monolithic structure. This device has been designed for use with the MC14568B phase comparator/counter in frequency synthesizers, phase−locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. http://onsemi.com SOIC−16 WB DW SUFFIX CASE 751G Features • Speed−up Circuitry for Zero Detection • Each 4−Bit Counter Can Divide Independently in BCD or Binary Mode • Can be Cascaded With MC14526B for Frequency Synthesizer • • • • Applications All Outputs are Buffered Schmitt Triggered Clock Conditioning NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable This Device is Pb−Free and is RoHS Compliant PIN ASSIGNMENT ZERO DETECT CTL1 1 16 VDD 2 15 Q P0 3 14 P7 P1 4 13 P6 P2 5 12 P5 P3 CASCADE FEEDBACK VSS 6 11 P4 7 10 CTL2 8 9 CLOCK MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Symbol VDD Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Vin, Vout Iin, Iout DC Supply Voltage Range Value Input or Output Voltage Range (DC or Transient) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 8 1 MARKING DIAGRAM 16 14569B AWLYYWWG 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: MC14569B/D MC14569B BLOCK DIAGRAM P0 P1 P2 P3 CTL = Low for Binary Count 3 CTL = High for BCD Count CLOCK 9 CASCADE 7 FEEDBACK 4 5 CTL1 CTL2 6 2 10 P4 P5 P6 P7 11 12 13 CLOCK LOAD BINARY/BCD COUNTER #1 ZERO DETECT ENCODER 14 BINARY/BCD COUNTER #2 VDD = PIN 16 VSS = PIN 8 15 Q 1 ZERO DETECT ORDERING INFORMATION Package Shipping† MC14569BDWG SOIC−16 WB (Pb−Free) 47 Units / Rail MC14569BDWR2G SOIC−16 WB (Pb−Free) 1000 Units / Tape & Reel NLV14569BDWR2G* SOIC−16 WB (Pb−Free) 1000 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 2 MC14569B ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) – 55_C Characteristic Symbol 25_C VDD Vdc Min Max Min Typ (Note 2) 125_C Max Min Max Unit Output Voltage Vin = VDD or 0 “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc Vin = 0 or VDD “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) “1” Level 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 –1.3 –3.4 –4.2 –0.88 –2.25 –8.8 − − − − –1.7 –0.36 –0.9 –2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc IT 5.0 10 15 Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) VIH Vdc IOH Source Sink Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Vdc mAdc IT = (0.58 mA/kHz) f + IDD IT = (1.20 mA/kHz) f + IDD IT = (1.95 mA/kHz) f + IDD mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001. http://onsemi.com 3 MC14569B SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) All Types VDD Vdc Min Typ (Note 5) Max Unit Output Rise Time tTLH 5.0 10 15 − − − 100 50 40 200 100 80 ns Output Fall Time tTHL 5.0 10 15 − − − 100 50 40 200 100 80 ns Turn−On Delay Time Zero Detect Output tPLH 5.0 10 15 − − − 420 175 125 700 300 250 5.0 10 15 − − − 675 285 200 1200 500 400 5.0 10 15 − − − 380 150 100 600 300 200 5.0 10 15 − − − 530 225 155 1000 400 300 ns tWH 5.0 10 15 300 150 115 100 45 30 − − − ns fcl 5.0 10 15 − − − 3.5 9.5 13.0 2.1 5.1 7.8 MHz tTLH, tTHL 5.0 10 15 Symbol Characteristic ns Q Output tPHL Turn−Off Delay Time Zero Detect Output ns Q Output Clock Pulse Width Clock Pulse Frequency Clock Pulse Rise and Fall Time ns ms NO LIMIT 5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. SWITCHING WAVEFORMS 20 ns 20 ns 20 ns 20 ns CLOCK 10% 90% 50% fin = fmax CLOCK 10% tWH tWH tPHL tPLH Q 10% 90% 50% tPHL tPLH 90% 90% 50% ZERO DETECT tTHL tTLH 10% tTLH Figure 1. tTHL Figure 2. http://onsemi.com 4 MC14569B PIN DESCRIPTIONS INPUTS CONTROLS P0, P1, P2, P3 (Pins 3, 4, 5, 6) − Preset Inputs. Programmable inputs for the least significant counter. May be binary or BCD depending on the control input. P4, P5, P6, P7 (Pins 11, 12, 13, 14) − Preset Inputs. Programmable inputs for the most significant counter. May be binary or BCD depending on the control input. Clock (Pin 9) − Preset data is decremented by one on each positive transition of this signal. Cascade Feedback (Pin 7) − This pin is normally set high. When low, loading of the preset inputs (P0 through P7) is inhibited, i.e., P0 through P7 are “don’t cares.” Refer to Table 1 for output characteristics. CTL1 (Pin 2) − This pin controls the counting mode of the least significant counter. When set high, counting mode is BCD. When set low, counting mode is binary. CTL2 (Pin 10) − This pin controls the counting mode of the most significant counter. When set high, counting mode is BCD. When set low, counting mode is binary. OUTPUTS Zero Detect (Pin 1) − This output is normally low and goes high for one clock cycle when the counter has decremented to zero. Q (Pin 15) − Output of the last stage of the most significant counter. This output will be inactive unless the preset input P7 has been set high. SUPPLY PINS VSS (Pin 18) − Negative Supply Voltage. This pin is usually connected to ground. VDD (Pin 16) − Positive Supply Voltage. This pin is connected to a positive supply voltage ranging from 3.0 V to 18 V. OPERATING CHARACTERISTICS one pulse appears on the Zero Detect output. (See Timing Diagram.) The Q output is the output of the last stage of the most significant counter (See Tables 1 through 5, Mode Controls.) When cascading the MC14569B to the MC14526B, the Cascade Feedback input, Q, and Zero Detect outputs must be respectively connected to “0”, Clock, and Load of the following counter. If the MC14569B is used alone, Cascade Feedback must be connected to VDD. The MC14569B is a programmable divide−by−N dual 4−bit down counter. This counter may be programmed (i.e., preset) in BCD or binary code through inputs P0 to P7. For each counter, the counting sequence may be chosen independently by applying a high (for BCD count) or a low (for binary count) to the control inputs CTL1 and CTL2. The divide ratio N (N being the value programmed on the preset inputs P0 to P7) is automatically loaded into the counter as soon as the count 1 is detected. Therefore, a division ratio of one is not possible. After N clock cycles, 18 CL = 50 pF f, FREQUENCY (MHz), TYPICAL 16 14 12 VDD = 15 V 10 8.0 10 V 6.0 4.0 5.0 V 2.0 0 - 40 - 20 0 + 20 + 40 + 60 TA, AMBIENT TEMPERATURE (°C) http://onsemi.com 5 + 80 + 100 MC14569B Table 1Mode Controls (Cascade Feedback = Low) Counter Control Values Divide Ratio CTL1 CTL2 Zero Detect Q 0 0 1 1 0 1 0 1 256 160 160 100 256 160 160 100 NOTE: Data Preset Inputs (P0−P7) are “Don’t Cares” while Cascade Feedback is Low. Table 2Mode Controls (CTL1 = Low, CTL2 = Low, Cascade Feedback = High) Divide Ratio Preset Inputs P7 P6 P5 P4 P3 P2 P1 P0 Zero Detect 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 256 X 2 3 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 15 16 0 0 1 0 0 0 0 0 32 0 1 0 0 0 0 0 0 64 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 27 128 26 64 Q Comments Max Count Illegal State Min Count 127 128 256 X X X X X X X X X X X X X X X X X X X X 128 0 0 0 136 136 1 1 1 1 1 1 255 255 25 32 24 16 23 8 22 4 21 2 20 1 Counter #2 Binary Counter #1 Binary Q Output Active Bit Value Counting Sequence X = No Output (Always Low) http://onsemi.com 6 MC14569B Table 3Mode Controls (CTL1 = High, CTL2 = Low, Cascade Feedback = High) Divide Ratio Preset Inputs P7 P6 P5 P4 P3 P2 P1 P0 Zero Detect 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 160 X 2 3 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 9 10 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 19 20 0 0 1 1 0 0 0 0 30 0 1 0 0 0 0 0 0 40 0 1 0 1 0 0 0 0 50 0 1 1 0 0 0 0 0 60 0 1 1 1 0 0 0 0 70 1 0 0 0 0 0 0 0 1 0 0 1 0 1 1 Q Comments Max Count Illegal State Min Count 80 160 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 80 0 0 0 90 90 1 1 0 0 0 0 150 150 1 1 1 1 1 0 0 1 159 159 80 40 20 10 8 4 2 1 Counter #2 Binary Counter #1 BCD Q Output Active Bit Value Counting Sequence X = No Output (Always Low) http://onsemi.com 7 MC14569B Table 4Mode Controls (CTL1 = Low, CTL2 = High, Cascade Feedback = High) Divide Ratio Preset Values P7 P6 P5 P4 P3 P2 P1 P0 Zero Detect 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 160 X 2 3 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 15 16 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 31 32 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 Q Comments Max Count Illegal State Min Count 48 160 X X X X X X X X X X X X X X X X X 0 0 0 64 X 0 1 0 0 0 0 80 X 0 1 1 1 0 0 0 0 112 X 1 0 0 0 0 0 0 0 128 128 1 0 0 1 0 0 0 0 144 144 1 0 0 1 1 1 1 1 159 159 27 128 26 64 25 32 24 16 23 8 22 4 21 2 20 1 Counter #2 BCD Counter #1 Binary Q Output Active Bit Value Counting Sequence X = No Output (Always Low) http://onsemi.com 8 MC14569B Table 5Mode Controls (CTL1 = High, CTL2 = High, Cascade Feedback = High) Divide Ratio Preset Values P7 P6 P5 P4 P3 P2 P1 P0 Zero Detect 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 100 X 2 3 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 9 10 0 0 1 1 0 0 0 0 30 0 1 0 0 0 0 0 0 40 0 1 0 1 0 0 0 0 50 0 1 1 1 0 0 0 0 70 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 80 40 Q Comments Max Count illegal state Min Count 80 100 X X X X X X X X X X X X X X X X X X X X X X X X X X X 80 0 0 0 90 90 0 1 1 0 0 1 99 99 20 10 8 4 2 1 Counter #2 BCD Q Output Active Bit Value Counter #1 BCD Counting Sequence X = No Output (Always Low) TIMING DIAGRAM MC14569B CLOCK 1 2 3 4 5 6 7 8 DIVIDE BY 2 ZERO DETECT OUTPUT DIVIDE BY 3 DIVIDE BY 4 DIVIDE BY 12 http://onsemi.com 9 9 10 11 12 13 14 15 16 MC14569B LOGIC DIAGRAM CTL1 2 DP Q D DP Q P0 P1 P2 3 D DP Q 4 5 P3 PE C D PE C DP Q PE D C DP Q D 6 PE C DP Q D DP Q D DP Q D PE C PE C PE C PE C IU VDD CASCADE 7 FEEDBACK CLOCK VDD 9 1 ZERO DETECT P4 P5 P6 P7 CTL2 11 12 13 14 DP D C Q PE DP D C Q PE DP D C Q PE DP D Q PE C 15 10 http://onsemi.com 10 MC14569B TYPICAL APPLICATIONS fin C CF Q C MC14569B ZERO DETECT PE CF MC14522B OR MC14526B Q4 C “0” PE DP0 - - - - - - DP3 CF MC14522B OR MC14526B Q4 Q1/C2 “0” PE MC14568B DP0 - - - - - - DP3 “0” DP0 - - - - - - DP3 LSD fout MSD Figure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B (40 kHz) VSS PCout G VSS CT1 F VSS “0” fout VCO PCin C1 (144 - 146 MHz) Q1/C2 PE VDD DP0 - - - - DP3 MC14011 CF Q MC14569B C ZERO DETECT MIXER 2k 2M CRYSTAL OSCILLATOR Frequencies shown in parenthesis are given as an example (143.5 MHz) Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer (Channel Spacing 10 kHz) http://onsemi.com 11 MC14569B PACKAGE DIMENSIONS SOIC−16 WB CASE 751G−03 ISSUE D A D 9 1 8 h X 45 _ E 0.25 H 8X M B M 16 q 16X M B B T A MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_ S B S L A 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. 14X C A1 e T SEATING PLANE SOLDERING FOOTPRINT 16X 0.58 11.00 1 16X 1.27 PITCH 1.62 DIMENSIONS: MILLIMETERS ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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