AD AD624C Precision instrumentation amplifier Datasheet

a
FEATURES
Low Noise: 0.2 ␮V p-p 0.1 Hz to 10 Hz
Low Gain TC: 5 ppm max (G = 1)
Low Nonlinearity: 0.001% max (G = 1 to 200)
High CMRR: 130 dB min (G = 500 to 1000)
Low Input Offset Voltage: 25 ␮V, max
Low Input Offset Voltage Drift: 0.25 ␮V/ⴗC max
Gain Bandwidth Product: 25 MHz
Pin Programmable Gains of 1, 100, 200, 500, 1000
No External Components Required
Internally Compensated
Precision
Instrumentation Amplifier
AD624
FUNCTIONAL BLOCK DIAGRAM
50V
–INPUT
G = 100
AD624
225.3V
4445.7V
G = 200
124V
VB
G = 500
10kV
SENSE
80.2V
RG1
RG2
20kV
10kV
20kV
10kV
OUTPUT
10kV
50V
REF
+INPUT
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD624 is a high precision, low noise, instrumentation
amplifier designed primarily for use with low level transducers,
including load cells, strain gauges and pressure transducers. An
outstanding combination of low noise, high gain accuracy, low
gain temperature coefficient and high linearity make the AD624
ideal for use in high resolution data acquisition systems.
1. The AD624 offers outstanding noise performance. Input
noise is typically less than 4 nV/√Hz at 1 kHz.
2. The AD624 is a functionally complete instrumentation amplifier. Pin programmable gains of 1, 100, 200, 500 and 1000
are provided on the chip. Other gains are achieved through
the use of a single external resistor.
The AD624C has an input offset voltage drift of less than
0.25 µV/°C, output offset voltage drift of less than 10 µV/°C,
CMRR above 80 dB at unity gain (130 dB at G = 500) and a
maximum nonlinearity of 0.001% at G = 1. In addition to these
outstanding dc specifications, the AD624 exhibits superior ac
performance as well. A 25 MHz gain bandwidth product, 5 V/µs
slew rate and 15 µs settling time permit the use of the AD624 in
high speed data acquisition applications.
3. The offset voltage, offset voltage drift, gain accuracy and gain
temperature coefficients are guaranteed for all pretrimmed
gains.
The AD624 does not need any external components for pretrimmed gains of 1, 100, 200, 500 and 1000. Additional gains
such as 250 and 333 can be programmed within one percent
accuracy with external jumpers. A single external resistor can
also be used to set the 624’s gain to any value in the range of 1
to 10,000.
5. A sense terminal is provided to enable the user to minimize
the errors induced through long leads. A reference terminal is
also provided to permit level shifting at the output.
4. The AD624 provides totally independent input and output
offset nulling terminals for high precision applications.
This minimizes the effect of offset voltage in gain ranging
applications.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD624–SPECIFICATIONS (@ V = ⴞ15 V, R = 2 k⍀ and T = +25ⴗC, unless otherwise noted)
S
Model
Min
GAIN
Gain Equation
(External Resistor Gain
Programming)
Gain Range (Pin Programmable)
Gain Error
G=1
G = 100
G = 200, 500
Nonlinearity
G=1
G = 100, 200
G = 500
Gain vs. Temperature
G=1
G = 100, 200
G = 500
AD624A
Typ
 40, 000
 R
 G
INPUT
Input Impedance
Differential Resistance
Differential Capacitance
Common-Mode Resistance
Common-Mode Capacitance
Input Voltage Range1
Max Differ. Input Linear (VDL)
109
10
109
10
± 20
± 10
12 V −
8
± 10
 40, 000
 R
 G

Max
G
2

Min

AD624C
Typ
 40, 000
 R
 G
+ 1 ± 20%

Max
Min

 40, 000
 R
 G
+ 1 ± 20%

1 to 1000
AD624S
Typ
Max
Units

+ 1 ± 20%

1 to 1000
± 0.05
± 0.25
± 0.5
± 0.03
± 0.15
± 0.35
± 0.02
± 0.1
± 0.25
± 0.05
± 0.25
± 0.5
%
%
%
± 0.005
± 0.005
± 0.005
± 0.003
± 0.003
± 0.005
± 0.001
± 0.001
± 0.005
± 0.005
± 0.005
± 0.005
%
%
%
5
10
25
5
10
15
5
10
15
5
10
15
ppm/°C
ppm/°C
ppm/°C
200
2
5
50
75
0.5
3
25
25
0.25
2
10
75
2.0
3
50
µV
µV/°C
mV
µV/°C
± 50
80
110
115
± 50
± 35
± 20
± 25
± 15
× VD



± 10
12 V −
G
2

± 20
± 15
± 50
± 10
± 20
109
10
109
10
× VD
75
105
120



dB
dB
dB
75
105
110
± 50
109
10
109
10
70
100
110
NOISE
Voltage Noise, 1 kHz
R.T.I.
R.T.O.
R.T.I., 0.1 Hz to 10 Hz
G=1
G = 100
G = 200, 500, 1000
Current Noise
0.1 Hz to 10 Hz
AD624B
Typ
75
105
110
± 50
DYNAMIC RESPONSE
Small Signal –3 dB
G=1
G = 100
G = 200
G = 500
G = 1000
Slew Rate
Settling Time to 0.01%, 20 V Step
G = 1 to 200
G = 500
G = 1000
A
1 to 1000
INPUT CURRENT
Input Bias Current
vs. Temperature
Input Offset Current
vs. Temperature
SENSE INPUT
RIN
IIN
Voltage Range
Gain to Output

1 to 1000
OUTPUT RATING
V
, RL = 2 kΩ
Min
+ 1 ± 20%
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage
vs. Temperature
Output Offset Voltage
vs. Temperature
OUT
Offset Referred to the Input vs. Supply
G=1
70
G = 100, 200
95
G = 500
100
Max Common-Mode Linear (V CM)
Common-Mode Rejection dc
to 60 Hz with 1 kΩ Source Imbalance
G=1
G = 100, 200
G = 500
Max
L
± 10
12 V −
G
2

± 50
± 35
Ω
pF
Ω
pF
109
10
109
10
× VD
80
110
130



± 10
12 V −
G
2

nA
pA/°C
nA
pA/°C
× VD



V
V
dB
dB
dB
70
100
110
± 10
± 10
± 10
± 10
V
1
150
100
50
25
5.0
1
150
100
50
25
5.0
1
150
100
50
25
5.0
1
150
100
50
25
5.0
MHz
kHz
kHz
kHz
kHz
V/µs
15
35
75
15
35
75
15
35
75
15
35
75
µs
µs
µs
4
75
4
75
4
75
4
75
nV/√Hz
nV/√Hz
10
0.3
0.2
10
0.3
0.2
10
0.3
0.2
10
0.3
0.2
µV p-p
µV p-p
µV p-p
60
60
60
60
pA p-p
10
30
1
12
8
± 10
10
30
1
–2–
12
8
± 10
10
30
1
12
8
± 10
10
30
1
12
kΩ
µA
V
%
REV. C
AD624
Model
Min
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
AD624A
Typ
16
± 10
20
30
Max
Min
24
16
± 10
1
TEMPERATURE RANGE
Specified Performance
Storage
POWER SUPPLY
Power Supply Range
Quiescent Current
–25
–65
ⴞ6
AD624B
Typ
20
30
Max
Min
24
16
± 10
1
+85
+150
–25
–65
ⴞ15
ⴞ18
ⴞ6
3.5
5
AD624C
Typ
20
30
Max
Min
24
16
20
30
± 10
1
+85
+150
–25
–65
ⴞ15
ⴞ18
ⴞ6
3.5
5
AD624S
Typ
Max
Units
24
kΩ
µA
V
%
+125
+150
°C
°C
1
+85
+150
–55
–65
ⴞ15
ⴞ18
ⴞ6
3.5
5
ⴞ15
ⴞ18
3.5
5
V
mA
NOTES
VDL is the maximum differential input voltage at G = 1 for specified nonlinearity, V DL at other gains = 10 V/G. V D = actual differential input voltage.
1
Example: G = 10, V D = 0.50. VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production unit at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
1
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 420 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD624A/B/C . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
AD624S . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature (Soldering, 60 secs) . . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CONNECTION DIAGRAM
–INPUT
1
16 RG1
+INPUT
2
15 OUTPUT NULL
RG2
3
14 OUTPUT NULL
AD624
INPUT NULL
4
INPUT NULL
5
13 G = 100
TOP VIEW
(Not to Scale) 12 G = 200
REF
6
11 G = 500
–VS
7
10 SENSE
+VS
8
9
SHORT TO
RG2 FOR
DESIRED
GAIN
OUTPUT
FOR GAINS OF 1000 SHORT RG1 TO PIN 12
AND PINS 11 AND 13 TO RG2
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions
Dimensions shown in inches and (mm).
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD624AD
AD624BD
AD624CD
AD624SD
AD624SD/883B*
AD624AChips
AD624SChips
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–25°C to +85°C
–25°C to +85°C
16-Lead Ceramic DIP
16-Lead Ceramic DIP
16-Lead Ceramic DIP
16-Lead Ceramic DIP
16-Lead Ceramic DIP
Die
Die
D-16
D-16
D-16
D-16
D-16
*See Analog Devices’ military data sheet for 883B specifications.
REV. C
–3–
AD624–Typical Characteristics
10
5
0
5
15
10
SUPPLY VOLTAGE – 6V
INPUT BIAS CURRENT – 6nA
2.0
0
5
10
15
SUPPLY VOLTAGE – 6V
14
30
8
6
4
0
16
10k
20
10
0
–10
–20
–30
10
5
15
SUPPLY VOLTAGE – 6V
0
–40
–125
20
–75
–25
25
75
TEMPERATURE – 8C
125
Figure 6. Input Bias Current vs.
Temperature
Figure 5. Input Bias Current vs.
Supply Voltage
–1
DVOS FROM FINAL VALUE – mV
14
12
10
8
6
4
2
0
100
1k
LOAD RESISTANCE – V
Figure 3. Output Voltage Swing vs.
Load Resistance
40
10
Figure 4. Quiescent Current vs.
Supply Voltage
10
16
12
20
20
0
10
20
2
0
INPUT BIAS CURRENT – 6nA
10
5
15
SUPPLY VOLTAGE – 6V
0
10
5
15
INPUT VOLTAGE – 6V
20
Figure 7. Input Bias Current vs. CMV
0
1
500
GAIN – V/V
AMPLIFIER QUIESCENT CURRENT – mA
4.0
5
Figure 2. Output Voltage Swing vs.
Supply Voltage
8.0
6.0
10
0
0
20
Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1
15
INPUT BIAS CURRENT – nA
+258C
OUTPUT VOLTAGE SWING – V p-p
OUTPUT VOLTAGE SWING – 6V
INPUT VOLTAGE RANGE – 6V
15
0
30
20
20
2
3
100
10
4
1
5
6
0
7
0
1.0
2.0 3.0 4.0 5.0 6.0 7.0
WARM-UP TIME – Minutes
8.0
Figure 8. Offset Voltage, RTI, Turn
On Drift
–4–
1
10
100
1k
10k 100k
FREQUENCY – Hz
1M
10M
Figure 9. Gain vs. Frequency
REV. C
AD624
–100
CMRR – dB
G=1
–80
–60
–40
–20
20
G = 1, 100
G = 500
10
G = 100
G = 1000
BANDWIDTH LIMITED
0
1
10
100
1k
10k 100k
FREQUENCY – Hz
1M
0
1k
10M
1000
G = 500
–VS = –15V dc+
1V p-p SINEWAVE
120
VOLT NSD – nV/ Hz
POWER SUPPLY REJECTION – dB
160
100
80
G = 100
60
100
G=1
G = 10
10
G = 100, 1000
G = 1000
1
40
G=1
20
0
10
0.1
100
1k
10k
FREQUENCY – Hz
100k
Figure 13. Negative PSRR vs.
Frequency
1
10
100
1k
10k
FREQUENCY – Hz
100k
Figure 14. RTI Noise Spectral
Density vs. Gain
140
–VS = –15V dc+
1V p-p SINEWAVE
G = 500
120
100
80
G = 100
60
40
G=1
20
0
10
1M
Figure 11. Large Signal Frequency
Response
Figure 10. CMRR vs. Frequency RTI,
Zero to 1k Source Imbalance
140
10k
100k
FREQUENCY – Hz
-
POWER SUPPLY REJECTION – dB
G = 100
160
100
100k
1k
10k
FREQUENCY – Hz
Figure 12. Positive PSRR vs.
Frequency
CURRENT NOISE SPECTRAL DENSITY – fA/ Hz
–120
30
G = 500
FULL-POWER RESPONSE – V p-p
–140
100k
10k
1000
100
10
0.1
1
10
100
10k
FREQUENCY – Hz
100k
Figure 15. Input Current Noise
–12 TO 12
1%
0.1%
0.01%
1%
0.1%
0.01%
–8 TO 8
–4 TO 4
OUTPUT
STEP –V
4 TO –4
8 TO –8
12 TO –12
0
Figure 16. Low Frequency Voltage
Noise, G = 1 (System Gain = 1000)
REV. C
Figure 17. Low Frequency Voltage
Noise, G = 1000 (System Gain =
100,000)
–5–
5
10
15
SETTLING TIME – ms
Figure 18. Settling Time, Gain = 1
20
AD624
–12 TO 12
1%
0.1%
0.01%
–8 TO 8
–4 TO 4
OUTPUT
STEP –V
4 TO –4
8 TO –8
1%
12 TO –12
0
Figure 19. Large Signal Pulse
Response and Settling Time, G = 1
5
0.01%
0.1%
10
15
SETTLING TIME – ms
20
Figure 20. Settling Time Gain = 100
–12 TO 12
1%
0.1%
Figure 21. Large Signal Pulse
Response and Settling Time,
G = 100
0.01%
–8 TO 8
–4 TO 4
OUTPUT
STEP –V
4 TO –4
8 TO –8
1%
12 TO –12
0
Figure 22. Range Signal Pulse
Response and Settling Time,
G = 500
5
0.1%
0.01%
10
15
SETTLING TIME – ms
20
Figure 23. Settling Time Gain = 1000
–6–
Figure 24. Large Signal Pulse
Response and Settling Time,
G = 1000
REV. C
AD624
10kV
1%
INPUT
20V p-p
1kV
10T
10kV
1%
VOUT
+VS
100kV
1%
RG1
G = 100
G = 200
1kV
0.1%
500V
0.1%
AD624
G = 500
200V
0.1%
RG2
–VS
Figure 25. Settling Time Test Circuit
THEORY OF OPERATION
The AD624 is a monolithic instrumentation amplifier based on
a modification of the classic three-op-amp instrumentation
amplifier. Monolithic construction and laser-wafer-trimming
allow the tight matching and tracking of circuit components and
the high level of performance that this circuit architecture is capable of.
A preamp section (Q1–Q4) develops the programmed gain by
the use of feedback concepts. Feedback from the outputs of A1
and A2 forces the collector currents of Q1–Q4 to be constant
thereby impressing the input voltage across RG.
The gain is set by choosing the value of RG from the equation,
40 k
+ 1. The value of RG also sets the transconductGain =
RG
ance of the input preamp stage increasing it asymptotically to
the transconductance of the input transistors as RG is reduced
for larger gains. This has three important advantages. First, this
approach allows the circuit to achieve a very high open loop gain
of 3 × 108 at a programmed gain of 1000 thus reducing gain
related errors to a negligible 3 ppm. Second, the gain bandwidth
product which is determined by C3 or C4 and the input transconductance, reaches 25 MHz. Third, the input voltage noise
reduces to a value determined by the collector current of the
input transistors for an RTI noise of 4 nV/√Hz at G ≥ 500.
The AD524 should be considered in applications that require
protection from severe input overload. If this is not possible,
external protection resistors can be put in series with the inputs
of the AD624 to augment the internal (50 Ω) protection resistors. This will most seriously degrade the noise performance.
For this reason the value of these resistors should be chosen to
be as low as possible and still provide 10 mA of current limiting
under maximum continuous overload conditions. In selecting
the value of these resistors, the internal gain setting resistor and
the 1.2 volt drop need to be considered. For example, to protect the device from a continuous differential overload of 20 V
at a gain of 100, 1.9 kΩ of resistance is required. The internal
gain resistor is 404 Ω; the internal protect resistor is 100 Ω.
There is a 1.2 V drop across D1 or D2 and the base-emitter
junction of either Q1 and Q3 or Q2 and Q4 as shown in Figure
27, 1400 Ω of external resistance would be required (700 Ω in
series with each input). The RTI noise in this case would be
4 KTRext +(4 nV / Hz )2 = 6.2 nV / Hz
+VS
I1
50mA
C3
50V
+VS
200
AD624
500
1mF
RG2
G500
–VS
–VS
1kV
R53
10kV
RG2
Q2,
R56
20kV Q4
R54
10kV
80.2V
VO
R55
10kV
REF
500
I4
50mA
50V
200
+IN
225.3V
100
1mF
–VS
1.62MV 1.82kV
Figure 27. Simplified Circuit of Amplifier; Gain Is Defined
as (R56 + R57)/(RG) + 1. For a Gain of 1, RG Is an Open
Circuit.
Figure 26. Noise Test Circuit
INPUT CONSIDERATIONS
INPUT OFFSET AND OUTPUT OFFSET
Under input overload conditions the user will see RG + 100 Ω
and two diode drops (~1.2 V) between the plus and minus
inputs, in either direction. If safe overload current under all
conditions is assumed to be 10 mA, the maximum overload
voltage is ~ ± 2.5 V. While the AD624 can withstand this continuously, momentary overloads of ± 10 V will not harm the
device. On the other hand the inputs should never exceed the
supply voltage.
REV. C
C4
A3
R57
20kV
4445V
16.2kV
G1, 100, 200
A2
124V
1/2
AD712
9.09kV
A1
RG1
13
50mA
1mF
1/2
AD712
100V
Q1, Q3
–IN
16.2kV
R52
10kV
SENSE
+VS
100
I2
50mA
VB
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may
be adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but there are many smallsignal high-gain applications that don’t have this capability.
Voltage offset and offset drift each have two components; input
and output. Input offset is that component of offset that is
–7–
AD624
directly proportional to gain i.e., input offset as measured at
the␣ output at G = 100 is 100 times greater than at G = 1.
Output␣ offset is independent of gain. At low gains, output offset
drift is␣ dominant, while at high gains input offset drift dominates.␣ Therefore, the output offset voltage drift is normally
specified␣ as drift at G = 1 (where input effects are insignificant),
while␣ input offset voltage drift is given by drift specification at a
high␣ gain (where output offset effects are negligible). All inputrelated␣ numbers are referred to the input (RTI) which is to say
that the␣ effect on the output is “G” times larger. Voltage offset
vs. power␣ supply is also specified at one or more gain settings
and is also␣ RTI.
Table I.
By separating these errors, one can evaluate the total error independent of the gain setting used. In a given gain configuration␣ both errors can be combined to give a total error referred to
the␣ input (R.T.I.) or output (R.T.O.) by the following formula:
Total Error R.T.I. = input error + (output error/gain)
Total Error R.T.O. = (Gain × input error) + output error
As an illustration, a typical AD624 might have a +250 µV output␣ offset and a –50 µV input offset. In a unity gain configuration,␣ the total output offset would be 200 µV or the sum of the
two.␣ At a gain of 100, the output offset would be –4.75 mV
or:␣ +250 µV + 100 (–50 µV) = –4.75 mV.␣
Gain
(Nominal)
Temperature
Coefficient
(Nominal)
Pin 3
to Pin
Connect Pins
1
100
125
137
186.5
200
250
333
375
500
624
688
831
1000
–0 ppm/°C
–1.5 ppm/°C
–5 ppm/°C
–5.5 ppm/°C
–6.5 ppm/°C
–3.5 ppm/°C
–5.5 ppm/°C
–15 ppm/°C
–0.5 ppm/°C
–10 ppm/°C
–5 ppm/°C
–1.5 ppm/°C
+4 ppm/°C
0 ppm/°C
–
13
13
13
13
12
12
12
12
11
11
11
11
11
–
–
11 to 16
11 to 12
11 to 12 to 16
–
11 to 13
11 to 16
13 to 16
–
13 to 16
11 to 12; 13 to 16
16 to 12
16 to 12; 13 to 11
Pins 3 and 16 programs the gain according to the formula
40k
RG =
G −1
(see Figure 29). For best results RG should be a precision resistor with a low temperature coefficient. An external RG affects both
gain accuracy and gain drift due to the mismatch between it and
the internal thin-film resistors R56 and R57. Gain accuracy is
determined by the tolerance of the external RG and the absolute
accuracy of the internal resistors (±20%). Gain drift is determined
by the mismatch of the temperature coefficient of RG and the temperature coefficient of the internal resistors (–15 ppm/°C typ),
and the temperature coefficient of the internal interconnections.
The AD624 provides for both input and output offset adjustment.␣ This optimizes nulling in very high precision applications
and␣ minimizes offset voltage effects in switched gain applications. In␣ such applications the input offset is adjusted first at the
highest␣ programmed gain, then the output offset is adjusted at
G = 1.
GAIN
+VS
The AD624 includes high accuracy pretrimmed internal
gain␣ resistors. These allow for single connection programming of␣ gains of 1, 100, 200 and 500. Additionally, a variety
of gains␣ including a pretrimmed gain of 1000 can be achieved
through␣ series and parallel combinations of the internal resistors. Table I␣ shows the available gains and the appropriate
pin connections␣ and gain temperature coefficients.
–INPUT
RG1
1.5kV
VOUT
AD624
2.105kV
OR
1kV
RG2
REFERENCE
+INPUT
–VS
The gain values achieved via the combination of internal
resistors␣ are extremely useful. The temperature coefficient of the
gain is␣ dependent primarily on the mismatch of the temperature
coefficients of the various internal resistors. Tracking of these
resistors␣ is extremely tight resulting in the low gain TCs shown
in␣ Table I.
G = 40.000 + 1 = 20 620%
2.105
Figure 29. Operating Connections for G = 20
The AD624 may also be configured to provide gain in the output stage. Figure 30 shows an H pad attenuator connected to
the reference and sense lines of the AD624. The values of R1,
R2 and R3 should be selected to be as low as possible to minimize the gain variation and reduction of CMRR. Varying R2
will precisely set the gain without affecting CMRR. CMRR is
determined by the match of R1 and R3.
If the desired value of gain is not attainable using the internal␣ resistors, a single external resistor can be used to achieve
any␣ gain between 1 and 10,000. This resistor connected between
+VS
INPUT
OFFSET
10kV NULL
–INPUT
+VS
RG1
RG1
G = 100
G = 100
G = 200
VOUT
AD624
G = 500
RG2
R2
5kV
VOUT
AD624
G = 200
RL
G = 500
RG2
OUTPUT
SIGNAL
COMMON
+INPUT
R1
6kV
–INPUT
+INPUT
–VS
–VS
Figure 28. Operating Connections for G = 200
G=
R3
6kV
(R2||20kV) + R1 + R3)
(R2||20kV)
(R1 + R2 + R3) || RL
2kV
Figure 30. Gain of 2500
–8–
REV. C
AD624
NOISE
+VS
The AD624 is designed to provide noise performance near the
theoretical noise floor. This is an extremely important design
criteria as the front end noise of an instrumentation amplifier is
the ultimate limitation on the resolution of the data acquisition
system it is being used in. There are two sources of noise in an
instrument amplifier, the input noise, predominantly generated
by the differential input stage, and the output noise, generated
by the output amplifier. Both of these components are present
at the input (and output) of the instrumentation amplifier. At
the input, the input noise will appear unaltered; the output
noise will be attenuated by the closed loop gain (at the output,
the output noise will be unaltered; the input noise will be amplified by the closed loop gain). Those two noise sources must be
root sum squared to determine the total noise level expected at
the input (or output).
AD624
LOAD
c. AC-Coupled
Figure 31. Indirect Ground Returns for Bias Currents
Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
provided, those currents will charge stray capacitances, causing
the output to drift uncontrollably or to saturate. Therefore,
when amplifying “floating” input sources such as transformers
and thermocouples, as well as ac-coupled sources, there must
still be a dc path from each input to ground, (see Figure 31).
The low frequency (0.1 Hz to 10 Hz) voltage noise due to the
output stage is 10 µV p-p, the contribution of the input stage is
0.2 µV p-p. At a gain of 10, the RTI voltage noise would be
2
1 µV p-p,
2
 10 
  + (0.2) . The RTO voltage noise would be
G
10.2 µV p-p,
(
102 + 0.2(G )
)
2
TO
POWER
SUPPLY
GROUND
–VS
COMMON-MODE REJECTION
. These calculations hold for
applications using either internal or external gain resistors.
INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of a dc amplifier. Bias currents are an additional
source of input error and must be considered in a total error
budget. The bias currents when multiplied by the source resistance imbalance appear as an additional offset voltage. (What is
of concern in calculating bias current errors is the change in bias
current with respect to signal voltage and temperature.) Input
offset current is the difference between the two input bias currents. The effect of offset current is an input offset voltage whose
magnitude is the offset current times the source resistance.
+VS
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed by equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance. “Common-Mode
Rejection Ratio” (CMRR) is a ratio expression while “CommonMode Rejection” (CMR) is the logarithm of that ratio. For
example, a CMRR of 10,000 corresponds to a CMR of 80 dB.
In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across
differing track resistances and a differential phase shift due to
varied stray capacitances or cable capacitances. In many applications shielded cables are used to minimize noise. This technique can create common-mode rejection errors unless the
shield is properly driven. Figures 32 and 33 shows active data
guards which are configured to improve ac common-mode
rejection by “bootstrapping” the capacitances of the input
cabling, thus minimizing differential phase shift.
+VS
–INPUT
AD624
G = 200
LOAD
100V
RG2
–VS
VOUT
AD624
AD711
TO
POWER
SUPPLY
GROUND
REFERENCE
+INPUT
–VS
a. Transformer Coupled
Figure 32. Shield Driver, G ≥ 100
+VS
+VS
–INPUT
100V
RG1
AD712
AD624
AD624
LOAD
–VS
100V
RG2
REFERENCE
+INPUT
TO
POWER
SUPPLY
GROUND
–VS
Figure 33. Differential Shield Driver
b. Thermocouple
REV. C
–VS
VOUT
–9–
AD624
“inside the loop” of an instrumentation amplifier to provide the
required current without significantly degrading overall performance. The effects of nonlinearities, offset and gain inaccuracies
of the buffer are reduced by the loop gain of the IA output
amplifier. Offset drift of the buffer is similarly reduced.
GROUNDING
Many data-acquisition components have two or more ground
pins which are not connected together within the device. These
grounds must be tied together at one point, usually at the system power supply ground. Ideally, a single solid ground would
be desirable. However, since current flows through the ground
wires and etch stripes of the circuit cards, and since these paths
have resistance and inductance, hundreds of millivolts can be
generated between the system ground point and the data acquisition components. Separate ground returns should be provided
to minimize the current flow in the path from the most sensitive
points to the system ground point. In this way supply currents
and logic-gate return currents are not summed into the same
return path as analog signals where they would cause measurement errors (see Figure 34).
REFERENCE TERMINAL
The reference terminal may be used to offset the output by up
to ± 10 V. This is useful when the load is “floating” or does not
share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. It must be remembered that the total output swing is ± 10 volts, from ground, to
be shared between signal and reference offset.
+VS
SENSE
VIN+
ANALOG P.S.
+15V C –15V
DIGITAL P.S.
C +5V
AD624
LOAD
REF
0.1 0.1
mF mF
VIN–
0.1 0.1
mF mF
1mF 1mF
1mF
DIG
COM
AD624
ANALOG
GROUND*
–VS
Figure 36. Use of Reference Terminal to Provide Output
Offset
DIGITAL
DATA
OUTPUT
AD583
SAMPLE
AND HOLD
AD574A
VOFFSET
AD711
+
SENSE TERMINAL
When the IA is of the three-amplifier configuration it is necessary that nearly zero impedance be presented to the reference
terminal. Any significant resistance, including those caused by
PC layouts or other connection techniques, which appears
between the reference pin and ground will increase the gain of
the noninverting signal path, thereby upsetting the commonmode rejection of the IA. Inadvertent thermocouple connections
created in the sense and reference lines should also be avoided
as they will directly affect the output offset voltage and output
offset voltage drift.
The sense terminal is the feedback point for the instrument
amplifier’s output amplifier. Normally it is connected to the
instrument amplifier output. If heavy load currents are to be
drawn through long leads, voltage drops due to current flowing
through lead resistance can cause errors. The sense terminal can
be wired to the instrument amplifier at the load thus putting the
IxR drops “inside the loop” and virtually eliminating this error
source.
In the AD624 a reference source resistance will unbalance the
CMR trim by the ratio of 10 kΩ/RREF. For example, if the reference source impedance is 1 Ω, CMR will be reduced to 80 dB
(10 kΩ/1 Ω = 80 dB). An operational amplifier may be used to
provide that low impedance reference point as shown in Figure
36. The input offset voltage characteristics of that amplifier will
add directly to the output offset voltage performance of the
instrumentation amplifier.
OUTPUT
REFERENCE
SIGNAL
GROUND
*IF INDEPENDENT, OTHERWISE RETURN AMPLIFIER REFERENCE
TO MECCA AT ANALOG P.S. COMMON
Figure 34. Basic Grounding Practice
Since the output voltage is developed with respect to the potential on the reference terminal an instrumentation amplifier can
solve many grounding problems.
An instrumentation amplifier can be turned into a voltage-tocurrent converter by taking advantage of the sense and reference
terminals as shown in Figure 37.
V+
(SENSE)
OUTPUT
CURRENT
BOOSTER
VIN+
SENSE
X1
AD624
+INPUT
R1
+VX–
RL
VIN–
(REF)
IL
AD624
V–
AD711
–INPUT
REF
Figure 35. AD624 Instrumentation Amplifier with Output
Current Booster
Typically, IC instrumentation amplifiers are rated for a full
± 10 volt output swing into 2 kΩ. In some applications, however, the need exists to drive more current into heavier loads.
Figure 35 shows how a current booster may be connected
IL =
VIN
VX
40.000
1+
=
R1
R1
RG
A2
LOAD
Figure 37. Voltage-to-Current Converter
–10–
REV. C
AD624
50V
–IN
1
16
OUTPUT
OFFSET
TRIM
50V
+IN
2
3
INPUT
OFFSET
TRIM
4
VB
20kV
R1
10kV
80.2V
15
4445.7V
14
10kV
124V
11
+5V
10kV
7
10
AD624
+VS
1mF
35V
K1 – K3 =
THERMOSEN DM2C
4.5V COIL
D1 – D3 = IN4148
GAIN TABLE
A B
GAIN
0 0
100
0 1
500
1 0
200
1 1
1
D1
OUT
C2
ANALOG
COMMON
K2
K1
9
8
C1
RELAY
SHIELDS
225.3V
6
–VS
G = 500
K3
R2
10kV
12
10kV
G = 200
K2
13
20kV
5
10kV
G = 100
K1
NC
INPUTS A
GAIN
RANGE B
K3
D2
D3
Y0
Y1
74LS138
DECODER
7407N
BUFFER
DRIVER
Y2
10mF
+5V
LOGIC
COMMON
Figure 38. Gain Programmable Amplifier
By establishing a reference at the “low” side of a current setting
resistor, an output current may be defined as a function of input
voltage, gain and the value of that resistor. Since only a small
current is demanded at the input of the buffer amplifier A2, the
forced current IL will largely flow through the load. Offset and
drift specifications of A2 must be added to the output offset and
drift specifications of the IA.
symmetrical bipolar transmission is ideal in this application. The
multiplying DAC’s advantage is that it can handle inputs of
either polarity or zero without affecting the programmed gain.
The circuit shown uses an AD7528 to set the gain (DAC A) and
to perform a fine adjustment (DAC B).
Figure 38 shows the AD624 being used as a software programmable gain amplifier. Gain switching can be accomplished with
mechanical switches such as DIP switches or reed relays. It
should be noted that the “on” resistance of the switch in series
with the internal gain resistor becomes part of the gain equation
and will have an effect on gain accuracy.
A significant advantage in using the internal gain resistors in a
programmable gain configuration is the minimization of thermocouple signals which are often present in multiplexed data
acquisition systems.
If the full performance of the AD624 is to be achieved, the user
must be extremely careful in designing and laying out his circuit
to minimize the remaining thermocouple signals.
The AD624 can also be connected for gain in the output stage.
Figure 39 shows an AD547 used as an active attenuator in the
output amplifier’s feedback loop. The active attenuation presents a very low impedance to the feedback resistors therefore
minimizing the common-mode rejection ratio degradation.
1
(–INPUT)
+IN
16
50V
2
80.2V
3
INPUT
OFFSET
NULL
10kV
14
4
20kV
20kV
VB
13
12
6
10kV
124V
11
10kV
10kV
7
10
AD624
+VS
9
8
VOUT
1mF
35V
10pF
VSS
VDD GND
+VS
–VS
39.2kV
1kV
28.7kV
1kV
316kV
1kV
AD7590
–11–
OUTPUT
OFFSET
NULL
TO –V
10kV
225.3V
5
10kV
–VS
15
4445.7V
AD711
Another method for developing the switching scheme is to use a
DAC. The AD7528 dual DAC which acts essentially as a pair of
switched resistive attenuators having high analog linearity and
REV. C
50V
(+INPUT)
–IN
PROGRAMMABLE GAIN
A1 A2 A3 A4 WR
Figure 39. Programmable Output Gain
AD624
In many applications complex software algorithms for autozero
applications are not available. For these applications Figure 42
provides a hardware solution.
50V
+INPUT
(–INPUT)
G = 100
AD624
225.3V
4445.7V
G = 200
+VS
VB
124V
15 16
10kV
G = 500
80.2V
20kV
RG1
RG2
14
10kV
VOUT
20kV
RG1
10kV
AD624
10kV
9 10
0.1mF LOW
LEAKAGE
13
RG2
VOUT
CH
1kV
50V
–INPUT
(+INPUT)
–VS
12 11
AD542
+VS
1/2
AD712
DAC A
VDD
DB0
DATA
INPUTS
CS
AD7510DIKD
VSS
256:1
DB7
GND
AD7528
A1
WR
A2
A3
A4
200ms
DAC A/DAC B
1/2
AD712
DAC B
ZERO PULSE
Figure 42. Autozero Circuit
Figure 40. Programmable Output Gain Using a DAC
AUTOZERO CIRCUITS
In many applications it is necessary to provide very accurate
data in high gain configurations. At room temperature the offset
effects can be nulled by the use of offset trimpots. Over the
operating temperature range, however, offset nulling becomes a
problem. The circuit of Figure 41 shows a CMOS DAC operating in the bipolar mode and connected to the reference terminal
to provide software controllable offset adjustments.
The microprocessor controlled data acquisition system shown in
Figure 43 includes includes both autozero and autogain capability. By dedicating two of the differential inputs, one to ground
and one to the A/D reference, the proper program calibration
cycles can eliminate both initial accuracy errors and accuracy
errors over temperature. The autozero cycle, in this application,
converts a number that appears to be ground and then writes
that same number (8 bit) to the AD624 which eliminates the
zero error since its output has an inverted scale. The autogain
cycle converts the A/D reference and compares it with full scale.
A multiplicative correction factor is then computed and applied
to subsequent readings.
+VS
–INPUT
RG2
RG1
VREF
G = 100
G = 200
AD583
AD624
VOUT
AD624
AD7507
G = 500
VIN
AD574A
AGND
RG2
RG1
+INPUT
–VS
39kV
–VS
AD589
VREF
R3
20kV
RFB
OUT1
LSB
C1
+VS
AD7524
CS
OUT2
WR
–VREF
20kV
+VS
MSB
DATA
INPUTS
A0 A2
EN A1
1/2
AD712
R4
10kV
R6
5kV
20kV
R5
20kV
AD7524
LATCH
1/2
AD712
10kV
1/2
AD712
1/2
5kV AD712
DECODE
CONTROL
–VS
GND
ADDRESS BUS
Figure 41. Software Controllable Offset
MICROPROCESSOR
Figure 43. Microprocessor Controlled Data Acquisition
System
–12–
REV. C
AD624
WEIGH SCALE
Figure 44 shows an example of how an AD624 can be used to
condition the differential output voltage from a load cell. The
10% reference voltage adjustment range is required to accommodate the 10% transducer sensitivity tolerance. The high
linearity and low noise of the AD624 make it ideal for use in
applications of this type particularly where it is desirable to
measure small changes in weight as opposed to the absolute
value. The addition of an autogain/autotare cycle will enable the
system to remove offsets, gain errors, and drifts making possible
true 14-bit performance.
+15V
+15V
+10V
NOTE 2
10V 610%
R3
10V
100V
AD584
AD707
+5V
R1
30kV
+2.5V
SCALE
R2
20kV ERROR
ADJUST
VBG
2N2219
Figure 45 is an example of an ac bridge system with the AD630
used as a synchronous demodulator. The oscilloscope photograph shows the results of a 0.05% bridge imbalance caused by
the 1 Meg resistor in parallel with one leg of the bridge. The top
trace represents the bridge excitation, the upper middle trace is
the amplified bridge output, the lower-middle trace is the output of the synchronous demodulator and the bottom trace is the
filtered dc system output.
This system can easily resolve a 0.5 ppm change in bridge
impedance. Such a change will produce a 6.3 mV change in the
low-pass filtered dc output, well above the RTO drifts and noise.
The AC-CMRR of the AD624 decreases with the frequency of
the input signal. This is due mainly to the package-pin capacitance associated with the AD624’s internal gain resistors. If
AC-CMRR is not sufficient for a given application, it can be
trimmed by using a variable capacitor connected to the amplifier’s
RG2 pin as shown in Figure 45.
R3
10kV
–INPUT
SENSE
G500
G200
G100
R4
10kV
ZERO
ADJUST
(FINE)
AD624
RG2
R5
3MV
+VS
1kHz
BRIDGE
EXCITATION
OUT
10kV
1kV
+10V FULL
SCALE
OUTPUT
RG1
1kV
1kV
A/D
CONVERTER
RG2
1MV
4–49pF
CERAMIC ac
BALANCE
CAPACITOR
REFERENCE
+INPUT
R7
100k
V
AD624C
G = 1000
1kV
GAIN = 500
TRANSDUCER
SEE NOTE 1
R6
100kV
ZERO ADJUST
(COARSE)
–VS
MODULATION
INPUT
2.5kV
PHASE
SHIFTER
NOTES
1. LOAD CELL TEDEA MODEL 1010 10kG. OUTPUT 2mV/V610%.
2. R1, R2 AND R3 SELECTED FOR AD584. OUTPUT 10V 610%.
BA
2.5kV
B
5kV
Figure 44. AD624 Weigh Scale Application
10kV
AC BRIDGE
10kV
Bridge circuits which use dc excitation are often plagued by
errors caused by thermocouple effects, l/f noise, dc drifts in the
electronics, and line noise pickup. One way to get around these
problems is to excite the bridge with an ac waveform, amplify
the bridge output with an ac amplifier, and synchronously
demodulate the resulting signal. The ac phase and amplitude
information from the bridge is recovered as a dc signal at the
output of the synchronous demodulator. The low frequency
system noise, dc drifts, and demodulator noise all get mixed to
the carrier frequency and can be removed by means of a lowpass filter. Dynamic response of the bridge must be traded off
against the amount of attenuation required to adequately suppress these residual carrier components in the selection of the
filter.
–VS
CARRIER
INPUT
MODULATED
OUTPUT
SIGNAL
VOUT
–V
AD630
COMP
+VS
Figure 45. AC Bridge
0V
BRIDGE EXCITATION
(20V/div) (A)
0V
AMPLIFIED BRIDGE
OUTPUT (5V/div) (B)
0V
DEMODULATED BRIDGE
OUTPUT (5V/div) (C)
0V
2V
FILTER OUTPUT
2V/div) (D)
Figure 46. AC Bridge Waveforms
REV. C
–13–
AD624
+VS
ERROR BUDGET ANALYSIS
To illustrate how instrumentation amplifier specifications are
applied, we will now examine a typical case where an AD624 is
required to amplify the output of an unbalanced transducer.
Figure 47 shows a differential transducer, unbalanced by ≈5 Ω,
supplying a 0 to 20 mV signal to an AD624C. The output of the
IA feeds a 14-bit A to D converter with a 0 to 2 volt input voltage range. The operating temperature range is –25°C to +85°C.
Therefore, the largest change in temperature ∆T within the
operating range is from ambient to +85°C (85°C – 25°C =
60°C.)
+10V
10kV
RG1
350V
350V
G = 100
350V
14-BIT
ADC
0 TO 2V
F.S.
AD624C
350V
In many applications, differential linearity and resolution are of
prime importance. This would be so in cases where the absolute
value of a variable is less important than changes in value. In
these applications, only the irreducible errors (20 ppm =
0.002%) are significant. Furthermore, if a system has an intelligent processor monitoring the A to D output, the addition of an
autogain/autozero cycle will remove all reducible errors and may
eliminate the requirement for initial calibration. This will also
reduce errors to 0.002%.
RG2
–VS
Figure 47. Typical Bridge Application
Table II. Error Budget Analysis of AD624CD in Bridge Application
Error Source
AD624C
Specifications
Gain Error
Gain Instability
Gain Nonlinearity
Input Offset Voltage
Input Offset Voltage Drift
± 0.1%
10 ppm
± 0.001%
± 25 µV, RTI
± 0.25 µV/°C
Output Offset Voltage1
Output Offset Voltage Drift1
± 2.0 mV
± 10 µV/°C
Bias Current–Source
Imbalance Error
Offset Current–Source
Imbalance Error
Offset Current–Source
Resistance Error
Offset Current–Source
Resistance–Drift
Common-Mode Rejection
5 V dc
Noise, RTI
(0.1 Hz–10 Hz)
± 15 nA
± 10 nA
± 10 nA
± 100 pA/°C
115 dB
0.22 µV p-p
Calculation
± 0.1% = 1000 ppm
(10 ppm/°C) (60°C) = 600 ppm
± 0.001% = 10 ppm
± 25 µV/20 mV = ± 1250 ppm
(± 0.25 µV/°C) (60°C)= 15 µV
15 µV/20 mV = 750 ppm
± 2.0 mV/20 mV = 1000 ppm
(± 10 µV/°C) (60°C) = 600 µV
600 µV/20 mV = 300 ppm
(± 15 nA)(5 Ω ) = 0.075 µV
0.075 µV/20mV = 3.75 ppm
(± 10 nA)(5 Ω) = 0.050 µV
0.050 µV/20 mV = 2.5 ppm
(10 nA) (175 Ω) = 1.75 µV
1.75 µV/20 mV = 87.5 ppm
(100 pA/°C) (175 Ω) (60°C) = 1 µV
1 µV/20 mV = 50 ppm
115 dB = 1.8 ppm × 5 V = 9 µV
9 µV/20 mV = 444 ppm
0.22 µV p-p/20 mV = 10 ppm
Total Error
Effect on
Absolute
Accuracy
at TA = +25ⴗC
Effect on
Absolute
Effect
Accuracy
on
at TA = +85ⴗC Resolution
1000 ppm
_
–
1250 ppm
1000 ppm
600 ppm
–
1250 ppm
–
–
10 ppm
–
–
1000 ppm
750 ppm
1000 ppm
–
–
–
300 ppm
–
3.75 ppm
3.75 ppm
–
2.5 ppm
2.5 ppm
–
87.5 ppm
87.5 ppm
–
–
50 ppm
–
450 ppm
450 ppm
–
_
–
10 ppm
3793.75 ppm
5493.75 ppm
20 ppm
NOTE
1
Output offset voltage and output offset voltage drift are given as RTI figures.
For a comprehensive study of instrumentation amplifier design
and applications, refer to the Instrumentation Amplifier Application
Guide, available free from Analog Devices.
–14–
REV. C
AD624
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.005 (0.13) MIN
C805d–0–7/99
Side-Brazed Solder Lid Ceramic DIP
(D-16)
0.080 (2.03) MAX
16
9
0.310 (7.87)
0.220 (5.59)
1
8
PIN 1
0.840 (21.34) MAX
0.100
(2.54)
BSC
0.150
(3.81)
MAX
0.070 (1.78) SEATING
PLANE
0.030 (0.76)
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
PRINTED IN U.S.A.
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
REV. C
–15–