DS34LV87T www.ti.com SNLS116D – JULY 2006 – REVISED APRIL 2013 DS34LV87T Enhanced CMOS Quad Differential Line Driver Check for Samples: DS34LV87T FEATURES DESCRIPTION • The DS34LV87T is a high speed quad differential CMOS driver that meets the requirements of both TIA/EIA-422-B and ITU-T V.11. The CMOS DS34LV87T features low static ICC of 100 μA max which makes it ideal for battery powered and power conscious applications. The TRI-STATE enable, EN, allows the device to be disabled when the device is not in use to minimize power. The dual enable scheme allows for flexibility in turning devices on or off. 1 • • • • • • • • • Meets TIA/EIA-422-B (RS-422) and ITU-T V.11 Recommendation Interoperable With Existing 5V RS-422 Networks Ensured VOD of 2V Min Over Operating Conditions Balanced Output Crossover for Low EMI (Typical Within 40 mV of 50% Voltage Level) Low Power Design (330 μW @ 3.3V Static) ESD ≥ 7 kV on Cable I/O Pins (HBM) Industrial Temperature Range Ensured AC Parameter: – Maximum Driver Skew: 2 ns – Maximum Transition Time: 10 ns Pin Compatible With DS26C31 Available in SOIC Packaging Protection diodes protect all the driver inputs against electrostatic discharge. The driver and enable inputs (DI and EN) are compatible with LVTTL and LVCMOS devices. Differential outputs have the same VOD (≥2V) ensure as the 5V version. The outputs have enhanced ESD Protection providing greater than 7 kV tolerance. TRUTH TABLE (1) Connection Diagram (1) Figure 1. Dual-In-Line Package (Top View) See Package Number D0016A Enables Input EN DI Outputs DO+ DO− Z L X Z H H H L H L L H L = Low logic state X = Irrelevant H = High logic state Z = TRI-STATE 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated DS34LV87T SNLS116D – JULY 2006 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) −0.5V to +7V Supply Voltage (VCC) Enable Input Voltage (EN) −0.5V to VCC + 0.5V Driver Input Voltage (DI) −0.5V to VCC + 0.5V Clamp Diode Current ±20 mA DC Output Current, per pin ±150 mA Driver Output Voltage (Power Off: DO+, DO−) Maximum Package Power Dissipation @+25°C D Package −0.5V to +7V 1226 mW Derate D Package 9.8 mW/°C above +25°C −65°C to +150°C Storage Temperature Range Lead Temperature Range (Soldering, 4 sec.) ESD Ratings (HBM, 1.5k, 100 pF) +260°C ≥ 7 kV Driver Outputs ≥ 2.5 kV Other Pins (1) (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the device should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation. RECOMMENDED OPERATING CONDITIONS Supply Voltage (VCC) Operating Free Air Temperature Range (TA) DS34LV87T Min Typ 3.0 3.3 3.6 V −40 25 +85 °C 500 ns Input Rise and Fall Time 2 Submit Documentation Feedback Max Units Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS34LV87T DS34LV87T www.ti.com SNLS116D – JULY 2006 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (1) (2) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified Symbol Parameter Conditions VOD1 Output Differential Voltage RL= ∞, (No Load) VOD2 Output Differential Voltage RL = 100Ω See Figure 2 ΔVOD2 Change in Magnitude of Output Differential Voltage VOD3 Output Differential Voltage VOC Common Mode Voltage ΔVOC Change in Magnitude of Common Mode Voltage IOZ TRI-STATE Leakage Current VOUT = VCC or GND Drivers Disabled ISC Output Short Circuit Current VOUT = 0V VIN = VCC or GND (4) IOFF Output Leakage Current VCC= 0V, VOUT = 3V VCC = 0V, VOUT = −0.25V Typ Max Units 3.3 4.0 V 2.6 −400 7 400 mV RL = 3900Ω (V.11), See Figure 2 (3) 3.2 3.5 V RL = 100Ω See Figure 2 1.5 2 V 6 400 mV ±0.5 ±20 μA −70 −150 mA 0.03 100 μA −0.08 −100 μA 2.0 VCC V GND 0.8 V 10 μA −400 High Level Input Voltage VIL Low Level Input Voltage IIH High Level Input Current VIN= VCC IIL Low Level Input Current VIN = GND VCL Input Clamp Voltage IIN = −18 mA ICC Power Supply Current No Load, VIN (all) = VCC or GND (2) (3) (4) DO+, DO− Min 2 VIH (1) Pin −40 DI, EN V −10 VCC μA −1.5 V 100 μA Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except differential voltages VOD1, VOD2, VOD3. All typical values are given for VCC= 3.3V and TA = +25°C. This specification limit is for compliance with TIA/EIA-422-B and ITU-T V.11. Only one output shorted at a time. The output (true or complement) is configured High. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS34LV87T 3 DS34LV87T SNLS116D – JULY 2006 – REVISED APRIL 2013 www.ti.com SWITCHING CHARACTERISTICS (1) (2) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified Symbol Parameter Conditions Typ Max Units 6 10.5 16 ns 6 11 16 ns tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD Differential Skew |tPHLD–tPLHD| 0.5 2.0 ns tSK1 Skew, Pin to Pin (same device) 1.0 2.0 ns tSK2 Skew, Part to Part (3) 3.0 5.0 ns tTLH Differential Transition Time Low to High (20% to 80%) 4.2 10 ns tTHL Differential Transition Time High to Low (80% to 20%) 4.7 10 ns tPHZ Disable Time High to Z 12 20 ns tPLZ Disable Time Low to Z 9 20 ns tPZH Enable Time Z to High 22 32 ns tPZL Enable Time Z to Low 22 32 fMAX Maximum Operating Frequency (4) 32 (1) (2) (3) (4) 4 RL = 100Ω, CL = 50 pF See Figure 3 and Figure 4 Min See Figure 5 and Figure 6 ns MHz f = 1 MHz, tr and tf ≤ 6 ns (10% to 90%). See TIA/EIA-422-B specifications for exact test conditions. Devices are at the same VCC and within 5°C within the operating temperature range. All channels switching, output duty cycle criteria is 40%/60% measured at 50%. This parameter is ensured by design and characterization. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS34LV87T DS34LV87T www.ti.com SNLS116D – JULY 2006 – REVISED APRIL 2013 PARAMETER MEASUREMENT INFORMATION Figure 2. Differential Driver DC Test Circuit Figure 3. Differential Driver Propagation Delay and Transition Time Test Circuit Generator waveform for all tests unless otherwise specified: f = 1 MHz, Duty Cycle = 50%, Zo = 50Ω, tr ≤ 10 ns, tf ≤ 10 ns. CL includes probe and fixture capacitance. Figure 4. Differential Driver Propagation Delay and Transition Time Waveforms Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS34LV87T 5 DS34LV87T SNLS116D – JULY 2006 – REVISED APRIL 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Figure 5. Driver Single-Ended Tri-state Test Circuit Figure 6. Driver Single-Ended Tri-state Waveforms 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS34LV87T DS34LV87T www.ti.com SNLS116D – JULY 2006 – REVISED APRIL 2013 TYPICAL APPLICATION INFORMATION General application guidelines and hints for differential drivers and receivers may be found in the following application notes: • Transmission Line Drivers and Receivers for TIA/EIA Standards RS-422 and RS-423(SNLA137) • A Comparison of Differential Termination Techniques(SNLA304) Power Decoupling Recommendations: Bypass caps must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1 μF in parallel with 0.01 μF at the power supply pin. A 10 μF or greater tantalum or electrolytic should be connected at the power entry point on the printed circuit board. RT is optional although highly recommended to reduce reflection Figure 7. Typical Driver Connection Figure 8. Typical Driver Output Waveforms Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS34LV87T 7 DS34LV87T SNLS116D – JULY 2006 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 8 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 7 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS34LV87T PACKAGE OPTION ADDENDUM www.ti.com 12-Oct-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS34LV87TM NRND SOIC D 16 48 TBD Call TI Call TI -40 to 85 DS34LV87 TM DS34LV87TM/NOPB ACTIVE SOIC D 16 48 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS34LV87 TM DS34LV87TMX NRND SOIC D 16 2500 TBD Call TI Call TI -40 to 85 DS34LV87 TM DS34LV87TMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS34LV87 TM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 12-Oct-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS34LV87TMX SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 DS34LV87TMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS34LV87TMX SOIC D 16 2500 367.0 367.0 35.0 DS34LV87TMX/NOPB SOIC D 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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