Intersil HA5352IP Fast acquisition dual sample and hold amplifier Datasheet

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HA5352
®
May 1997
Fast Acquisition
Dual Sample and Hold Amplifier
Features
Description
• Fast Acquisition to 0.01% . . . . . . . . . . . . . . . 70ns (Max)
The HA5352 is a fast acquisition, wide bandwidth Dual Sample and Hold amplifier built with the Intersil HBC-10 BiCMOS
process. This Sample and Hold amplifier offers the combination of features; fast acquisition time (70ns to 0.01%), excellent DC precision and extremely low power dissipation,
making it ideal for use in multi-channel systems that require
low power.
• Low Offset Error . . . . . . . . . . . . . . . . . . . . . . . .±2mV (Max)
• Low Pedestal Error . . . . . . . . . . . . . . . . . . . . .±10mV (Max)
• Low Droop Rate . . . . . . . . . . . . . . . . . . . . . 2µV/µs (Max)
• Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . 40MHz
• Low Power Dissipation per Amp . . . . . . .220mW (Max)
• Total Harmonic Distortion (Hold Mode) . . . . . . . -72dBc
(VIN = 5VP-P at 1MHz)
• Fully Differential Inputs
• On Chip Hold Capacitor
Applications
• Synchronous Sampling
The HA5352 comes in an open loop configuration with fully
differential inputs providing flexibility for user defined feedback. In unity gain the HA5352 is completely self-contained
and requires no external components. The on-chip 15pF
hold capacitors are completely isolated to minimize droop
rate and reduce the sensitivity of pedestal error. The
HA5352 Dual Sample and Hold is available in a 14 lead
PDIP and 16 lead SOIC packages saving board space while
its pinout is designed to simplify layout.
Ordering Information
• Wide Bandwidth A/D Conversion
PART
NUMBER
• Deglitching
• Peak Detection
HA5352IP
• High Speed DC Restore
HA5352IB
TEMPERATURE
RANGE
-40oC
o
to
+85oC
o
-40 C to +85 C
PACKAGE
14 Lead Plastic DIP
16 Lead Plastic SOIC (W)
Pinouts
HA5352 (300 mil SOIC)
TOP VIEW
GND1
1
16 V1+
-IN
2
15 S/H1 CONTROL
+IN
3
14 NC
NC
4
V1-
5
12 V2-
+IN2
6
11 OUT2
-IN2
7
GND2
8
S/H1
13 OUT1
10 S/H2 CONTROL
S/H2
9 V2+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
3-1
HA5352 (PDIP)
TOP VIEW
GND1 1
14 V1+
-IN1 2
13 S/H1 CONTROL
+IN1 3
12 OUT1
V1- 4
11 V2-
+IN2 5
10 OUT2
-IN2 6
9 S/H2 CONTROL
GND2 7
8 V2+
File Number
3394.5
Specifications HA5352
Absolute Maximum Ratings
Operating Conditions
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . +11V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
Voltage between S/H control and ground. . . . . . . . . . . . . . . . . +5.5V
Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±37mA
Junction Temperature (Plastic Packages) . . . . . . . . . . . . . . +150oC
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . +300oC
(SOIC - Lead Tips Only)
Operating Temperature Range
HA5352I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC ≤ TA ≤ +85oC
Storage Temperature Range . . . . . . . . . . . . . -65oC ≤ TA ≤ +150oC
Thermal Package Characteristics
θJA
Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90oC/W
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95oC/W
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
Test Conditions: VSUPPLY = ±5V; CH = Internal = 15pF, Digital Input: VIL = +0.0V (Sample), V IH = 4.0V
(Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise
Specified
HA5352I
PARAMETERS
TEMP
MIN
TYP
MAX
UNITS
Full
-2.5
-
+2.5
V
Input Resistance (Note 2)
+25oC
100
500
-
kΩ
Input Capacitance
+25oC
-
-
5
pF
Input Offset Voltage
+25oC
-2
-
2
mV
Full
-3.0
-
3.0
mV
Offset Voltage Temperature Coefficient
Full
-
15
-
µV/oC
Bias Current
Full
-
2.5
5
µA
Offset Current
Full
-1.5
-
+1.5
µA
Common Mode Range
Full
-2.5
-
+2.5
V
Common Mode Rejection (±2.5VDC, Note 3)
Full
60
80
-
dB
+25oC
95
108
-
dB
Full
85
-
-
dB
+25oC
-
40
-
MHz
Rise Time (200mV Step)
+25oC
-
8.5
-
ns
Overshoot (200mV Step)
+25oC
0
-
30
%
Full
88
105
-
V/µs
+25oC,
+85oC
2.1
-
5.0
V
-40oC
2.4
-
5.0
V
Full
0
-
0.8
V
INPUT CHARACTERISTICS
Input Voltage Range
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (±2.5VOUT)
Unity Gain -3dB Bandwidth
TRANSIENT RESPONSE
Slew Rate (5V Step)
DIGITAL INPUT CHARACTERISTICS
Input Voltage (High)
Input Voltage (Low)
VIH
VIL
3-2
Specifications HA5352
Electrical Specifications
Test Conditions: VSUPPLY = ±5V; CH = Internal = 15pF, Digital Input: VIL = +0.0V (Sample), V IH = 4.0V
(Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise
Specified (Continued)
HA5352I
PARAMETERS
TEMP
MIN
TYP
MAX
UNITS
Input Current (VIL = 0V)
IIL
Full
-1
-
+1
µA
Input Current (VIH = 5V)
IIH
Full
-1
-
+1
µA
Output Voltage (R L = 510Ω)
Full
-3
-
+3
V
Output Current (R L = 100Ω)
+25oC,
+85oC
20
25
-
mA
-40oC
15
-
-
mA
Full
-
13
-
MHz
+25oC
-
0.02
-
Ω
Sample Mode
+25oC
-
325
-
µVrms
Hold Mode
+25oC
-
325
-
µVrms
VIN = 4.5VP-P, FIN = 100kHz
+25oC
-
-80
-76
dBc
VIN = 5VP-P, FIN = 1MHz
+25oC
-
-74
-69
dBc
VIN = 1VP-P, FIN = 10MHz
+25oC
-
-57
-52
dBc
Signal to Noise Ratio
(RMS Signal to RMS Noise)
VIN = 4.5VP-P, FIN = 100kHz
+25oC
-
73
-
dB
Crosstalk
VIN = 5VP-P, FIN = 10MHz
+25oC
-
75
-
dB
VIN = 4.5VP-P, FIN = 100kHz, FS ≅ 100kHz
+25oC
-
-78
-74
dBc
VIN = 5VP-P, FIN = 1MHz, FS ≅ 1MHz
+25oC
-
-72
-67
dBc
VIN = 1VP-P, FIN = 10MHz, FS ≅ 1MHz
+25oC
-
-51
-47
dBc
VIN = 4.5VP-P, FIN =100kHz, FS ≅ 100kHz
+25oC
-
70
-
dB
0V to 2.0V Step to ±1mV
+25oC
-
53
-
ns
0V to 2.0V Step to 0.01% (±200µV)
+25oC
-
64
70
ns
-2.5V to +2.5V Step to 0.01% (±500µV)
+25oC
-
90
100
ns
OUTPUT CHARACTERISTICS
Full Power Bandwidth (5VP-P, A V = +1, -3dB)
Output Resistance - Hold Mode
TOTAL OUTPUT NOISE, D.C. TO 10MHz
SAMPLE MODE DISTORTION CHARACTERISTICS
Total Harmonic Distortion
HOLD MODE DISTORTION CHARACTERISTICS (50% Duty Cycle S/H)
Total Harmonic Distortion
Signal to Noise Ratio
(RMS Signal to RMS Noise)
SAMPLE AND HOLD CHARACTERISTICS
Acquisition Time
3-3
Specifications HA5352
Electrical Specifications
Test Conditions: VSUPPLY = ±5V; CH = Internal = 15pF, Digital Input: VIL = +0.0V (Sample), V IH = 4.0V
(Hold). Non-Inverting Unity Gain Configuration (Output Tied to -Input), CL = 5pF, Unless Otherwise
Specified (Continued)
HA5352I
PARAMETERS
TEMP
MIN
TYP
MAX
UNITS
+25oC
-
0.3
-
µV/µs
Full
-2
-
2
µV/µs
Full
-10
-
+10
mV
Hold Mode Settling Time (to ±1mV)
25oC
-
50
-
ns
Hold Mode Feedthrough (5VP-P, 500kHz, Sine)
25oC
-
72
-
dB
EADT (Effective Aperture Delay Time)
+25oC
-
+1
-
ns
Aperture Time (Note 2)
+25oC
-
10
-
ns
Aperture Uncertainty
+25oC
-
10
20
ps
Aperture Match
+25oC
-
30
-
ps
Supply Current (per Amp)
Full
-
20
22
mA
Total Supply Current
Full
-
40
44
mA
PSRR (+V or -V, 10% Delta)
Full
60
74
-
dB
Droop Rate
Hold Step Error (VIL = 0V, VIH = 4.0V, t R = 5ns)
POWER SUPPLY CHARACTERISTICS
NOTES:
1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied.
2. Derived from Computer Simulation only, not tested.
3. +CMRR is measured from 0V to +2.5V, -CMRR is measured from 0V to -2.5V.
3-4
HA5352
Die Characteristics
DIE DIMENSIONS:
2530 x 3110 x 525 ±25.4µm
100 x 122 x 19 ±1mil
METALLIZATION:
Type: Metal 1: AlSiCu/TiW
Thickness: Metal 1: 6kÅ ± 750Å
Type: Metal 2: AlSiCu
Thickness: Metal 2: 16kÅ ± 1.1kÅ
GLASSIVATION:
Type: Sandwich Passivation
Nitride - 4kÅ, Undoped Si Glass(USG) - 8kÅ, Total - 12kÅ
±2kÅ
SUBSTRATE POTENTIAL: VTRANSISTOR COUNT: 312
Metallization Mask Layout
HA5352
-IN1
GND1 GND1
V1+ V1+ V1+
S/H CONTROL1
+IN1
VOUT1
VOUT1
V1V1-
V2-
V1-
V2V2VOUT2
VOUT2
+IN2
S/H CONTROL2
-IN2
GND2 GND2
V2+
3-5
V2+ V2+
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