Maxim MAX6917EO50 I2c-compatible rtc with microprocessor supervisor, alarm, and nv ram controller Datasheet

19-3702; Rev 1; 10/05
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
The MAX6917 provides all the features of a real-time
clock (RTC) plus a microprocessor (µP) supervisory circuit, NV RAM controller, and backup-battery monitor
function. In addition, 96 x 8 bits of static RAM are available for scratchpad storage. The MAX6917 communicates with a µP through an I2C-bus-compatible serial
interface.
The real-time clock/calendar provides seconds, minutes, hours, day, date, month, and year information.
The end of the month date is automatically adjusted for
months with fewer than 31 days, including corrections
for leap years through 2099. The clock operates in
either 24hr or 12hr format with an AM/PM indicator. A
time/date-programmable alarm function is provided
with an open-drain, active-low alarm output.
The µP supervisory circuit features an open-drain,
active-low reset available in three different reset thresholds. A manual reset input and a watchdog function are
included as well.
The NV RAM controller provides power for external SRAM
from a backup battery plus chip-enable gating. The backup battery also provides data retention of the on-board 96
x 8 bits of RAM. An open-drain, active-low, battery-on signal alerts the system when operating from a battery.
The battery-test circuitry periodically tests the backup
battery for a low-battery condition. An optional external
resistor network selects different battery thresholds. A
freshness seal prevents battery drain until the first VCC
power-up.
The MAX6917 has a crystal-fail-detect circuit and a
data-valid bit. The MAX6917 is available in a 20-pin
QSOP package and is guaranteed to operate over the
extended (-40°C to +85°C) temperature range.
Applications
Features
♦ Real-Time Clock Counts
Seconds, Minutes, Hours, Date,
Month, Day of Week, and Year
with Leap-Year Compensation Through 2099
♦ Fast (400kHz) I2C-Bus-Compatible Interface
♦ 96 x 8 Bits of RAM for Scratchpad Data Storage
♦ Uses Standard 32.768kHz, 6pF Load, Watch
Crystal
♦ Single-Byte or Multiple-Byte (Burst Mode) Data
Transfer for Read or Write of Clock Registers or
RAM
♦ Battery Monitor and Low-Battery Warning Output
Internal Default for Lithium Backup-Battery
Testing
Pins Available for Other Backup-Battery
Testing Configurations
♦ Dual Power-Supply Pins for Primary and Backup
Power
♦ Battery-On Output
♦ NV RAM Controller
Chip-Enable Gating (Control of CE with Reset
and Power Valid)
VOUT for SRAM Power
♦ Microprocessor Supervisor with Watchdog Input
♦ Programmable Time/Date Alarm Output
♦ Data Valid Bit (Loss of All Voltage Alerts User of
Corrupt Data)
♦ Crystal-Fail Detect
Point-of-Sale Equipment
♦ Reference Output Frequencies—1Hz and
32.768kHz
Programmable Logic Controllers
♦ Small, 20-Pin, QSOP Surface-Mount Package
Intelligent Instruments
Fax Machines
Ordering Information
Digital Thermostats
Industrial Control
Pin Configuration and Selector Guide appear at end of data
sheet.
PART
TEMP RANGE
PINPACKAGE
PKG
CODE
MAX6917EO30+
-40°C to +85°C
20 QSOP
E20-2
MAX6917EO33+
-40°C to +85°C
20 QSOP
E20-2
MAX6917EO50+
-40°C to +85°C
20 QSOP
E20-2
+Denotes lead-free package.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX6917
General Description
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
ABSOLUTE MAXIMUM RATINGS
VBATT, VCC to GND ...............................................-0.3V to +6.0V
All Other Pins to GND ................................-0.3V to (VCC + 0.3V)
All Other Pins to GND ............................-0.3V to (VBATT + 0.3V)
Input Currents
VCC ..................................................................................200mA
VBATT .................................................................................20mA
GND ....................................................................................20mA
All Other Pins ....................................................................±20mA
Output Currents
VOUT Continuous ..........................................................200mA
All Other Outputs ............................................................20mA
Continuous Power Dissipation
20-Pin QSOP (derate 9.1mW/°C over TA = +70°C) .....727mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2)
PARAMETER
Operating Voltage Range
(Note 3)
Operating Voltage Range BATT
(Note 4)
Timekeeping Current VBATT
(Note 5)
Active Supply Current VCC
(Note 6)
2
SYMBOL
VCC
VBATT
IBATT
ICCA
CONDITIONS
MIN
TYP
MAX
MAX6917EO30
2.7
3.0
3.3
MAX6917EO33
3.0
3.3
3.6
MAX6917EO50
4.5
5.0
5.5
MAX6917EO30
2.0
5.5
MAX6917EO33
2.0
5.5
MAX6917EO50
2.0
5.5
1Hz, 32kHz
outputs disabled;
XTAL FAIL
disabled
VBATT = 2V, VCC = 0
1
VBATT = 3V, VCC = 0
1.4
VBATT = 3.6V, VCC = 0
1.9
VBATT = 5.5V, VCC = 0
3.8
1Hz, 32kHz
outputs disabled;
XTAL FAIL
enabled
VBATT = 2V, VCC = 0
1.23
VBATT = 3V, VCC = 0
1.61
VBATT = 3.6V, VCC = 0
2.3
VBATT = 5.5V, VCC = 0
4.08
1Hz, 32kHz
enabled, outputs
open; XTAL FAIL
disabled
VBATT = 2V, VCC = 0
2.82
1Hz, 32kHz
enabled, outputs
open; XTAL FAIL
enabled
1Hz, 32kHz
outputs disabled;
XTAL FAIL
disabled
VBATT = 3V, VCC = 0
4.7
VBATT = 3.6V, VCC = 0
6.1
VBATT = 5.5V, VCC = 0
10.6
VCC = 3.3V, VBATT = 0
0.1
VCC = 3.6V, VBATT = 0
0.12
VCC = 5.5V, VBATT = 0
0.2
VCC = 3.3V, VBATT = 0
0.9
VCC = 3.6V, VBATT = 0
0.11
VCC = 5.5V, VBATT = 0
0.18
_______________________________________________________________________________________
UNITS
V
V
µA
mA
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2)
PARAMETER
Standby Current VCC (Note 5)
SYMBOL
ICCS
CONDITIONS
MIN
TYP
MAX
1Hz, 32kHz
enabled, outputs
open; XTAL FAIL
enabled
VCC = 3.3V, VBATT = 0
27
VCC = 3.6V, VBATT = 0
30
VCC = 5.5V, VBATT = 0
81
1Hz, 32kHz
outputs disabled;
XTAL FAIL
disabled
VCC = 3.3V, VBATT = 0
20
VCC = 3.6V, VBATT = 0
25
VCC = 5.5V, VBATT = 0
76
UNITS
µA
VOUT
VOUT in VCC Mode (Note 4)
VOUT in Battery-Backup Mode
(Notes 4, 7)
VOUT
VOUT
VCC = 2.7V, VBATT = 0, IOUT = 35mA
VCC 0.2
VCC = 3.0V, VBATT = 0, IOUT = 35mA
VCC 0.2
VCC = 4.5V, VBATT = 0, IOUT = 70mA
VCC 0.2
VBATT = 2V, VCC = 0, IOUT = 400µA
VBATT 0.02
VBATT = 3V, VCC = 0, IOUT = 800µA
VBATT 0.03
VBATT = 4.5V, VCC = 0, IOUT = 1.5mA
VBATT 0.05
V
V
VBATT-to-VCC Switchover
Threshold
VTRU
Power-up (VCC < VRST) switch from VBATT
to VCC (Note 7)
VBATT
+ 0.1
VCC-to-VBATT Switchover
Threshold
VTRD
Power-down (VCC < VRST) switch from VCC
to VBATT (Note 7)
VBATT
V
V
- 0.1
CE_IN AND CE_OUT (Figures 10, 14, 15, 16)
CE_IN Leakage Current
IIL, IIH
Disabled, VCC < VRST,
VCE_IN = VCC or GND
-1
+1
µA
CE_IN-to-CE_OUT Resistance
VCC = VCC(MIN), VIH = 0.9VCC,
CE_OUT connected to GND;
VIL = 0.1VCC, CE_OUT connected to VCC
46
140
Ω
CE_IN-to-CE_OUT Propagation
Delay
tCED
50Ω source-impedance driver,
CLOAD = 10pF, VCC = VCC(MIN),
VIH = 0.9VCC, VIL = 0.1VCC
(Note 8); measured from 50% point on
CE_IN to the 50% point of CE_OUT
10
20
ns
RESET Active to CE_OUT High
Delay
tRCE
MR high to low
10
50
µs
2
_______________________________________________________________________________________
3
MAX6917
DC ELECTRICAL CHARACTERISTICS (continued)
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CE_OUT Active-Low Delay After
VCC > VRST
tRP
CE_OUT High Voltage
VOH
CONDITIONS
IOH = -100µA, VBATT = 2V, VCC = 0,
RESET = low
MIN
TYP
MAX
UNITS
140
200
280
ms
0.8 x
VBATT
V
MR INPUT (Figure 10)
MR Input Voltage
VIL
0.8
2.0
VIH
MR Pullup Resistance
Internal pullup resistor
MR Minimum Pulse Width
50
kΩ
1
MR Glitch Immunity
tGW
MR to RESET Delay
tRD
VCC = VCC(MIN), VBATT = 0
V
µs
35
ns
450
600
ns
s
WDI INPUT (Figure 12)
VCC > VRST from rising edge of RESET
1.00
1.6
2.25
tWDL
Long watchdog timeout period
1.00
1.6
2.25
s
tWDS
Short watchdog timeout period
140
200
280
ms
WDI Initial Timeout Period
Watchdog Timeout Period
Minimum WDI Input Pulse Width
WDI Input Threshold
tWDI
ns
0.8
2.0
VIH
WDI Input-Leakage Current
VCC Standby Current with WDI
Max Frequency
100
VIL
VWDI = VCC or GND
ICCSW
-100
Watchdog frequency = 1MHz,
VCC = VCC(MAX), 1Hz, 32kHz outputs
disabled (Note 5)
V
+100
nA
450
µA
BATTERY TEST AND TRIP (Figures 17, 18, and 19)
VBATT Trip Point
VBTP
Internal mode
2.45
2.6
2.70
V
TRIP Input Threshold
VTRIP
VCC = VCC(MAX), VBATT = 2V,
external mode
1.14
1.24
1.31
V
TRIP Input Comparator
Hysteresis
VTRIP_HYST
10
TRIP Input Current
ITRIP_LKG
External mode
Battery Test Load
RLOAD_INT
Internal
TEST Output-High Voltage
VTEST_HIGH ITEST = -5mA
TEST Output-Low Voltage
VTEST_LOW
-100
0.50
0.91
mV
+100
nA
1.30
MΩ
VOUT 0.3V
V
ITEST = 5mA
0.3
VBATT = 2V, VCC = 0, IOL = 5mA
0.5
VCC = 2.7V, VBATT = 0, IOL = 10mA
0.5
VCC = 4.5V, VBATT = 0, IOL = 20mA
0.5
V
BATT_LO, ALM OUTPUT
Output Low Voltage
Off-Leakage
4
VOL
ILKG
-100
_______________________________________________________________________________________
+100
V
nA
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BATT_ON OUTPUT
Output Low Voltage
VOL
Off-Leakage
VBATT = 2V, VCC = 0, IOL = 5mA
0.5
VBATT = 2.7V, VCC = 0, IOL = 10mA
0.5
VBATT = 4.5V, VCC = 0, IOL = 20mA
0.5
ILKG
-100
+100
V
nA
RESET
RESET Threshold Voltage
VRST Hysteresis
VRST
MAX6917EO30
2.5
2.63
2.7
MAX6917EO33
2.8
2.93
3.0
MAX6917EO50
4.1
4.38
4.5
VHYST
VCC Falling-Reset Delay
tRPD
30
VCC falling from VRST(MAX) MAX6917EO30
to VRST(MIN), measured
MAX6917EO33
from the beginning of VCC
MAX6917EO50
falling to RESET low
Main Reset Active-Timeout Period
tRP
140
RESET Output Voltage
VOL
Off-Leakage
ILKG
-100
Input High Voltage
VIH
0.7 x
VCC
Input Low Voltage
VIL
V
mV
27
75
37
90
50
120
200
280
ms
0.2
V
+100
nA
RESET asserted, IOL = 1.6mA, VBATT = 2V,
VCC = 0
µs
I2C DIGITAL INPUTS SCL, SDA
Input Hysteresis
0.3 x
VCC
0.05 x
VCC
VHYS
Input Leakage Current
VIN = 0 to VCC
Input Capacitance
SDA Output Low Voltage
VOL
V
-100
V
V
+100
nA
(Note 8)
10
pF
IOL = 4mA, VCC = VCC(MIN)
0.4
V
VCC = 0, VBATT = 2V,
IOL = 100µA
0.2
VCC = 2.7V, VBATT = 0,
IOL = 1mA
0.4
VCC = 4.5V, VBATT = 0,
IOL = 2mA
0.5
FREQUENCY OUTPUTS (32kHz and 1Hz)
32kHz and 1Hz
OUT Low Voltage
VOL
V
_______________________________________________________________________________________
5
MAX6917
DC ELECTRICAL CHARACTERISTICS (continued)
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
32kHz and 1Hz
OUT High Voltage
VOH
CONDITIONS
MIN
VCC = 0, VBATT = 2V,
IOH = -100µA
VOUT 0.1V
VCC = 2.7V, VBATT = 0,
IOH = -1mA
VOUT 0.3V
VCC = 4.5V, VBATT = 0,
IOH = -2mA
VOUT 0.4V
TYP
MAX
UNITS
V
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
800
400,000
Hz
tTIMEOUT
1
2
s
tBUF
1.3
µs
0.6
µs
0.6
µs
FAST I2C-BUS TIMING (Figure 2 (Note 9))
SCL Clock Frequency
Bus Timeout
fSCL
Bus Free Time Between STOP
and START Conditions
Hold Time After (Repeated)
START Conditions
tHD:STA
Repeated START Condition
Setup Time
tHD:STA
(Note 10)
After this period, the first clock is generated
STOP Condition Setup Time
tSU:STO
Data Hold Time
tHD:DAT
0.6
Data Setup Time
tSU:DAT
100
ns
SCL Low Period
tLOW
1.3
µs
SCL High Period
tHIGH
0.6
µs
(Notes 11, 14)
µs
0
0.9
µs
SCL/SDA Rise Time (Receiving)
tR
(Note 12)
20 +
0.1 × Cb
300
ns
SCL/SDA Fall Time (Receiving)
tF
(Notes 12, 13)
20 +
0.1 × Cb
300
ns
SCL/SDA Fall Time (Transmitting)
tF
(Notes 12, 13)
20 +
0.1 × Cb
250
ns
Pulse Width of Spike Suppressed
tSP
50
ns
Capacitive Load for Each Bus
Line
Cb
400
pF
BATTERY-TEST TIMING (Figure 18)
Battery Test to BATT_LO Active
0
tBL
(Note 8)
Battery-Test Cycle—Normal
tBTCN
(Note 8)
Battery-Test Pulse Width
tBTPW
(Note 8)
1
24
s
hr
1
s
Note 1: VRST is the reset threshold for VCC. See the Selector Guide section.
Note 2: All parameters are 100% tested at T A = +85°C. Limits overtemperature are guaranteed by design and are not
production tested.
6
_______________________________________________________________________________________
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
I2C serial interface is operational for VCC > VRST.
See the Detailed Description section (VOUT function).
IBATT is specified with SDA = SCL = VCC, CE_IN = WDI = GND, VOUT , CE_OUT, and MR floating. ICCS is specified with SDA =
SCL = VCC, CE_IN = WDI = GND, VOUT, CE_OUT, and MR floating.
I2C serial interface operating at 400kHz, SDA pulled high, and WDI = VCC or GND, VOUT and CE_OUT floating.
For OUT switchover to BATT, VCC must fall below VRST and VBATT. For OUT switchover to VCC, VCC must be above VRST or
above VBATT.
Guaranteed by design. Not subject to production testing.
All values are referred to VIH (MIN) and VIL(MAX) levels.
Minimum SCL clock frequency is limited by the MAX6917 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for 1s to 2s. When using the burst read or write command, all 96 bytes of RAM must be read/written
within the timeout period. See the Timeout Feature section.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V IH(MIN) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Cb is the total capacitance of one bus line in pF.
The maximum tF for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tF is
specified at 250ns. This allows series-protection resistors to be connected between the SDA/SCL pins and the SDA/SCL bus
lines without exceeding the maximum specified tF.
The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Typical Operating Characteristics
(VCC = 3V, VBATT = 3V, TA = +25°C, unless otherwise noted.)
VCC-TO-OUT VOLTAGE vs. TEMPERATURE
VCC = 3V
VBATT = 0V
IOUT = 35mA
30
25
VCC = 3.3V
VBATT = 0V
IOUT = 35mA
20
15
MAX6917 toc02
VCC-TO-OUT VOLTAGE (mV)
35
BATT-TO-OUT VOLTAGE vs. TEMPERATURE
10
9
BATT-TO-OUT VOLTAGE (mV)
MAX6917 toc01
40
8
VCC = 0V
VBATT = 3V
IOUT = 800µA
7
6
5
4
3
VCC = 0V
VBATT = 2V
IOUT = 400µA
2
1
10
0
15
10
35
60
85
-40
10
35
60
TEMPERATURE (°C)
TIMEKEEPING CURRENT
vs. TEMPERATURE
TIMEKEEPING CURRENT
vs. TEMPERATURE
1.6
MAX6917 toc03a
1.6
VBATT = 3V
1.4
VBATT = 3V
1.4
85
1.2
IBATT (µA)
1.2
IBATT (µA)
15
TEMPERATURE (°C)
MAX6917 toc03b
-40
1.0
0.8
1.0
0.8
SCL = SDA = VCC = 0V
1Hz, 32kHz OUTPUTS DISABLED
XTAL FAIL DISABLED
0.6
SCL = SDA = VCC = 0V
1Hz, 32kHz OUTPUTS DISABLED
XTAL FAIL ENABLED
0.6
0.4
0.4
-40
15
10
35
TEMPERATURE (°C)
60
85
-40
15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX6917
AC ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(VCC = 3V, VBATT = 3V, TA = +25°C, unless otherwise noted.)
RESET TIMEOUT PERIOD
vs. TEMPERATURE
2.8
2.6
SCL = SDA = VCC = 0V
1Hz, 32kHz OUTPUTS ENABLED
XTAL FAIL DISABLED
210
205
200
195
180
85
1
-40
15
10
TEMPERATURE (°C)
40
RESET THRESHOLD (V)
RESET COMPARATOR DELAY (µs)
MAX6917 toc06
VCC FALLING AT 10V/ms
35
30
25
20
15
10
5
15
10
35
60
2.675
2.670
2.665
2.660
2.645
2.640
RESET GOES LOW BELOW
THIS THRESHOLD
2.635
2.630
2.625
2.620
2.615
85
RESET ASSERTS ABOVE THIS LINE
60
50
40
30
20
210
205
200
195
190
180
15
10
35
60
85
-40
8
RISING EDGE OF CE_IN TO
RISING EDGE OF CE_OUT
7
VCC = 3V
VCC = 3.3V
4
3
2
10
35
60
85
CHIP-ENABLED PROPAGATION DELAY
vs. CE_OUT LOAD CAPACITANCE
6
5
15
TEMPERATURE (°C)
VCC = 5V
1
0
100 150 200 250 300 350 400 450 500
8
WD TIME BIT SET TO 1
215
CHIP-ENABLED PROPAGATION DELAY
vs. CE_OUT LOAD CAPACITANCE
70
1000
185
-40
CHIP-ENABLED PROPAGATION DELAY (ns)
90
100
220
TEMPERATURE (°C)
MAX6917 toc09
100
10
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
2.655
2.650
MAXIMUM TRANSIENT DURATION
vs. RESET COMPARATOR OVERDRIVE
OVERDRIVE (mV)
1
VCC FALLING (V/ms)
RESET GOES HIGH ABOVE
THIS THRESHOLD
TEMPERATURE (°C)
80
0.1
85
RESET THRESHOLD vs. TEMPERATURE
(MAX6917EO30)
50
-40
60
TEMPERATURE (°C)
RESET COMPARATOR DELAY
vs. TEMPERATURE
45
35
MAX6917 toc08
60
WATCHDOG TIMEOUT PERIOD (ms)
35
8
CHIP-ENABLED PROPAGATION DELAY (ns)
10
MAX6917 toc07
15
10
190
185
2.2
-40
100
FALLING EDGE OF CE_IN TO
FALLING EDGE OF CE_OUT
7
6
MAX6917 toc10b
2.4
215
MAX6917 toc10a
IBATT (µA)
3.0
1000
RESET DELAY (µs)
3.2
220
MAX6917 toc04
VBATT = 3V
RESET TIMEOUT PERIOD (ms)
MAX6917 toc03c
3.4
RESET COMPARATOR DELAY
vs. VCC FALLING
MAX6917 toc05
TIMEKEEPING CURRENT
vs. TEMPERATURE
MAXIMUM TRANSIENT DURATION (µs)
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
VCC = 3V
5
VCC = 3.3V
4
3
VCC = 5V
2
1
0
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
_______________________________________________________________________________________
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
0.070
0.035
0.030
0.025
2.25
0.060
0.055
0.050
1.50
0.040
1.25
4.7
5.1
0.50
2.7
5.5
3.1
SUPPLY VOLTAGE (V)
MAX6917 toc12b
SCL = SDA = VCC = 0V
1Hz, 32kHz OUTPUTS DISABLED
XTAL FAIL ENABLED
2.25
IBATT (µA)
2.00
1.75
TA = +85°C
1.50
1.25
1.00
TA = -40°C
TA = +25°C
0.75
0.50
2.5
3.0
3.5
4.0
4.5
5.0
5.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
4.7
5.1
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VBATT (V)
VCC TO VOUT vs. OUTPUT CURRENT
(NORMAL MODE)
SCL = SDA = VCC = 0V
1Hz, 32kHz OUTPUTS ENABLED
XTAL FAIL DISABLED
TA = +85°C
0.08
0.07
VCC = +2.7V
0.06
VCC = +3.3V
0.05
0.04
VCC = +5V
0.03
0.02
TA = -40°C
0.01
TA = +25°C
0
2.0
2.5
3.0
3.5
VBATT (V)
4.0
4.5
5.0
0
5.5
10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
VBATT (V)
VBATT-TO-VOUT vs. OUTPUT CURRENT
(BATTERY BACKUP MODE)
0.025
VBATT-TO-VOUT DROP (V)
2.0
4.3
TIMEKEEPING CURRENT
vs. SUPPLY VOLTAGE
3.00
2.50
3.9
SUPPLY VOLTAGE (V)
TIMEKEEPING CURRENT
vs. SUPPLY VOLTAGE
2.75
3.5
VCC TO VOUT DROP (V)
4.3
MAX6917 toc12c
3.9
TA = +25°C
0.020
MAX6917 toc14
3.5
TA = -40°C
0.75
0.025
3.1
TA = +85°C
1.00
TA = -40°C, +25°C, +85°C
0.030
2.7
1.75
0.045
0.035
TA = -40°C, +25°C, +85°C
2.00
MAX6917 toc13
0.040
IBATT (µA)
2.50
IBATT (µA)
0.065
0.060
0.055
0.050
0.045
SCL = SDA = VCC = 0V
1Hz, 32kHz OUTPUTS DISABLED
XTAL FAIL DISABLED
2.75
0.065
ICCA (mA)
ICCA (mA)
0.075
0.070
SCL = 400kHz, SDA = VCC
1Hz, 32kHz OUTPUTS DISABLED
XTAL FAIL DISABLED
0.075
3.00
MAX6917 toc11b
SCL = 400kHz, SDA = VCC
1Hz, 32kHz OUTPUTS ENABLED
XTAL FAIL ENABLED
TIMEKEEPING CURRENT
vs. SUPPLY VOLTAGE
0.080
MAX6917 toc11a
0.085
0.080
ACTIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX6917 toc12a
ACTIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VBATT = +2V
0.015
VBATT = +3.3V
0.010
VBATT = +5V
0.005
0
0
0.4
0.8
1.2
1.6
2.0
2.4
OUTPUT CURRENT (mA)
_______________________________________________________________________________________
9
MAX6917
Typical Operating Characteristics (continued)
(VCC = 3V, VBATT = 3V, TA = +25°C, unless otherwise noted.)
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Pin Description
PIN
FUNCTION
1
VOUT
Supply Output for External SRAM or Other ICs Requiring Use of Backup-Battery Power. When VCC rises
above the reset threshold or above VBATT, VOUT is connected to VCC. When VCC falls below VRESET and
VBATT, VBATT is connected to VOUT. Connect a 0.1µF low-leakage bypass capacitor from VOUT to GND.
Leave open if not used.
2
TEST
External Battery Test. Active high for 1s during each battery test. Intended to drive an external MOSFET
or bipolar transistor for an external battery-test configuration. External test must be selected in the control
register to use TEST; otherwise, it remains low. Leave open if not used.
3
TRIP
External Trip Set. If a different battery-low threshold is desired other than the internal POR default of
VBTP, then connect RSET+ between VBATT and TRIP and RSET- between TRIP and the drain or collector of
an external transistor whose base or gate is connected to TEST; Figure 17 (see the Battery Test section).
External test must be selected in the control register to use TRIP. Leave open if not used.
4
BATT_ON
5
CE_IN
Open-Drain Battery-On Indicator. BATT_ON is active low when the MAX6917 is powered from VBATT.
Chip-Enable Input. The input to the chip-enable gating circuitry. Connect CE_IN to GND if unused.
MR
Manual-Reset Input. A logic low on MR asserts RESET. RESET remains asserted as long as MR is low
and for tRP after MR returns high. The active-low MR input has an internal pullup resistor. MR can be
driven from a TTL or CMOS-logic line or shorted to ground with a switch. Internal debouncing circuitry
ensures noise immunity. Leave MR open if unused.
7
WDI
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the
internal watchdog timer runs out and RESET is asserted. The internal watchdog timer clears while RESET
is asserted or when WDI sees a rising or falling edge. The watchdog function can be disabled from the
control register. The timeout period is configurable in the control register for 200ms or 1.6s.
8
GND
9
X1
32.768kHz Crystal-Oscillator Input
10
X2
32.768kHz Crystal-Oscillator Output
6
10
NAME
Ground
______________________________________________________________________________________
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
PIN
NAME
11
32KHZ
12
1HZ
1Hz Output. Buffered push-pull output that is enabled from the FOUT configuration register.
13
SDA
Open-Drain Data Input/Output. I2C bus serial data input/output connection.
14
SCL
Serial Clock Input. I2C bus clock for input/output data transfers.
15
ALM
Open-Drain, Active-Low Alarm Output. ALM goes low when RTC time matches alarm thresholds set in
the alarm threshold registers. ALM stays low until cleared by reading or writing to the alarm configuration
register or to any of the alarm threshold registers.
16
CE_OUT
Chip-Enable Output. CE_OUT goes low only when CE_IN is low and RESET is not asserted. If CE_IN is
low when RESET is asserted, CE_OUT remains low for tRCE or until CE_IN goes high, whichever occurs
first. CE_OUT is pulled to VOUT.
17
BATT_LO
Open-Drain, Battery-Low Indicator. BATT_LO is active low when the VBATT input is tested below VBTP if
the internal trip is selected in the control register (POR default). If external trip is selected in the control
register, then BATT_LO is active low when TRIP is less than VTRIP.
18
RESET
19
VCC
20
VBATT
FUNCTION
32.768kHz Output. Buffered push-pull output that is enabled from the FOUT configuration register.
Open-Drain, Active-Low Reset Output. RESET pulses low for tRP when triggered, and stays low
whenever VCC is below the reset threshold or when MR is logic low. RESET remains low for tRP after
either VCC rises above the reset threshold or MR goes from low to high.
Main Supply Input. Connect a 0.1µF bypass capacitor from VCC to GND.
Backup-Battery Input. When VCC falls below the reset threshold and VBATT, VOUT switches from VCC to
VBATT. When VCC rises above VBATT or the reset threshold, VOUT reconnects to VCC. VBATT may exceed
VCC. Connect VBATT to GND if no backup-battery supply is used. Connect a 0.1µF low-leakage bypass
capacitor from VBATT to GND.
Detailed Description
Functional Description
The MAX6917 contains eight 8-bit timekeeping registers,
seven 8-bit alarm threshold registers, one status register,
one control register, one alarm-configuration register, and
96 x 8 bits of SRAM. In addition to single-byte reads and
writes to registers and RAM, there is a burst timekeeping
register read/write command, a burst RAM read/write
command, and a battery-test command that allows software-commanded testing of the backup battery at any
time. An I2C-bus-compatible interface allows serial communication with a µP. When VCC is less than the reset
threshold, the serial interface is disabled to prevent erroneous data from being written to the MAX6917. A µP
supervisory section and an NVRAM controller are provided for ease of implementation with µP-based systems. A
crystal fail-detect circuit and a data-valid bit can be used
to guarantee RAM data integrity and valid timekeeping
data. Two reference frequencies outputs, 32.768kHz and
1Hz, are provided for external device clocking. Time and
calendar data are stored in a binary-coded decimal
(BCD) format. Figure 1 shows the functional diagram of
the MAX6917.
Real-Time Clock
The RTC provides seconds, minutes, hours, day, date,
month, and year information. The end of the months is
automatically adjusted for months with fewer than 31
days, including corrections for leap years through 2099.
Crystal Oscillator
The MAX6917 uses an external, standard 6pF load
watch crystal. No other external components are
required for this timekeeping oscillator. Power-up oscillator start time is dependent mainly upon applied VCC
and ambient temperature. The MAX6917, because of
its low timekeeping current, exhibits a typical startup
time of 1s to 2s.
I2C-Compatible Interface
The I2C bus allows bidirectional, 2-wire communication
between different ICs. The two lines are serial data line
(SDA) and serial clock line (SCL). Both lines must be
connected to a positive supply through individual
pullup resistors (see the Typical Application Circuit).
Data transfer can only be initiated when the bus is not
busy (both SDA and SCL are high). Figure 2 shows a
timing diagram for I2C communication.
______________________________________________________________________________________
11
MAX6917
Pin Description (continued)
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
WATCHDOG
TIMER
WDI
RESET
MAX6917
DEBOUNCE
CIRCUIT
MR
CRYSTALFAIL
DETECT
X1
X2
RESET
LOGIC
XTAL FAIL
DIVIDERS
OSCILLATOR
32.768kHz
CE
CONTROL
CE_IN
32KHZ
CLOCK
BURST
SECONDS
1HZ
MINUTES
TEST
HOURS
TRIP
GND
VBATT
VOUT
VCC
BATT_LO
DATE
POWER
CONTROL
AND
MONITOR
MONTH
CONTROL
LOGIC
BATT_ON
DAY
YEAR
CONTROL
CENTURY
SCL
INPUTSHIFT
REGISTERS
SDA
ALARM
CONFIG
ADDRESS
REGISTER
BATT
TEST
STATUS
96 x 8
RAM
ALM
ALARM
CONTROL
LOGIC
DATA
VALID
LOGIC
CONFIG
ALARM
THRESHOLDS
FOUT
CONFIG
RAM
BURST
Figure 1. Functional Diagram
12
______________________________________________________________________________________
CE_OUT
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6917
SDA
tBUFF
tF
tR
tLOW
SCL
tHD:STA
tSP
tR
tF
tHD:DAT
tHD:STA
tSU:DAT
tSU:STA
tHIGH
S
tSU:STO
Sr
P
S
S = START CONDITION
P = STOP CONDITION
Sr = REPEATED START CONDITION
Figure 2. I2C Communication Timing Diagram
To maximize battery life and prevent erroneous data
from being entered into the MAX6917, the serial bus
interface is disabled when VCC is below VRST. If the
SDA or SCL serial interface lines are held low for longer
than 1s to 2s, the serial bus interface resets and awaits
for a new START condition (see the START and STOP
Conditions section).
I2C System Configuration
2
I C-compatible bus that generates a
A device on the
message is called a transmitter and a device that
receives the message is called a receiver. The device
that controls the message is the master and the
devices that are controlled by the master are called
slaves (Figure 3). The word message refers to data in
the form of three 8-bit bytes for a single read or write.
The first byte is the slave ID byte, the second byte is
the address/command byte, and the third is the data.
START and STOP Conditions
Data transfer can only be initiated when the bus is not
busy (both SDA and SCL are high). A high-to-low transition of SDA while SCL is high defines a START (S)
condition; low-to-high transition of SDA while SCL is
high defines a STOP (P) condition (Figures 2, 4). Any
time a START condition occurs, the slave ID must follow
immediately, regardless of completion of a previous
data transfer.
Bit Transfer
After the START condition occurs, 1 bit of data is transferred for each clock pulse. The data on SDA must
remain stable during the high portion of the clock pulse
as changes in data during this time are interpreted as a
control signal (Figure 5).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data
(Figure 6). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is stable low during the high portion of the clock pulse. A
master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this
case, the transmitter must leave the SDA high to enable
the master to generate a STOP condition. If a STOP
condition is received before the current byte of data
transfer is completed in burst mode, the last incomplete
byte is ignored if it is a burst transaction to RAM or the
whole burst transaction is ignored if it is a burst transaction to the timekeeping registers. There is no limit to
the number of bytes that can be transmitted between a
START and a STOP condition.
Slave Address
Before any data is transmitted on the I2C-bus-compatible serial interface, the device that is expected to
respond must be addressed first. The first byte sent
after the START (S) condition is the address byte or 7bit slave ID. The MAX6917 acts as a slave transmitter/receiver. Therefore, SCL is only an input clock
signal and SDA is a bidirectional data line. The slave
address for the MAX6917 is shown in Figure 7.
______________________________________________________________________________________
13
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Address/Command Byte
The second byte of data sent after the START condition
is the address/command byte (Figure 8). Each data
transfer is initiated by an address/command byte. Bits
7–1 specify the designated register or RAM location to
be read or written to, and the LSB (bit 0) specifies a
write operation if logic zero or a read operation if logic
one. The command byte is always input starting with
the MSB (bit 7).
Reading from the Timekeeping Registers
The timekeeping registers (seconds, minutes, hours,
date, month, day, and year) and the control register
can be read either with a single read or a burst read
(Figure 9). Since the RTC runs continuously and a read
takes a finite amount of time, there is the possibility that
the clock counters could change during a read operation, thereby reporting inaccurate timekeeping data. In
the MAX6917, each clock counter’s data is buffered by
a latch. Clock counter data is latched by the I2C bus
read command (on the falling edge of SCL when the
slave acknowledge bit is sent, after the address/command byte has been sent by the master to read a timekeeping register). Collision-detection circuitry ensures
that this does not happen coincident with a seconds
counter update to ensure accurate time data is being
read. This avoids time-data changes during a read
operation. The clock counters continue to count and
keep accurate time during the read operation.
If single reads are used to read each of the timekeeping registers individually, then it is necessary to do
some error checking on the receiving end. An error can
occur when the seconds counter increments before all
the other registers are read out. For example, suppose
a carry of 13:59:59 to 14:00:00 occurs during singleread operations of the timekeeping registers. Then the
net data could become 14:59:59, which is erroneous
real-time data. To prevent this with single-read operations, read the seconds register first (initial seconds)
and store this value for future comparison. When the
remaining timekeeping registers have been read out,
read the seconds register again (final seconds). If the
initial seconds value is 59, check that the final-seconds
value is still 59; if not, repeat the entire single-read
process for the timekeeping registers. A comparison of
the initial-seconds value with the final-seconds value
can indicate if there was a bus-delay problem in reading the timekeeping data (difference should always be
1s or less). Using a 100kHz bus speed, and sequential
single reads, it would take under 2.5ms to read all
seven of the timekeeping registers plus a second read
of the seconds register.
The most accurate way to read the timekeeping registers is to perform a burst read. With burst reads, the
main timekeeping registers (seconds, minutes, hours,
date, month, day, year) and the control register are
read sequentially, in the order listed with the seconds
register first. They must be all read out as a group of
SDA
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
Figure 3. I2C System Configuration
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE OF
DATA
ALLOWED
Figure 5. Bit Transfer
START
CONDITION
SDA
SCL
SCL
S
P
START
CONDITION
STOP
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGE
1
2
SDA
BY TRANSMITTER
SDA
BY RECEIVER
S
Figure 4. START and STOP Conditions
14
Figure 6. Acknowledge
______________________________________________________________________________________
8
9
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
1
0
1
0
0
0
MSB
R/W
MAX6917
1
SDA
ACK
LSB
SCL
Figure 7. MAX6917 Slave Address
BIT 7
A7
eight registers, with 8 bytes each, for proper execution
of the burst-read function. All seven timekeeping registers are latched upon the receipt of the burst-read command. The worst-case error that can occur between the
actual time and the read time is 1s.
BIT 0
A6
A5
A4
A3
A2
A1
R/W
Writing to the Timekeeping Registers
The time and date can be set by writing to the timekeeping registers (seconds, minutes, hours, date,
month, day, year, and century). To avoid changing the
Figure 8. Address/Command Byte
SINGLE WRITE
S
1 1 0 1 0 0 0 0 AS
R/W
START CONDITION
SINGLE READ
S
ACKNOWLEDGE
FROM SLAVE
1 1 0 1 0 0 0 0 AS
R/W
START CONDITION
BURST WRITE
S
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
1 1 0 1 0 0 0 0 AS
ACKNOWLEDGE
FROM SLAVE
ADDR
ACKNOWLEDGE
FROM SLAVE
0 AS
8-BIT DATA
ACKNOWLEDGE
FROM SLAVE
ADDR
AS
P
ACKNOWLEDGE
FROM SLAVE
1 AS
Sr
NO ACKNOWLEDGE
FROM MASTER
1 1 0 1 0 0 0 1 AS
8-BIT DATA
AM
P
R/W
REPEATED START CONDITION
ACKNOWLEDGE
FROM SLAVE
ADDR
ACKNOWLEDGE
FROM SLAVE
0 AS
FIRST 8-BIT DATA
STOP CONDITION
ACKNOWLEDGE
FROM SLAVE
AS
LAST 8-BIT DATA
AS
P
R/W
STOP CONDITION
START CONDITION
BURST READ
S
ACKNOWLEDGE
FROM SLAVE
1 1 0 1 0 0 0 0 AS
R/W
START CONDITION
ADDR = 7-BIT RAM OR REGISTER ADDRESS
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
AS = ACKNOWLEDGE FROM SLAVE
AM = ACKNOWLEDGE FROM MASTER
AM = NOT ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE
FROM SLAVE
ADDR
ACKNOWLEDGE
FROM SLAVE
1 AS
Sr
1 1 0 1 0 0 0 1 AS
R/W
REPEATED START CONDITION
ACKNOWLEDGE
FROM MASTER
FIRST 8-BIT DATA
AM
NO ACKNOWLEDGE
FROM MASTER
LAST 8-BIT DATA
AM
P
STOP CONDITION
Figure 9. Read and Write Operations
______________________________________________________________________________________
15
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
current time by an incomplete write operation, the current time value is buffered from being written directly to
the clock counters. The new data sent replaces the current contents of this input buffer. This time update data
is loaded into the clock counters after the stop bit at the
end of the I2C bus write operation. Collision-detection
circuitry ensures that this does not happen coincident
with a seconds-counter update to guarantee that accurate time data is being written. This avoids time data
changes during a write operation. An incomplete write
operation aborts the time-update procedures and the
contents of the input buffer are discarded. The clock
counters reflect the new time data beginning with the
first 1s clock cycle after the stop bit. The clock counter
is reset immediately after a write to the seconds register or a burst write to the timekeeping registers. This
ensures that 1s clock tick is synchronous to timekeeping writes.
If single-write operations (Figure 9) are used to write to
each of the timekeeping registers, then error checking is
needed. If the seconds register is the one to be updated, update it first and then read it back and store its
value as the initial seconds. Update the remaining timekeeping registers and then read the seconds register
again (final seconds). If initial seconds was 59, ensure it
is still 59. If initial seconds was not 59, ensure that final
seconds is within 1s of initial seconds. If the seconds
register is not to be written to, then read the seconds
register first and save it as initial seconds. Write to the
required timekeeping registers and then read the seconds register again (final seconds). If initial seconds
was 59, ensure it is still 59. If initial seconds was not 59,
ensure that final seconds is within 1s of initial seconds.
Although both single writes and burst writes are possible, the most accurate way to write to the timekeeping
counters is to do a burst write (Figure 9). In the burst
write, the main timekeeping registers (seconds, minutes, hours, date, month, day, year) and the control
register are written sequentially. They must be all written to as a group of eight registers, with 8 bytes each,
for proper execution of the burst-write function. All
seven timekeeping registers and the control register
are simultaneously loaded into the input buffer at the
end of the 2-wire bus write operation. The worst-case
error that can occur between the actual time and the
write time update is 1s.
16
To avoid rollover issues when writing time data to the
MAX6917, the remaining time and date registers must
be written within 1s of updating the seconds register
when using single writes. For burst writes, all eight registers must be written within this period (1s).
The weekday data in the day register increments at
midnight. Values that correspond to the day of the
week are user defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday, and so on). If
invalid values are written to the timekeeping registers,
the operation becomes undefined.
Timeout Feature
The purpose of the bus timeout feature is to reset the serial bus interface and change the SDA line of the MAX6917
from an output to an input, which puts the SDA line into a
high-impedance state. This is necessary when the
MAX6917 is transmitting data and becomes stuck at a
logic-low level. If the SDA line is stuck low, any other
device on the bus is not able to communicate.
The timeout feature looks for a valid START and STOP
condition to determine whether SDA has been stuck
low. A valid START condition initiates the timeout
counter in reference to the internal 1Hz clock. Counting
begins on the first rising edge of the 1Hz clock after a
valid START condition. If a valid STOP condition is
detected before the next rising edge of the 1Hz clock,
the timeout counter is stopped and awaits a new valid
START condition. If a valid STOP condition is not
detected before the next rising edge of the 1Hz clock,
the I2C interface resets to the idle state and waits for a
new I2C transaction. Depending on the occurrence of
the START condition, that initiates the timeout counter,
in reference to the internal 1Hz clock, the timeout period can be 1s to 2s. The lower limit of the timeout period
(1s) imposes a limit on the SCL frequency of the
MAX6917 because a burst read/write requires up to 96
bytes of information to be transmitted in between a
START and STOP condition.
______________________________________________________________________________________
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Control Register
The control register contains bits for configuring the
MAX6917 for custom applications. Bit D0 (BATT ON
BLINK) and D1 (BATT LO BLINK) are used to enable a
1Hz blink rate on BATT_ON and BATT_LO when they
are active; see the Battery Test section for details. D2
(WD TIME) and D3 (WD EN) are used to enable the
watchdog function and select its timeout. For details,
see the Watchdog Input section. D5 (INT/EXT TEST)
sets whether the internal resistor ratio or an external
resistor ratio is to be used to check for the low-battery
condition; see the Battery Test section for details. D6
(XTAL EN) enables the crystal-fail-detect circuitry when
set. See the Crystal-Fail Detect section for details. D7
(WP) is the write protect bit. Before any write operation
to the registers (except the control register) or RAM, bit
7 must be zero. When set to one, the write-protect bit
prevents write operations to any register (except the
control register) or RAM location.
Timekeeping and Alarm Thresholds Registers
Time and date data is stored in the timekeeping and
alarm threshold registers in BCD format as shown in Table
1. The weekday data in the day register is user defined (a
common format is 1 = Sunday, 2 = Monday, etc.)
AM/PM and 12hr/24hr Mode
For both timekeeping and alarm threshold registers
(Table 1), D7 of the hours register is defined as the
12hr or 24hr mode-select bit. When set to one, the 12hr
mode is selected. In the 12hr mode, D5 is the AM/PM
bit with logic one being PM. In the 24hr mode, D5 is the
second 10hr bit (20hr to 23hr).
Clock-Burst Mode
Addressing the clock-burst register specifies burstmode operation. In this mode, the first eight clock/calendar registers (seven timekeeping and the control
register) can be consecutively read or written to by
using the address/command byte 00h for a write or 01h
for a read (Table 1). If the write-protect bit is set to one
when a write-clock/calendar-burst mode is specified,
no data transfer occurs to any of the seven timekeeping
registers or the control register. When writing to the
clock/calendar registers in the burst mode, the first
eight registers must be written to for the data to be
transferred.
RAM
The static RAM consists of 96 x 8 bits addressed consecutively in the RAM address/command space. Even
address/commands (3Eh to FCh) are used for RAM
writes and odd address/commands (3Fh to FDh) are
used for RAM reads (Table 2).
RAM-Burst Mode
Sending the RAM-burst address/command (FEh for
write, FFh for read) specifies burst-mode operation. In
this mode, the 96 RAM locations can be consecutively
read or written to starting with bit 7 of address/command 3Eh for writes, and 3Fh for reads. A burst read
outputs all 96 bytes of RAM. When writing to RAM in
burst mode, it is not necessary to write all 96 bytes for
the data to transfer; each complete byte written is
transferred to the RAM. When reading from RAM, data
are output until all 96 bytes have been read, or until the
data transfer is stopped by the I2C master.
Status Register
The status register contains individual bits for monitoring the status of several functions of the MAX6917. Bits
D0–D3 are unused and always read zero (Table 1). D4
(ALM OUT) reflects the state of the alarm function; see
the Alarm-Generation Function section for details. D5
(BATT LO) indicates the state of the battery connected
to VBATT; see the Battery Test section for more information. D6 (DATA VALID) alerts the user if all power was
lost. See the Data Valid Bit section for details. D7 (XTAL
FAIL) is the output of the crystal-fail detect circuit. See
the Crystal-Fail Detect section for details.
______________________________________________________________________________________
17
MAX6917
Registers
Tables 1 and 2 show the register map, as well as the
register descriptions for the MAX6917.
Table 1. Register Map
REGISTER ADDRESS
FUNCTION
A7
A6
CLOCK
BURST
0
0
SEC
1
0
A5
0
A4
0
A3
0
A2
0
REGISTER FUNCTION
A1
0
A0
0
1
0
0
0
0
0
R
1
0
0
0
0
0
R
1
0
0
0
0
0
R
W
DATE
0
MONTH
1
0
1
0
0
0
0
R
W
0
0
1
1
1
0
0
0
0
0
0
0
1
CENTURY
0
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0–59
0
0
1
0
1
1
0
0
1
1
0
0
0
0
0
0
1 SEC
0
0
0
0
0
10 MIN
0
0
0
1 MIN
0
0
0
12/24
0
POR STATE
0
01–28/29
01–30/31
POR STATE
0–59
POR STATE
0
0
10 HR
00–23
01–12
1 HR
AM/
PM
10 HR
0
0
0
0
0
0
0
10 DATE
0
0
0
0
0
0
10 M
0
0
0
0
0
0
0
0
R
01–07
POR STATE
0
0
0
0
0
0
0
0
0
0
00–99
POR STATE
0
1
1
1
0
0
WP
XTAL
EN
0
WD
EN
WD
TIME
POR STATE
0
1
0
1
0
00–99
POR STATE
0
0
1
1
DAY
DATE
0
0
R
R
R
ONE
YEAR
SEC
R
0
32kHz
VCC
EN
W
R
W
POR STATE
1
0
INT/
EXT
TEST
0
XTAL
FAIL
0
0
0
0
1
WEEKDAY
0
0
1
0
0
BATT BATT
LO
ON
BLINK BLINK
0
0
0
0
1
HR
MIN
SEC
0
0
0
0
1kHz
VBAT
EN
0
0
0
0
0
0
0
0
0
0
BATT
LO
ALM
OUT
0
0
0
0
0
0
0
0
0
0
POR STATE DEFINES THE POWER-ON RESET STATE OF THE REGISTER.
18
1
100 YEAR
1kHz 32kHz
VCC VBATT
EN
EN
1
0
1 YEAR
1000 YEAR
0
0
1 MONTH
10 YEAR
R
W
0
1 DATE
01–12
POR STATE
STATUS
D0
10 SEC
0
W
0
D1
0
POR STATE
POR STATE
FOUT
CONFIGURATION
D2
POR STATE
W
ALARM
CONFIGURATION
D3
R
W
CONTROL
D4
W
W
YEAR
D5
MONTH
DAY
D6
W
W
HR
D7
R
W
MIN
VALUE
DATA
VALID
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
______________________________________________________________________________________
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6917
Table 1. Register Map (continued)
REGISTER ADDRESS
FUNCTION
BATT TEST
REGISTER FUNCTION
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
1
1
0
1
0
0
0
0
1
1
1
0
VALUE
D7
D6
D5
D4
D3
D2
D1
D0
ALARM
THRESHOLDS:
SEC
R
W
MIN
0
0
0
1
1
1
1
R
W
HR
0
0
1
0
0
0
0
R
W
DATE
0
MONTH
0
DAY
0
YEAR
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
R
W
0
0
0
0
1
0
1
0
1
0
1
10 SEC
1
1
1
1 SEC
1
1
0
1
10 MIN
1
1
1
1
12/24
0
POR STATE
1
0
1
1
1
1
01–28/29
01–30/31
POR STATE
0
0
0
0
10 DATE
1
1
0–59
POR STATE
0
0
1
1
1
1
1
1 DATE
1
1
1
1
1 MONTH
1
1
1
10 HR
00–23
01–12
AM/
PM
10 HR
1 HR
R
01–12
0
0
0
POR STATE
0
0
0
R
01–07
POR STATE
0
0
0
0
0
0
0
0
0
0
W
R
R
W
1
1 MIN
W
W
TEST
CONFIGURATION
(FACTORY
RESERVED)
0–59
POR STATE
10 M
1
10 YEAR
WEEK DAY
1
1
1
1 YEAR
00–99
POR STATE
1
1
1
1
1
1
1
1
POR STATE
0
0
0
0
0
0
0
0
RAM DATA 0
00h-FFh
X
X
X
X
X
X
X
X
RAM DATA 95
00h-FFh
X
X
X
X
X
X
X
X
RAM REGISTERS:
RAM 0
1
1
1
1
1
R
W
1
1
1
1
...
...
RAM 95
1
1
0
R
W
RAM BURST
1
1
1
1
1
1
1
R
W
POR STATE DEFINES THE POWER-ON RESET STATE OF THE REGISTER.
______________________________________________________________________________________
19
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Power Control
Alarm-Generation Function
VBATT provides power as a battery backup. VCC provides the primary power in dual-supply systems where
VBATT is connected as a backup source to maintain
timekeeping in the absence of primary power. When
VCC rises above the reset threshold, VRST, VCC powers
the MAX6917. When VCC falls below the reset threshold, VRST, and is less than VTRD, VBATT powers the
MAX6917. If VCC falls below the reset threshold, VRST,
and is more than VTRU, VCC still powers the MAX6917.
VCC slew rate in power-down is limited to 10V/ms (max)
for proper data retention.
The alarm function is configured using the alarm-configuration register and the alarm-threshold registers
(Table 1). Writing a one to D7 (ONE SEC) in the alarmconfiguration register sets the alarm function to occur
once every second, regardless of any other setting in
the alarm-configuration register or in any of the alarmthreshold registers. When the alarm is triggered, D4
(ALM OUT) in the status register is set to one and the
open-drain alarm output ALM goes low. The alarm is
cleared by reading or writing to the alarm-configuration
register or by reading or writing to any of the alarmthreshold registers. This resets the ALM output to a
high and the ALM OUT bit to zero.
When D7 (ONE SEC) is set to zero in the alarm-configuration register, then the alarm function is set by the
remaining bits in the alarm-configuration register and
the contents of the respective alarm-threshold register.
For example, writing 01h (0000 0001) to the alarm-configuration register causes the alarm to trigger every
time the seconds-timekeeping register matches the
seconds alarm-threshold register (i.e., once every
minute on a specific second). Writing 02h (0000 0010)
to the alarm configuration register causes the alarm to
trigger on a minutes match (i.e., once every hour).
Writing a 4Fh (0100 1111) to the alarm configuration
register causes the alarm to be triggered on a specific
second, of a specific minute, of a specific hour, of a
specific date, of a specific year.
When setting the alarm-threshold registers, ensure that
both the hour-timekeeping register and the hour-alarmthreshold register are using the same-hour format
(either 12hr or 24hr format).
The alarm function, as well as the ALM output, is operational in both VCC and battery-backup mode.
VOUT Function
VOUT is an output supply voltage for battery-backed-up
devices such as SRAM. When V CC rises above the
reset threshold or is greater than VBATT, VOUT connects
to VCC (Figure 19). When VCC falls below V RST and
V BATT , V OUT connects to V BATT . There is a typical
±100mV hysteresis associated with the switching
between VCC and VBATT on the VOUT output. Connect
a 0.1µF capacitor from VOUT to GND.
Power-On Reset (POR)
The MAX6917 contains an integral POR circuit that
ensures all registers are reset to a known state on powerup. Once either VCC or VBATT rises above 1.6V (typ), the
POR circuit releases the registers for normal operation.
When VCC or VBATT drops to less than 0.9V (typ), the
MAX6917 resets all register contents to the POR defaults.
Oscillator Start Time
The MAX6917 oscillator typically takes 1s to 2s to begin
oscillating. To ensure the oscillator is operating correctly, the system software should validate proper timekeeping. This is accomplished by reading the seconds
register. Any reading with more than 0s, from the POR
value of 0s, is a validation of proper startup.
20
______________________________________________________________________________________
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6917
Table 2. Hex Register Address and Description
WRITE ADDRESS/COMMAND
(HEX)
READ ADDRESS/COMMAND
(HEX)
DESCRIPTION
POR SETTING
(HEX)
00
01
Clock burst
N/A
02
03
Seconds
00
04
05
Minutes
00
06
07
Hour
00
01
08
09
Date
0A
0B
Month
01
0C
0D
Day
01
0E
0F
Year
70
10
11
Control
48
12
13
Century
00
14
15
Alarm configuration
19
16
17
FOUT configuration
C0
18
19
Status
00
N/A
1A
N/A
Battery test
1C
1D
Seconds alarm threshold
7F
1E
1F
Minutes alarm threshold
7F
20
21
Hours alarm threshold
BF
22
23
Date alarm threshold
3F
24
25
Month alarm threshold
1F
26
27
Day alarm threshold
07
28
29
Year alarm threshold
FF
2A
2B
Test configuration
00
3E
3F
RAM 0
Indeterminate
40
41
RAM 1
Indeterminate
42
43
RAM 2
Indeterminate
44
45
RAM 3
Indeterminate
46
47
RAM 4
Indeterminate
•
•
•
•
•
•
•
•
•
•
•
•
F4
F5
RAM 91
Indeterminate
F6
F7
RAM 92
Indeterminate
F8
F9
RAM 93
Indeterminate
FA
FB
RAM 94
Indeterminate
FC
FD
RAM 95
Indeterminate
FE
FF
RAM BURST
Indeterminate
______________________________________________________________________________________
21
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Crystal-Fail Detect
The crystal-fail detect circuit looks for a loss of oscillation
from the 32.768kHz oscillator for 30 cycles (typ) or more.
Both the control register and the status register are used
in the crystal-failure detection scheme (Table 1).
The crystal-fail detect circuit sets the XTAL FAIL bit in
the status register to one for a crystal failure and to zero
for normal operation. Once the status register is read,
the XTAL FAIL bit is reset to zero, if it was previously
one. If the crystal-fail-detect circuit continues to sense
a failed crystal, then the XTAL FAIL bit is set again.
On initial power-up, the crystal-fail detect circuit is
enabled. Since it takes a while for the low-power,
32.768kHz oscillator to start, the XTAL FAIL bit in the
status register can be set to one indicating a crystal
failure. The XTAL FAIL bit should be polled a number of
times to see if it is set to zero for successive polls. If the
polling is far enough apart, a few polled results could
guarantee that a maximum of 10s had elapsed since
power-on, at which time the oscillator would be considered truly failed if the XTAL FAIL bit remains one.
On subsequent power-ups, when XTAL EN is set to
one, if XTAL FAIL is set to one, time data should be
considered suspect.
The crystal-fail-detection circuit functions in both VCC
and VBATT modes when the XTAL EN bit is set in the
control register.
Manual Reset Input
A logic low on MR asserts RESET. RESET remains
asserted while MR is low, and for tRP after it returns
high (Figure 10). MR has an internal pullup resistor, so
it can be left open if it is not used. Internal debounce
circuitry requires a minimum low time on the MR input
of 1µs with 35ns maximum glitch immunity.
Reset Output
A µP’s reset input starts the µP in a known state. The
MAX6917’s µP supervisory circuit asserts a reset to
prevent code-execution errors during power-up, powerdown, and brownout conditions. The RESET output is
guaranteed to be active for 0V < VCC < VRST, provided
VBATT is greater than VBATT (min). If VCC drops below
and then exceeds the reset threshold, an internal timer
keeps RESET active for the reset timeout period tRP;
after this interval, RESET becomes inactive high. This
condition occurs at either power-up or after a V CC
brownout.
22
MR
CE OUT
tRCE
tRP
tRP
RESET
CE IN
Figure 10. Manual-Reset Timing Diagram
The RESET output is also activated when the watchdog
interrupt function is enabled but no transition is detected on the WDI input. In this case, RESET is active for
the period tRP before becoming inactive again. When
RESET is active, all inputs—WDI, MR, CE_IN, SDA, and
SCL—are disabled.
The MAX6917EO30 is optimized to monitor 3.0V ±10%
power supplies. Except when MR is asserted, RESET is
not active until VCC falls below 2.7V (3.0V - 10%), but is
guaranteed to occur before the power supply falls
below 2.5V (3.0V - 15%).
The MAX6917EO33 is optimized to monitor 3.3V ±10%
power supplies. Except when MR is asserted, RESET is
not active until VCC falls below 3.0V (3.0V is just above
3.3V - 10%), but is guaranteed to occur before the
power supply falls below 2.8V (3.3V - 15%).
The MAX6917EO50 is optimized to monitor 5.0V ±10%
power supplies. Except when MR is asserted, RESET is
not active until VCC falls below 4.5V (5.0V - 10%), but is
guaranteed to occur before the power supply falls
below 4.1V (4.1V is just below 5.0V - 15%).
Negative-Going VCC Transients
The MAX6917 is relatively immune to short-duration negative transients (glitches) while issuing resets to the µP during power-up, power-down, and brownout conditions.
Therefore, resetting the µP when VCC experiences only
small glitches is usually not recommended. Typically, a
VCC transient that goes 150mV below the reset threshold
and lasts for 90µs or less does not cause a reset pulse to
be issued. A 0.1µF capacitor mounted close to the VCC
pin provides additional transient immunity.
______________________________________________________________________________________
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6917
BUFFER
VCC
VRST
VCC
VCC
VCC
tRP
µP
MAX6917
RESET
4.7kΩ
RESET
tRP
tWD
tWD
RESET
WDI
GND
WD EN AND WD TIME ARE SET
TO ZERO AND THE WATCHDOG
FUNCTION IS DISABLED.
GND
Figure 11. Interfacing to µP with Bidirectional Reset I/O
Interfacing to µPs with Bidirectional
Reset Pins
Microprocessors with bidirectional reset pins, such as
the Motorola 68HC11 series, can contend with the
MAX6917 RESET output. If, for example, the RESET
output is driven high and the µP wants to pull it low,
indeterminate logic levels can result. To correct this,
connect a 4.7kΩ resistor between the RESET output
and the µP reset I/O as shown in Figure 11. Buffer the
RESET output to other system components.
Battery-On Output
The battery-on output, BATT_ON, is an open-drain output that indicates when the MAX6917 is powered from
the backup-battery input, VBATT. When VCC falls below
the reset threshold, V RST , and below V BATT , V OUT
switches from VCC to VBATT and BATT_ON becomes
low. When VCC rises above the reset threshold, VRST,
VOUT reconnects to VCC and BATT_ON becomes high
(open-drain output with pullup resistor). If desired, the
BATT_ON output can be register selected, through the
BATT ON BLINK bit in the control register, to toggle on
and off 0.5s on, 0.5s off when active. The POR default
is logic zero for no blink.
Watchdog Input
The watchdog circuit monitors the µP’s activity. If the
µP does not toggle the watchdog input (WDI) within the
register-selectable watchdog-timeout period, RESET is
asserted for tRP. At the same time, the WD EN and WD
TIME bits in the control register (Table 1) are reset to
zero and can only be set again by writing the appropriate command to the control register. Thus, once a
RESET is asserted due to a watchdog timeout, the
watchdog function is disabled (Figure 12).
Figure 12. Watchdog Timing Diagram
WDI can detect pulses as short as tWDI. Data bit D2 in
the control register controls the selection of the watchdog-timeout period. The power-up default is 1.6s (D2 =
0). A reset condition returns the timeout to 1.6s (D2 =
0). If D2 is set to one, then the watchdog-timeout period
is changed to 200ms. Data bit D3 in the control register
is the watchdog-enable function. A logic zero disables
the watchdog function, while a logic one enables it. The
POR state of WD EN is logic one, or the watchdog function is enabled. Disable the watchdog function by writing a zero to the WD EN bit in the control register,
within the 1.6s POR default timeout after power-up.
WDI does not include a pulldown or pullup feature. For
this reason, WDI should not be left floating. When the
WD EN bit in the control register is set to zero, WDI
should be connected to VCC or GND. WDI is disabled
and does not draw cross-conduction current when VCC
falls below VRST.
Watchdog Software Considerations
There is a way to help the watchdog-timer monitor software execution more closely, which involves setting and
resetting the watchdog input at different points in the
program rather than “pulsing” the watchdog input. This
technique avoids a “stuck” loop, in which the watchdog
timer would continue to be reset within the loop, keeping
the watchdog from timing out. Figure 13 shows an
example of a flow diagram where the I/O driving the
watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or
loop, then set high again when the program returns to
the beginning. If the program should “hang” in any subroutine, the problem would quickly be corrected since
the I/O is continually set low and the watchdog timer is
allowed to time out, causing a reset to be issued.
______________________________________________________________________________________
23
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
START
MAX6917
VOUT
SET WDI
HIGH
CHIP-ENABLE
OUTPUT
CONTROL
PROGRAM
CODE
RESET
GENERATOR
SUBROUTINE OF
PROGRAM LOOP
SET WDI HIGH
CE_IN
CE_OUT
RETURN
Figure 13. Watchdog Flow Diagram
Figure 14. Chip-Enable Gating
Chip-Enable Gating
Internal gating of chip-enable (CE) signals prevents
erroneous data from corrupting external SRAM in the
event of an undervoltage condition. The MAX6917 uses
a transmission gate from CE_IN to CE_OUT (Figure 14).
During normal operation (RESET inactive), the transmission gate is enabled and passes all CE transitions.
When reset is asserted, this path becomes disabled,
preventing erroneous data from corrupting the external
SRAM. The short CE propagation delay from CE_IN to
CE_OUT enables the MAX6917 to be used with most
µPs. If CE_IN is low when reset asserts, CE_OUT
remains low for tRCE to permit completion of the current
write cycle.
The propagation delay through the CE transmission
gate depends on VCC, the source impedance of the
driver connected to CE_IN, and the loading on
CE_OUT (see the Chip-Enable Propagation Delay vs.
CE_OUT Load Capacitance graph in the Typical
Operating Characteristics). For minimum propagation
delay, the capacitive load at CE_OUT should be minimized, and a low-output-impedance driver should be
used on CE_IN (Figure 15).
VCC
Chip-Enable Input
The CE transmission gate is disabled and CE_IN is high
impedance (disabled mode) while RESET is active. During
a power-down sequence when VCC passes the reset
threshold, the CE transmission gate disables and CE_IN
immediately becomes high impedance if the voltage at
CE_IN is high. If CE_IN is low when RESET becomes
active, the CE transmission gate disables at the moment
CE_IN goes high or tRCE after RESET is active, whichever
occurs first (see the Chip-Enable Timing diagram). This
permits the current write cycle to complete during powerdown. The CE transmission gate remains disabled and
CE_IN remains high impedance (regardless of CE_IN
activity) for most of the reset-timeout period (tRST) any time
a RESET is generated. When the CE transmission gate is
enabled, the impedance of CE_IN appears as a 46Ω (typ)
load in series with the load at CE_OUT.
24
VCC
BATT
3.6V
25Ω EQUIVALENT
SOURCE IMPEDANCE
MAX6917
50Ω
50Ω CABLE
CE_IN
CE_OUT
CL
10pF
50Ω
GND
CL INCLUDES LOAD CAPACITANCE AND SCOPE PROBE CAPACITANCE.
Figure 15. Propagation Delay Test Circuit
______________________________________________________________________________________
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6917
VRST
VRST
2.0V
VCC
tRP
tRPD
RESET
tRP
VCC
CE_OUT
VBATT
tRCE
tCED
CE_IN
Figure 16. Chip-Enable Timing Diagram
Chip-Enable Output
When the CE transmission gate is enabled, the impedance seen at CE_OUT is equivalent to a 46Ω (typ)
resistor in series with the source driving CE_IN. In the
disabled mode, the transmission gate is off and an
active pullup connects CE_OUT to VOUT (see Figures
14, 16). This pullup turns off when the transmission
gate is enabled.
Test Configuration Register
This is a read-only register.
from a reset condition caused by VCC < VRST, the DATA
VALID bit can be read to see if the data stored during
operation from the backup power supply is still valid (i.e.,
the backup power supply did not drop out). A one indicates valid data and a zero indicates corrupted data.
Any time the internal supply to the MAX6917 (either
VBATT or VCC depending upon the operating conditions)
drops below 1.5V to 1.6V (typ), the DATA VALID bit is set
to zero even if it has recently been set by a read of the
status register.
Data Valid Bit
DATA VALID has a POR setting of zero, indicating that
the data in the MAX6917 RTC is not guaranteed to be
valid (Table 1). A read of the status register sets the
DATA VALID bit to one, indicating valid data in the
MAX6917 RTC. In a system that uses a backup power
supply, the DATA VALID bit should be set to one by the
system software on first system power-up by reading the
status register. After that, any time the system recovers
______________________________________________________________________________________
25
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
VBATT
VCC
BATT_LO
BATT_LO
CONTROL
LOGIC
1.24V
RSET+_EXT
RSET+_INT
480kΩ
RLOAD_EXT
(OPTIONAL)
INT/EXT
TEST
TRIP
INT/EXT
TEST = 0
RSET-_EXT
VOUT
TEST
RSET-_INT
430kΩ
BATT
TEST
(±5mA)
MAX6917
QEXT
Figure 17. MAX6917 Battery Load and Test Circuit
Battery Test
Battery-Test Normal Operation
In normal operation, the battery-test circuitry uses the
control register POR settings of INT/EXT TEST, which is
set to logic low as default (Table 1). In this mode, all battery-test load resistors and threshold settings are internal.
When VCC rises above VRST, the MAX6917 automatically
performs one power-on battery monitor test. Additionally,
a battery check is performed every time that a reset is
issued, either from a manual reset or a watchdog timeout.
After that, periodic battery voltage monitoring at the factory-programmed time interval of 24hr begins while VCC is
applied.
After each 24hr period (t BTCN ) has elapsed, the
MAX6917 connects VBATT to an internal 0.91MΩ (typ)
test resistor (R SET+_Int + R SET-_Int ) for 1s (t BTPW )
(Figure 17). During this 1s, if VBATT falls below the factory-programmed battery trip point V BTP, the opendrain, battery-low output, BATT_LO, is asserted active
low and the BATT LO bit in the status register is set to
one. The BATT LO output can be register selected to
toggle at a 1Hz rate (0.5s on, 0.5s off) when active.
Once BATT LO is active, the 24hr tests stop until a
fresh battery is inserted and BATT LO is cleared by
writing any data to the battery test register at address
26
0x0D (Figure 18). Writing to this register performs a
battery test and provided that the fresh battery is not
low, deactivates the BATT LO output and resets BATT
LO in the status register. Normal 24hr testing resumes.
If a different load or BATT LO thresholds are desired for
testing the backup battery, then external program resistors can be used in conjunction with the TRIP and TEST
inputs (see the Battery Test-Control Register and Other
Test Options section).
Battery replacement following BATT_LO activation
should be done with VCC nominal and not in batterybackup mode so that SRAM data is not lost.
Alternatively, if SRAM data need not be saved, the battery can be replaced with the VCC supply removed. If a
battery is replaced in battery-backup mode, sufficient
time must be allowed for the voltage on the VOUT output to decay to zero. This ensures that the freshnessseal mode of operation has been reset and is active
when VCC is powered up again. If insufficient time is
allowed, then VCC must exceed VBATT during the subsequent power-up to ensure that the MAX6917 has left
battery-backup mode (Figure 19).
The MAX6917 does not constantly monitor an attached
battery because such monitoring would drastically
reduce the life of the battery. As a result, the MAX6917
______________________________________________________________________________________
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6917
VRST
VCC
VBATT
VBTP (BATTERY TEST POINT)
tBTCN
tBTPW
BATTERYTEST ACTIVE
tBL
ONCE THE BATTERY IS DETECTED AS LOW,
THE PERIODIC BATTERY TESTING CEASES.
A BATTERY CHECK CAN BE INITIATED BY
WRITING TO THE REGISTER 0x1A.
BATT_LO
Figure 18. Battery-Test Timing Diagram
VBATT
VRST
VRST
VRST
VRST
VCC
VBATT
0V
BATTERY
DETACH
BATTERY
ATTACH
BATTERY
DETACH
BATTERY
ATTACH
VBATT
FLOATING
VBATT
FLOATING
EXIT FRESHNESS
SEAL MODE
VOUT
0V
VBATT CONNECTED TO VOUT
VCC CONNECTED
TO VOUT
VBATT CONNECTED
TO VOUT
FRESHNESS
SEAL RESET
VCC CONNECTED
TO VOUT
VBATT CONNECTED
TO VOUT
Figure 19. Battery Switchover Diagram
only tests the battery for 1s every 24hr. If a good battery (one that has not been previously flagged with
BATT_LO) is removed between battery tests, the
MAX6917 does not immediately sense the removal and
does not activate BATT_LO until the next-scheduled
battery test. For this reason, a software-commanded
battery test should be performed after a battery
replacement by writing any data to the battery-test register at address 1Ah.
Battery monitoring is only a useful technique when testing can be done regularly over the entire life of a lithium
battery. Because the MAX6917 only performs battery
monitoring when VCC is nominal, systems that are pow-
ered down for excessively long periods can completely
drain their lithium cells without receiving any advanced
warning. To prevent such an occurrence, systems
using the MAX6917 battery-monitoring feature should
be powered up periodically (at least every few months)
to perform battery testing. Furthermore, anytime
BATT_LO is activated on the first battery test after a
power-up, data integrity should be checked through a
checksum or other technique. Timekeeping data would
also be suspect and should be checked for accuracy
against an accurate known reference.
______________________________________________________________________________________
27
MAX6917
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Rf
MAX6917
Rd
Cg
12pF
Cd
12pF
X1
X2
EXTERNAL
CRYSTAL
Figure 20. Oscillator Functional Schematic
GROUND PLANE
VIA CONNECTION
*
GUARD RING
*
MAX6917
*
*
*
*
X1
*
**
*
GROUND
PLANE VIA
CONNECTION
X2
*
SM WATCH CRYSTAL
*
**
*
GROUND PLANE
VIA CONNECTION
**
*LAYER 1 TRACE
**LAYER 2 LOCAL GROUND PLANE
CONNECT ONLY TO PIN 8
GROUND PLANE VIA CONNECTION
Figure 21. Crystal Layout
Freshness-Seal Mode
When the battery is first attached to the MAX6917 without
VCC power applied, the device does not immediately provide battery-backup power to VOUT (Figure 19). Only
after VCC exceeds VRST and later falls below both VRST
and VBATT does the MAX6917 leave freshness-seal mode
and provide battery-backup power. This mode allows a
battery to be attached during manufacturing but not used
until after the system has been activated for the first time.
As a result, no battery energy is drained during storage
and shipping.
Battery-Test Control Register and Other Test Options
There are two warning formats for the BATT_LO and
BATT_ON outputs. By setting D0 (BATT ON BLINK)
28
and/or D1 (BATT LO BLINK) in the control register to one,
the respective warning output toggles on every 0.5s and
off every 0.5s when set to active low by the internal
MAX6917 logic. This allows a more noticeable warning
indicator in systems where an LED is connected as a status or warning light for the end user. The POR default settings of zero leave these outputs set to logic low when
they are active.
D5 (INT/EXT TEST) selects whether the battery-test circuit is configured as internal or external (Table 1). If D5
is set to zero (default value), then the internal resistordivider is used between VBATT and GND to select the
battery-low trip point (Figure 17). The internal resistors,
RSET+_INT and RSET-_IINT, are used to divide VBATT in
half, as well as to provide the battery-test-load resistance of 0.91MΩ (typ).
If D5 (INT/EXT TEST) is set to one, then the two external
resistors, RSET+_EXT and RSET-_EXT, are used to divide
VBATT down to the ratio for a trip point set at TRIP of
1.24V (VTRIP) (typ). RSET+_EXT plus RSET-_EXT in series
provide the load resistance used during the 1s every24hr-battery test. If additional load resistance is
desired, then an external load resistor, RLOAD_EXT, can
be placed between VBATT and the collector or drain of
the transistor driven by TEST. The equivalent load resistance used to test the battery is then RLOAD_EXT in parallel with the series combination of RSET+_EXT plus
R SET-_EXT . In this mode, the internal resistors are
removed from TRIP and are not used as a load during
the battery-test pulse. TEST pulses high to perform the
battery test and remains low between tests.
One final battery-test feature of the MAX6917 is the
software write address/command of 1Ah that forces a
1s battery test to be performed every time it is sent.
Frequency Outputs
The 1Hz and 32kHz (32.768kHz) frequency outputs
provide buffered, push-pull outputs for timing or clocking of external devices. Each push-pull output is referenced to GND for logic-low output levels and
referenced to V OUT for logic-high output levels.
Disabled frequency outputs are held at a logic-low
level. The FOUT configuration register (Table 1) contains individual enable bits that control the state of the
respective frequency output for V CC operating mode
and for VBATT operating mode.
Bits D5 (32kHz VBATT EN) and D4 (1Hz VBATT EN) in
the FOUT configuration register enable the respective
frequency output when operating from VBATT, if set to
one, or disable the respective frequency output if set to
zero. POR settings disable all frequency outputs when
operating from VBATT.
______________________________________________________________________________________
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
Applications Information
Crystal Selection
Connect a 32.768kHz watch crystal directly to the
MAX6917 through pins 9 and 10 (X1, X2) (Figure 20).
Use a crystal with a specified load capacitance (CL) of
6pF. Refer to Applications Note 616: Considerations for
Maxim Real-Time Clock Crystal Selection from the
Maxim website (www.maxim-ic.com) for more information regarding crystal parameters and crystal selection,
as well as a list of crystal manufacturers.
When designing the PC board, keep the crystal as
close to the X1 and X2 pins of the MAX6917 as possible. Keep the trace lengths short and small to reduce
capacitive loading and prevent unwanted noise pickup.
Place a guard ring around the crystal and tie the ring to
ground to help isolate the crystal from unwanted noise
pickup. Keep all signals out from beneath the crystal
and the X1 and X2 pins to prevent noise coupling.
Finally, an additional local ground plane on an adjacent
PC board layer can be added under the crystal to
shield it from unwanted pickup from traces on other layers of the board. This plane should be isolated from the
regular PC board ground, tied to the GND pin of the
MAX6917, and needs to be no larger than the perimeter of the guard ring. Ensure that this ground plane
does not contribute to significant capacitance between
the signal line and ground on the connections that run
from X1 and X2 to the crystal. See Figure 21.
For frequency stability overtemperature, refer to the
Applications Note: Real-Time-Clock Selection and Optimization from the Maxim website (www.maxim-ic.com.)
Chip Information
PROCESS: CMOS
______________________________________________________________________________________
29
MAX6917
Bits D7 (32kHz VCC EN) and D6 (1Hz VCC EN) in the
FOUT configuration register enable the respective frequency output when operating from VCC, if set to one,
or disable the respective frequency output if set to
zero. POR settings enable both output frequencies
when operating from VCC.
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
MAX6917
Pin Configuration
Selector Guide
PART
SUPPLY VOLTAGE (V)
MAX6917EO30
3.0
MAX6917EO33
3.3
MAX6917EO50
5.0
TOP VIEW
VOUT 1
20 VBATT
TEST 2
19 VCC
TRIP 3
18 RESET
BATT_ON 4
17 BATT_LO
MAX6917
CE_IN 5
16 CE_OUT
MR 6
15 ALM
WDI 7
14 SCL
GND 8
13 SDA
X1 9
12 1HZ
X2 10
11 32KHZ
QSOP
Typical Application Circuit
3.3V
3.3V
3.3V 3.3V
3.3V
3.3V
LED
ALM
INTO
SDA
SDA
SCL
SCL
1HZ
INT1
BATT_LO
N.C.
BATT_ON
X1
CRYSTAL
X2
3.3V
VCC
0.1µF
MAX6917
CE_IN
CS
RESET
RST
WDI
P1.0
TEST
N.C.
TRIP
N.C.
µC
GND
N
32KHZ
VBATT
3.0V
N.C.
0.1µF
I/O
VOUT
0.1µF
CMOS SRAM
USER RESET
MR
CE_OUT
CE
GND
GND
30
______________________________________________________________________________________
I2C-Compatible RTC with Microprocessor
Supervisor, Alarm, and NV RAM Controller
QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX6917
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)