AD AD8392A Low power, high output current, quad op amp, dual-channel adsl/adsl2 line driver Datasheet

Low Power, High Output Current, Quad Op
Amp, Dual-Channel ADSL/ADSL2+ Line Driver
AD8392A
Data Sheet
VEE 1
28
GND
PD0 1, 2
2
27
NIC
PD1 1, 2
3
26
NIC
+VIN1
4
25
+VIN2
–VIN1
5
24
–VIN2
VOUT1
6
23
VOUT2
VCC
7
AD8392A
22
NIC
NIC
8
21
VCC
VOUT3
TOP VIEW
(Not To Scale)
9
20
VOUT4
19
–VIN4
1
–VIN3 10
2
3
+VIN3 11
4
18
+VIN4
NIC 12
17
PD1 3, 4
NIC 13
16
PD0 3, 4
GND 14
15
VEE
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. CONNECT THE EXPOSED
PAD TO GROUND PLANE.
06477-001
PIN CONFIGURATIONS
+VIN2
VCOM1, 2
NIC
ADSL/ADSL2+ CO line drivers
XDSL line drivers
GND
+VIN1
APPLICATIONS
VEE
Figure 1. AD8392AARE, 28-Lead TSSOP_EP
PD0 1, 2
Four current feedback, high current amplifiers
Ideal for use as ADSL/ADSL2+ dual-channel central office
(CO) line drivers
Low power operation
Power supply operation from ±5 V (+10 V) up to ±12 V (+24 V)
Less than 3 mA/amp quiescent supply current for full
power ADSL/ADSL2+ CO applications (20.4 dBm line
power, 5.5 CF)
Three active power modes plus shutdown
High output voltage and current drive
500 mA peak output drive current
42.6 V p-p differential output voltage
Low distortion
−93 dBc @1 MHz second harmonic
−103 dBc @ 1 MHz third harmonic
High speed: 515 V/μs differential slew rate
Additional functionality of AD8392AACP
On-chip, common-mode voltage generation
PD1 1, 2
FEATURES
32 31 30 29 28 27 26 25
NIC 1
1
–VIN1 2
22 VOUT2
VOUT1 3
The AD8392A is available in two thermally enhanced packages,
a 28-lead TSSOP_EP (AD8392AARE) and a 5 mm × 5 mm,
32-lead LFCSP (AD8392AACP). Four bias modes are available
via the use of two digital bits (PD1, PD0).
AD8392A
VCC 4
21 NIC
TOP VIEW
(Not to Scale)
NIC 5
20 VCC
19 VOUT4
VOUT3 6
–VIN3 7
3
4
NIC 8
18
–VIN4
17
NIC
+VIN4
PD1 3, 4
PD0 3, 4
VEE
GND
VCOM3, 4
10 11 12 13 14 15 16
NIC
9
+VIN3
The AD8392A is comprised of four high output current, low
power consumption, operational amplifiers. It is particularly
well suited for the CO driver interface in digital subscriber line
systems, such as ADSL and ADSL2+. The driver is capable of
providing enough power to deliver 20.4 dBm to a line, while
compensating for losses due to hybrid insertion and back
termination resistors.
NIC
23 –VIN2
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. CONNECT THE EXPOSED
PAD TO GROUND PLANE.
06477-002
GENERAL DESCRIPTION
24
2
Figure 2. AD8392AACP, 5 mm × 5 mm, 32-Lead LFCSP
Additionally, the AD8392AACP provides VCOM pins for on-chip,
common-mode voltage generation.
The low power consumption, high output current, high output
voltage swing, and robust thermal packaging enable the
AD8392A to be used as the CO line drivers in ADSL and other
xDSL systems.
Rev. A
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AD8392A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications........................................................................................8
Applications ....................................................................................... 1
Supplies, Grounding, and Layout ................................................8
General Description ......................................................................... 1
Power Management ......................................................................8
Pin Configurations ........................................................................... 1
Thermal Considerations...............................................................8
Revision History ............................................................................... 2
Typical ADSL/ADSL2+ Application ...........................................9
Specifications..................................................................................... 3
Multitone Power Ratio ............................................................... 10
Absolute Maximum Ratings............................................................ 4
Outline Dimensions ....................................................................... 11
Thermal Resistance ...................................................................... 4
Ordering Guide .......................................................................... 11
ESD Caution .................................................................................. 4
Notes................................................................................................. 12
Typical Performance Characteristics ............................................. 5
Theory of Operation ........................................................................ 7
REVISION HISTORY
6/2016—Rev. 0 to Rev. A
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Change to Applications Section, Figure 1, and Figure 2 ............. 1
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
10/2006—Revision 0: Initial Version
Rev. A | Page 2 of 12
Data Sheet
AD8392A
SPECIFICATIONS
VS = ±12 V or +24 V, RL = 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Peaking
Slew Rate
NOISE/DISTORTION PERFORMANCE
Second Harmonic Distortion
Third Harmonic Distortion
Multitone Input Power Ratio
Voltage Noise (RTI)
+Input Current Noise
−Input Current Noise
INPUT CHARACTERISTICS
RTI Offset Voltage
+Input Bias Current
−Input Bias Current
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Differential Output Voltage Swing
Single-Ended Output Voltage Swing
Linear Output Current
POWER SUPPLY
Operating Range (Dual Supply)
Operating Range (Single Supply)
Total Quiescent Current
PD1, PD0 = (0, 0)
PD1, PD0 = (0, 1)
PD1, PD0 = (1, 0)
PD1, PD0 = (1, 1) (Shutdown State)
PD = 0 Threshold
PD = 1 Threshold
+Power Supply Rejection Ratio
−Power Supply Rejection Ratio
Min
Typ
25
23
−4
63
41.2
20.6
Unit
Test Conditions/Comments
37
30
0.06
515
MHz
MHz
dB
V/µs
VOUT = 0.1 V p-p, RF = 2 kΩ
VOUT = 4 V p-p, RF = 2 kΩ
VOUT = 0.1 V p-p, RF = 2 kΩ
VOUT = 20 V p-p, RF = 2 kΩ
−93
−103
70
2.5
7.6
12.5
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
fC = 1 MHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
26 kHz to 2.2 MHz, ZLINE = 100 Ω differential load
f = 10 kHz
f = 10 kHz
f = 10 kHz
mV
µA
µA
MΩ
pF
dB
V+IN − V−IN
V p-p
V p-p
mA
ΔVOUT
ΔVOUT, RL = 50 Ω
RL = 10 Ω, fC = 100 kHz
±2
2
3
8
1
66
+4
7
10
42.6
21.3
500
±5
10
5.8
3.0
2.6
0.4
1.8
72
65
Max
74
69
±12
24
V
V
6.5
3.5
3.0
0.08
0.8
mA/amp
mA/amp
mA/amp
mA/amp
V
V
dB
dB
Rev. A | Page 3 of 12
(ΔVOS, DM (RTI))/(ΔVIN, CM)
ΔVOS, DM (RTI)/ΔVCC, ΔVCC = ±1 V
ΔVOS, DM (RTI)/ΔVEE, ΔVEE = ±1 V
AD8392A
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Rating
±13 V (+26 V)
See Figure 3
−65°C to +150°C
−40°C to +85°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
In single supply with RL to VS−, worst case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the LFCSP-32 and
TSSOP_EP packages on a JEDEC standard 4-layer board.
θJA values are approximations.
7
TJ = 150°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified
for the device soldered in the circuit board for surface-mount
packages.
Table 3.
Package Type
LFCSP-32 (CP)
TSSOP_EP (RE)
θJA
27.27
35.33
Unit
°C/W
°C/W
6
5
LFCSP-32
4
TSSOP-28/EP
3
2
1
0
–40 –30 –20 –10
Maximum Power Dissipation
0
10 20 30 40 50
TEMPERATURE (°C)
60
70
80
90
06477-003
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
RMS output voltages should be considered. If RL is referenced to
VS− as in single-supply operation, the total power is VS × IOUT.
MAXIMUM POWER DISSIPATION (W)
Table 2.
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming that the load (RL) is midsupply,
the total drive power is VS/2 × IOUT, some of which is dissipated
in the package and some in the load (VOUT × IOUT).
See the Thermal Considerations section for additional thermal
design guidance.
ESD CAUTION
Rev. A | Page 4 of 12
Data Sheet
AD8392A
TYPICAL PERFORMANCE CHARACTERISTICS
0
900
850
SIGNAL FEEDTHROUGH (dB)
POWER CONSUMPTION (mW)
–20
800
PD (0, 0)
750
700
PD (0, 1)
650
PD (1, 0)
600
550
–40
–60
–80
–100
16
17
19
18
20
21
OUTPUT POWER (dBm)
–120
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 4. Power Consumption vs. Output Power (138 kHz to 2.2 MHz),
ADSL/ADSL2+ Circuit (Figure 15), VS = ±12 V, RLOAD = 100 Ω, CF = 5.5
Figure 7. Signal Feedthrough vs. Frequency
VS = ±12 V, G = +5, VIN = 800 mV p-p, PD (1, 1), RF = 2 kΩ
15
10
PD (0, 0)
GAIN (dB)
5
PD (0, 1)
0
2
–5
PD (1, 0)
–10
1
100k
1M
10M
1G
100M
FREQUENCY (Hz)
CH1 500mV CH2 500mV
100ns
06477-042
–20
10k
06477-049
–15
Figure 8. Power-Up Time: PD (1, 1) to PD (0, 0)
VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 1 V p-p, RF = 2 kΩ
Figure 5. Small Signal Frequency Response
VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 100 mV p-p, RF = 2 kΩ
15
10
PD (0, 0)
0
2
–5
PD (0, 1)
–10
1
PD (1, 0)
–20
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
CH1 500mV CH2 500mV
400ns
Figure 9. Power-Down Time: PD (0, 0) to PD (1, 1)
VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 1 V p-p, RF = 2 kΩ
Figure 6. Large Signal Frequency Response
VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 4 V p-p, RF = 2 kΩ
Rev. A | Page 5 of 12
06477-041
–15
06477-045
GAIN (dB)
5
06477-048
450
15
06477-046
500
AD8392A
Data Sheet
100
OUTPUT IMPEDANCE (Ω)
OUTPUT
CHANNEL 2
CH1 200mV CH2 2V
06477-040
2
400ns
10
PD (0, 0)
1
PD (0, 1)
PD (1, 0)
0.1
0.01
10k
100k
1M
10M
1G
100M
FREQUENCY (Hz)
Figure 13. Output Impedance vs. Frequency
VS = ±12 V, G = +5, RF = 2 kΩ
Figure 10. Output Overdrive Recovery, ADSL/ADSL2+ Circuit (Figure 15),
DMT Waveform, VS = ±12 V
0
–10
–20
CROSSTALK (dB)
–30
49.9Ω
DIFF CHANNEL 1, 2
–40
–50
2kΩ
DIFF CHANNEL 3, 4
–60
100Ω
499Ω
2kΩ
–70
–80
1M
100M
10M
FREQUENCY (Hz)
49.9Ω
06477-025
–100
100k
06477-053
–90
Figure 14. Dual Differential Driver Circuit
Figure 11. Crosstalk vs. Frequency, Dual Differential Driver Circuit (Figure 14),
VS = ±12 V, VIN = 800 mV p-p
45
1.78kΩ
35
0.01µF
634Ω
4.99Ω
30
77Ω
VCM
1µF
20
77Ω
15
87Ω
100Ω
2kΩ
4.99Ω
0.01µF
634Ω
0
10
20
30
40
50
60
70
80
LOAD RESISTANCE (Ω)
90
100
Figure 12. Differential Output Swing vs. RLOAD
Dual Differential Driver Circuit (Figure 14)
1.78kΩ
Figure 15. ADSL/ADSL2+ Circuit
Rev. A | Page 6 of 12
06477-021
10
87Ω
2kΩ
25
06477-054
DIFFERENTIAL OUTPUT (V p-p)
40
06477-047
INPUT
CHANNEL 1
Data Sheet
AD8392A
THEORY OF OPERATION
Of course, for a real amplifier there are additional poles that
contribute excess phase, and there is a value for RF below which
the amplifier is unstable. Tolerance for peaking and desired
flatness determines the optimum RF in each application.
RF
The open-loop transimpedance is analogous to the open-loop
voltage gain of a voltage feedback amplifier. Figure 16 shows a
simplified model of a current feedback amplifier. Because RIN is
proportional to 1/gm, the equivalent voltage gain is TZ × gm,
where gm is the transconductance of the input stage. Basic
analysis of the follower with gain circuit yields
RG
RIN
IIN
VIN
Figure 16. Simplified Block Diagram
The AD8392A is capable of delivering 500 mA of output
current while swinging to within 2 V of either power supply
rail. The AD8392A also has a power management system
included on-chip. It features four user-programmable power
levels (three active power modes as well as the provision for
complete shutdown).
where:
RIN =
VOUT
RN
VO
TZ (S )
= G×
VIN
TZ (S ) + G × RIN + RF
G =1+
TZ
06477-022
The AD8392A is a current feedback amplifier with high
(500 mA) output current capability. With a current feedback
amplifier, the current into the inverting input is the feedback
signal, and the open-loop behavior is that of a transimpedance,
dVO/dIIN or TZ.
RF
RG
1
≈ 50 Ω
gm
Because G × 
RIN << RF for low gains, a current feedback
amplifier has relatively constant bandwidth vs. gain, the 3 dB
point being set when |TZ| = RF.
Rev. A | Page 7 of 12
AD8392A
Data Sheet
APPLICATIONS
SUPPLIES, GROUNDING, AND LAYOUT
The information in Table 3 and Figure 3 is based on a standard
JEDEC 4-layer board and a maximum die temperature of 150°C.
To provide additional guidance and design suggestions, a
thermal study was performed under a set of conditions more
closely aligned with an actual ADSL/ADSL2+ application.
The AD8392A can be powered from either single or dual
supplies, with the total supply voltage ranging from 10 V to
24 V. For optimum performance, a well regulated low ripple
supply should be used.
As with all high speed amplifiers, close attention should be paid
to supply decoupling, grounding, and overall board layout. Low
frequency supply decoupling should be provided with 10 µF
tantalum capacitors from each supply to ground. In addition, all
supply pins should be decoupled with 0.1 µF quality ceramic
chip capacitors placed as close as possible to the driver. An
internal low impedance ground plane should be used to provide
a common ground point for all driver and decoupling capacitor
ground requirements. Whenever possible, separate ground
planes should be used for analog and digital circuitry.
High speed layout techniques should be followed to minimize
parasitic capacitance around the inverting inputs. Some practical
examples of these techniques are keeping feedback traces as
short as possible and clearing away ground plane in the area of
the inverting inputs. Input and output traces should be kept
short and as far apart from each other as practical to avoid
crosstalk. When used as a differential driver, all differential
signal traces should be kept as symmetrical as possible.
POWER MANAGEMENT
In a typical ADSL/ADSL2+ line card, component density
usually dictates that most of the copper plane used for thermal
dissipation be internal. Additionally, each ADSL/ADSL2+ port
may be allotted only 1 square inch, or even less, of board space.
For these reasons, a special thermal test board was constructed
for this study. The 4-layer board measured approximately
4 inches × 4 inches and contained two internal 1 oz copper
ground planes, each measuring 2 inches × 3 inches. The top
layer contained signal traces and an exposed copper strip
¼ inch × 3 inches to accommodate heat sinking, with no
other copper on the top or bottom of the board.
Three 28-lead TSSOPs were placed on the board representing
six ADSL channels, or one channel per square inch of copper,
with each channel dissipating 700 mW on-chip (1.4 W per
package). The die temperature is then measured in still air and
in a wind tunnel with calibrated airflow of 100 LFM, 200 LFM,
and 400 LFM. Figure 17 shows the power dissipation vs. the
ambient temperature for each airflow condition. The figure
assumes a maximum die temperature of 135°C. No heat sink
was used.
The AD8392A can be configured in any of three active bias
states as well as a shutdown state via the use of two sets of
digitally programmable logic pins. Pin PD0 (1, 2) and Pin PD1
(1, 2) control Amplifier 1 and Amplifier 2, while PD0 (3, 4) and
Pin PD1 (3, 4) control Amplifier 3 and Amplifier 4. These pins
can be controlled directly with either 3.3 V or 5 V CMOS logic
by using the GND pins as a reference. If left unconnected, the
PD pins float low, placing the amplifier in the full bias mode.
Refer to the Specifications for the per amplifier quiescent
current for each of the available bias states.
4.5
TJ = 135°C
4.0
POWER DISSIPATION (W)
400LFM
3.5
200LFM
3.0
2.5
STILL AIR
2.0
100LFM
1.0
15
65
45
55
25
35
AMBIENT TEMPERATURE (°C)
75
85
Figure 17. Power Dissipation vs. Ambient
Temperature and Air Flow 28-Lead TSSOP/EP
THERMAL CONSIDERATIONS
When using a quad, high output current amplifier, such as the
AD8392A, special consideration should be given to system level
thermal design. In applications such as the ADSL/ADSL2+,
the AD8392A could be required to dissipate as much as 1.4 W
or more on-chip. Under these conditions, particular attention
should be paid to the thermal design to maintain safe operating
temperatures on the die. To aid in the thermal design, the
thermal information in the Thermal Resistance section can
be combined with what follows here.
5
06477-051
1.5
As is shown in Figure 13, the AD8392A exhibits low output
impedance for the three active states. The shutdown state
(PD1, PD0 = 1, 1) provides a high impedance output.
This data is only provided as guidance to assist in the thermal
design process. Due diligence should be performed with regards
to power dissipation because there are many factors that can
affect thermal performance.
Rev. A | Page 8 of 12
Data Sheet
AD8392A
TYPICAL ADSL/ADSL2+ APPLICATION
Additional definitions for calculating resistor values include:
In a typical ADSL/ADSL2+ application, a differential line driver
is used to take the signal from the analog front end (AFE) and
drive it onto the twisted pair telephone line. Referring to the
typical circuit representation in Figure 18, the differential input
appears at VIN+ and VIN− from the AFE, while the differential
output is transformer coupled to the telephone line at tip and
ring. The common-mode operating point, generally midway
between the supplies, is set through VCOM.
Value
Definition
VOA
Voltage at the amplifier outputs
K
Matching resistance reduction factor
AV
Gain from VIN to transformer primary
Negative feedback factor
β
Positive feedback factor
α
Note: R1 must be calculated before β and α.
R3
VOA =
R4
VIN+
VOA
VP
TIP
Rm
RBIAS
RIN
β=
R2
R2
VP
Rm
RING
VOA
06477-024
VIN–
R4
R3
Figure 18. Typical ADSL/ADSL2+ Application Circuit
In ADSL/ADSL2+ applications, it is common practice to
conserve power by using positive feedback to synthesize the
output resistance, thereby lowering the required ohmic value
of the line matching resistors, Rm. The circuit in Figure 18 is
somewhat unique in that the positive feedback introduced via
R3 has the effect of synthesizing the input resistance as well.
The following definitions and equations can be used to calculate
the resistor values necessary to obtain the desired gain, input
resistance, and output resistance for a given application. For
simplicity, the following calculations assume a lossless
transformer.
R2
VP
RL
AV =
R1
R1 + 2 R2
VLINE
N VIN
α = β (1 − k )
R1 =
2VP R2
VOA − VP
R4 =
RIN (VIN − VP )
2 VIN
R3 =
AV R4 (2 R1 Rm + R1 RL − α R1 RL − 2α R2 RL )
α RL (R1 + 2 R2 )
RBIAS =
α R3 R4
R4 − α (R3 + R4 )
After building the circuit with the closest 1% resistor values,
the actual gain, input resistance, and output resistance can be
verified with the following equations.
The following values are used in the design equations and are
assumed already known or chosen by the designer.
Value
VIN
RIN
N
VLINE
Rm
2 Rm
RL
With the above known quantities and definitions, the remaining
resistors can readily be calculated.
R1
RBIAS
k=
ROUT
1:N
VCOM
VLINE (1 + k )
N
Definition
Differential input voltage
Desired differential input resistance
Transformer turns ratio
Differential output voltage at tip and ring
Each is typically 5% to 15% of the transformer reflected
line impedance
Recommended in the amplifier data sheet
Voltage at the + inputs to the amplifier, approximately
½ VIN (must be less than VIN for positive input resistance)
Transformer reflected line impedance
Rev. A | Page 9 of 12
GAIN (VIN to LINE ) =
RIN =
N
R4  R4
 R4
β (k + 1)1 +
+
−
R3
R
BIAS  R3

2
 2 Rm + RL
1
− AV β
R4
 R4 RL
ROUT =




2 Rm N 2


 R4 R BIAS

R1 + 2R2

1 − 

R4 R BIAS
(
)
R1
R4
R
+
BIAS

 R3 +

R4
+ R BIAS







AD8392A
Data Sheet
0
MULTITONE POWER RATIO
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER 1.9664kHz
Figure 20. MTPR at 1.966 MHz
0
–10
–20
–30
–50
–60
–70
–80
–90
–100
CENTER 646.9kHz
SPAN 10kHz
06477-043
(dBm)
–40
Figure 19. MTPR at 647 kHz
Rev. A | Page 10 of 12
SPAN 10kHz
06477-044
(dBm)
The DMT signal used in ADSL/ADSL2+ systems carries data in
discrete tones or bins, which appear in the frequency domain in
evenly spaced 4.3125 kHz intervals. In applications using this
type of waveform, multitone power ratio (MTPR) is a commonly
used measure of linearity. MTPR is defined as the measured
difference from the peak of one tone that is loaded with data to
the peak of an adjacent tone that is intentionally left empty.
Figure 19 and Figure 20 show the AD8392A MTPR for a 5.5
crest factor waveform for empty bins in the ADSL and extended
ADSL2+ bandwidths.
Data Sheet
AD8392A
OUTLINE DIMENSIONS
9.80
9.70
9.60
3.55
3.50
3.45
15
28
4.50
4.40
4.30
1
3.05
3.00
2.95
EXPOSED
PAD
(Pins Up)
6.40
BSC
14
BOTTOM VIEW
TOP VIEW
1.20 MAX
0.15
0.05
SEATING
PLANE
COPLANARITY
0.10
0.65 BSC
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
8°
0°
0.20
0.09
0.30
0.19
0.75
0.60
0.45
02-23-2012-A
1.05
1.00
0.80
COMPLIANT TO JEDEC STANDARDS MO-153-AET
Figure 21. 28-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP_EP]
(RE-28-1)
Dimensions shown in millimeters
0.30
0.25
0.18
32
25
0.50
BSC
TOP VIEW
0.80
0.75
0.70
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
0.50
0.40
0.30
PIN 1
INDICATOR
1
24
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
112408-A
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 22. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD8392AAREZ
AD8392AAREZ-RL
AD8392AAREZ-R7
AD8392AACPZ-R2
AD8392AACPZ-RL
AD8392AACPZ-R7
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
28-Lead Thin Shrink Small Outline Package (TSSOP_EP)
28-Lead Thin Shrink Small Outline Package (TSSOP_EP)
28-Lead Thin Shrink Small Outline Package (TSSOP_EP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
Z = RoHS Compliant Part.
Rev. A | Page 11 of 12
Package Option
RE-28-1
RE-28-1
RE-28-1
CP-32-7
CP-32-7
CP-32-7
AD8392A
Data Sheet
NOTES
©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06477-0-6/16(A)
Rev. A | Page 12 of 12