TI MSP430F149IPAGR Mixed signal microcontroller Datasheet

 SLAS272F − JULY 2000 − REVISED JUNE 2004
D Low Supply-Voltage Range, 1.8 V . . . 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
D
D
− Active Mode: 280 µA at 1 MHz, 2.2V
− Standby Mode: 1.6 µA
− Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Wake-Up From Standby Mode in less
than 6 µs
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and Autoscan
Feature
16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
D Serial Communication Interface (USART),
D
D
D
Functions as Asynchronous UART or
Synchronous SPI Interface
− Two USARTs (USART0, USART1) —
MSP430x14x(1) Devices
− One USART (USART0) — MSP430x13x
Devices
Family Members Include:
− MSP430F133:
8KB+256B Flash Memory,
256B RAM
− MSP430F135:
16KB+256B Flash Memory,
512B RAM
− MSP430F147, MSP430F1471†:
32KB+256B Flash Memory,
1KB RAM
− MSP430F148, MSP430F1481†:
48KB+256B Flash Memory,
2KB RAM
− MSP430F149, MSP430F1491†:
60KB+256B Flash Memory,
2KB RAM
Available in 64-Pin Quad Flat Pack (QFP)
and 64-pin QFN
For Complete Module Descriptions, See the
MSP430x1xx Family User’s Guide,
Literature Number SLAU049
† The MSP430F14x1 devices are identical to the MSP430F14x
devices with the exception that the ADC12 module is not
implemented.
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 µs.
The MSP430x13x and the MSP430x14x(1) series are microcontroller configurations with two built-in 16-bit
timers, a fast 12-bit A/D converter (not implemented on the MSP430F14x1 devices), one or two universal serial
synchronous/asynchronous communication interfaces (USART), and 48 I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process and transmit the data to a host system. The timers make the configurations ideal for industrial control
applications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardware
multiplier enhances the performance and offers a broad code and hardware-compatible family solution.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000 − 2004, Texas Instruments Incorporated
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AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC 64-PIN QFP
(PM)
−40°C to 85°C
MSP430F133IPM
MSP430F135IPM
MSP430F147IPM
MSP430F1471IPM
MSP430F148IPM
MSP430F1481IPM
MSP430F149IPM
MSP430F1491IPM
PLASTIC 64-PIN QFP
(PAG)
PLASTIC 64-PIN QFN
(RTD)
MSP430F133IPAG
MSP430F135IPAG
MSP430F147IPAG
MSP430F148IPAG
MSP430F149IPAG
MSP430F133IRTD
MSP430F135IRTD
MSP430F147IRTD
MSP430F1471IRTD
MSP430F148IRTD
MSP430F1481IRTD
MSP430F149IRTD
MSP430F1491IRTD
pin designation, MSP430F133, MSP430F135
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/Rosc
P2.6/ADC12CLK
P2.7/TA0
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
DVCC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P5.6/ACLK
P5.5/SMCLK
AVCC
DVSS
AV SS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH
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P5.4/MCLK
P5.3
P5.2
P5.1
P5.0
P4.7/TBCLK
P4.6
P4.5
P4.4
P4.3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7
P3.6
P3.5/URXD0
SLAS272F − JULY 2000 − REVISED JUNE 2004
pin designation, MSP430F147, MSP430F148, MSP430F149
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P5.4/MCLK
P5.3/UCLK1
P5.2/SOMI1
P5.1/SIMO1
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/Rosc
P2.6/ADC12CLK
P2.7/TA0
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
DVCC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P5.6/ACLK
P5.5/SMCLK
AVCC
DVSS
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH
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pin designation, MSP430F1471, MSP430F1481, MSP430F1491
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/Rosc
P2.6
P2.7/TA0
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
DVCC
P6.3
P6.4
P6.5
P6.6
P6.7
Reserved
XIN
XOUT
DVSS
DVSS
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P5.6/ACLK
P5.5/SMCLK
AVCC
DVSS
AVSS
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH
PM, RTD PACKAGE
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P5.4/MCLK
P5.3/UCLK1
P5.2/SOMI1
P5.1/SIMO1
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
SLAS272F − JULY 2000 − REVISED JUNE 2004
functional block diagrams
MSP430x13x
XIN
XOUT
DVCC
DVSS
AVCC
P1
AVSS RST/NMI
P2
8
ROSC
Oscillator
XT2IN
System
Clock
XT2OUT
ACLK
16KB Flash
512B RAM
ADC12
SMCLK
8KB Flash
256B RAM
12-Bit
8 Channels
<10µs Conv.
P3
8
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
P4
8
P5
8
P6
8
I/O Port 3/4
16 I/Os
8
I/O Port 5/6
16 I/Os
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
4
TMS
Watchdog
Timer
TCK
TDI/TCLK
15/16-Bit
TDO/TDI
Timer_B3
Timer_A3
3 CC Reg
Shadow
Reg
3 CC Reg
POR
Comparator
A
USART0
UART Mode
SPI Mode
MSP430x14x
XIN
XOUT
DVCC
DVSS
AVCC
P1
AVSS RST/NMI
8
ROSC
Oscillator
XT2IN
System
Clock
XT2OUT
ACLK
60KB Flash
2KB RAM
ADC12
SMCLK 48KB Flash
2KB RAM
32KB Flash
1KB RAM
12-Bit
8 Channels
<10µs Conv.
P2
P3
8
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
P4
8
P5
8
P6
8
I/O Port 3/4
16 I/Os
8
I/O Port 5/6
16 I/Os
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
4
TMS
TCK
TDI/TCLK
TDO/TDI
Hardware
Multiplier
MPY, MPYS
MAC,MACS
Watchdog
Timer
15/16-Bit
Timer_B7
Timer_A3
7 CC Reg
Shadow
Reg
3 CC Reg
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Comparator
A
USART0
USART1
UART Mode
SPI Mode
UART Mode
SPI Mode
5
SLAS272F − JULY 2000 − REVISED JUNE 2004
functional block diagrams (continued)
MSP430x14x1
XIN
XOUT
DVCC
DVSS
AVCC
P1
AVSS RST/NMI
8
ROSC
Oscillator
XT2IN
System
Clock
XT2OUT
ACLK
60KB Flash
2KB RAM
SMCLK 48KB Flash
2KB RAM
32KB Flash
1KB RAM
P2
P3
8
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
P4
8
P5
8
P6
8
I/O Port 3/4
16 I/Os
8
I/O Port 5/6
16 I/Os
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
4
TMS
TCK
TDI/TCLK
TDO/TDI
6
Hardware
Multiplier
MPY, MPYS
MAC,MACS
Watchdog
Timer
15/16-Bit
Timer_B7
Timer_A3
7 CC Reg
Shadow
Reg
3 CC Reg
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Comparator
A
USART0
USART1
UART Mode
SPI Mode
UART Mode
SPI Mode
SLAS272F − JULY 2000 − REVISED JUNE 2004
Terminal Functions
MSP430x13x, MSP430x14x
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AVCC
AVSS
64
Analog supply voltage, positive terminal. Supplies the analog portion of the analog-to-digital converter.
62
Analog supply voltage, negative terminal. Supplies the analog portion of the analog-to-digital converter.
DVCC
1
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS
63
Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK
12
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
13
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1
14
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
15
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK
16
I/O
General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0
17
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1
18
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/
P2.0/ACLK
20
I/O
General-purpose digital I/O pin/ACLK output
P2.1/TAINCLK
21
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0
22
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive
P2.3/CA0/TA1
23
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
P2.4/CA1/TA2
24
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
P2.5/ROSC
P2.6/ADC12CLK
25
I/O
General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency
26
I/O
General-purpose digital I/O pin/conversion clock – 12-bit ADC
P2.7/TA0
27
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P3.0/STE0
28
I/O
General-purpose digital I/O pin/slave transmit enable – USART0/SPI mode
P3.1/SIMO0
29
I/O
General-purpose digital I/O pin/slave in/master out of USART0/SPI mode
P3.2/SOMI0
30
I/O
General-purpose digital I/O pin/slave out/master in of USART0/SPI mode
P3.3/UCLK0
31
I/O
General-purpose digital I/O/USART0 clock: external input − UART or SPI mode, output – SPI mode
P3.4/UTXD0
32
I/O
General-purpose digital I/O pin/transmit data out – USART0/UART mode
P3.5/URXD0
P3.6/UTXD1†
33
I/O
General-purpose digital I/O pin/receive data in – USART0/UART mode
34
I/O
General-purpose digital I/O pin/transmit data out – USART1/UART mode
P3.7/URXD1†
35
I/O
General-purpose digital I/O pin/receive data in – USART1/UART mode
P4.0/TB0
36
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0A or CCI0B input, compare: Out0 output
P4.1/TB1
37
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1A or CCI1B input, compare: Out1 output
P4.2/TB2
P4.3/TB3†
38
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI2A or CCI2B input, compare: Out2 output
39
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI3A or CCI3B input, compare: Out3 output
P4.4/TB4†
P4.5/TB5†
40
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI4A or CCI4B input, compare: Out4 output
41
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI5A or CCI5B input, compare: Out5 output
P4.6/TB6†
42
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI6A or CCI6B input, compare: Out6 output
P4.7/TBCLK
P5.0/STE1†
43
I/O
General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
44
I/O
General-purpose digital I/O pin/slave transmit enable – USART1/SPI mode
P5.1/SIMO1†
P5.2/SOMI1†
45
I/O
General-purpose digital I/O pin/slave in/master out of USART1/SPI mode
46
I/O
General-purpose digital I/O pin/slave out/master in of USART1/SPI mode
P5.3/UCLK1†
47
I/O
General-purpose digital I/O pin/USART1 clock: external input − UART or SPI mode, output – SPI mode
P5.4/MCLK
48
I/O
General-purpose digital I/O pin/main system clock MCLK output
49
I/O
General-purpose digital I/O pin/submain system clock SMCLK output
P5.5/SMCLK
† 14x devices only
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Terminal Functions (Continued)
MSP430x13x, MSP430x14x (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
P5.6/ACLK
50
I/O
General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUTH
51
I/O
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance − Timer_B7: TB0 to
TB6
P6.0/A0
59
I/O
General-purpose digital I/O pin/analog input a0 – 12-bit ADC
P6.1/A1
60
I/O
General-purpose digital I/O pin/analog input a1 – 12-bit ADC
P6.2/A2
61
I/O
General-purpose digital I/O pin/analog input a2 – 12-bit ADC
P6.3/A3
2
I/O
General-purpose digital I/O pin/analog input a3 – 12-bit ADC
P6.4/A4
3
I/O
General-purpose digital I/O pin/analog input a4 – 12-bit ADC
P6.5/A5
4
I/O
General-purpose digital I/O pin/analog input a5 – 12-bit ADC
P6.6/A6
5
I/O
General-purpose digital I/O pin/analog input a6 – 12-bit ADC
P6.7/A7
6
I/O
General-purpose digital I/O pin/analog input a7 – 12-bit ADC
RST/NMI
58
I
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices).
TCK
57
I
Test clock. TCK is the clock input port for device programming test and bootstrap loader start (in Flash
devices).
TDI/TCLK
55
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI
54
I/O
TMS
56
I
Test mode select. TMS is used as an input port for device programming and test.
VeREF+
VREF+
10
I
Input for an external reference voltage to the ADC
7
O
Output of positive terminal of the reference voltage in the ADC
VREF−/VeREF−
11
I
Negative terminal for the ADC’s reference voltage for both sources, the internal reference voltage, or an
external applied reference voltage
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
O
Output terminal of crystal oscillator XT1
XT2IN
53
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
XT2OUT
52
O
Output terminal of crystal oscillator XT2
QFN Pad
NA
NA
8
Test data output port. TDO/TDI data output or programming data input terminal
QFN package pad connection to DVSS recommended.
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Terminal Functions
MSP430x14x1
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AVCC
AVSS
64
Analog supply voltage, positive terminal.
62
Analog supply voltage, negative terminal.
DVCC
1
Digital supply voltage, positive terminal. Supplies all digital parts.
DVSS
63
Digital supply voltage, negative terminal. Supplies all digital parts.
P1.0/TACLK
12
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
13
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1
14
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
15
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK
16
I/O
General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0
17
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1
18
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK
20
I/O
General-purpose digital I/O pin/ACLK output
P2.1/TAINCLK
21
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0
22
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output/BSL receive
P2.3/CA0/TA1
23
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
P2.4/CA1/TA2
24
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
P2.5/ROSC
P2.6
25
I/O
General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency
26
I/O
General-purpose digital I/O pin
P2.7/TA0
27
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P3.0/STE0
28
I/O
General-purpose digital I/O pin/slave transmit enable – USART0/SPI mode
P3.1/SIMO0
29
I/O
General-purpose digital I/O pin/slave in/master out of USART0/SPI mode
P3.2/SOMI0
30
I/O
General-purpose digital I/O pin/slave out/master in of USART0/SPI mode
P3.3/UCLK0
31
I/O
General-purpose digital I/O/USART0 clock: external input − UART or SPI mode, output – SPI mode
P3.4/UTXD0
32
I/O
General-purpose digital I/O pin/transmit data out – USART0/UART mode
P3.5/URXD0
33
I/O
General-purpose digital I/O pin/receive data in – USART0/UART mode
P3.6/UTXD1
34
I/O
General-purpose digital I/O pin/transmit data out – USART1/UART mode
P3.7/URXD1
35
I/O
General-purpose digital I/O pin/receive data in – USART1/UART mode
P4.0/TB0
36
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0A or CCI0B input, compare: Out0 output
P4.1/TB1
37
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1A or CCI1B input, compare: Out1 output
P4.2/TB2
38
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI2A or CCI2B input, compare: Out2 output
P4.3/TB3
39
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI3A or CCI3B input, compare: Out3 output
P4.4/TB4
40
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI4A or CCI4B input, compare: Out4 output
P4.5/TB5
41
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI5A or CCI5B input, compare: Out5 output
P4.6/TB6
42
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI6A or CCI6B input, compare: Out6 output
P4.7/TBCLK
43
I/O
General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P5.0/STE1
44
I/O
General-purpose digital I/O pin/slave transmit enable – USART1/SPI mode
P5.1/SIMO1
45
I/O
General-purpose digital I/O pin/slave in/master out of USART1/SPI mode
P5.2/SOMI1
46
I/O
General-purpose digital I/O pin/slave out/master in of USART1/SPI mode
P5.3/UCLK1
47
I/O
General-purpose digital I/O pin/USART1 clock: external input − UART or SPI mode, output – SPI mode
P5.4/MCLK
48
I/O
General-purpose digital I/O pin/main system clock MCLK output
P5.5/SMCLK
49
I/O
General-purpose digital I/O pin/submain system clock SMCLK output
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Terminal Functions (Continued)
MSP430x14x1 (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
P5.6/ACLK
50
I/O
General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUTH
51
I/O
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance − Timer_B7: TB0 to
TB6
P6.0
59
I/O
General-purpose digital I/O pin
P6.1
60
I/O
General-purpose digital I/O pin
P6.2
61
I/O
General-purpose digital I/O pin
P6.3
2
I/O
General-purpose digital I/O pin
P6.4
3
I/O
General-purpose digital I/O pin
P6.5
4
I/O
General-purpose digital I/O pin
P6.6
5
I/O
General-purpose digital I/O pin
P6.7
6
I/O
General-purpose digital I/O pin
RST/NMI
58
I
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices).
TCK
57
I
Test clock. TCK is the clock input port for device programming test and bootstrap loader start (in Flash
devices).
TDI/TCLK
55
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI
54
I/O
TMS
56
I
Test mode select. TMS is used as an input port for device programming and test.
DVSS
10
I
Connect to DVSS
Reserved
7
DVSS
11
XIN
XOUT
Test data output port. TDO/TDI data output or programming data input terminal
Reserved, do not connect externally
I
Connect to DVSS
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
9
O
Output terminal of crystal oscillator XT1
XT2IN
53
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
XT2OUT
52
O
Output terminal of crystal oscillator XT2
QFN Pad
NA
NA
10
QFN package pad connection to DVSS recommended.
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in conjunction with seven addressing modes for source
operand and four addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
SYNTAX
EXAMPLE
OPERATION
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
M(EDE) −−> M(TONI)
Absolute
F F
MOV &MEM,&TCDAT
M(MEM) −−> M(TCDAT)
R10
−−> R11
M(2+R5)−−> M(6+R6)
Indirect
F
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) −−> M(Tab+R6)
Indirect
autoincrement
F
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) −−> R11
R10 + 2−−> R10
F
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
#45
−−> M(TONI)
D = destination
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operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
−
All clocks are active
D Low-power mode 0 (LPM0);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
−
12
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External Reset
Watchdog
Flash memory
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 & 4)
OFIFG (see Notes 1 & 4)
ACCVIFG (see Notes 1 & 4)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
Timer_B7 (see Note 5)
TBCCR0 CCIFG (see Note 2)
Maskable
0FFFAh
13
Timer_B7 (see Note 5)
TBCCR1 to 6 CCIFGs,
TBIFG (see Notes 1 & 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog timer
WDTIFG
Maskable
0FFF4h
10
USART0 receive
URXIFG0
Maskable
0FFF2h
9
USART0 transmit
UTXIFG0
Maskable
0FFF0h
8
ADC12 (see Note 6)
ADC12IFG (see Notes 1 & 2)
Maskable
0FFEEh
7
Timer_A3
TACCR0 CCIFG (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 CCIFG,
TACCR2 CCIFG,
TAIFG (see Notes 1 & 2)
Maskable
0FFEAh
5
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 & 2)
Maskable
0FFE8h
4
Maskable
0FFE6h
3
0FFE4h
2
0FFE2h
1
0FFE0h
0, lowest
USART1 receive
URXIFG1
USART1 transmit
UTXIFG1
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7
(see Notes 1 & 2)
Maskable
NOTES: 1.
2.
3.
4.
Multiple source flags
Interrupt flags are located in the module.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
5. Timer_B7 in MSP430x14x(1) family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs. In Timer_B3 there are only interrupt
flags TBCCR0, 1, and 2 CCIFGs and the interrupt-enable bits TBCCTL0, 1, and 2 CCIEs.
6. ADC12 is not implemented on the 14x1 devices.
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special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
7
Address
0h
6
UTXIE0
rw-0
URXIE0
rw-0
5
4
ACCVIE
NMIIE
rw-0
3
2
1
OFIE
rw-0
rw-0
0
WDTIE
rw-0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
Flash access violation interrupt enable
URXIE0:
USART0: UART and SPI receive-interrupt enable
UTXIE0:
USART0: UART and SPI transmit-interrupt enable
7
Address
6
01h
5
4
UTXIE1
URXIE1
rw-0
3
2
1
0
2
1
0
rw-0
URXIE1:
USART1: UART and SPI receive-interrupt enable
UTXIE1:
USART1: UART and SPI transmit-interrupt enable
interrupt flag register 1 and 2
7
Address
02h
6
UTXIFG0
rw-1
5
URXIFG0
3
NMIIFG
rw-0
OFIFG
rw-0
rw-1
WDTIFG
rw-(0)
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
URXIFG0:
USART0: UART and SPI receive flag
UTXIFG0:
USART0: UART and SPI transmit flag
Address
03h
7
6
5
4
UTXIFG1
URXIFG1
rw-1
14
4
3
rw-0
URXIFG1:
USART1: UART and SPI receive flag
UTXIFG1:
USART1: UART and SPI transmit flag
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module enable registers 1 and 2
7
UTXE0
Address
04h
rw-0
6
URXE0
USPIE0
5
4
3
2
1
rw-0
URXE0:
USART0: UART receive enable
UTXE0:
USART0: UART transmit enable
USPIE0:
USART0: SPI (synchronous peripheral interface) transmit and receive enable
Address
0
7
6
05h
5
UTXE1
rw-0
4
URXE1
USPIE1
3
2
1
0
rw-0
URXE1:
USART1: UART receive enable
UTXE1:
USART1: UART transmit enable
USPIE1:
USART1: SPI (synchronous peripheral interface) transmit and receive enable
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset by PUC.
SFR Bit Not Present in Device
Legend: rw:
rw-0:
memory organization
MSP430F133
MSP430F135
MSP430F147
MSP430F1471
MSP430F148
MSP430F1481
MSP430F149
MSP430F1491
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
8KB
0FFFFh − 0FFE0h
0FFFFh − 0E000h
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
48KB
0FFFFh − 0FFE0h
0FFFFh − 04000h
60KB
0FFFFh − 0FFE0h
0FFFFh − 01100h
Information memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
256 Byte
02FFh − 0200h
512 Byte
03FFh − 0200h
1KB
05FFh − 0200h
2KB
09FFh − 0200h
2KB
09FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
PM, PAG & RTD Package Pins
Data Transmit
13 - P1.1
Data Receive
22 - P2.2
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
8 KB
16 KB
32 KB
48 KB
60 KB
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
Segment 1
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
Segment 2
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0E400h
0E3FFh
0C400h
0C3FFh
08400h
083FFh
04400h
043FFh
01400h
013FFh
0E200h
0E1FFh
0C200h
0C1FFh
08200h
081FFh
04200h
041FFh
01200h
011FFh
0E000h
010FFh
0C000h
010FFh
08000h
010FFh
04000h
010FFh
01100h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
01000h
01000h
Segment 0
w/ Interrupt Vectors
Main
Memory
Segment n-1
Segment n
Segment A
Information
Memory
Segment B
16
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number
SLAU049.
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
oscillator and system clock
The clock system in the MSP430x13x and MSP43x14x(1) family of devices is supported by the basic clock
module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator
(DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements
of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source
and stabilizes in less than 6 µs. The basic clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
hardware multiplier (MSP430x14x and MSP430x14x1 Only)
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
USART0
The MSP430x13x and the MSP430x14x(1) have one hardware universal synchronous/asynchronous receive
transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered
transmit and receive channels.
USART1 (MSP430x14x and MSP430x14x1 Only)
The MSP430x14x(1) has a second hardware universal synchronous/asynchronous receive transmit (USART1)
peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4
pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
Operation of USART1 is identical to USART0.
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comparator_A
The primary function of the comparator_A module is to support precision slope analog−to−digital conversions,
battery−voltage supervision, and monitoring of external analog signals.
ADC12 (Not implemented in the MSP430x14x1)
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
Device Input Signal
Module Input Name
12 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
21 - P2.1
TAINCLK
INCLK
13 - P1.1
TA0
CCI0A
22 - P2.2
TA0
CCI0B
DVSS
DVCC
GND
14 - P1.2
15 - P1.3
TA1
VCC
CCI1A
CAOUT (internal)
CCI1B
DVSS
DVCC
GND
TA2
VCC
CCI2A
ACLK (internal)
CCI2B
DVSS
DVCC
GND
Module Block
Module Output Signal
Timer
NA
Output Pin Number
13 - P1.1
17 - P1.5
CCR0
TA0
27 - P2.7
14 - P1.2
18 - P1.6
CCR1
TA1
23 - P2.3
ADC12 (internal)
15 - P1.3
19 - P1.7
CCR2
TA2
24 - P2.4
VCC
timer_B3 (MSP430x13x Only)
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
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timer_B7 (MSP430x14x and MSP430x14x1 Only)
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B3/B7 Signal Connections†
Input Pin Number
Device Input Signal
Module Input Name
43 - P4.7
TBCLK
TBCLK
Module Block
Module Output Signal
Timer
NA
Output Pin Number
ACLK
ACLK
SMCLK
SMCLK
43 - P4.7
TBCLK
INCLK
36 - P4.0
TB0
CCI0A
36 - P4.0
36 - P4.0
TB0
CCI0B
ADC12 (internal)
DVSS
DVCC
GND
37 - P4.1
37 - P4.1
TB1
VCC
CCI1A
TB1
CCI1B
DVSS
DVCC
GND
38 - P4.2
TB2
VCC
CCI2A
38 - P4.2
TB2
CCI2B
DVSS
DVCC
GND
39 - P4.3
39 - P4.3
TB3
VCC
CCI3A
TB3
CCI3B
DVSS
DVCC
GND
40 - P4.4
TB4
VCC
CCI4A
40 - P4.4
TB4
CCI4B
DVSS
DVCC
GND
41 - P4.5
TB5
VCC
CCI5A
41 - P4.5
TB5
CCI5B
DVSS
DVCC
GND
42 - P4.6
TB6
VCC
CCI6A
ACLK (internal)
CCI6B
DVSS
DVCC
GND
CCR0
TB0
37 - P4.1
ADC12 (internal)
CCR1
TB1
38 - P4.2
CCR2
TB2
39 - P4.3
CCR3
TB3
40 - P4.4
CCR4
TB4
41 - P4.5
CCR5
TB5
42 - P4.6
CCR6
TB6
VCC
† Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SLAS272F − JULY 2000 − REVISED JUNE 2004
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog Timer control
WDTCTL
0120h
Timer_B7/
Timer_B3
(see Note 1)
Timer_B interrupt vector
TBIV
011Eh
Timer_B control
TBCTL
0180h
Capture/compare control 0
TBCCTL0
0182h
Capture/compare control 1
TBCCTL1
0184h
Capture/compare control 2
TBCCTL2
0186h
Capture/compare control 3
TBCCTL3
0188h
Capture/compare control 4
TBCCTL4
018Ah
Capture/compare control 5
TBCCTL5
018Ch
Capture/compare control 6
TBCCTL6
018Eh
Timer_B register
TBR
0190h
Capture/compare register 0
TBCCR0
0192h
Capture/compare register 1
TBCCR1
0194h
Capture/compare register 2
TBCCR2
0196h
Capture/compare register 3
TBCCR3
0198h
Capture/compare register 4
TBCCR4
019Ah
Capture/compare register 5
TBCCR5
019Ch
Capture/compare register 6
TBCCR6
019Eh
Timer_A interrupt vector
TAIV
012Eh
Timer_A control
TACTL
0160h
Capture/compare control 0
TACCTL0
0162h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 2
TACCTL2
0166h
Timer_A3
Reserved
0168h
Reserved
016Ah
Reserved
016Ch
Reserved
016Eh
Timer_A register
TAR
0170h
Capture/compare register 0
TACCR0
0172h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 2
TACCR2
0176h
Reserved
0178h
Reserved
017Ah
Reserved
017Ch
Reserved
Hardware
Multiplier
(MSP430x14x and
MSP430x14x1
only)
017Eh
Sum extend
SUMEXT
013Eh
Result high word
RESHI
013Ch
Result low word
RESLO
013Ah
Second operand
OP2
0138h
Multiply signed +accumulate/operand1
MACS
0136h
Multiply+accumulate/operand1
MAC
0134h
Multiply signed/operand1
MPYS
0132h
Multiply unsigned/operand1
MPY
0130h
NOTE 1: Timer_B7 in MSP430x14x(1) family has 7 CCRs, Timer_B3 in MSP430x13x family has 3 CCRs.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
Flash
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
ADC12
Conversion memory 15
(Not implemented in Conversion memory 14
the MSP430x14x1)
Conversion memory 13
ADC12MEM15
015Eh
ADC12MEM14
015Ch
ADC12MEM13
015Ah
Conversion memory 12
ADC12MEM12
0158h
Conversion memory 11
ADC12MEM11
0156h
Conversion memory 10
ADC12MEM10
0154h
Conversion memory 9
ADC12MEM9
0152h
Conversion memory 8
ADC12MEM8
0150h
Conversion memory 7
ADC12MEM7
014Eh
Conversion memory 6
ADC12MEM6
014Ch
Conversion memory 5
ADC12MEM5
014Ah
Conversion memory 4
ADC12MEM4
0148h
Conversion memory 3
ADC12MEM3
0146h
Conversion memory 2
ADC12MEM2
0144h
Conversion memory 1
ADC12MEM1
0142h
Conversion memory 0
ADC12MEM0
0140h
Interrupt-vector-word register
ADC12IV
01A8h
Inerrupt-enable register
ADC12IE
01A6h
Inerrupt-flag register
ADC12IFG
01A4h
Control register 1
ADC12CTL1
01A2h
Control register 0
ADC12CTL0
01A0h
ADC memory-control register15
ADC12MCTL15
08Fh
ADC memory-control register14
ADC12MCTL14
08Eh
ADC memory-control register13
ADC12MCTL13
08Dh
ADC memory-control register12
ADC12MCTL12
08Ch
ADC memory-control register11
ADC12MCTL11
08Bh
ADC memory-control register10
ADC12MCTL10
08Ah
ADC memory-control register9
ADC12MCTL9
089h
ADC memory-control register8
ADC12MCTL8
088h
ADC memory-control register7
ADC12MCTL7
087h
ADC memory-control register6
ADC12MCTL6
086h
ADC memory-control register5
ADC12MCTL5
085h
ADC memory-control register4
ADC12MCTL4
084h
ADC memory-control register3
ADC12MCTL3
083h
ADC memory-control register2
ADC12MCTL2
082h
ADC memory-control register1
ADC12MCTL1
081h
ADC memory-control register0
ADC12MCTL0
080h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SLAS272F − JULY 2000 − REVISED JUNE 2004
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
USART1
(MSP430x14x and
MSP430x14x1 only)
USART0
Comparator_A
Basic Clock
Port P6
Port P5
Port P4
Port P3
Port P2
22
Transmit buffer
U1TXBUF
07Fh
Receive buffer
U1RXBUF
07Eh
Baud rate
U1BR1
07Dh
Baud rate
U1BR0
07Ch
Modulation control
U1MCTL
07Bh
Receive control
U1RCTL
07Ah
Transmit control
U1TCTL
079h
USART control
U1CTL
078h
Transmit buffer
U0TXBUF
077h
Receive buffer
U0RXBUF
076h
Baud rate
U0BR1
075h
Baud rate
U0BR0
074h
Modulation control
U0MCTL
073h
Receive control
U0RCTL
072h
Transmit control
U0TCTL
071h
USART control
U0CTL
070h
Comparator_A port disable
CAPD
05Bh
Comparator_A control2
CACTL2
05Ah
Comparator_A control1
CACTL1
059h
Basic clock system control2
BCSCTL2
058h
Basic clock system control1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P1
Special Functions
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag2
IFG2
003h
SFR interrupt flag1
IFG1
002h
SFR interrupt enable2
IE2
001h
SFR interrupt enable1
IE1
000h
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 4.1 V
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SLAS272F − JULY 2000 − REVISED JUNE 2004
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNITS
Supply voltage during program execution, VCC (AVCC = DVCC = VCC)
MSP430F13x,
MSP430F14x(1)
1.8
3.6
V
Supply voltage during flash memory programming, VCC
(AVCC = DVCC = VCC)
MSP430F13x,
MSP430F14x(1)
2.7
3.6
V
0.0
0.0
V
−40
85
°C
450
8000
kHz
1000
8000
kHz
450
8000
1000
8000
DC
4.15
DC
8
Supply voltage, VSS (AVSS = DVSS = VSS)
MSP430x13x
MSP430x14x(1)
Operating free-air temperature range, TA
LFXT1 crystal frequency, f(LFXT1)
(see Notes 1 and 2)
LF selected, XTS=0
Watch crystal
XT1 selected, XTS=1
Ceramic resonator
XT1 selected, XTS=1
Crystal
Ceramic resonator
XT2 crystal frequency, f(XT2)
Crystal
VCC = 1.8 V
VCC = 3.6 V
Processor frequency (signal MCLK), f(System)
32768
Hz
kHz
MHz
NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1MΩ resistor from XOUT to VSS is recommended when VCC <
2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15MHz at VCC ≥ 2.2 V. In XT1 mode,
the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8MHz at VCC ≥ 2.8 V.
2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f (MHz)
8.0 MHz
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Supply voltage range,
’F13x/’F14x(1), during
program execution
4.15 MHz
1.8 V
2.7 V 3 V
Supply Voltage − V
Supply voltage range, ’F13x/’F14x(1),
during flash memory programming
3.6 V
Figure 1. Frequency vs Supply Voltage, MSP430F13x or MSP430F14x(1)
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
PARAMETER
TEST CONDITIONS
NOM
MAX
VCC = 2.2 V
280
350
VCC = 3 V
420
560
VCC = 2.2 V
2.5
7
9
20
VCC = 2.2 V
VCC = 3 V
32
45
55
70
VCC = 2.2 V
11
14
VCC = 3 V
17
22
0.8
1.5
0.9
1.5
TA = 85°C
TA = −40°C
1.6
2.8
1.8
2.2
TA = 25°C
TA = 85°C
1.6
1.9
2.3
3.9
0.1
0.5
0.1
0.5
0.8
2.5
0.1
0.5
0.1
0.5
0.8
2.5
Active mode, (see Note 1)
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
XTS=0, SELM=(0,1)
TA = −40°C to 85°C
Active mode, (see Note 1)
f(MCLK) = f(SMCLK) = 4 096 Hz,
f(ACLK) = 4,096 Hz
XTS=0, SELM=(0,1)
XTS=0, SELM=3
TA = −40°C to 85°C
I(LPM0)
Low-power mode, (LPM0)
(see Note 1)
TA = −40°C to 85°C
I(LPM2)
Low-power mode, (LPM2),
f(MCLK) = f (SMCLK) = 0 MHz,
f(ACLK) = 32.768 Hz, SCG0 = 0
TA = −40°C to 85°C
I(AM)
I(AM)
I(LPM3)
Low-power mode, (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 1 (see Note 2)
TA = −40°C
TA = 25°C
I(LPM4)
Low-power mode, (LPM4)
f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz, SCG0 = 1
µA
A
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
UNIT
A
µA
VCC = 3 V
TA = −40°C
TA = 25°C
MIN
VCC = 3 V
A
µA
µA
A
µA
µA
µA
µA
NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. Timer_B is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current
consumption in LPM2 and LPM3 are measured with ACLK selected.
Current consumption of active mode versus system frequency, F-version
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage, F-version
I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT−
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ − VIT−)
MIN
TYP
MAX
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
1.1
1.5
1.5
1.9
0.4
0.9
VCC = 3 V
VCC = 2.2 V
0.90
1.3
0.3
1.1
0.5
1
VCC = 3 V
UNIT
V
V
V
standard inputs − RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
VIL
VIH
TEST CONDITIONS
Low-level input voltage
VCC = 2.2 V / 3 V
High-level input voltage
MIN
TYP
VSS
0.8×VCC
MAX
VSS+0.6
VCC
UNIT
V
V
inputs Px.x, TAx, TBx
PARAMETER
t(int)
TEST CONDITIONS
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
TA0, TA1, TA2
t(cap)
f(TAext)
f(TBext)
Timer_A, Timer_B capture
timing
Timer_A, Timer_B clock
frequency externally applied
to pin
TB0, TB1, TB2, TB3, TB4, TB5, TB6 (see
Note 2)
TACLK, TBCLK, INCLK: t(H) = t(L)
VCC
2.2 V/3 V
MIN
TYP
MAX
1.5
2.2 V
62
3V
50
2.2 V
62
3V
50
UNIT
cycle
ns
ns
2.2 V
8
3V
10
MHz
f(TAint)
2.2 V
8
Timer_A, Timer_B clock
SMCLK or ACLK signal selected
MHz
frequency
f(TBint)
3V
10
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. Seven capture/compare registers in ’x14x(1) and three capture/compare registers in ’x13x.
leakage current (see Note 1)
PARAMETER
Ilkg(P1.x)
Ilkg(P2.x)
Leakage
current (see
Note 1)
TEST CONDITIONS
Port P1
V(P1.x) (see Note 2)
V(P2.3) V(P2.4) (see Note 2)
MIN
TYP
MAX
VCC = 2.2 V/3 V
Port P2
±50
Ilkg(P6.x)
Port P6 V(P6.x) (see Note 2)
±50
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
±50
nA
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
IOH(max) = −1 mA,
IOH(max) = −6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOH(max) = −1 mA,
IOH(max) = −6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
See Note 2
See Note 2
TYP
MAX
VCC−0.25
VCC−0.6
VCC
VCC
VCC−0.25
VCC−0.6
VCC
VCC
VSS
VSS
VSS+0.25
VSS+0.6
VSS
VSS
VSS+0.25
VSS+0.6
See Note 2
See Note 2
UNIT
V
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±6 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±24 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER
fTAx
fACLK,
fMCLK,
fSMCLK
TEST CONDITIONS
TA0..2, TB0−TB6,
Internal clock source, SMCLK signal
applied (see Note 1)
CL = 20 pF
TYP
DC
MAX
UNIT
fSystem
MHz
P5.6/ACLK, P5.4/MCLK, P5.5/SMCLK
CL = 20 pF
fSystem
P2.0/ACLK
CL = 20 pF,
VCC = 2.2 V / 3 V
tXdc
MIN
Duty cycle of output frequency,
P1.4/SMCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
fACLK = fLFXT1 = fXT1
fACLK = fLFXT1 = fLF
fACLK = fLFXT1/n
fSMCLK = fLFXT1 = fXT1
fSMCLK = fLFXT1 = fLF
40%
60%
30%
70%
50%
40%
60%
35%
65%
fSMCLK = fLFXT1/n
50%−
15 ns
50%
50%−
15 ns
fSMCLK = fDCOCLK
50%−
15 ns
50%
50%−
15 ns
NOTE 1: The limits of the system clock MCLK has to be met; the system (MCLK) frequency should not exceed the limits. MCLK and SMCLK
frequencies can be different.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
25
TA = 25°C
VCC = 2.2 V
P2.7
14
12
I OL − Low-Level Output Current − mA
I OL − Low-Level Output Current − mA
16
TA = 85°C
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P2.7
20
TA = 85°C
15
10
5
0
0.0
2.5
TA = 25°C
0.5
VOL − Low-Level Output Voltage − V
1.0
Figure 2
2.5
3.0
3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
0
VCC = 2.2 V
P2.7
I OH − High-Level Output Current − mA
I OH − High-Level Output Current − mA
2.0
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−2
1.5
VOL − Low-Level Output Voltage − V
−4
−6
−8
−10
TA = 85°C
−12
VCC = 3 V
P2.7
−5
−10
−15
−20
TA = 85°C
−25
TA = 25°C
TA = 25°C
−14
0.0
0.5
1.0
1.5
2.0
2.5
−30
0.0
VOH − High-Level Output Voltage − V
1.0
1.5
Figure 5
POST OFFICE BOX 655303
2.0
2.5
3.0
VOH − High-Level Output Voltage − V
Figure 4
28
0.5
• DALLAS, TEXAS 75265
3.5
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
TYP
f = 1 MHz
t(LPM3)
f = 2 MHz
Delay time
MAX
UNIT
6
6
VCC = 2.2 V/3 V
f = 3 MHz
µs
6
RAM
PARAMETER
TEST CONDITIONS
VRAMh
CPU HALTED (see Note 1)
MIN
TYP
MAX
1.6
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
TYP
MAX
VCC = 2.2 V
VCC = 3 V
MIN
25
40
45
60
I(DD)
CAON=1, CARSEL=0, CAREF=0
CAON=1, CARSEL=0,
CAREF=1/2/3, no load at
P2.3/CA0/TA1 and P2.4/CA1/TA2
VCC = 2.2 V
30
50
I(Refladder/Refdiode)
VCC = 3 V
45
71
CAON =1
VCC = 2.2 V/3 V
0
PCA0=1, CARSEL=1, CAREF=1,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
VCC = 2.2 V/3 V
0.23
0.24
0.25
PCA0=1, CARSEL=1, CAREF=2,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
VCC = 2.2 V/3 V
0.47
0.48
0.5
PCA0=1, CARSEL=1, CAREF=3,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2 TA = 85°C
VCC = 2.2 V
390
480
540
VCC = 3 V
400
490
550
V(IC)
V(Ref025)
V(Ref050)
Common-mode input
voltage
Voltage @ 0.25 V
V
node
CC
Voltage @ 0.5V
V
CC
CC
CC
node
VCC−1
UNIT
µA
µA
V
V(RefVT)
(see Figure 6)
V(offset)
Vhys
Offset voltage
See Note 2
30
mV
CAON=1
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
−30
Input hysteresis
0
0.7
1.4
mV
TA = 25
25°C,
C, Overdrive 10 mV,
Without filter: CAF=0
VCC = 2.2 V
VCC = 3 V
130
210
300
80
150
240
TA = 25
25°C,
C, Overdrive 10 mV,
With filter: CAF=1
VCC = 2.2 V
VCC = 3 V
1.4
1.9
3.4
0.9
1.5
2.6
25°C,
TA = 25
C, Overdrive 10 mV,
Without filter: CAF=0
VCC = 2.2 V
VCC = 3 V
130
210
300
80
150
240
TA = 25
25°C,
C, Overdrive 10 mV,
With filter: CAF=1
VCC = 2.2 V
VCC = 3 V
1.4
1.9
3.4
0.9
1.5
2.6
t(response LH)
t(response HL)
mV
ns
µs
ns
µs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
650
650
VCC = 2.2 V
V(REFVT) − Reference Volts −mV
V(REFVT) − Reference Volts −mV
VCC = 3 V
600
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
600
Typical
550
500
450
400
−45
95
−25
−5
15
35
55
TA − Free-Air Temperature − °C
0 V VCC
1
CAF
CAON
Low Pass Filter
V+
V−
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 8. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V−
400 mV
V+
t(response)
Figure 9. Overdrive Definition
30
95
Figure 7. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 6. V(RefVT) vs Temperature, VCC = 3 V
0
75
TA − Free-Air Temperature − °C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
PUC/POR
PARAMETER
TEST CONDITIONS
t(POR_Delay)
Internal time delay to release POR
VPOR
VCC threshold at which POR
release delay time begins
(see Note 1)
TA = −40°C
TA = 25°C
VCC threshold required to
generate a POR (see Note 2)
VCC |dV/dt| ≥ 1V/ms
V(min)
MIN
VCC = 2.2 V/3 V
TA = 85°C
TYP
MAX
UNIT
150
250
µs
1.4
1.8
V
1.1
1.5
V
0.8
1.2
V
0.2
V
t(reset)
RST/NMI low time for PUC/POR
Reset is accepted internally
2
µs
NOTES: 1. VCC rise time dV/dt ≥ 1V/ms.
2. When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less
than −1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms.
V
VCC
V
POR
No POR
POR
V
(min)
POR
t
Figure 10. Power-On Reset (POR) vs Supply Voltage
2
1.8
1.8
1.5
V POR − V
1.6
1.4
1.2
1.4
1.2
1
1.2
0.8
0.8
0.6
0.4
25°C
0.2
0
−40
−20
0
20
40
60
80
TA − Temperature − °C
Figure 11. VPOR vs Temperature
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO (see Note 1)
PARAMETER
f(DCO03)
f(DCO13)
f(DCO23)
f(DCO33)
f(DCO43)
f(DCO53)
f(DCO63)
f(DCO73)
TEST CONDITIONS
MIN
Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
MAX
UNIT
VCC = 2.2 V
VCC = 3 V
0.08
0.12
0.15
0.08
0.13
0.16
VCC = 2.2 V
VCC = 3 V
0.14
0.19
0.23
0.14
0.18
0.22
VCC = 2.2 V
VCC = 3 V
0.22
0.30
0.36
0.22
0.28
0.34
VCC = 2.2 V
VCC = 3 V
0.37
0.49
0.59
0.37
0.47
0.56
VCC = 2.2 V
VCC = 3 V
0.61
0.77
0.93
0.61
0.75
0.90
VCC = 2.2 V
VCC = 3 V
1
1.2
1.5
1
1.3
1.5
VCC = 2.2 V
VCC = 3 V
Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
NOM
1.6
1.9
2.2
1.69
2.0
2.29
2.4
2.9
3.4
2.7
3.2
3.65
fDCO40
× 1.7
fDCO40
× 2.1
fDCO40
× 2.5
VCC = 2.2 V
VCC = 3 V
f(DCO47)
Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C
VCC = 2.2 V/3 V
f(DCO77)
Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C
VCC = 2.2 V
VCC = 3 V
S(Rsel)
S(DCO)
SR = fRsel+1 / fRsel
SDCO = fDCO+1 / fDCO
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
Dt
Temperature drift, Rsel = 4, DCO = 3, MOD = 0
(see Note 2)
VCC = 2.2 V
VCC = 3 V
DV
Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0
(see Note 2)
VCC = 2.2 V/3 V
4
4.5
4.9
4.4
4.9
5.4
1.35
1.65
2
1.07
1.12
1.16
−0.31
−0.36
−0.40
−0.33
−0.38
−0.43
0
5
10
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%/°C
%/V
Frequency Variance
NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f(System).
2. This parameter is not production tested.
Max
f DCO_7
Min
Max
f DCO_0
Min
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
1
f DCOCLK
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
2.2
3
VCC − V
0
1
Figure 12. DCO Characteristics
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2
3
4
5
6
7
DCO
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
main DCO characteristics
D Individual devices have a minimum and maximum operation frequency. The specified parameters for
fDCOx0 to fDCOx7 are valid for all devices.
D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps with Rsel1, ... Rsel6 overlaps with
Rsel7.
D DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO.
D Modulation control bits MOD0 to MOD4 select how often fDCO+1 is used within the period of 32 DCOCLK
cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to
f(DCO) × (2MOD/32 ).
DCO when using ROSC (see Note 1)
PARAMETER
TEST CONDITIONS
fDCO, DCO output frequency
Rsel = 4, DCO = 3, MOD = 0, DCOR = 1,
TA = 25°C
Dt, Temperature drift
Rsel = 4, DCO = 3, MOD = 0, DCOR = 1
VCC
2.2 V
MIN
NOM
MAX
1.8±15%
3V
UNIT
MHz
1.95±15%
MHz
±0.1
%/°C
10
%/V
2.2 V/3 V
Dv, Drift with VCC variation
Rsel = 4, DCO = 3, MOD = 0, DCOR = 1
2.2 V/3 V
NOTES: 1. ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C.
crystal oscillator, LFXT1 oscillator (see Note 1)
PARAMETER
CXIN
CXOUT
VIL
VIH
Integrated input capacitance
Integrated output capacitance
Input levels at XIN
TEST CONDITIONS
MIN
NOM
XTS=0; LF oscillator selected
VCC = 2.2 V/3 V
XTS=1; XT1 oscillator selected
VCC = 2.2 V/3 V
UNIT
12
pF
2
XTS=0; LF oscillator selected
VCC = 2.2 V/3 V
12
pF
XTS=1; XT1 oscillator selected
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V (see Note 2)
MAX
2
VSS
0.8 × VCC
0.2 × VCC
V
VCC
V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
CXT2IN
Input capacitance
CXT2OUT
Output capacitance
VIL
VIH
Input levels at XT2IN
TEST CONDITIONS
MIN
NOM
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
MAX
2
pF
2
VCC = 2.2 V/3 V (see Note 2)
VSS
0.8 × VCC
UNIT
pF
0.2 × VCC
V
VCC
V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0, USART1 (see Note 1)
PARAMETER
t(τ)
( )
USART0/1: deglitch time
TEST CONDITIONS
VCC = 2.2 V
VCC = 3 V
MIN
NOM
MAX
200
430
800
150
280
500
UNIT
ns
NOTE 1: The signal applied to the USART0/1 receive signal/terminal (URXD0/1) should meet the timing requirements of t(τ) to ensure that the
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0/1 line.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
AVCC
Analog supply voltage
AVCC and DVCC are connected together
AVSS and DVSS are connected together
V(AVSS) = V(DVSS) = 0 V
V(P6.x/Ax)
Analog input voltage
range (see Note 2)
All P6.0/A0 to P6.7/A7 terminals. Analog inputs
selected in ADC12MCTLx register and P6Sel.x=1
0 ≤ x ≤ 7; V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC)
IADC12
Operating supply current
into AVCC terminal
(see Note 3)
fADC12CLK = 5.0 MHz
ADC12ON = 1, REFON = 0
SHT0=0, SHT1=0, ADC12DIV=0
Operating supply current
into AVCC terminal
(see Note 4)
IREF+
CI †
Input capacitance
fADC12CLK = 5.0 MHz
ADC12ON = 0,
REFON = 1, REF2_5V = 1
fADC12CLK = 5.0 MHz
ADC12ON = 0,
REFON = 1, REF2_5V = 0
Only one terminal can be selected
at one time, P6.x/Ax
NOM
MAX
UNIT
2.2
3.6
V
0
VAVCC
V
2.2 V
0.65
1.3
3V
0.8
1.6
3V
0.5
0.8
2.2 V
0.5
0.8
3V
0.5
0.8
mA
mA
mA
2.2 V
40
pF
RI†
Input MUX ON resistance 0V ≤ VAx ≤ VAVCC
3V
2000
Ω
† Not production tested, limits verified by design
NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results.
3. The internal reference supply current is not included in current consumption parameter IADC12.
4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VeREF+
Positive external
reference voltage input
VeREF+ > VREF−/VeREF− (see Note 2)
1.4
VAVCC
V
VREF− /VeREF−
Negative external
reference voltage input
VeREF+ > VREF−/VeREF− (see Note 3)
0
1.2
V
(VeREF+ −
VREF−/VeREF−)
Differential external
reference voltage input
VeREF+ > VREF−/VeREF− (see Note 4)
1.4
VAVCC
V
IVeREF+
IVREF−/VeREF−
Static input current
0V ≤VeREF+ ≤ VAVCC
±1
µA
2.2 V/3 V
Static input current
0V ≤ VeREF− ≤ VAVCC
2.2 V/3 V
±1
µA
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER
Positive built-in reference
voltage output
VREF+
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
active
IVREF+
Load current out of VREF+
terminal
Load-current regulation
VREF+ terminal
IL(VREF)+ †
TEST CONDITIONS
REF2_5V = 1 for 2.5 V
IVREF+ ≤ IVREF+max
3V
REF2_5V = 0 for 1.5 V
IVREF+ ≤ IVREF+max
2.2 V/3 V
MIN
NOM
MAX
2.4
2.5
2.6
1.44
1.5
1.56
UNIT
V
REF2_5V = 0, IVREF+ ≤ 1mA
2.2
REF2_5V = 1, IVREF+ ≤ 0.5mA
V
VREF+ + 0.15
REF2_5V = 1, IVREF+ ≤ 1mA
VREF+ + 0.15
2.2 V
0.01
−0.5
mA
3V
−1
2.2 V
±2
3V
±2
IVREF+ = 500 µA ± 100 µA
Analog input voltage ~1.25 V;
REF2_5V = 1
3V
±2
LSB
20
ns
IVREF+ = 500 µA +/− 100 µA
Analog input voltage ~0.75 V;
REF2_5V = 0
IDL(VREF) +‡
Load current regulation
VREF+ terminal
IVREF+ =100 µA → 900 µA,
CVREF+=5 µF, ax ~0.5 x VREF+
Error of conversion result ≤ 1 LSB
3V
CVREF+
Capacitance at pin VREF+
(see Note 1)
REFON =1,
0 mA ≤ IVREF+ ≤ IVREF+max
2.2 V/3 V
TREF+†
Temperature coefficient of
built-in reference
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA
2.2 V/3 V
tREFON†
Settle time of internal
reference voltage (see
Figure 13 and Note 2)
IVREF+ = 0.5 mA, CVREF+ = 10 µF,
VREF+ = 1.5 V, VAVCC = 2.2 V
5
LSB
µF
10
±100
ppm/°C
17
ms
† Not production tested, limits characterized
‡ Not production tested, limits verified by design
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10 µF tantalum and 100 nF ceramic.
NOTES: 2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
100 µF
tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in µF
10 µF
1 µF
0
1 ms
10 ms
100 ms
tREFON
Figure 13. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
SLAS272F − JULY 2000 − REVISED JUNE 2004
DVCC
From
Power
Supply
+
−
10 µ F
DVSS
100 nF
AVCC
+
−
10 µ F
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
AVSS
10 µ F
VREF+ or VeREF+
100 nF
VREF−/VeREF−
+
−
10 µ F
MSP430F14x
100 nF
+
−
Apply
External
Reference
MSP430F13x
100 nF
Figure 14. Supply Voltage and Reference Voltage Design VREF−/VeREF− External Supply
From
Power
Supply
DVCC
+
−
10 µ F
DVSS
100 nF
AVCC
+
−
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
10 µ F
AVSS
MSP430F14x
100 nF
VREF+ or VeREF+
+
−
10 µ F
MSP430F13x
100 nF
Reference Is Internally
Switched to AVSS
VREF−/VeREF−
Figure 15. Supply Voltage and Reference Voltage Design VREF−/VeREF− = AVSS, Internally Connected
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
fADC12CLK
fADC12OSC
Internal ADC12
oscillator
MIN
NOM
5
MAX
UNIT
6.3
MHz
For specified performance of ADC12
linearity parameters
2.2V/
3V
0.45
ADC12DIV=0,
fADC12CLK=fADC12OSC
2.2 V/
3V
3.7
6.3
MHz
CVREF+ ≥ 5 µF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
2.2 V/
3V
2.06
3.51
µs
tCONVERT
Conversion time
tADC12ON‡
Turn on settling time of
the ADC
(see Note 1)
tSample‡
Sampling time
RS = 400 Ω, RI = 1000 Ω,
CI = 30 pF
τ = [RS + RI] x CI;(see Note 2)
External fADC12CLK from ACLK, MCLK or SMCLK:
ADC12SSEL ≠ 0
13×ADC12DIV×
1/fADC12CLK
µs
100
3V
1220
2.2 V
1400
ns
ns
† Not production tested, limits characterized
‡ Not production tested, limits verified by design
NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC, linearity parameters
PARAMETER
EI
Integral linearity error
ED
Differential linearity
error
EO
Offset error
EG
Gain error
ET
Total unadjusted
error
TEST CONDITIONS
1.4 V ≤ (VeREF+ − VREF−/VeREF−) min ≤ 1.6 V
1.6 V < (VeREF+ − VREF−/VeREF−) min ≤ [V(AVCC)]
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
NOM
MAX
±2
UNIT
2.2 V/3 V
±1.7
LSB
2.2 V/3 V
±1
LSB
2.2 V/3 V
±2
±4
LSB
2.2 V/3 V
±1.1
±2
LSB
2.2 V/3 V
±2
±5
LSB
37
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in VMID
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
REFON = 0, INCH = 0Ah,
ADC12ON=NA, TA = 25_C
2.2 V
40
120
3V
60
160
VSENSOR†
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V
986
986±5%
3V
986
986±5%
TCSENSOR†
2.2 V
3.55
3.55±3%
ADC12ON = 1, INCH = 0Ah
3V
3.55
3.55±3%
ISENSOR
Operating supply current into
AVCC terminal (see Note 1)
2.2 V
30
3V
30
tSENSOR(sample)†
Sample time required if channel
10 is selected (see Note 2)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at channel 11
(see Note 3)
ADC12ON = 1, INCH = 0Bh
1.1
1.1±0.04
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID is ~0.5 x VAVCC
2.2 V
VMID
3V
1.5
1.50±0.04
tVMID(sample)
Sample time required if channel
11 is selected (see Note 4)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
UNIT
µA
A
mV
mV/°C
µss
2.2 V
NA
3V
NA
A
µA
V
ns
† Not production tested, limits characterized
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
is high). Therefore it includes the constant current through the sensor and the reference.
2. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
3. No additional current is needed. The VMID is used during sampling.
4. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Flash Memory
TEST
CONDITIONS
PARAMETER
VCC(PGM/
ERASE)
VCC
MIN
NOM
MAX
UNIT
Program and Erase supply voltage
2.7
3.6
V
fFTG
IPGM
Flash Timing Generator frequency
257
476
kHz
Supply current from DVCC during program
2.7 V/ 3.6 V
3
5
mA
IERASE
tCPT
Supply current from DVCC during erase
2.7 V/ 3.6 V
3
7
mA
Cumulative program time
see Note 1
2.7 V/ 3.6 V
4
ms
tCMErase
Cumulative mass erase time
see Note 2
2.7 V/ 3.6 V
Program/Erase endurance
TJ = 25°C
200
104
ms
105
tRetention
Data retention duration
tWord
tBlock, 0
Word or byte program time
Block program time for 1st byte or word
tBlock, 1-63
tBlock, End
Block program time for each additional byte or word
tMass Erase
tSeg Erase
Mass erase time
5297
Segment erase time
4819
Block program end-sequence wait time
cycles
100
years
35
30
21
see Note 3
tFTG
6
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
RInternal
Internal pull-up resistance on TMS, TCK, TDI/TCLK
see Note 2
VCC
MIN
2.2 V
0
NOM
MAX
UNIT
5
MHz
3V
0
10
MHz
2.2 V/ 3 V
25
60
90
kΩ
MIN
NOM
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC(FB)
VFB
Supply voltage during fuse-blow condition
IFB
tFB
Supply current into TDI/TCLK during fuse blow
TA = 25°C
Voltage level on TDI/TCLK for fuse-blow: F versions
VCC
2.5
6
Time to blow fuse
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic
port P1, P1.0 to P1.7, input/output with Schmitt-trigger
P1SEL.x
0
P1DIR.x
Direction Control
From Module
1
Pad Logic
P1.0/TACLK ..
0
P1OUT.x
Module X OUT
1
P1.7/TA2
P1IN.x
EN
Module X IN
D
P1IRQ.x
P1IE.x
Q
P1IFG.x
EN
Set
Interrupt
Flag
Interrupt
Edge
Select
P1IES.x
P1SEL.x
PnSel.x
PnDIR.x
Dir. CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
DVSS
P1IN.0
P1IE.0
P1IFG.0
P1IES.0
P1IN.1
TACLK†
CCI0A†
P1IE.1
P1IFG.1
P1IES.1
P1IE.2
P1IFG.2
P1IES.2
P1Sel.1
P1DIR.1
P1DIR.1
P1OUT.1
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
Out0 signal†
Out1 signal†
P1Sel.3
P1DIR.3
P1DIR.3
P1OUT.3
Out2 signal†
P1IN.3
CCI1A†
CCI2A†
P1IE.3
P1IFG.3
P1IES.3
P1Sel.4
P1DIR.4
P1DIR.4
P1OUT.4
SMCLK
P1IN.4
unused
P1IE.4
P1IFG.4
P1IES.4
P1Sel.5
P1DIR.5
P1DIR.5
P1OUT.5
P1IN.5
unused
P1IE.5
P1IFG.5
P1IES.5
P1Sel.6
P1DIR.6
P1DIR.6
P1OUT.6
Out0 signal†
Out1 signal†
P1IN.6
unused
P1IE.6
P1IFG.6
P1IES.6
P1Sel.7
P1DIR.7
P1DIR.7
P1OUT.7
Out2 signal†
P1IN.7
unused
P1IE.7
P1IFG.7
P1IES.7
P1IN.2
† Signal from or to Timer_A
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-trigger
P2SEL.x
0
P2DIR.x
Direction Control
From Module
0: Input
1: Output
1
0
P2OUT.x
Module X OUT
1
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
Pad Logic
P2.6/ADC12CLK
P2.7/TA0
P2IN.x
EN
Module X IN
P2IRQ.x
Bus Keeper
D
P2IE.x
P2IFG.x
Set
Interrupt
Flag
CAPD.X
Interrupt
Edge
Select
EN
Q
P2IES.x
P2SEL.x
x: Bit Identifier 0 to 2, 6, and 7 for Port P2
PnSel.x
PnDIR.x
Dir. CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
ACLK
P2IN.0
P2IE.0
P2IFG.0
P2IES.0
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
P2IN.1
P2IE.1
P2IFG.1
P2IES.1
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
DVSS
CAOUT†
unused
INCLK‡
P2IN.2
CCI0B‡
P2IE.2
P2IFG.2
P2IES.2
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
ADC12CLK¶
Out0 signal§
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
† Signal from Comparator_A
‡ Signal to Timer_A
§ Signal from Timer_A
¶ ADC12CLK signal is output of the 12-bit ADC module
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2SEL.3
0: Input
1: Output
0
P2DIR.3
Direction Control
From Module
1
Pad Logic
P2.3/CA0/TA1
0
P2OUT.3
Module X OUT
1
P2IN.3
EN
Module X IN
Bus Keeper
D
P2IRQ.3
P2IE.3
P2IFG.3
EN
Set
Q
Interrupt
Flag
Interrupt
Edge
Select
CAPD.3
Comparator_A
CAEX
P2CA
P2IES.3
P2SEL.3
CAREF
CAF
+
CCI1B
To Timer_A3
−
P2SEL.4
P2IES.4
Interrupt
Flag
P2IFG.4
P2IRQ.4
Set
EN
Q
P2IE.4
CAREF
Reference Block
Edge
Select
Interrupt
CAPD.4
D
Module X IN
Bus Keeper
EN
P2IN.4
Module X OUT
P2OUT.4
From Module
Direction Control
P2DIR.4
1
0
1
P2.4/CA1/TA2
Pad Logic
1: Output
0: Input
0
P2SEL.4
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
P2IN.3
unused
P2IE.3
P2IFG.3
P2IES.3
P2Sel.4
P2DIR.4
† Signal from Timer_A
P2DIR.4
P2OUT.4
Out1 signal†
Out2 signal†
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.5, input/output with Schmitt-trigger and Rosc function for the basic clock module
0: Input
1: Output
P2SEL.5
0
P2DIR.5
Direction Control
From Module
Pad Logic
1
P2.5/Rosc
0
P2OUT.5
Module X OUT
1
Bus Keeper
P2IN.5
EN
Module X IN
P2IRQ.5
D
P2IE.5
Q
P2IFG.5
EN
Set
Interrupt
Flag
VCC
Edge
Select
Interrupt
Internal to
Basic Clock
Module
0
1
to
P2IES.5
P2SEL.5
DCOR
DC Generator
CAPD.5
DCOR: Control Bit From Basic Clock Module
If it Is Set, P2.5 Is Disconnected From P2.5 Pad
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.5
P2DIR.5
P2DIR.5
P2OUT.5
DVSS
P2IN.5
unused
P2IE.5
P2IFG.5
P2IES.5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
Pad Logic
P3OUT.x
Module X OUT
0
P3.0/STE0
1
P3.4/UTXD0
P3.5/URXD0
P3.6/UTXD1‡
P3.7/URXD1¶
P3IN.x
EN
D
Module X IN
x: Bit Identifier, 0 and 4 to 7 for Port P3
PnSel.x
PnDIR.x
P3Sel.0
P3DIR.0
P3Sel.4
P3DIR.4
P3Sel.5
P3DIR.5
P3Sel.6
P3DIR.6
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
DVSS
DVCC
P3OUT.0
DVSS
UTXD0†
P3IN.0
STE0
P3IN.4
DVSS
DVCC
P3OUT.5
DVSS
UTXD1‡
P3IN.5
Unused
URXD0§
DVSS
P3IN.7
P3OUT.4
P3OUT.6
P3Sel.7
P3DIR.7
DVSS
P3OUT.7
† Output from USART0 module
‡ Output from USART1 module in x14x(1) configuration, DVSS in x13x configuration
§ Input to USART0 module
¶ Input to USART1 module in x14x(1) configuration, unused in x13x configuration
44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P3IN.6
Unused
URXD1¶
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.1, input/output with Schmitt-trigger
P3SEL.1
SYNC
MM
STC
STE
0
P3DIR.1
0: Input
1: Output
1
DCM_SIMO
Pad Logic
P3.1/SIMO0
0
P3OUT1
(SI)MO0
From USART0
1
P3IN.1
EN
SI(MO)0
To USART0
D
port P3, P3.2, input/output with Schmitt-trigger
P3SEL.2
SYNC
MM
STC
STE
0
P3DIR.2
0: Input
1: Output
1
DCM_SOMI
Pad Logic
P3.2/SOMI0
0
P3OUT.2
SO(MI)0
From USART0
1
P3IN.2
EN
(SO)MI0
To USART0
D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
45
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.3, input/output with Schmitt-trigger
P3SEL.3
SYNC
MM
STC
STE
0
P3DIR.3
0: Input
1: Output
1
DCM_UCLK
Pad Logic
P3.3/UCLK0
0
P3OUT.3
UCLK.0
From USART0
1
P3IN.3
EN
UCLK0
D
To USART0
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.
SPI, slave mode:
The clock applied to UCLK0 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
46
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.0 to P4.6, input/output with Schmitt-trigger
P4SEL.x
0
P4DIR.x
Direction Control
From Module
Module X IN
0: Input
1: Output
1
w
Pad Logic
P5SEL.7
P4OUT.x
Module X OUT
0
P4.0/TB0 ..
1
P4.6/TB6
TBOUTHiZ
Bus Keeper
P4IN.x
EN
Module X IN
D
x: bit identifier, 0 to 6 for Port P4
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P4Sel.0
P4DIR.0
P4DIR.0
P4OUT.0
P4DIR.1
P4DIR.1
P4OUT.1
Out0 signal†
Out1 signal†
P4IN.0
P4Sel.1
P4IN.1
CCI0A / CCI0B‡
CCI1A / CCI1B‡
P4Sel.2
P4DIR.2
P4DIR.2
P4OUT.2
Out2 signal†
P4IN.2
CCI2A / CCI2B‡
P4Sel.3
P4DIR.3
P4DIR.3
P4OUT.3
P4DIR.4
P4DIR.4
P4OUT.4
Out3 signal†
Out4 signal†
P4IN.3
P4Sel.4
CCI3A / CCI3B‡
CCI4A / CCI4B‡
P4Sel.5
P4DIR.5
P4DIR.5
P4OUT.5
P4IN.5
P4DIR.6
P4DIR.6
P4OUT.6
Out5 signal†
Out6 signal†
P4Sel.6
† Signal from Timer_B
‡ Signal to Timer_B
§ From P5.7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P4IN.4
P4IN.6
CCI5A / CCI5B‡
CCI6A‡
47
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.7, input/output with Schmitt-trigger
P4SEL.7
0: Input
1: Output
0
P4DIR.7
1
Pad Logic
P4.7/TBCLK
0
P4OUT.7
DVSS
1
P4IN.7
EN
Timer_B,
D
TBCLK
port P5, P5.0 and P5.4 to P5.7, input/output with Schmitt-trigger
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
Pad Logic
P5OUT.x
Module X OUT
0
P5.0/STE1
1
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH
P5IN.x
EN
Module X IN
D
x: Bit Identifier, 0 and 4 to 7 for Port P5
PnSel.x
PnDIR.x
Dir. CONTROL FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P5Sel.0
P5DIR.0
STE.1
P5OUT.4
DVSS
MCLK
P5IN.0
P5DIR.4
P5IN.4
unused
P5Sel.5
P5DIR.5
DVSS
DVCC
DVCC
P5OUT.0
P5Sel.4
P5OUT.5
SMCLK
P5IN.5
unused
P5Sel.6
P5DIR.6
P5OUT.6
ACLK
P5IN.6
unused
P5Sel.7
P5DIR.7
DVCC
DVSS
P5OUT.7
DVSS
P5IN.7
TBOUTHiZ
NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B7.
48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.1, input/output with Schmitt-trigger
P5SEL.1
SYNC
MM
0
P5DIR.1
1
DCM_SIMO
STC
STE
0: Input
1: Output
Pad Logic
P5.1/SIMO1
0
P5OUT.1
(SI)MO1
From USART1
1
P5IN.1
EN
SI(MO)1
To USART1
D
port P5, P5.2, input/output with Schmitt-trigger
P5SEL.2
SYNC
MM
STC
STE
0
P5DIR.2
0: Input
1: Output
1
DCM_SOMI
Pad Logic
P5.2/SOMI1
0
P5OUT.2
SO(MI)1
From USART1
1
P5IN.2
EN
(SO)MI1
To USART1
D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
49
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.3, input/output with Schmitt-trigger
P5SEL.3
SYNC
MM
STC
STE
0
P5DIR.3
0: Input
1: Output
1
DCM_SIMO
Pad Logic
P5.3/UCLK1
0
P5OUT.3
UCLK1
From USART1
1
P5IN.3
EN
D
UCLK1
To USART1
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P5.3/UCLK1 direction
is always input.
SPI, slave mode:
The clock applied to UCLK1 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode).
50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.0 to P6.7, input/output with Schmitt-trigger
P6SEL.x
0
P6DIR.x
Direction Control
From Module
0: Input
1: Output
1
Pad Logic
P6.0 .. P6.7
0
P6OUT.x
Module X OUT
1
Bus Keeper
P6IN.x
EN
Module X IN
D
Note: Not implemented in the MSP430x14x1 devices
From ADC
To ADC
x: Bit Identifier, 0 to 7 for Port P6
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 µA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12.
PnSel.x
PnDIR.x
DIR. CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P6Sel.0
P6DIR.0
P6DIR.0
P6OUT.0
DVSS
P6IN.0
unused
P6Sel.1
P6DIR.1
P6DIR.1
P6OUT.1
DVSS
P6IN.1
unused
P6Sel.2
P6DIR.2
P6DIR.2
P6OUT.2
DVSS
P6IN.2
unused
P6Sel.3
P6DIR.3
P6DIR.3
P6OUT.3
DVSS
P6IN.3
unused
P6Sel.4
P6DIR.4
P6DIR.4
P6OUT.4
DVSS
P6IN.4
unused
P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
P6IN.5
unused
P6Sel.6
P6DIR.6
P6DIR.6
P6OUT.6
DVSS
P6IN.6
unused
P6Sel.7
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
P6IN.7
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
51
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DVCC DVCC
TDI
Fuse
Burn & Test
Fuse
Test
TDI/TCLK
&
Emulation
Module
DVCC
TMS
TMS
DVCC
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
TCK
TCK
52
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 16). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITDI/TCLK
ITF
Figure 16. Fuse Check Mode Current: MSP430F13x, MSP430F14x(1)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
53
PACKAGE OPTION ADDENDUM
www.ti.com
10-Mar-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430A009IPMR
ACTIVE
LQFP
PM
64
MSP430F133IPAG
ACTIVE
TQFP
PAG
64
MSP430F133IPM
ACTIVE
LQFP
PM
MSP430F133IPMR
ACTIVE
LQFP
MSP430F133IRTDR
ACTIVE
MSP430F133IRTDT
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
VQFN
RTD
64
2500 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
ACTIVE
VQFN
RTD
64
250
Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F135IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
MSP430F135IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F135IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F135IRTDR
ACTIVE
VQFN
RTD
64
2500 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F135IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F1471IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1471IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1471IPMRG
ACTIVE
LQFP
PM
64
MSP430F1471IPMRG4
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
TBD
CU NIPDAU
Level-3-260C-168 HR
MSP430F1471IRTDR
ACTIVE
VQFN
RTD
64
2500 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F1471IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F147IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
MSP430F147IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F147IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F147IPMR-KAM
ACTIVE
LQFP
PM
64
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F147IPMRG4
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F147IRTDR
ACTIVE
VQFN
RTD
64
2500 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F147IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F1481IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Addendum-Page 1
Call TI
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
10-Mar-2010
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F1481IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1481IRTDR
ACTIVE
VQFN
RTD
64
2500 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F1481IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F148IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
MSP430F148IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F148IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F148IRTDR
ACTIVE
VQFN
RTD
64
2500 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F148IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F1491IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1491IPMG4
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1491IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1491IPMRG4
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F1491IRTDR
ACTIVE
VQFN
RTD
64
2500 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F1491IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F149IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
MSP430F149IPAGR
ACTIVE
TQFP
PAG
64
1500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
MSP430F149IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F149IPMG4
ACTIVE
LQFP
PM
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F149IPMR
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F149IPMRG4
ACTIVE
LQFP
PM
64
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F149IRTDR
ACTIVE
VQFN
RTD
64
2500 Green (RoHS &
no Sb/Br)
CU SN
Level-3-260C-168 HR
MSP430F149IRTDT
ACTIVE
VQFN
RTD
64
250
CU SN
Level-3-260C-168 HR
(1)
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Mar-2010
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430F133IPMR
LQFP
PM
64
1000
330.0
24.4
12.3
12.3
2.5
16.0
24.0
Q2
MSP430F135IPMR
LQFP
PM
64
1000
330.0
24.4
12.3
12.3
2.5
16.0
24.0
Q2
MSP430F1471IPMR
LQFP
PM
64
1000
330.0
24.4
12.3
12.3
2.5
16.0
24.0
Q2
MSP430F147IPMR
LQFP
PM
64
1000
330.0
24.4
12.3
12.3
2.5
16.0
24.0
Q2
MSP430F1481IPMR
LQFP
PM
64
1000
330.0
24.4
12.3
12.3
2.5
16.0
24.0
Q2
MSP430F148IPMR
LQFP
PM
64
1000
330.0
24.4
12.3
12.3
2.5
16.0
24.0
Q2
MSP430F1491IPMR
LQFP
PM
64
1000
330.0
24.4
12.3
12.3
2.5
16.0
24.0
Q2
MSP430F149IPAGR
TQFP
PAG
64
1500
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
MSP430F149IPMR
LQFP
PM
64
1000
330.0
24.4
12.3
12.3
2.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F133IPMR
LQFP
PM
64
1000
333.2
345.9
41.3
MSP430F135IPMR
LQFP
PM
64
1000
333.2
345.9
41.3
MSP430F1471IPMR
LQFP
PM
64
1000
333.2
345.9
41.3
MSP430F147IPMR
LQFP
PM
64
1000
333.2
345.9
41.3
MSP430F1481IPMR
LQFP
PM
64
1000
333.2
345.9
41.3
MSP430F148IPMR
LQFP
PM
64
1000
333.2
345.9
41.3
MSP430F1491IPMR
LQFP
PM
64
1000
333.2
345.9
41.3
MSP430F149IPAGR
TQFP
PAG
64
1500
346.0
346.0
41.0
MSP430F149IPMR
LQFP
PM
64
1000
333.2
345.9
41.3
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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