Intersil ISL95810 Single digitally controlled potentiometer (xdcp) Datasheet

ISL95810
®
Single Digitally Controlled Potentiometer (XDCP™)
Data Sheet
October 7, 2005
FN8090.1
Low Noise, Low Power I2C Bus, 256 Taps
Features
The ISL95810 integrates a digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit.
• 256 resistor taps - 0.4% resolution
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the I2C
bus interface. The potentiometer has an associated volatile
Wiper Register (WR) and a non-volatile Initial Value Register
(IVR), that can be directly written to and read by the user.
The content of the WR controls the position of the wiper. At
power-up the device recalls the contents of the DCP’s IVR to
the WR.
The DCP can be used as three-terminal potentiometer or as
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
ISL95810WIU8*
TEMP
PART
RTOTAL
(kΩ)
RANGE (°C)
MARKING
AIU
10
ISL95810WIU8Z*
(Note)
ISL95810WIRT8Z*
(Note)
ISL95810UIU8*
AIT
ISL95810UIU8Z*
(Note)
AOK
50
ISL95810UIRT8Z*
(Note)
• Wiper resistance: 70Ω typical @ 3.3V
• Non-volatile storage of wiper position
• Standby current 5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ, 10kΩ total resistance
• High reliability
- Endurance: 200,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ 75°C
• 8 Ld MSOP and 8 Ld TDFN packaging
• Pb-free plus anneal available (RoHS compliant)
Pinout
Ordering Information
PART NUMBER
• I2C serial interface
ISL95810
(8 LD MSOP)
TOP VIEW
PACKAGE
-40 to 85
8 Ld MSOP
-40 to 85
8 Ld MSOP
(Pb-free)
-40 to 85
8 Ld 3 x 3 TDFN
(Pb-free)
-40 to 85
8 Ld MSOP
-40 to 85
8 Ld MSOP
(Pb-free)
-40 to 85
8 Ld 3 x 3 TDFN
(Pb-free)
WP
1
8
VCC
RH
SCL
2
7
SDA
3
6
RL
GND
4
5
RW
ISL95810
(8 LD TDFN)
TOP VIEW
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
1
WP 1
8 VCC
SCL 2
7 RH
SDA 3
6 RL
GND 4
5 RW
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL95810
Block Diagram
VCC
RH
SDA
WIPER
REGISTER
I2C AND
SCL
RW
CONTROL
NON-VOLATILE
WP
REGISTER
RL
GND
Pin Descriptions
TSSOP PIN
SYMBOL
1
WP
Hardware write protection. Active low. Prevents any “Write” operation of the I2C interface.
2
SCL
I2C interface clock
3
SDA
Serial data I/O for the I2C interface
4
GND
Ground
5
RW
“Wiper” terminal of the DCP
6
RL
“Low” terminal of the DCP
7
RH
“High” terminal of the DCP
8
VCC
Power supply
2
DESCRIPTION
FN8090.1
October 7, 2005
ISL95810
Absolute Maximum Ratings
Recommended Operating Conditions
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at Any Digital Interface Pin
with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at Any DCP Pin with
Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Power Rating of Each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
Wiper Current of Each DCP. . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
SYMBOL
RTOTAL
Over recommended operating conditions unless otherwise stated.
PARAMETER
RH to RL Resistance
TEST CONDITIONS
MIN
W, U versions respectively
CH/CL/CW
ILkgDCP
Wiper Resistance
-20
VCC = 3.3V @ 25°C
Wiper current = VCC/RTOTAL
70
Potentiometer Capacitance
(Note 13)
Leakage on DCP Pins (Note 13)
MAX
UNIT
10, 50
RH to RL Resistance Tolerance
RW
TYP
(Note 1)
kΩ
+20
%
200
Ω
10/10/25
Voltage at pin from GND to VCC
pF
0.1
1
µA
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)
INL (Note 6)
Integral Non-Linearity
DNL (Note 5)
Differential Non-Linearity
-1
Monotonic over all tap positions
W option -0.75
LSB (Note 2)
LSB (Note 2)
-0.5
LSB (Note 2)
0
1
7
LSB (Note 2)
U option
0
0.5
2
W option
-7
-1
0
-2
-0.5
0
U option
ZSerror (Note 3) Zero-Scale Error
W option
FSerror (Note 4) Full-Scale Error
U option
TCV (Note 7, 13) Ratiometric Temperature
Coefficient
1
-0.75
-0.5
DCP Register set to 80 hex
LSB (Note 2)
±4
ppm/°C
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)
RINL (Note 11)
Integral Non-Linearity
DCP register set between 20 hex and FF hex.
Monotonic over all tap positions
RDNL (Note 5)
Differential Non-Linearity
DCP register set between 20 hex W option -0.75
and FF hex. Monotonic over all tap U option -0.5
positions
Roffset (Note 9)
TCR
(Note 12, 13)
Offset
-1
W option
0
U option
0
1
Resistance Temperature Coefficient DCP register set between 20 hex and FF hex
MI (Note 8)
-0.75
MI (Note 8)
-0.5
MI (Note 8)
1
7
MI (Note 8)
0.5
2
MI (Note 8)
±45
ppm/°C
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
fSCL = 400kHz; SDA = Open; (for I2C, Active,
1
mA
ICC1 (Note 15)
VCC Supply Current
(Volatile write/read)
Read and Volatile Write States only)
ICC2 (Note 15)
VCC Supply Current
(Nonvolatile Write)
fSCL = 400kHz; SDA = Open; (for I2C, Active,
Nonvolatile Write State only)
3
mA
ISB (Note 15)
VCC Current (Standby)
VCC = +5.5V, I2C Interface in Standby State
5
µA
VCC = +3.6V, I2C Interface in Standby State
2
µA
3
FN8090.1
October 7, 2005
ISL95810
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
ILkgDig
tDCP (Note 13)
Vpor
PARAMETER
TEST CONDITIONS
Leakage Current, at Pins SDA,
SCL, and WP Pins
Voltage at pin from GND to VCC
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
Power-On Recall Voltage
Minimum VCC at which memory recall occurs
VCCRamp
VCC Ramp Rate
tD (Note 13)
Power-Up Delay
MIN
-10
1.8
TYP
(Note 1)
MAX
UNITS
10
µA
1
µs
2.6
V
0.2
VCC above Vpor, to DCP Initial Value Register
recall completed, and I2C Interface in standby state
V/ms
3
ms
EEPROM SPECIFICATIONS
EEPROM Endurance
EEPROM Retention
Temperature ≤75°C
200,000
Cycles
50
Years
SERIAL INTERFACE SPECIFICATIONS
VIL
WP, SDA, and SCL Input Buffer
LOW Voltage
-0.3
0.3*VCC
V
VIH
WP, SDA, and SCL Input Buffer
HIGH Voltage
0.7*VCC
VCC+0.3
V
Hysteresis (Note 13) SDA and SCL Input Buffer
Hysteresis
VOL (Note 13)
SDA Output Buffer LOW Voltage,
Sinking 4mA
Cpin (Note 13)
fSCL
0.05*
VCC
0
V
0.4
V
WP, SDA, and SCL Pin
Capacitance
10
pF
SCL Frequency
400
kHz
tIN (Note 13)
Pulse Width Suppression Time at Any pulse narrower than the max spec is
SDA and SCL Inputs
suppressed.
50
ns
tAA (Note 13)
SCL Falling Edge to SDA Output
Data Valid
900
ns
tBUF (Note 13)
Time the Bus Must be Free Before SDA crossing 70% of VCC during a STOP
the Start of a New Transmission condition, to SDA crossing 70% of VCC during
the following START condition.
1300
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to
SDA entering the 30% to 70% of VCC window.
0
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC.
600
ns
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STO:NV
STOP Condition Hold Time for
Non-Volatile Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
2
µs
Output Data Hold Time
From SCL falling edge crossing 30% of VCC, until
SDA enters the 30% to 70% of VCC window.
0
ns
SDA and SCL Rise Time
From 30% to 70% of VCC
tDH (Note 13)
tR (Note 13)
4
SCL falling edge crossing 30% of VCC, until SDA
exits the 30% to 70% of VCC window.
20 +
0.1 * Cb
ns
250
ns
FN8090.1
October 7, 2005
ISL95810
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
From 70% to 30% of VCC
MAX
UNITS
20 +
0.1 * Cb
250
ns
400
tF (Note 13)
SDA and SCL Fall Time
Cb (Note 13)
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
Rpu (Note 13)
SDA and SCL Bus Pull-Up
Resistor Off-Chip
1
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
TYP
(Note 1)
tWP (Notes 13, 14) Non-Volatile Write Cycle Time
pF
kΩ
12
20
ms
tSU:WP
WP Setup Time
Before START condition
600
ns
tHD:WP
WP Hold Time
After STOP condition
600
ns
SDA vs SCL Timing
tF
SCL
tHIGH
tLOW
tR
tSU:DAT
tSU:STA
SDA
(INPUT TIMING)
tHD:DAT
tHD:STA
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
WP Pin Timing
STOP
START
SCL
tHD:STO
tHD:STO:NV
CLK 1
SDA IN
tSU:WP
tHD:WP
WP
NOTES:
1. Typical values are for TA = 25°C and 3.3V supply voltage.
2. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = V(RW)0/LSB.
4. FS error = [V(RW)255 – VCC]/LSB.
5. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
6. INL = [V(RW)i – (i • LSB – V(RW)0)]/LSB for i = 1 to 255.
Max ( V ( RW ) i ) – Min ( V ( RW ) i )
10 6
7. TC V = ---------------------------------------------------------------------------------------------- × ----------------- for i = 16 to 240 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper
[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 125°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
8. MI = |R255 – R0|/255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
Roffset = R0/MI, when measuring between RW and RL.
9. Roffset = R255/MI, when measuring between RW and RH.
10. RDNL = (Ri – Ri-1)/MI, for i = 32 to 255.
11. RINL = [Ri – (MI • i) – R0]/MI, for i = 32 to 255.
6
[ Max ( Ri ) – Min ( Ri ) ]
10
12. TC R = ---------------------------------------------------------------- × ----------------- for i = 32 to 255, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the
[ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 125°C minimum value of the resistance over the temperature range.
13. This parameter is not 100% tested.
5
FN8090.1
October 7, 2005
ISL95810
14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a
valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile
write cycle.
15. VIL = 0V, VIH = VCC
Typical Performance Curves
1.8
160
VCC = 2.7, T = 85°C
VCC = 2.7, T = -40°C
1.6
VCC = 2.7, T = 25°C
1.4
120
1.2
STANDBY ICC (µA)
WIPER RESISTANCE (Ω)
140
100
80
60
40
VCC = 5.5, T = -40°C
20
0.8
50
0.4
VCC = 5.5, T = 85°C
VCC = 5.5, T = 25°C
100
150
200
85°C
0.6
0.2
25°C
0.0
2.7
0
0
-40°C
1.0
250
3.2
3.7
TAP POSITION (DECIMAL)
0.3
0.15
VCC = 5.5, T = -40°C
4.7
5.2
FIGURE 2. STANDBY ICC vs VCC
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = VCC / RTOTAL ] for 50kΩ (U)
0.2
4.2
VCC (V)
VCC = 2.7, T = -40°C
VCC = 5.5, T = -40°C
VCC = 2.7, T = -40°C
VCC = 2.7, T = 25°C
0.2
VCC = 5.5, T = 85°C
0.1
0.05
INL (LSB)
DNL (LSB)
0.1
0
-0.05
-0.1
-0.15
-0.2
0
0
VCC = 2.7, T = 25°C
VCC = 2.7, T = 85°C
-0.1
VCC = 5.5, T = 25°C
VCC = 2.7, T = 85°C
VCC = 5.5, T = 85°C
-0.2
-0.3
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
6
VCC = 5.5, T = 25°C
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
FN8090.1
October 7, 2005
ISL95810
Typical Performance Curves
(Continued)
0
0.4
-0.1
-0.2
0.35
VCC = 5.5V
FSerror (LSB)
ZSerror (LSB)
-0.3
0.3
2.7V
0.25
-0.4
VCC = 2.7V
-0.5
-0.6
-0.7
0.2
-0.8
5.5V
-0.9
0.15
-40
-20
0
20
40
60
-1
-40
80
0
-20
0.3
60
80
0.5
VCC = 2.7, T = 25°C
0.4
VCC = 5.5, T = 25°C
0.2
VCC = 2.7, T = 25°C
0.3
VCC = 5.5, T = -40°C
0.2
INL (LSB)
0.1
DNL (LSB)
40
FIGURE 6. FSerror vs TEMPERATURE
FIGURE 5. ZSerror vs TEMPERATURE
0
-0.1
0.1
VCC = 5.5, T = 85°C
0
-0.1
-0.2
VCC = 5.5, T = 85°C
-0.3
VCC = 2.7, T = 85°C
VCC = 2.7, T = -40°C
VCC = 5.5, T = -40°C
-0.2
-0.3
32
82
132
182
TAP POSITION (DECIMAL)
-0.4 VCC = 2.7, T = 85°C
VCC = 5.5, T = 25°C
-0.5
32
82
132
232
VCC = 2.7, T = -40°C
182
232
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
50kΩ (U)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
50kΩ (U)
20
1.50
1.00
10
0.50
0.00
2.7V
TC (ppm/°C)
END TO END RTOTAL CHANGE (%)
20
TEMPERATURE (°C)
TEMPERATURE (°C)
5.5V
-0.50
0
-10
-1.00
-1.50
-40
-20
0
20
40
60
TEMPERATURE (°C)
FIGURE 9. END TO END RTOTAL % CHANGE vs
TEMPERATURE
7
80
-20
32
82
132
182
232
TAP POSITION (DECIMAL)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FN8090.1
October 7, 2005
ISL95810
Typical Performance Curves
(Continued)
35
INPUT
25
TC (ppm/°C)
15
5
OUTPUT
-5
Tap Position = Mid Point
RTOTAL = 9.4K
-15
-25
32
57
82
107
132
157
182
207
232
TAP POSITION (DECIMAL)
FIGURE 12. FREQUENCY RESPONSE (2.2MHz)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
Signal at Wiper (Wiper Unloaded)
SCL
Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)
Wiper Movement Mid Point
From 80h to 7fh
FIGURE 13. MIDSCALE GLITCH, CODE 80h to 7Fh (WIPER 0)
8
FIGURE 14. LARGE SIGNAL SETTLING TIME
FN8090.1
October 7, 2005
ISL95810
Principles of Operation
The ISL95810 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory, and a I2C
serial interface providing direct communication between a
host and the potentiometer and memory.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). The DCP has its own WR.
When the WR of the DCP contains all zeroes (WR<7:0>:
00h), its wiper terminal (RW) is closest to its “Low” terminal
(RL). When the WR of the DCP contains all ones (WR<7:0>:
FFh), its wiper terminal (RW) is closest to its “High” terminal
(RH). As the value of the WR increases from all zeroes (00h)
to all ones (255 decimal), the wiper moves monotonically
from the position closest to RL to the closest to RH. At the
same time, the resistance between RW and RL increases
monotonically, while the resistance between RH and RW
decreases monotonically.
While the ISL95810 is being powered up, The WR is reset to
80h (128 decimal), which locates RW roughly at the center
between RL and RH. Soon after the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the ISL95810 reads the value stored in non-volatile
Initial Value Registers (IVRs) and loads it into the WR.
The WR and IVR can be read or written directly using the
I2C serial interface as described in the following sections.
Memory Description
The ISL95810 volatile and non-volatile registers are
accessed by I2C interface operations at addresses 0 and 2
decimal. The non-volatile byte at addresses 0 contains the
initial value loaded at power-up into the volatile Wiper
Register (WR) of the DCP. The byte at address 1 is
reserved; the user should not write to it, and its value should
be ignored if read.
The volatile WR, and the non-volatile Initial Value Register
(IVR) of the DCP are accessed with the same Address Byte,
set to 00 hex in both cases.
A volatile byte at address 2 decimal, controls what byte is
read or written when accessing DCP registers: the WR, the
IVR, or both.
When the byte at address 2 is all zeroes, which is the default
at power-up:
• A read operation to addresses 0 outputs the value of the
non-volatile IVR.
9
• A write operation to addresses 0 writes the same value to
the WR and IVR of the corresponding DCP.
When the byte at address 2 is 80h (128 decimal):
• A read operation to addresses 0 outputs the value of the
volatile WR.
• A write operation to addresses 0 only writes to the
corresponding volatile WR.
It is not possible to write to an IVR without writing the same
value to its corresponding WR.
00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be
written to address 2.
The ISL95810 is pre-programed with 80h in the IVR.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
2
-
Access Control
1
0
Reserved
IVR
WR
WR: Wiper Register, IVR: Initial value Register.
I2C Serial Interface
The ISL95810 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL95810
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power-up of the ISL95810 the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL95810 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the powerup sequence and during internal non-volatile write cycles.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15). A STOP condition at the end
of a read operation, or at the end of a write operation to
FN8090.1
October 7, 2005
ISL95810
The ISL95810 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL95810 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte, initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).
A valid Identification Byte contains 0101000 as the seven
MSBs. The LSB in the Read/Write bit. Its value is “1” for a
Read operation, and “0” for a Write operation (See Table 2).
TABLE 2. IDENTIFICATION BYTE FORMAT
0
1
0
1
0
0
(MSB)
0
R/W
(LSB)
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE ISL95810
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
0 1 0 1 0 0 0 0
0 0 0 0 0 0
A
C
K
S
T
O
P
DATA
BYTE
A
C
K
A
C
K
FIGURE 17. BYTE WRITE SEQUENCE
10
FN8090.1
October 7, 2005
ISL95810
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH
R/W=0
ADDRESS
BYTE
0 1 0 1 0 0 0 0
A
C
K
S
T
O
P
A
C
K
0 1 0 1 0 0 0 1
0 0 0 0 0 0
A
C
K
SIGNALS FROM
THE SLAVE
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W=1
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 18. READ SEQUENCE
Write Operation
Read Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL95810 responds with an ACK. At this time, if the Data
Byte is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the ISL95810 begins its internal
write cycle to non-volatile memory. During the internal nonvolatile write cycle, the device ignores transitions at the SDA
and SCL pins, and the SDA output is at a high impedance
state. When the internal non-volatile write cycle is
completed, the ISL95810 enters its standby state (See
Figure 17).
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL95810 responds with an ACK. Then the ISL95810
then transmits the Data Byte. The master then terminates
the read operation (issuing a STOP condition) following the
last bit of the Data Byte (See Figure 18).
The byte at address 02h determines if the Data Bytes being
read are from volatile or non-volatile memory (See “Memory
Description” on page 9.)
The byte at address 02h determines if the Data Byte is to be
written to volatile and/or non-volatile memory (See “Memory
Description” on page 7).
Data Protection
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP is active (LOW) the
device ignores Data Bytes of a Write Operation, does not
respond to the Data Bytes with an ACK, and instead, goes to
its standby state waiting for a new START condition.
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
received. If the Address Byte is 0 or 2, the Data Byte is
transferred to the Wiper Register (WR) or to the Access
Control Register respectively, at the falling edge of the SCL
pulse that loads the last bit (LSB) of the Data Byte. If the
Address Byte is 0, and the Access Control Register is all
zeros (default), then the STOP condition initiates the internal
write cycle to non-volatile memory.
11
FN8090.1
October 7, 2005
ISL95810
MSOP Packaging Information
8-Lead Plastic, MSOP, Package Code U8
0.118 ± 0.002
(3.00 ± 0.05)
0.012 + 0.006/-0.002
(0.30 + 0.15/-0.05)
0.0256 (0.65) Typ.
R 0.014 (0.36)
0.118 ± 0.002
(3.00 ± 0.05)
0.030 (0.76)
0.0216 (0.55)
0.036 (0.91)
0.032 (0.81)
0.040 ± 0.002
(1.02 ± 0.05)
7° Typ.
0.008 (0.20)
0.004 (0.10)
0.0256" Typical
0.007 (0.18)
0.005 (0.13)
0.150 (3.81)
Ref.
0.193 (4.90)
Ref.
NOTE:
1.ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
12
0.025"
Typical
0.220"
FOOTPRINT
0.020"
Typical
8 Places
FN8090.1
October 7, 2005
ISL95810
Thin Dual Flat No-Lead Plastic Package (TDFN)
2X
L8.3x3B
0.15 C A
A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
2X
MILLIMETERS
0.15 C B
E
SYMBOL
MIN
0.70
0.75
0.80
-
-
-
0.05
-
0.38
5, 8
2.40
7, 8
1.60
7, 8
0.20 REF
0.23
D
D2
B
SIDE VIEW
A3
D2
(DATUM B)
7
2.30
-
1.50
-
0.65 BSC
-
k
0.20
-
-
-
L
0.20
0.30
0.40
8
N
8
Nd
4
8
2
3
Rev. 0 6/04
NOTES:
D2/2
1
6
INDEX
AREA
0.08 C
-
3.00 BSC
1.35
e
A
C
SEATING
PLANE
0.10 C
E2
0.30
3.00 BSC
2.15
E
//
NOTES
A
b
TOP VIEW
MAX
A1
A3
6
INDEX
AREA
NOMINAL
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
(DATUM A)
E2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
E2/2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
e
8
5
(Nd-1)Xe
REF.
0.10 M C A B
BOTTOM VIEW
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
CL
(A1)
NX (b)
L
5
SECTION "C-C"
C C
e
TERMINAL TIP
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN8090.1
October 7, 2005