ICST ICS570MI Multiplier and zero delay buffer Datasheet

ICS570
Multiplier and Zero Delay Buffer
Description
Features
The ICS570 is a high-performance Zero Delay Buffer
(ZDB) which integrates ICS’ proprietary analog/digital
Phase Locked Loop (PLL) techniques. The A version is
recommended for 5 V designs and the B version for
3.3 V designs. The chip is part of ICS’ ClockBlocksTM
family, and was designed as a performance upgrade to
meet today’s higher speed and lower voltage
requirements. The zero delay feature means that the
rising edge of the input clock aligns with the rising
edges of both output clocks, giving the appearance of
no delay through the device. There are two outputs on
the chip, one being a low-skew divide by two of the
other output. The device incorporates an all-chip power
down/tri-state mode that stops the internal PLL and
puts both outputs into a high impedance state.
• 8-pin SOIC package
• Available in Pb (lead) free package (A and B versions
The ICS570 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to graphics/video. By allowing off-chip
feedback paths, the device can eliminate the delay
through other devices.
The ICS570 A and B versions were designed to
improve input to output jitter from the original ICS570M
version, and are recommended for all new designs.
only)
• Pin-for-pin replacement and upgrade to ICS570M
• Functional equivalent to AV9170 (not a pin-for-pin
•
•
•
•
•
•
•
•
•
•
•
•
replacement)
Low input to output skew of 300 ps max (>60 MHz
outputs)
Ability to choose between 14 different multipliers
from 0.5x to 32x
Output clock frequency up to 168 MHz at 3.3 V
Can recover degraded input clock duty cycle
Output clock duty cycle of 45/55
Power Down and Tri-State Mode
Passes spread spectrum clock modulation
Full CMOS clock swings with 25 mA drive capability
at TTL levels
Advanced, low power CMOS process
ICS570B has an operating voltage of 3.3 V (±5%)
ICS570A has an operating voltage of 5.0 V (±5%)
Industrial temperature version available
Block Diagram
IC L K
S 1 :0
F B IN
d ivid e
by N
Phase
D e te c to r,
C h a rg e
Pum p,
and Loop
F ilte r
VCO
C LK
/2
C LK2
E xte rn a l fe e d b a ck ca n co m e fro m C L K o r C L K /2 (se e ta b le o n p a g e 2 )
MDS 570 I
1
Revision 030905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Pin Assignment
S1
1
8
CLK/2
VDD
2
7
CLK
GND
3
6
S0
ICLK
4
5
FBIN
8 pin (150 mil) SOIC
Clock Multiplier Decoding Table
(Multiplies Input clock by amount shown)
FBIN from CLK
S1 S0
#1
#6
FBIN from CLK/2
CLK
CLK2
CLK
CLK2
pin #7
pin #8
pin #7
pin #8
0
0
0
M
x3
x1.5
ICS570B (3.3 V)
ICS570A (5.0 V)
ICLK Input Range FB from CLK/2* ICLK Input Range FB from CLK/2*
Power Down and Tri-State
-
-
x6
x3
3.75 to 28
2.5 to 25
0
1
x4
x2
x8
x4
2.75 to 19
2.5 to 19
M
0
x8
x4
x16
x8
2.5 to 9.5
2.5 to 9.5
M
M
x6
x3
x12
x6
2.5 to 12.5
2.5 to 12.5
M
1
x10
x5
x20
x10
2.5 to 7.5
2.5 to 7.5
1
0
x1
/2
x2
x1
11 to 75
5 to 75
1
M
x16
x8
x32
x16
1
1
x2
x1
x4
x2
0 = connect directly to ground
M = leave unconnected (self-biases to VDD/2)
1 = connect directly to VDD
*Input range with CLK feedback is double that for CLK/2
2.5 to 5
2.5 to 5
5.5 to 37.5
2.5 to 37.5
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
S1
Input
Select 1 for output clock. Connect to GND, VDD, or float per decoding table above.
2
VDD
Power
Connect to +3.3 V (ICS570B). Connect to +5.0 V (ICS570A).
3
GND
Power
Connect to ground.
4
ICLK
Input
Reference clock input.
5
FBIN
Input
Feedback clock input.
6
S0
Input
Select 0 for output clock. Connect to GND, VDD, or float per decoding table above.
7
CLK
Output
Clock output per table above.
8
CLK/2
Output
Clock output per table above. Low skew divide by two of pin 7 clock.
MDS 570 I
2
Revision 030905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
External Components
The ICS570 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the part to minimize lead inductance. No external power supply filtering is required for
this device. A 33Ω series terminating resistor can be used next to each output pin.
Recommended Circuit
S1
CLK
VDD
CLK/2
ICLK
GND
S0
Input
CLK
FBIN
CLK/2
x2 Mode (S1, S0 = 1, 0)
CLK/2 Feedback
ICLK
CLK
CLK/2
x2 Mode (S1, S0 = 1, 1)
CLK Feedback
Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK.
However, the CLK/2 could be a falling edge compared with ICLK. ICS recommends using CLK/2 feedback
whenever possible. This will synchronize the rising edges of all three clocks.
MDS 570 I
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Revision 030905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Clock Period Jitter Tables (ICS570A)
All jitter values are considered typical measured at 25°C with 27Ω termination resistor and 15 pF loads on
both CLK and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left
unconnected to improve output jitter on the active output clocks.
Absolute and One Sigma Jitter (ps)
CLK = 50M
S1 S0
CLKIN (MHz)
Multiplier
CLK/2 = 25M
P to P
1 sigma
Multiplier
P to P
1 sigma
0
M
8.333
6x
±115
80
3x
±65
20
0
1
6.25
8x
±115
80
4x
±60
20
M
0
3.125
16x
±120
80
8x
±55
20
M
M
4.167
12x
±120
90
6x
±60
20
M
1
2.5
20x
±120
80
10x
±60
20
1
0
25
2x
±120
70
1x
±55
20
1
M
1.5625
32x
±120
80
16x
±50
20
1
1
12.5
4x
±120
80
2x
±55
20
1 sigma
Multiplier
Absolute and One Sigma Jitter (ps)
CLK = 100M
S1 S0
CLKIN (MHz)
Multiplier
P to P
CLK/2 = 50M
P to P
1 sigma
0
M
16.667
6x
±135
100
3x
±55
20
0
1
12.5
8x
±140
100
4x
±50
20
M
0
6.25
16x
±140
110
8x
±55
20
M
M
8.333
12x
±140
110
6x
±55
20
M
1
5
20x
±135
100
10x
±50
20
1
0
50
2x
±120
90
1x
±50
20
1
M
3.125
32x
±135
100
16x
±55
20
1
1
25
4x
±130
90
2x
±65
20
1 sigma
Multiplier
Absolute and One Sigma Jitter (ps)
CLK = 150M
S1 S0
CLKIN (MHz)
Multiplier
P to P
CLK/2 = 75M
P to P
1 sigma
0
M
25
6x
±160
120
3x
±55
20
0
1
18.375
8x
±165
120
4x
±55
20
M
0
9.375
16x
±170
120
8x
±50
20
M
M
12.5
12x
±160
120
6x
±55
20
M
1
7.5
20x
±160
120
10x
±55
20
1
0
75
2x
±155
110
1x
±55
20
1
M
4.6875
32x
±165
120
16x
±55
20
1
1
37.5
4x
±160
110
2x
±50
20
MDS 570 I
4
Revision 030905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Clock Period Jitter Tables (ICS570B)
All jitter values are considered typical measured at 25°C with 27Ω termination resistor and 15 pF loads on
both CLK and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left
unconnected to improve output jitter on the active output clocks.
Absolute and One Sigma Jitter (ps)
CLK = 50M
S1 S0
CLKIN (MHz)
Multiplier
CLK/2 = 25M
P to P
1 sigma
Multiplier
P to P
1 sigma
0
M
8.333
6x
±110
80
3x
±55
20
0
1
6.25
8x
±125
90
4x
±50
20
M
0
3.125
16x
±130
90
8x
±55
20
M
M
4.167
12x
±120
90
6x
±55
20
M
1
2.5
20x
±115
90
10x
±55
20
1
0
25
2x
±130
50
1x
±55
20
1
M
1.5625
32x
±120
90
16x
±55
20
1
1
12.5
4x
±120
60
2x
±55
20
1 sigma
Multiplier
Absolute and One Sigma Jitter (ps)
CLK = 100M
S1 S0
CLKIN (MHz)
Multiplier
P to P
CLK/2 = 50M
P to P
1 sigma
0
M
16.667
6x
±100
70
3x
±45
20
0
1
12.5
8x
±100
70
4x
±45
20
M
0
6.25
16x
±110
80
8x
±45
20
M
M
8.333
12x
±100
70
6x
±45
20
M
1
5
20x
±105
70
10x
±40
20
1
0
50
2x
±90
60
1x
±40
20
1
M
3.125
32x
±95
70
16x
±45
20
1
1
25
4x
±105
70
2x
±60
20
1 sigma
Multiplier
Absolute and One Sigma Jitter (ps)
CLK = 150M
S1 S0
CLKIN (MHz)
Multiplier
P to P
CLK/2 = 75M
P to P
1 sigma
0
M
25
6x
±115
70
3x
±50
20
0
1
18.375
8x
±120
80
4x
±50
20
M
0
9.375
16x
±130
90
8x
±50
20
M
M
12.5
12x
±130
90
6x
±45
20
M
1
7.5
20x
±130
90
10x
±45
20
1
0
75
2x
±115
90
1x
±45
20
1
M
4.6875
32x
±130
90
16x
±50
20
1
1
37.5
4x
±110
70
2x
±60
20
MDS 570 I
5
Revision 030905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS570. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature, Commercial version
0 to +70°C
Ambient Operating Temperature, Industrial version
-40 to +85°C
Storage Temperature
-65 to +150°C
Junction Temperature
125°C
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature, Commercial version
Ambient Operating Temperature, Industrial version
Power Supply Voltage (measured in respect to GND)
Typ.
Max.
Units
0
70
°C
-40
+85
°C
+3.45
V
+3.15
+3.3
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Operating Current
Symbol Conditions
VDD
IDD
Typ.
Max.
Units
V
ICS570B
3.15
3.45
ICS570A
4.75
5.25
ICS570B
3.3 V, 50M input,
S1:0 = 11
16
mA
ICS570A
5.0 V, 50M input,
S1:0 = 11
25
mA
Input High Voltage
VIH
ICLK, FBIN
Input Low Voltage
VIL
ICLK, FBIN
Input High Voltage
VIH
S0, S1
Input Low Voltage
(mid-level)
VIM
S0, S1
MDS 570 I
Min.
6
2
V
0.8
VDD-0.5
V
V
VDD/2
V
Revision 030905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Parameter
Symbol Conditions
Min.
Typ.
Max.
Units
0.5
V
Input Low Voltage
VIL
S0, S1
Output High Voltage (CMOS
High)
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -12 mA
2.4
V
Output Low Voltage
VOL
IOL = 12mA
Short Circuit Current
IOS
Each output
Input Capacitance
CIN
S0, S1
0.4
V
±100
mA
5
pF
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Input Frequency, ICLK
FBIN from CLK/2
Output Clock Frequency
CLK
Output to Output Skew
ICS570B
Output to Output Skew
ICS570A
Input to Output Jitter
40 - 150 MHz
Min.
Typ.
Max. Units
See table on page 2
10
168
MHz
100
175
ps
100
200
ps
100-250
ps
ICLK to FBIN,
CLK>30MHz, Note 1
-300
300
ps
ICLK to FBIN,
CLK<10MHz, Note 1
-600
600
ps
ICLK to FBIN
CLK>30MHz, Note 1
-1
1
ns
Input Skew, ICS570A
ICLK to FBIN,
CLK<10MHz, Note 1
-1.5
1.5
ns
Output Clock Rise Time
0.8 to 2.0V, Note 2
0.75
ns
Output Clock Fall Time
2.0 to 0.8V, Note 2
0.75
ns
Output Clock Duty Cycle
at VDD/2
Input Skew, ICS570B
45
49 - 51
55
%
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2
Note 2: Measured with 27Ω terminating resistor and 15 pF loads
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
MDS 570 I
Symbol
Conditions
Min.
Typ.
Max. Units
θJA
Still air
150
°C/W
θJA
1 m/s air flow
140
°C/W
θJA
3 m/s air flow
120
°C/W
40
°C/W
θJC
7
Revision 030905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
E
Symbol
A
A1
B
C
D
E
e
H
h
L
α
H
INDEX
AREA
1 2
D
A
Millimeters
Inches
Min
Max
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
Min
Max
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.1890
.1968
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0°
8°
h x 45
A1
C
-Ce
B
SEATING
PLANE
L
.10 (.004)
MDS 570 I
8
C
Revision 030905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS570A
ICS570AT
ICS570AI
ICS570AIT
ICS570AILF
ICS570AILFT
ICS570ALF
ICS570ALFT
ICS570B
ICS570BT
ICS570BLF
ICS570BLFT
ICS570BI
ICS570BIT
ICS570BILF
ICS570BILFT
ICS570M
ICS570MT
ICS570MI
ICS570MIT
ICS570A
ICS570A
ICS570AI
ICS570AI
570AILF
570AILF
570ALF
570ALF
ICS570B
ICS570B
ICS570BL
ICS570BL
ICS570BI
ICS570BI
570BILF
570BILF
ICS570M
ICS570M
ICS570MI
ICS570MI
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
0 to +70° C
0 to +70° C
-40 to 85° C
-40 to 85° C
-40 to 85° C
-40 to 85° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
-40 to 85° C
-40 to 85° C
-40 to 85° C
-40 to 85° C
0 to +70° C
0 to +70° C
-40 to 85° C
-40 to 85° C
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 570 I
9
Revision 030905
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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