Integrated Circuits Inc. aP8921A/10A APLUS MAKE YOUR PRODUCTION A-PLUS VOICE OTP IC aP8921A – 21sec aP8910A – 10sec APLUS INTEGRATED CIRCUITS INC. Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. Sales E-mail: [email protected] (115)台北市南港區成功路一段 32 號 3 樓之 10. TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 Support E-mail: WEBSITE : http: //www.aplusinc.com.tw Ver 5.0 1 [email protected] Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A FEATURES • • • • Standard CMOS process. Embedded 512K/256K bits EPROM. 21/10 sec Voice Length at 6KHz sampling and 4-bit ADPCM compression. Maximum 12 voice groups. • • • • Combination of voice blocks to extend playback duration. 960 table entries are available for voice block combinations. User selectable PCM or ADPCM data compression. Two triggering modes are available (EPROM programmable options). - Key Trigger Mode – Combinations of S1 ~ S4 to trigger 12 Voice Groups; SBT sequential trigger is possible. - CPU Parallel Trigger Mode – Combinations of S1 ~ S4 with SBT goes HIGH to strobe start the voice playback. • • Voice Group Trigger Options: Edge / Level; Hold / Un-hold; Retrigger / Non-retrigger. Whole Chip Options: Ramp / No-ramp; Output Options; Key / CPU trigger mode. • • • • 16ms (@ 8KHz sampling rate) Debounce Time in Key Trigger Mode. 65us (@ 8KHz sampling rate) Debounce Time in CPU Parallel Trigger Mode. RST pin set to HIGH to stop playback at once. Two user programmable outputs for STOP pulse, BUSY signal and flashing LED. • • • • Built-in oscillator to control sampling frequency with an external resistor. 2.6V – 5.0V; Wide range single power supply and < 5uA low stand-by current. PWM Vout1 and Vout2 drive speaker directly. D/A COUT to drive speaker through an external BJT. • Development System support voice compilation and options selection. DESCRIPTION aP8921A/10A series high performance Voice OTP is fabricated with Standard CMOS process with embedded 512K/256K bits EPROM. It can store up to 21/10sec voice message with 4-bit ADPCM compression at 6KHz sampling rate. 8-bit PCM is also available as user selectable option. Two trigger modes, simple Key trigger mode and Parallel CPU trigger mode facilitate different user interface. User selectable triggering and output signal options provide maximum flexibility to various applications. Built-in resistor controlled oscillator, 8-bit current mode D/A output and PWM direct speaker driving output minimize the number of external components. controlled programmer and developing software are available. Ver 5.0 2 PC Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A PIN CONFIGURATIONS OUT1 1 16 RST VOUT1 2 15 SBT VOUT2 3 14 S4 VSS 4 13 S3 OUT2 5 12 VDD V33 6 11 S2 COUT 7 10 S1 OSC 8 9 VPP PIN NAMES PIN Playback Mode OTP Program Mode 1 OUT1 OEB 2 VOUT1 - PWM output to drive speaker directly 3 VOUT2 - PWM output to drive speaker directly 4 VSS VSS 5 OUT2 IO 6 V33 V33 7 COUT - 8 OSC ACLK 9 VPP VPP 10 S1 S1 Trigger pin (input with internal pull-down) 11 S2 S2 Trigger pin (input with internal pull-down) 12 VDD VDD 13 S3 S3 Trigger (input with internal pull-down) 14 S4 S4 Trigger (input with internal pull-down) 15 SBT PGM Trigger pin (input with internal pull-down) 16 RST DCLK Reset pin (input with internal pull-down) Ver 5.0 Description Programmable output (I/O pin) Power Ground Programmable output (I/O pin) Power Supply for OTP programming D/A current output Oscillator input Supply voltage for OTP programming 2.6 – 5.0V Positive Power Supply 3 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A PIN DESCRIPTIONS S1 ~ S4 Input Trigger Pins: - S1 to S4 is used to trigger the 12 Voice Groups in both Key and CPU Parallel Trigger Mode. - In OTP Programming Mode, S1 to S4 are used as program enable pins. SBT Input Trigger Pin: - In Key Trigger Mode, this pin is trigger pin to trigger the playback of Voice Groups one by one sequentially. - In CPU Parallel Command Mode, this pin is used as address strobe to latch the input from S1 to S4 and starts the voice playback. - In OTP Programming Mode, this pin is used as PGM signal. VDD and V33 Power Supply Pin for normal and programming operation VSS Power Ground Pin VOUT1 and VOUT2 Digital PWM output pins which can drive speaker and buzzer directly for voice playback. OSC During voice playback, an external resistor is connected between this pin and the VDD pin to set the sampling frequency. In OTP Programming Mode, this is the ACLK input signal. VPP No connection during voice playback. separate 6.5V power supply. In OTP Programming Mode, this pin is connected to a OUT1 and OUT2 - In Key Trigger Mode and CPU Parallel Command Mode, these pins are user programmable pins for the STOP pulse, BUSY and LED signals. - During OTP programming, OUT1 serves as OEB while OUT2 serves as data IO. COUT Analog 8-bit current mode D/A output for voice playback RST Chip reset in playback mode or DCLK pin in OTP programming mode. Ver 5.0 4 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A VOICE SECTION COMBINATIONS Voice files created by the PC base developing system are stored in the built-in EPROM of the aP8921A/10A chip as a number of fixed length Voice Blocks. Voice Blocks are then selected and grouped into Voice Groups for playback. Up to 12 Voice Groups are allowed. A Voice Block Table is used to store the information of combinations of Voice Blocks and then group them together to form Voice Group. Chip aP8921A aP8910A Memory size 512K bits 256K bits Max no. of Voice Block 126 126 No. of bytes per Voice Block 512 256 Max. no. of Voice Group 12 12 No. of Voice Table entries 960 960 21 sec 10 sec Voice Length (@ 6KHz 4-bit ADPCM) Example of Voice Block Combination Assume here we have three voice files, they are “How are You?”, Sound Effect and Music. Each of the voice file is divided into a number of fixed length Voice Block and stored into the memory. Voice File 1 - “How are You?” is stored in Voice Block B0 to B12. Voice File 2 - Sound Effect is stored in Voice Block B13 to B15. Voice File 3 - Music is Voice Block B16 to B40. Voice Blocks are grouped together using Voice Table to form Voice Group for playback: Group no. Voice Group contents Voice Table Entries Group 1 “How are You?” B0 … B12 Group 2 Sound Effect + “How are You?” B13 … B15 + B0 … B12 Group 3 “How are You?” + Music B0 … B12 + B16 … B40 Group 4 Music B16 … B40 Voice Data Compression Voice File data is stored in the on-chip EPROM as either 4-bit ADPCM or 8-bit PCM format. Voice data stored as 4-bit ADPCM provides 2:1 data compression which can save 50% of memory space. On the other hand, voice data are stored as 8-bit PCM format means no data compression is employed but voice playback quality will be better. Ver 5.0 5 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A Programmable Options In both Key Trigger Mode and CPU Parallel Trigger Mode, user can select different trigger functions and output signals to be sent out from the pins OUT1 and OUT2. Options affect all Voice Group playback are called Whole Chip Options. Options only affect the playback of individual Voice Group are called Group Options. Whole Chip Options • • Key or CPU Parallel Trigger Mode. Ramp-up-down enable or disable: When COUT is used for playback, Ramp-up-down should be enabled. This function eliminates the ‘POP’ noise at the beginning and end of voice playback. When VOUT1 and VOUT2 are used to drive speaker directly, Ramp-up-down should be disabled. Fig. 1 Ramp-up-down Enable • Fig.2 Ramp-up-down Disable Output Options: This option sets up the three output pins OUT1 and OUT2 to send out different signals during voice playback. Four settings are allowed: aP8910A aP8921A OUT1 OUT2 OUT1 OUT2 Option 1 LED2 LED1 LED2 LED1 Option 2 STOP LED1 LED2 STOP Option 3 LED2 BUSY LED2 BUSY Option 4 - - STOP BUSY Note: Stop plus must be set to enable in order to have STOP plus to come out. Fig. 3 Ver 5.0 Output waveforms 6 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A Group Options User selectable options that affect each individual group are called Group Options. • • • • They are: Edge or Level trigger Unholdable or Holdable trigger Re-triggerable or non-retriggerable Stop pulse disable or enable Fig. 4 to Fig. 9 show the voice playback with different combination of triggering mode and the relationship between outputs and voice playback. Fig. 4 Level, Unholdable, Non-retriggerable Fig. 5 Fig. 6 Ver 5.0 Level Holdable SBT sequential trigger with Level Holdable and Unholdable 7 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A Fig. 7 Edge, Unholdable, Non-retrigger Fig. 8 Fig. 9 Ver 5.0 Edge, Holdable SBT sequential trigger with Edge Holdable and Unholdable 8 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A Overlap trigger is supported with Level/Unholdable trigger options: Fig. 10 Ver 5.0 Overlap trigger 9 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A TRIGGER MODES Two trigger modes, the KEY and CPU modes, are available for aP8921A/10A series which are determined by setting the EPORM programmable options during voice data compilation. For both trigger modes, up to 12 Voice Groups are being played back according to the following setting of trigger pins S1 to S4. Voice Group S1 S2 S3 S4 1 HIGH NC NC NC 2 NC HIGH NC NC 3 NC NC HIGH NC 4 NC NC NC HIGH 5 HIGH HIGH NC NC 6 NC HIGH HIGH NC 7 NC NC HIGH HIGH 8 HIGH NC NC HIGH 9 HIGH HIGH HIGH NC 10 NC HIGH HIGH HIGH 11 HIGH NC HIGH HIGH 12 HIGH HIGH NC HIGH Note: Where NC (open or no connection) should be replaced by a logic input LOW in CPU Parallel Trigger Mode. Key Trigger Mode With this trigger mode, up to 12 Voice Groups are triggered by setting S1 to S4 to HIHG or NC in different combinations. Each Voice Group can have its only independent trigger options (See Fig. 4, 5, 7 and 8 for trigger options definition). Voice Groups can also be triggered sequentially by setting SBT pin to HIGH. Ver 5.0 10 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A CPU Parallel Trigger Mode In this mode, S1 to S4 are set to HIGH or LOW according to the table above and followed by setting the SBT input pin to HIGH, the corresponding Voice Group will be triggered. Trigger options defined in Fig. 4, 5, 7 and 8 are valid for this mode. Fig. 11 CPU Parallel Trigger Mode Note that SBT pin cannot be used as Single Button Sequential trigger in this mode. acts as a Strobe input to clock-in the data input from S1 to S4 into the chip. Voice Groups address is determined by the Voice Group Trigger Table. In stead, it For example: S1..S4 = 1000 for Voice Group #1 S1..S4 = 0100 for Voice Group #2 ••• S1..S4= 1100 for Voice Group #5 ••• S1..S4 = 1110 for Voice Group #9 ••• S1..S4 = 1101 for Voice Group #12 Ver 5.0 11 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDD - VSS Rating -0.5 Unit ~ +6 V VIN VSS - 0.3<VIN<VDD/33 + 0.3 V VOUT VSS <VOUT<VDD/33 V T (Operating): -40 ~ +85 ℃ T (Junction) -40 ~ +125 ℃ T (Storage) -55 ~ +125 ℃ Ver 5.0 12 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A DC CHARACTERISTICS ( TA = 0 to 70℃, VDD = 4.5V, VSS = 0V ) Symbol Parameter Min. Typ. Max. Unit Condition VDD Operating Voltage 2.6 4.5 5.0 V ISB Standby current 1 5 µA I/O open IOP Operating current 15 mA I/O open VIH "H" Input Voltage 2.5 3.0 3.5 V VDD=3.0V VIL "L" Input Voltage -0.3 0 0.5 V VDD=3.0V IOL VOUT low O/P Current 110 mA Vout=0.3V, VDD=5.0V IOH VOUT high O/P Current -110 mA Vout=2.5V, VDD=5.0V ICO COUT O/P Current -3 mA VCOUT=1.0V IOH O/P high Current -8 mA VOH=2.5V, VDD=5.0V IOL O/P low Current 8 mA VOL=0.3V, VDD=5.0V ∆F/F Frequency Stability -5 +5 % Fosc(5.0V) – Fosc(4.0V) Fosc(4.5V) Ver 5.0 13 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A AC CHARACTERISTICS ( TA = 0 to 70℃ ℃, VDD = 4.5V, VSS = 0V, 8KHz sampling ) KEY Trigger Mode S1~S4, SBT COUT tKDD tKD tDN tUP tSTPD tSTPW STOP BUSY tBD tBH CPU Parallel Mode Addr. S1~S4 tASH SBT Ver 5.0 tASH tSBTW 14 Aug 23, 2011 Integrated Circuits Inc. Symbol Parameter tKD aP8921A/10A Min. Typ. Max. Unit Note Key trigger debounce time 16 ms 1 tKD Key trigger debounce time – retrigger 24 ms 1 tUP Ramp up time 0 128/Fs −− s 3 tDN Ramp down time 0 −− 256/Fs s 3 tKDD Key trigger delay after ramp down −− 0 −− ms tSTPD STOP pulse output delay time 256 µs tSTPW STOP pulse width 64 ms tBD BUSY signal output delay time 100 ns tBH BUSY signal output hold time 100 ns tASH Address set-up / hold time 100 ns tSBTW SBT stroke pulse width 65 µs 1 tLEDC LED flash frequency 3 Hz 2 1 Notes : 1. This parameter is inversely proportional to the sampling frequency. 2. This parameter is proportional to the sampling frequency. 3. Fs is sampling frequency in Hz Ver 5.0 15 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A OSCILLATOR RESISTANCE TABLE Sampling Frequency ROSC KΩ Ω Sampling Frequency KHz ROSC KΩ Ω 22 83 400 5.4 18 108 370 5.9 16 125 350 6.3 15 134 330 6.5 13 158 300 7.0 12 168 280 7.6 11 183 250 8.5 10 202 220 9.5 9 227 200 10.3 8 252 170 11.9 7 296 150 13.8 6 344 120 16.5 100 19.3 91 20.5 82 22.4 KHz Note: The data in the above tables are within 3% accuracy and measured at VDD = 4.5V. Oscillator frequency is subjected to IC lot to lot variation. FREQUENCY AGAINST VDD STABILITY aP8 9 2 1 A Freq en cy Stab il ity (Ro sc = 29 3 K Oh m) 10.0% 5.0% △F (%) 0.0% -5.0% -10.0% -15.0% -20.0% -25.0% -30.0% 5.50 5.00 4.50 4.00 3.50 3.00 2.60 VDD (V) Ver 5.0 16 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A TYPICAL APPLICATIONS Fig. 12 Using 4.5V Battery Note 1: Two capacitors Cin and Cout must be connected from VDD and V33 pins to VSS to stabilize the power supply to the chip. When small capacity battery, e.g. AG10, is used, Cin and Cout may need to be as large as 22uF. However, if Cin and Cout is too large, the power-up reset generated by 0.1uF at the RST pin may not be function because it takes longer time for both Cin and Cout to discharge. Note 2: 16 Ohm speaker will provide lauder and better sound quality when the VOUT speaker direct drive is used. Note 3: The value of the 390 Ohm base resistor should be modified according to different Vdd value, the kind of speaker and NPN transistor. Note 4: The VPP pin should be leave unconnected for playback. Ver 5.0 17 Aug 23, 2011 Integrated Circuits Inc. aP8921A/10A BONDING PADS aP8921A Fig. 12 Pad Locations Notes: 1. VPP pad should be not connected during voice playback. 2. Substrate should be connected to the Power GND. Ver 5.0 18 Aug 23, 2011