Integral IN74ACT299 8-bit bidirectional universal shift register with parallel i/o Datasheet

IN74ACT299
8-BIT BIDIRECTIONAL UNIVERSAL
SHIFT REGISTER WITH PARALLEL I/O
High-Speed Silicon-Gate CMOS
•
•
•
•
The IN74ACT299 is identical in pinout to the LS/ALS299,
HC/HCT299. The IN74ACT299 may be used as a level converter
for interfacing TTL or NMOS outputs to High Speed CMOS inputs.
The IN74ACT299 features a multiplexed parallel input/output
data port to achieve full 8-bit handling in a 20 pin package. Due to
the large output drive capability and the 3-state feature, this
device is ideally suited for interface with bus lines in a busoriented system.
Two Mode-Select inputs and two Output Enable inputs are
used to choose the mode of operation as listed in the Function
Table. Synchronous parallel loading is accomplished by taking
both Mode-Select lines, S1 and S2, high. This places the outputs in
the high-impedance state, which permits data applied to the data
port to be clocked into the register. Reading out of the register can
be accomplished when the outputs are enabled. The active-low
asynchronous Reset overrides all other inputs.
• TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
Outputs Source/Sink 24 mA
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
1
ORDERING INFORMATION
IN74ACT299N Plastic
IN74ACT299DW SOIC
TA = -40° to 85° C for all
packages
PIN ASSIGNMENT
IN74ACT299
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
VOUT
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
mA
±20
IOUT
DC Output Sink/Source Current, per Pin
mA
±50
ICC
DC Supply Current, VCC and GND Pins
mA
±50
PD
Power Dissipation in Still Air, Plastic DIP+
750
mW
SOIC Package+
500
Tstg
Storage Temperature
-65 to +150
°C
260
TL
Lead Temperature, 1 mm from Case for 10
°C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage (Referenced to GND)
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to
GND)
TJ
Junction Temperature (PDIP)
TA
Operating Temperature, All Package Types
IOH
Output Current - High
IOL
Output Current - Low
t r, tf
Input Rise and Fall Time * VCC =4.5 V
VCC =5.5 V
(except Schmitt Inputs)
*
VIN from 0.8 V to 2.0 V
Min
4.5
0
-40
0
0
Max
5.5
VCC
Unit
V
V
140
+85
-24
24
10
8.0
°C
°C
mA
mA
ns/V
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and
VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
VCC). Unused outputs must be left open.
2
IN74ACT299
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
Guaranteed
VCC
Limits
Symbol
Parameter
Test Conditions
V
25 °C -40°C to
85°C
VIH
Minimum
High- VOUT= 0.1 V or VCC-0.1 4.5
2.0
2.0
Level
Input V
5.5
2.0
2.0
Voltage
VIL
Maximum Low - VOUT= 0.1 V or VCC-0.1 4.5
0.8
0.8
Level
Input V
5.5
0.8
0.8
Voltage
VOH
Minimum
High- IOUT ≤ -50 µA
4.5
4.4
4.4
Level
Output
5.5
5.4
5.4
Voltage
*
VIN=VIH
or
VIL
3.76
3.86
IOH=-24
mA 4.5
4.76
4.86
5.5
IOH=-24 mA
VOL
Maximum
Low- IOUT ≤ 50 µA
4.5
0.1
0.1
Level
Output
5.5
0.1
0.1
Voltage
*
VIN=
VIH
or
VIL
0.44
0.36
IOL=24
mA 4.5
0.44
0.36
5.5
IOL=24 mA
IIN
Maximum Input VIN=VCC or GND
5.5
±0.1
±1.0
Leakage Current
5.5
1.5
Additional Max. VIN=VCC - 2.1 V
∆ICCT
ICC/Input
IOZ
Maximum Three- VIN (OE)= VIH or VIL 5.5
±0.6
±6.0
State
Leakage VIN =VCC or GND
Current
VOUT =VCC or GND
VOLD=1.65 V Max
IOLD
+Minimum
5.5
75
Dynamic Output
Current
VOHD=3.85 V Min
IOHD
+Minimum
5.5
-75
Dynamic Output
Current
VIN=VCC or GND
ICC
Maximum
5.5
8.0
80
Quiescent Supply
Current
(per Package)
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
3
Unit
V
V
V
V
µA
mA
µA
mA
mA
µA
IN74ACT299
AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
Symbol
Parameter
Unit
25 °C
-40°C to
85°C
Min Max Min
Max
fmax
Maximum Clock Frequency (Figure 1)
120
110
MHz
tPLH
Propagation Delay, Clock to QA’ or QH’ 4.0 12.5 3.0
14.0
ns
(Figure 1)
tPHL
Propagation Delay, Clock to QA’ or QH’ 4.0 13.5 3.5
15.0
ns
(Figure 1)
tPLH
Propagation Delay, Clock to QA thru QH 4.5 12.5 4.5
13.5
ns
(Figure 1)
tPHL
Propagation Delay, Clock to QA thru QH 5.0 15.0 4.5
16.5
ns
(Figure 1)
tPHL
Propagation Delay, Reset to QA’ or QH’ 4.0 15.0 4.0
18.0
ns
(Figure 2)
tPHL
Propagation Delay, Reset to QA thru QH 4.0 14.5 3.5
17.5
ns
(Figure 2)
tPZH
Propagation Delay , OE1, OE2 to QA thru 2.5 12.0 1.5
13.0
ns
QH (Figure 3)
tPZL
Propagation Delay , OE1, OE2 to QA thru 2.0 12.0 1.5
13.5
ns
QH (Figure 3)
tPHZ
Propagation Delay , OE1, OE2 to QA thru 2.0 12.5 2.0
13.5
ns
QH (Figure 3)
tPLZ
Propagation Delay , OE1, OE2 to QA thru 2.5 11.5 2.0
12.5
ns
QH (Figure 3)
CIN
Maximum Input Capacitance
4.5
4.5
pF
CPD
Typical @25°C,VCC=5.0 V
170
Power Dissipation Capacitance
pF
TIMING REQUIREMENTS(VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)
Symbo
l
tsu
tsu
tsu
th
th
th
trec
tw
tw
Parameter
Minimum Setup Time, Mode Select S1 or S2 to Clock
(Figure 4)
Minimum Setup Time, Data Inputs PA thru PH to Clock
(Figure 4)
Minimum Setup Time, Data Inputs SA, SH to Clock (Figure 4)
Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure
4)
Minimum Hold Time, Clock to Data Inputs PA thru PH (Figure
4)
Minimum Hold Time, Clock to Data Inputs SA, SH (Figure 4)
Minimum Recovery Time, Reset Inactive to Clock (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
Minimum Pulse Width, Reset (Figure 2)
4
Guaranteed
Limits
25 °C
-40°C to
85°C
5.0
5.5
Unit
ns
4.0
4.5
ns
4.5
1.0
5.0
1.0
ns
ns
1.0
1.0
ns
1.0
1.5
4.0
3.5
1.0
1.5
4.5
3.5
ns
ns
ns
ns
IN74ACT299
FUNCTION TABLE
Inputs
Response
Mode Rese Mode
Output Clock Serial PA/ PB/ PC/ PD/ PE/ PF/ PG/ PH/ QA’ QH’
t
Select Enables
Inputs QA QB QC QD QE QF QG QH
S2 S1 OE1 OE2
DA DH
Reset
L
X L
L
L
X
X X L L L L L L L L L
L
L
L X
L
L
X
X X L L L L L L L L L
L
L
H H
X
X
X
X X
QA through QH=Z
L
L
Shift
H
L H
H
X
D X Shift Right: QA through QH=Z; D QG
Right
DA
FA; FA
FB; etc
H
L H
X
H
D X Shift Right: QA through QH=Z; D QG
DA
FA; FA FB; etc
H
L H
L
L
D X
Shift Right: DA FA =QA;
D QG
FA
FB =QB; etc
Shift
H
H L
H
X
X D Shift Left: QA through QH=Z; QB D
Left
DH
FH; FH
FG; etc
H
H L
X
H
X D Shift Left: QA through QH=Z; QB D
DH
FH; FH
FG; etc
H
H L
L
L
X D
Shift Left: DH
FH =QH;
QB D
FH
FG =QG; etc
Parallel H
H H
X
X
X X
Parallel Load:PN
FN
PA PH
Load
Hold
H
L L
H
X
X
X X Hold: QA through QH=Z; FN=FN PA PH
H
L L
X
H
X
X X Hold: QA through QH=Z; FN=FN PA PH
H
L L
L
L
X
X X
Hold: QN =QH
PA PH
Z = high impedance
D = data on serial input
F = flip-flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the
highimpedance state; however, sequential operation or clearing of the register is not affected.
5
IN74ACT299
Figure 1. Switching Waveform
Figure 2. Switching Waveform
Figure 3. Switching Waveform
Figure 4. Switching Waveform
6
IN74ACT299
EXPANDED LOGIC DIAGRAM
7
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