CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate Multiple Output Frequencies Low Jitter for Clock Distribution Generates the Following Clocks: – VIDCLK 74.175824 MHz/54 MHz (Buffered) – AUDCLK 16.9344 MHz/12.288 MHz – CPUCLK 64 MHz – ASICCLK 32 MHz – USBCLK 48 MHz – MCCLK 38.4 MHz/19.2 MHz/12 MHz Operates From Single 3.3-V Supply Low Peak-to-Peak Period Jitter (150 ps Max) PLLs Are Powered Down, if No Valid REF_IN Clock (< 5 MHz) is Detected or the VDD is Below 2 V PLL Loop Filter Components Integrated Packaged in TSSOP (PW) 20-Pin Package Industrial Temperature Range -40°C to 85°C Applications APPLICATIONS • Digital Television With a Memory Card Interface DESCRIPTION The CDC5806 is a clock generator which synthesizes video clocks, audio clocks, CPU clock, ASIC clock, USB clock, and a memory card clock from a 54-MHz system clock. Three phase-locked loops (PLLs) are used to generate the different frequencies from the system clock. On-chip loop filters and internal feedback eliminate the need for external components. Since the CDC5806 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLLs. The PLL stabilization time begins after the reference clock input has a stable phase and frequency. The device operates from a single 3.3-V supply voltage. The CDC5806 device is characterized for operation from -40°C to 85°C. PW PACKAGE (TOP VIEW) VIDSEL REF_IN PLL1VDD VIDCLK PLL1VSS PLL2VDD AUDCLK PLL2VSS AUDSEL MCSEL 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ASICCLK PLL3VDD PLL3VSS CPUCLK PLL3VDD PLL3VSS USBCLK PLL3VDD PLL3VSS MCCLK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM PLL1VDD PLL2VDD PLL3VDD 100 kΩ VIDSEL 100 kΩ VIDCLK MUX REF_IN LVCMOS PLL 1 74.175824 MHz AUDCLK LVCMOS 100 kΩ AUDSEL CPUCLK 100 kΩ Power /3 LVCMOS /6 LVCMOS /4 LVCMOS PLL 2 12.288/16.9344 MHz Down Logic PLL3VDD PLL 3 192 MHz 100 kΩ ASICCLK USBCLK MCSEL /5 100 kΩ MCCLK LVCMOS /10 /16 PLL1VSS 2 PLL2VSS PLL3VSS MUX CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 Terminal Functions TERMINAL NAME NO TYPE DESCRIPTION REF_IN 2 I LVCMOS Reference frequency input VIDSEL 1 I LVCMOS VIDSEL select input for VIDCLK. It selects between 74.175824 MHz from PLL1 and buffered input frequency of 54 MHz, 100k||100k pull to mid-level. AUDSEL 9 I LVCMOS AUDSEL select input for AUDCLK. It selects between 16.9344 MHz and 12.288 MHz from PLL2, 100k||100k pull to mid level. MCSEL 10 I LVCMOS MCSEL select input for MCCLK. It selects from 38.4 MHz, 19.2 MHz, and 12 MHz from PLL3, 100k||100k pull to mid level. VIDCLK 4 O LVCMOS VIDCLK output 74.175824 MHz or 54 MHz AUDCLK 7 O LVCMOS AUDCLK output 16.9344 MHz or 12.288 MHz CPUCLK 17 O LVCMOS CPUCLK output 64 MHz ASICCLK 20 O LVCMOS ASICCLK output 32 MHz USBCLK 14 O LVCMOS USBCLK output 48 MHz MCCLK 4 O LVCMOS MCCLK output 38.4 MHz / 19.2 MHz / 12 MHz VDD_PLL1 3 Power 3.3-V supply for PLL1 and VIDCLK VDD_PLL2 6 Power 3.3-V supply for PLL2 and AUDCLK VDD_PLL3 13, 16, 19 Power 3.3-V supply for PLL3 and CPUCLK, ASICCLK, USBCLK, and MCCLK VSS_PLL1 5 Ground Ground for PLL1 and VIDCLK VSS_PLL2 8 Ground Ground for PLL2 and AUDCLK VSS_PLL3 12, 15, 18 Ground Ground for PLL3 and CPUCLK, ASICCLK, USBCLK, and MCCLK FUNCTIONAL DESCRIPTION OF THE LOGIC Table 1. Select Function for Video, Audio, CPU, ASIC, and USB Clocks VIDSEL AUDSEL VIDCLK AUDCLK CPUCLK ASICCLK USBCLK Unit L L L M 54 (buffered) 12.288 64 32 48 MHz Reserved Reserved 64 32 48 L MHz H 54 (buffered) 16.9344 64 32 48 MHz M L Reserved Reserved 64 32 48 MHz M M Reserved Reserved REFCLK/3 REFCLK/6 REFCLK/4 MHz M H Reserved Reserved 64 32 48 MHz H L 74.175824 12.288 64 32 48 MHz H M Reserved Reserved 64 32 48 MHz H H 74.175824 16.9344 64 32 48 MHz Table 2. Select Function for MC Clock MCSEL MCCLK MCCLK if VIDSEL = M and AUDSEL = M UNIT H 12 MHz REFCLK/16 MHz M 38.4 MHz REFCLK/5 MHz L 19.2 MHz REFCLK/10 MHz 3 CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted) (1) Supply voltage range, VDD 0.5 V to 4.6 V Input voltage range, VI (2) 0.5 V to VDD + 0.5 V Output voltage range, VO (2) 0.5 V to VDD + 0.5 V ±20 mA Input current (VI < 0, VI>VDD) Continuous output current, IO ±50 mA Package thermal impedance,ΘJA (3): TSSOP20 package 104 C/W Storage temperature range Tstg (1) 65°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51 (no airflow condition) and JEDEC2S1P (high-k board). (2) (3) RECOMMENDED OPERATING CONDITIONS VDD Supply voltage TA Operating free-air temperature VIL Low-level input voltage REF_IN VI Input voltage threshold REF_IN thresh MIN NOM MAX 3 3.3 3.6 V 85 °C 0.3 VDD V -40 0.5 VDD UNIT V VIH High-level input voltage REF_IN VIL(L) Three level input low for control inputs 0.7 VDD V VIM(M) Three level input mid for control inputs 0.4 VDD VIH(H) Three level input high for control inputs 0.87 VDD IOH High-level output current LVCMOS -8 mA IOL Low-level output current LVCMOS 8 mA VI Input voltage range LVCMOS 0 3.6 V CL Output load LVCMOS 5 10 pF 0.13 VDD V 0.6 VDD V V TIMING REQUIREMENTS over recommended ranges of supply voltage, load, and operating free-air temperature PARAMETER MIN NOM MAX UNIT REF_IN REQUIREMENTS fCLK_IN LVCMOS REF_IN clock input frequency tr / tf Rise and fall time REF_IN signal (20% to 80%) dutyREF Duty cycle of REF_IN (VDD/2) 54 MHz 4 40% ns 60% AUDSEL, VIDSEL, MCSEL REQUIREMENTS tr / tf Rise and fall time (20% to 80%) t1 Transitional time between AUDSEL and VIDSEL control pins (1) (1) 4 4 6 ns ns If VIDSEL and AUDSEL are switched from from one state to another state at the same time, then the CPUCLK, ASICCLK, USBCLK, or MCCLK are affected. This is due to the selected reserved mode with VIDSEL = M and AUDSEL = M. This mode causes the PLL3 to be bypassed and the REFCLK will be seen with the appropriate divider ratios at the correspondent outputs. CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 DEVICE CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OVERALL ICC Supply current Test load ICC(ST) Standby current VPUC 35 fIN = 0 MHz, VDD = 3.6 V Supply voltage threshold for power up control circuit 45 mA 1.1 mA 2 V LVCMOS VIK LVCMOS input voltage VDD = 3 V, II = –18 mA –1.2 V II REF_IN input current VI = 0 V or VDD ±5 µA II SELECT input current VI = 0 V or VDD ±55 µA VOH High-level output voltage VDD = MIN to MAX, IOH = –5 mA VOL Low-level output voltage VDD = MIN to MAX, IOL= 5 mA VDD – 0.4 VDD = 3 V, VO = VDD – 0.4 V IOH High-level output current V 0.4 VDD = 3.3 V, VO = 1.65 V –35 VDD = 3.6 V, VO = 0.4 V Low-level output current mA –75 VDD = 3 V, VO = 0.4 V IOL V –5 5 VDD = 3.3 V, VO = 1.65 V 35 VDD = 3.6 V, VO = VDD – 0.4V mA 75 AC CI Input capacitance (Ref_IN) ferr Output accuracy VIDCLK, CPUCLK, ASICCLK, USBCLK, MCCLK (38.4 MHz, 19.2 MHz, 12 MHz) See Note (1) ±1 ppm ferr Output accuracy AUDCLK (16.9344 MHz, 12.288 MHz) See Note (1) ±40 ppm tL PLL start up lock time See Figure 2 0.5 ms tL(ω) PLL lock time after frequency change on AUDCLK See Figure 2 0.5 ms odc Duty cycle for MCCLK Threshold = VDD/2 47% 50% 53% odc Duty cycle for VIDCLK, AUDCLK, CPUCLK, ASICCLK, USBCLK Threshold = VDD/2 45% 50% 55% tr/tf Rise and fall time of the output 20%–80% of VO tjit(per) (1) Peak-to-peak period jitter for 2 pF 2 VIDCLK (74.175824 MHz) 75 150 CPUCLK (64 MHz) 60 150 USBCLK (48 MHz) 65 150 MCCLK (38.4 MHz) 65 150 60 150 MCCLK (19.2 MHz) 70 150 AUDCLK (16.9344 MHz) 75 150 AUDCLK (12.288 MHz) 85 150 MCCLK (12 MHz) 65 150 ASICCLK (32 MHz) 10,000 cycles ns ps This parameter is assured by design as a result of the chosen settings of the internal dividers in the PLL's. 5 CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 VDD R = 1 kΩ From Output of DUT R = 1 kΩ CL = 10 pF Figure 1. LVCMOS Output Test Load tL Lock-Up Time fAUDCLK /MHz tL(ω) Lock Time ftarget < 1% ftarget < 1% Time/ms VDD /V VPUC Time/ms fREF_IN /MHz f = 54 MHz Time/ms AUDSEL /V Time/ms Figure 2. Timing Diagram of PLL Lock Time of Audio Clock 6 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) CDC5806PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDC5806 CDC5806PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDC5806 CDC5806PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDC5806 CDC5806PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CDC5806 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-May-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDC5806PWR Package Package Pins Type Drawing TSSOP PW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-May-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDC5806PWR TSSOP PW 20 2000 333.2 345.9 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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