FEDR27V6452L-002-03 Issue Date: Oct. 01, 2008 MR27V6452L 4M–Word × 16–Bit or 8M–Word × 8–Bit Page Mode P2ROM FEATURES · 4,194,304-word × 16-bit / 8,388,608-word × 8-bit electrically switchable configuration · Page size of 8-word x 16-Bit or 16-word x 8-Bit · 3.0 V to 3.6 V power supply · Random Access time.....................90 ns MAX · Page Access time ..........................30 ns MAX · Operating current ..........................50 mA MAX (5MHz) · Standby current .............................10 µA MAX · Input/Output TTL compatible · Three-state output PACKAGES MR27V6452L-xxxMA ·MR27V6452L-xxxTN MR27V6452L-xxxTA 44-pin plastic SOP (SOP44-P-600-1.27-K) 48-pin plastic TSOP (TSOP I 48-P-1220-0.50-1K) 56-pin plastic TSOP (TSOP I 56-P-1420-0.50-K) P2ROM ADVANCED TECHNOLOGY P2ROM stands for Production Programmed ROM. This exclusive LAPIS Semiconductor technology utilizes factory test equipment for programming the customers code into the P2ROM prior to final production testing. Advancements in this technology allows production costs to be equivalent to MASKROM and has many advantages and added benefits over the other non-volatile technologies, which include the following; · Short lead time, since the P2ROM is programmed at the final stage of the production process, a large P2ROM inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive lead-time and minimize liability as a custom product. · No mask charge, since P2ROMs do not utilize a custom mask for storing customer code, no mask charges apply. · No additional programming charge, unlike Flash and OTP that require additional programming and handling costs, the P2ROM already has the code loaded at the factory with minimal effect on the production throughput. The cost is included in the unit price. · Custom Marking is available at no additional charge. · Pin Compatible with Mask ROM and some FLASH products. 1/11 FEDR27V6452L-002-03 MR27V6452L / P2ROM PIN CONFIGURATION (TOP VIEW) A21 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# D0 D8 D1 D9 D2 D10 D3 D11 44 A20 43 A19 1 2 42 A8 41 A9 3 4 40 A10 39 A11 5 6 38 A12 37 A13 7 8 36 A14 35 A15 9 10 34 A16 33 BYTE# 11 12 32 VSS 31 D15/A–1 13 14 15 30 D7 29 D14 16 28 D6 27 D13 17 18 26 D5 25 D12 19 20 24 D4 23 VCC 21 22 44SOP A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 NC NC A21 NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 2 47 BYTE# 3 46 VSS 4 45 D15/A–1 5 44 D7 6 43 D14 7 42 D6 8 41 D13 9 40 D5 10 39 D12 11 38 D4 12 37 VCC 13 36 D11 14 35 D3 15 34 D10 16 33 D2 17 32 D9 18 31 D1 19 30 D8 20 29 D0 21 28 OE# 22 27 VSS 23 26 CE# 24 25 A0 48TSOP(Type-I) NC NC A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 NC NC A21 NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC 1 56 NC 2 55 NC 3 54 A16 4 53 BYTE# 5 52 VSS 6 51 D15/A-1 7 50 D7 8 49 D14 9 48 D6 10 47 D13 11 46 D5 12 45 D12 13 44 D4 14 43 VCC 15 42 D11 16 41 D3 17 40 D10 18 39 D2 19 38 D9 20 37 D1 21 36 D8 22 35 D0 23 34 OE# 24 33 VSS 25 32 CE# 26 31 A0 27 30 NC 28 29 NC* 56TSOP(Type-I) (Unit: mm) *:Different from FLASH products. 2/11 FEDR27V6452L-002-03 MR27V6452L / P2ROM BLOCK DIAGRAM A–1 OE# CE OE BYTE# Row Decoder CE# Memory Cell Matrix 4M × 16-Bit or 8M × 8-Bit Column Decoder A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 Address Buffer × 8/× 16 Switch Multiplexer Output Buffer D0 D2 D1 D4 D3 D6 D5 D8 D7 D10 D9 D12 D11 D14 D13 D15 In 8-bit output mode, these pins are placed in a high-Z state and pin D15 functions as the A-1 address pin. PIN DESCRIPTIONS Pin name Functions D15 / A–1 Data output / Address input A0 to A21 Address inputs D0 to D14 Data outputs CE# Chip enable input OE# Output enable input BYTE# Word / Byte select input VCC Power supply voltage VSS Ground NC No connect 3/11 FEDR27V6452L-002-03 MR27V6452L / P2ROM FUNCTION TABLE Mode CE# OE# BYTE# Read (16-Bit) L L H Read (8-Bit) L L L Output disable L H D0 to D7 D8 to D14 DOUT Hi–Z D15/A–1 DOUT H L/H Hi–Z 3.3 V L H ∗ H Standby VCC ∗ Hi–Z L ∗ ∗: Don’t Care (H or L) ABSOLUTE MAXIMUM RATINGS Parameter Symbol Operating temperature under bias Ta Storage temperature Condition — Tstg Value Unit 0 to 70 °C –55 to 125 °C –0.5 to VCC+0.5 V –0.5 to VCC+0.5 V Input voltage VI Output voltage VO Power supply voltage VCC –0.5 to 5 V Power dissipation per package PD Ta = 25°C 1.0 W Output short circuit current IOS — 10 mA relative to VSS RECOMMENDED OPERATING CONDITIONS Parameter Symbol VCC power supply voltage VCC Input “H” level VIH Input “L” level VIL Condition Typ. 3.0 — 3.6 V 2.2 — VCC+0.5∗ V –0.5∗∗ — 0.6 V VCC = 3.0 to 3.6 V Max. (Ta = 0 to 70°C) Unit Min. Voltage is relative to VSS. ∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns. ∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns. PIN CAPACITANCE Parameter Symbol Input CIN1 BYTE# CIN2 Output COUT Condition VI = 0 V VO = 0 V Min. (VCC = 3.3 V, Ta = 25°C, f = 1 MHz) Typ. Max. Unit — — 12 — — 200 — — 12 pF 4/11 FEDR27V6452L-002-03 MR27V6452L / P2ROM ELECTRICAL CHARACTERISTICS DC Characteristics (VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C) Min. Typ. Max. Unit Symbol Condition Input leakage current ILI VI = 0 to VCC — — 10 μA Output leakage current ILO VO = 0 to VCC — — 10 μA ICCSC CE# = VCC — — 10 μA ICCST CE# = VIH — — 1 mA — — 50 mA — 2.2 — VCC+0.5∗ V Parameter VCC power supply current (Standby) VCC power supply current (Read) ICCA Input “H” level VIH CE# = VIL, OE# = VIH f=5MHz Input “L” level VIL — –0.5∗∗ — 0.6 V Output “H” level VOH IOH = –1 mA 2.4 — — V Output “L” level VOL IOL = 2 mA — — 0.4 V Voltage is relative to VSS. ∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns. ∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns. AC Characteristics Parameter Symbol Address cycle time Condition (VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C) Min. Max. Unit tC — 90 — ns Address access time tACC CE# = OE# = VIL — 90 ns Page cycle time tPC — 30 — ns Page access time tPAC — — 30 ns CE# access time tCE OE# = VIL — 90 ns OE# access time Output disable time Output hold time tOE CE# = VIL — 30 ns tCHZ OE# = VIL 0 20 ns tOHZ CE# = VIL 0 20 ns tOH CE# = OE# = VIL 0 — ns Measurement conditions Input signal level --------------------------------- 0 V/3 V Input timing reference level -------------------- 1/2Vcc Output load ---------------------------------------- 50 pF Output timing reference level ----------------- 1/2Vcc Output load Output 44SOP 5/11 FEDR27V6452L-002-03 MR27V6452L / P2ROM TIMING CHART (READ CYCLE) Random Access Mode Read Cycle tC tC Address tOH tACC tCE CE# tCHZ tOE tOH OE# tOHZ tACC Valid Data Dout Valid Data Hi-Z Hi-Z Page Access Mode Read Cycle tC A3 to A21 tPC tPC A-1 to A2 (Byte mode) A0 to A2 (Word mode) tCE tOH CE# tOE tCHZ OE# tACC tPAC tPAC tOHZ Dout Hi-Z Hi-Z 6/11 FEDR27V6452L-002-03 MR27V6452L / P2ROM PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 7/11 FEDR27V6452L-002-03 MR27V6452L / P2ROM (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 8/11 FEDR27V6452L-002-03 MR27V6452L / P2ROM (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 9/11 FEDR27V6452L-002-03 MR27V6452L / P2ROM REVISION HISTORY Document Page Date Previous Edition Current Edition FEDR27V6452L-02-01 Sep. 21, 2005 – – FEDR27V6452L-02-02 Oct, 18,2005 1 1, 6 FEDR27V6452L-02-03 Jun, 07,2007 1 1,2,5,9 FEDR27V6452L-002-03 Oct,1,2008 – – No. Description Final edition 1 Add MR27V6452L-xxxMA Add MR27V6452L-xxxTA tC, tACC, tCE =100ns->90ns Changed company logo and name to OKI SEMICONDUCTOR 10/11 FEDR27V6452L-002-03 MR27V6452L / P2ROM NOTICE No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. 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