Intersil ISL80103IR15Z High performance 2a and 3a linear regulator Datasheet

ISL80102, ISL80103
Features
The ISL80102 and ISL80103 are low voltage,
high-current, single output LDOs specified for 2A and 3A
output current, respectively. These LDOs operate from
input voltages of 2.2V to 6V and are capable of providing
output voltages of 0.8V to 5V on the adjustable VOUT
versions. Fixed output voltage options are available in
1.5V, 1.8V, 2.5V, 3.3V and 5V. Other custom voltage
options available upon request.
• Stable with all Capacitor Types (Note 11)
For applications that demand in-rush current less than
the current limit, an external capacitor on the soft start
pin provides adjustment. The ENABLE feature allows the
part to be placed into a low quiescent current shutdown
mode. A sub-micron BiCMOS process is utilized for this
product family to deliver the best in class analog
performance and overall value.
• 2A and 3A Output Current Ratings
• 2.2V to 6V Input Voltage Range
• ±1.8% VOUT Accuracy Guaranteed Over Line, Load
and TJ = -40°C to +125°C
• Very Low 120mV Dropout Voltage at 3A (ISL80103)
• Fixed and Adjustable VOUT Versions
• Very Fast Transient Response
• Excellent 62dB PSRR
• 100µVRMS Output Noise
• Power-Good Output
• Adjustable In-Rush Current Limiting
These CMOS LDOs will consume significantly lower
quiescent current as a function of load over bipolar LDOs,
which translates into higher efficiency and the ability to
consider packages with smaller footprints. Quiescent
current is modestly compromised to enable a leading
class fast load transient response, and hence a lower
total AC regulation band for an LDO in this category.
• Short Circuit and Over-Temperature Protection
• Available in a 10 Ld DFN (now), 5Ld TO220 and 5Ld
TO263 (soon)
Applications*(see page 14)
• Servers
• Telecommunications and Networking
• Medical Equipment
• Instrumentation Systems
• Routers and Switchers
Typical Application
ISL80102, ISL80103
1.8V ±1.8%
2.5V ±10%
9
VIN
CIN
10
VIN
VOUT
VIN
VOUT
1
2
VOUT
COUT
10µF
10µF
RPG
ON
7
OFF
6
*CSS
SENSE
ENABLE
3
4
SS
PG
100kΩ
PGOOD
GND
5
*CSS is optional, (see Note 12) on page 5.
March 22, 2010
FN6660.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL80102, ISL80103
High Performance 2A and 3A Linear Regulators
ISL80102, ISL80103
Block Diagram
VIN
R5
10µA
10µA
M4
M5
+
R8
R7
EN
EN
+
R2
R4
EN
VOUT
SENSE
ADJ
-
PG
-
500mV +
-
V TO I
M8
500mV
R1
+
M7
SS
M1
POWER PMOS
IL
LEVEL
SHIFT
M6
-
R9
M3
EN
ENABLE
IL/10,000
M2
+
+
485mV -
EN
*R3
GND
*R3 is open for ADJ versions.
Ordering Information
PART NUMBER
(Notes 1, 2, 4)
PART
MARKING
VOUT VOLTAGE
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG
DWG. #
ISL80102IRAJZ
DZJA
ADJ
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR15Z
DZMA
1.5V (Note 3)
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR18Z
DZNA
1.8V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR25Z
DZPA
2.5V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR33Z
DZRA
3.3V (Note 3)
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80102IR50Z
DZSA
5.0V (Note 3)
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IRAJZ
DZAA
ADJ
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR15Z
DZDA
1.5V (Note 3)
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR18Z
DZEA
1.8V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR25Z
DZFA
2.5V
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR33Z
DZGA
3.3V (Note 3)
-40 to +125
10 Ld 3x3 DFN
L10.3x3
ISL80103IR50Z
DZHA
5.0V (Note 3)
-40 to +125
10 Ld 3x3 DFN
L10.3x3
NOTES:
1. Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. The 1.5V, 3.3V and 5V fixed output voltages will be released in the future. Please contact Intersil Marketing for more details.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL80102, ISL80103. For more information on
MSL please see tech brief TB363.
2
FN6660.1
March 22, 2010
ISL80102, ISL80103
Pin Configuration
ISL80102, ISL80103
(10 LD 3X3 DFN)
TOP VIEW
VOUT
1
10 VIN
VOUT
2
9 VIN
SENSE/ADJ
3
8 DNC
PG
4
7 ENABLE
GND
5
6 SS
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2
VOUT
3
SENSE/ADJ
4
PG
5
GND
6
SS
7
ENABLE
8
DNC
Do not connect this pin to ground or supply. Leave floating.
9, 10
VIN
Input supply pin.
Output voltage pin.
Remote voltage sense for internally fixed VOUT options. ADJ pin for externally set VOUT.
VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Must be grounded if
not used.
GND pin.
External cap adjusts in-rush current.
VIN independent chip enable. TTL and CMOS compatible.
EPAD
EPAD at ground potential. Soldering it directly to GND plane is optional.
Typical Application
ISL80102, ISL80103
1.8V
2.5V ±10%
VIN
9
CIN
10
VOUT
VIN
VOUT
VIN
1
VOUT
COUT
2
10µF
10µF
RPG
100kΩ
R1
10kΩ
7
EN
OPEN DRAIN COMPATIBLE
6
*CSS
PG
4
PGOOD
ENABLE
**CPB
SS
GND
ADJ
3
1500pF
5
R3
2.61kΩ
R4
1.0kΩ
*CSS is optional, (see Note 12) on page 5.
**CPB is optional. See “Functional Description” on page 12 for more information.
FIGURE 1. TYPICAL APPLICATION DIAGRAM
3
FN6660.1
March 22, 2010
ISL80102, ISL80103
Absolute Maximum Ratings (Note 7)
Thermal Information
VIN relative to GND . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
VOUT relative to GND . . . . . . . . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, SENSE/ADJ, SS
Relative to GND. . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance (Typical)
Recommended Operating Conditions
θJA (°C/W) θJC (°C/W)
10 Ld 3x3 DFN Package (Notes 5, 6)
48
4
Maximum Junction Temperature (Plastic Package). . . +150°C
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(Note 10)
Junction Temperature Range (TJ) . .
VIN relative to GND . . . . . . . . . . . .
VOUT range . . . . . . . . . . . . . . . . . .
PG, ENABLE, SENSE/ADJ, SS relative
PG sink current . . . . . . . . . . . . . . .
. . . . . -40°C to +125°C
. . . . . . . . . 2.2V to 6V
. . . . . . . . 800mV to 5V
to GND . . . . . 0V to 6V
. . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
Electrical Specifications
PARAMETER
Unless otherwise noted, all parameters are established over the following specified
conditions: VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, ILOAD = 0A
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Functional Description” on page 12 and Tech Brief TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
Pulse load techniques used by ATE to ensure TJ = TA defines established limits.
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNITS
DC CHARACTERISTICS
DC Output Voltage Accuracy
VOUT
VOUT Options: 1.8V.
VIN =2.2V; ILOAD = 0A
VOUT Options: 1.8V.
2.2V < VIN < 3.6V; 0A < ILOAD < 3A
0.5
-1.8
VOUT Options: 2.5V
VIN =VOUT + 0.4V; ILOAD = 0A
Feedback Pin (ADJ Version)
VFB
DC Input Line Regulation
ΔVOUT/ΔVIN
VOUT Options: 2.5V
VOUT + 0.4V < VIN < 6V; 0A < ILOAD < 3A
-1.8
2.2V < VIN < 6V, 0A < ILOAD < 3A
491
VOUT + 0.4V < VIN < 3.6V, VOUT = 1.8V
%
500
509
mV
0.1
0.4
%
0.1
0.8
%
0A < ILOAD < 2A, All voltage options
-0.6
%
ISHDN
VDO
4
-1.8
%
IQ
Dropout Voltage (Note 9)
%
-0.8
VADJ = 0.5V
Ground Pin Current in
Shutdown
%
ΔVOUT/ΔIOUT 0A < ILOAD < 3A, All voltage options
Feedback Input Current
Ground Pin Current
1.8
0.5
VOUT + 0.4V < VIN < 6V, VOUT = 2.5V
DC Output Load Regulation
%
0.01
1
µA
ILOAD = 0A, 2.2V < VIN < 6V
7.5
9
mA
ILOAD = 3A, 2.2V < VIN < 6V
8.5
12
mA
ENABLE Pin = 0.2V, VIN = 5V
0.4
ENABLE Pin = 0.2V, VIN = 6V
3.3
16
µA
ILOAD = 3A, VOUT = 2.5V, 10 LD 3x3 DFN
120
185
mV
ILOAD = 2A, VOUT = 2.5V, 10 LD 3x3 DFN
81
125
mV
µA
FN6660.1
March 22, 2010
ISL80102, ISL80103
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified
conditions: VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, ILOAD = 0A
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Functional Description” on page 12 and Tech Brief TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
Pulse load techniques used by ATE to ensure TJ = TA defines established limits.
PARAMETER
SYMBOL
Output Short Circuit Current
(3A Version)
ISC
Thermal Shutdown
Hysteresis (Rising Threshold)
MIN
MAX
(Note 8) TYP (Note 8) UNITS
VOUT = 0V, VOUT + 0.4V < VIN < 6V
5.0
A
VOUT = 0V, VOUT + 0.4V < VIN < 6V
2.8
A
TSD
VOUT + 0.4V < VIN < 6V
160
°C
TSDn
VOUT + 0.4V < VIN < 6V
15
°C
PSRR
f = 1kHz, ILOAD = 1A; VIN = 2.2V
55
dB
f = 120Hz, ILOAD = 1A; VIN = 2.2V
62
Output Short Circuit Current
(2A Version)
Thermal Shutdown
Temperature
TEST CONDITIONS
AC CHARACTERISTICS
Input Supply Ripple
Rejection
ILOAD = 10mA, BW = 300Hz < f < 300kHz
Output Noise Voltage
100
µVRMS
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
VEN(HIGH)
2.2V < VIN < 6V
Hysteresis (Rising Threshold)
VEN(HYS)
2.2V < VIN < 6V
135
COUT = 10µF, ILOAD = 1A
150
Enable Pin Turn-on Delay
tEN
0.3
0.8
VIN = 6V, EN = 3V
Enable Pin Leakage Current
0.95
V
mV
µs
1
µA
SOFT-START CHARACTERISTICS
Reset Pull-Down resistance
RPD
Soft Start Charge Current
ICHG
323
Ω
-7
-4.5
-2
µA
75
84
92
%VOUT
PG PIN CHARACTERISTICS
VOUT PG Flag Threshold
VOUT PG Flag Hysteresis
4
PG Flag Low Voltage
ISINK = 500µA
PG Flag Leakage Current
VIN = 6V, PG = 6V
%
47
100
mV
0.05
1
µA
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
9. Dropout is defined by the difference in supply VIN and VOUT when the supply produces a 2% drop in VOUT from its nominal
value.
10. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current =
lifetime average current.
11. Minimum cap of 10µF X5R/X7R on VIN and VOUT required for stability.
12. If the current limit for in-rush current is acceptable in application, do not use this feature. Used only when large bulk capacitance
required on VOUT for application.
5
FN6660.1
March 22, 2010
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A.
1.8
2.0
1.8
1.6
OUTPUT VOLTAGE (V)
ΔVOUT (%)
1.2
0.6
0
-0.6
-1.2
+125°C
1.4
1.2
+25°C
1.0
-40°C
0.8
0.6
0.4
0.2
-1.8
-50
-25
0
25
50
75
100 125
JUNCTION TEMPERATURE (°C)
0
150
GROUND CURRENT (mA)
ΔVOUT (%)
1.2
0.6
+25°C
0.0
-0.6
-40°C
-1.2
+125°C
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
5
6
8
7
6
5
4
3
2
1
0
3.0
3
2
4
12.0
8.9
11.5
11.0
CURRENT (mA)
-40°C
8.5
8.3
+25°C
8.1
+125°C
7.9
-40°C
10.5
10.0
9.5
+125°C
9.0
8.5
7.7
+25°C
8.0
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
3.0
FIGURE 6. GROUND CURRENT vs OUTPUT CURRENT
6
6
FIGURE 5. GROUND CURRENT vs SUPPLY VOLTAGE
9.1
8.7
5
INPUT VOLTAGE (V)
FIGURE 4. ΔVOUT vs OUTPUT CURRENT
GROUND CURRENT (mA)
3
2
4
SUPPLY VOLTAGE (V)
9
1.8
7.5
1
FIGURE 3. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
FIGURE 2. ΔVOUT vs TEMPERATURE
-1.8
0
7.5
0.8
1.4
2.0
2.6
3.2
3.8
OUTPUT VOLTAGE (V)
4.4
5.0
FIGURE 7. GROUND CURRENT vs OUTPUT VOLTAGE
FN6660.1
March 22, 2010
ISL80102, ISL80103
Typical Operating Performance
12
4.5
11
10
9
8
7
6
5
4
3
2
1
0
-40 -25 -10
4.0
3.5
3.0
2.5
2.0
1.5
1.0
VIN = 5V
0.5
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 8. SHUTDOWN CURRENT vs TEMPERATURE
DROPOUT VOLTAGE (mV)
GROUND CURRENT (µA)
5.0
150
140
130
120
110
2A
100
90
3A
80
70
60
50
40
30
20
1A
10
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 10. DROPOUT VOLTAGE vs TEMPERATURE
VIN = 6V
5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 9. SHUTDOWN CURRENT vs TEMPERATURE
DROPOUT VOLTAGE (mV)
GROUND CURRENT (µA)
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (A)
2.5
3.0
FIGURE 11. DROPOUT VOLTAGE vs OUTPUT CURRENT
0.90
0.85
0.80
VIN (1V/DIV)
VOLTAGE (V)
0.75
0.70
0.65
SS (1V/DIV)
0.60
0.55
0.50
0.45
VOUT (1V/DIV)
0.40
0.35
0.30
-40 -25 -10 5 20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 12. ENABLE THRESHOLD VOLTAGE vs
TEMPERATURE
7
PG (1V/DIV)
TIME (10ms/DIV)
FIGURE 13. POWER-UP (VIN = 2.2V)
FN6660.1
March 22, 2010
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
EN (1V/DIV)
VIN (1V/DIV)
SS (1V/DIV)
SS (1V/DIV)
VOUT (1V/DIV)
VOUT (1V/DIV)
PG (1V/DIV)
PG (1V/DIV)
TIME (50µs/DIV)
TIME (10ms/DIV)
FIGURE 15. ENABLE START-UP
FIGURE 14. POWER-DOWN (VIN = 2.2V)
300
SS (1V/DIV)
VOUT (1V/DIV)
START-UP TIME (µs)
EN (1V/DIV)
250
200
150
100
50
0
2.0
PG (1V/DIV)
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
TIME (5ms/DIV)
FIGURE 16. ENABLE SHUTDOWN
CURRENT LIMIT (A)
START-UP TIME (µs)
200
150
100
50
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 18. START-UP TIME vs TEMPERATURE
8
6.0
FIGURE 17. START-UP TIME vs SUPPLY VOLTAGE
300
250
5.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-40 -25 -10
ISL80103
ISL80102
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 19. CURRENT LIMIT vs TEMPERATURE
FN6660.1
March 22, 2010
ISL80102, ISL80103
Typical Operating Performance
CURRENT LIMIT (A)
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
ISL80103
VOUT (1V/DIV)
ISL80102
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
6.0
FIGURE 20. CURRENT LIMIT vs SUPPLY VOLTAGE
IOUT (1A/DIV)
TIME (10ms/DIV)
FIGURE 21. CURRENT LIMIT RESPONSE (ISL80102)
VOUT (1V/DIV)
IOUT (1A/DIV)
TIME (100ms/DIV)
FIGURE 22. THERMAL CYCLING (ISL80102)
VOUT (1V/DIV)
IOUT (2A/DIV)
TIME (20ms/DIV)
FIGURE 23. CURRENT LIMIT RESPONSE (ISL80103)
EN (1V/DIV)
VOUT (1V/DIV)
IOUT (2A/DIV)
IOUT (2A/DIV)
VOUT (1V/DIV)
TIME (50ms/DIV)
FIGURE 24. THERMAL CYCLING (ISL80103)
9
TIME (1ms/DIV)
FIGURE 25. IN-RUSH CURRENT WITH NO
SOFT-START CAPACITOR, COUT = 1000µF
FN6660.1
March 22, 2010
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
EN (1V/DIV)
EN (1V/DIV)
IOUT (2A/DIV)
IOUT (2A/DIV)
VOUT (1V/DIV)
VOUT (1V/DIV)
TIME (1ms/DIV)
FIGURE 26. IN-RUSH WITH 22nF SOFT-START
CAPACITOR, COUT = 1000µF
VOUT (50mV/DIV)
IOUT (2A/DIV)
TIME (1ms/DIV)
FIGURE 27. IN-RUSH WITH 47nF SOFT-START
CAPACITOR, COUT = 1000µF
VOUT (50mV/DIV)
IOUT (2A/DIV)
di/dt = 30A/µs
di/dt = 30A/µs
TIME (200µs/DIV)
FIGURE 28. LOAD TRANSIENT 0A TO 3A,
COUT = 10µF CERAMIC
TIME (200µs/DIV)
FIGURE 29. LOAD TRANSIENT 0A TO 3A,
COUT = 10µF CERAMIC + 100µF OSCON
VOUT (50mV/DIV)
VOUT (50mV/DIV)
IOUT (2A/DIV)
IOUT (2A/DIV)
di/dt = 30A/µs
TIME (200µs/DIV)
FIGURE 30. LOAD TRANSIENT 1A TO 3A,
COUT = 10µF CERAMIC
10
di/dt = 30A/µs
TIME (200µs/DIV)
FIGURE 31. LOAD TRANSIENT 1A TO 3A,
COUT = 10µF CERAMIC + 100µF OSCON
FN6660.1
March 22, 2010
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued)
VOUT (20mV/DIV)
VOUT (20mV/DIV)
di/dt = 3A/μsec
IOUT (2A/DIV)
IOUT (2A/DIV)
di/dt = 3A/µs
di/dt = 3A/µs
TIME (50µs/DIV)
TIME (50µs/DIV)
FIGURE 32. LOAD TRANSIENT 0A TO 3A,
COUT = 10µF CERAMIC, No CPB (ADJ
VERSION)
FIGURE 33. LOAD TRANSIENT 0A TO 3A,
COUT = 10µF CERAMIC, CPB = 1500pF
(ADJ VERSION)
3.2V
80
2.2V
70
VIN (1V/DIV)
60
dB
50
1A
40
30
20
VOUT (10mV/DIV)
100mA
10
0
10
100
TIME (200µs/DIV)
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 35. PSRR vs LOAD
FIGURE 34. LINE TRANSIENT
80
10
70
100µF
NOISE µV/√Hz
60
dB
50
40
30
20
10
0
10µF
IL = 100mA
10
100
1k
10k
FREQUENCY (Hz)
FIGURE 36. PSRR vs COUT
11
47µF
100k
1M
1
0.1
0.01
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 37. SPECTRAL NOISE DENSITY vs
FREQUENCY
FN6660.1
March 22, 2010
ISL80102, ISL80103
Input Voltage Requirements
Despite other output voltages offered, this family of LDOs
is optimized for a true 2.5V to 1.8V conversion where the
input supply can have a tolerance of as much as ±10%
for conditions noted in the “Electrical Specifications” table
on page 4. Minimum guaranteed input voltage is 2.2V,
however, due to the nature of an LDO, VIN must be some
margin higher than the output voltage plus dropout at
the maximum rated current of the application if active
filtering (PSRR) is expected from VIN to VOUT. The
dropout spec of this family of LDOs has been generously
specified in order to allow applications to design for a
level of efficiency that can accommodate the smaller
outline package for those applications that cannot
accommodate the profile of the TO220/263.
capacitances on VOUT where high levels of charging
current can be seen for a significant period of time. The
in-rush currents can cause VIN to drop below minimum
which could cause VOUT to shutdown. Figure 38 shows
the relationship between in-rush current and CSS with a
COUT of 1000µF.
5.0
IN-RUSH CURRENT LIMIT (A)
Functional Description
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Enable Operation
The Enable turn-on threshold is typically 770mV with a
hysteresis of 135mV. An internal pull-up or pull-down
resistor is available upon request. As a result, this pin
must not be left floating. This pin must be tied to VIN if it
is not used. A 1kΩ to 10kΩ pull-up resistor will be
required for applications that use open collector or open
drain outputs to control the Enable pin. The Enable pin
may be connected directly to VIN for applications that are
always on.
Power-Good Operation
Applications not using this feature must connect this pin
to ground. The PGOOD flag is an open-drain NMOS that
can sink up to 10mA during a fault condition. The PGOOD
pin requires an external pull-up resistor which is typically
connected to the VOUT pin. The PGOOD pin should not
be pulled up to a voltage source greater than VIN. The
PGOOD fault can be caused by the output voltage going
below 84% of the nominal output voltage, or the current
limit fault, or low input voltage. The PGOOD does not
function during thermal shutdown. The PGOOD functions
in shutdown.
Soft-Start Operation (Optional)
If the current limit for in-rush current is acceptable in the
application, do not use this feature. The soft-start circuit
controls the rate at which the output voltage comes up to
regulation at power-up or LDO enable. A constant
current charges an external soft-start capacitor. The
external capacitor always gets discharged to ground pin
potential at the beginning of start-up or enabling. The
discharge rate is the RC time constant of RPD and CSS.
See Figures 25 through 28 in the “Typical Operating
Performance Curves” beginning on page 10. RPD is the
ON-resistance of the pull down MOSFET, M8. RPD is 300Ω
typically.
The soft-start feature effectively reduces the in-rush
current at power-up or LDO enable until VOUT reaches
regulation. The in-rush current can be an issue for
applications that require large, external bulk
12
0
20
40
60
CSS (nF)
80
100
FIGURE 38. IN-RUSH CURRENT vs SOFT-START
CAPACITANCE
Output Voltage Selection
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage. This
voltage is then fed back to the error amplifier. The output
voltage can be programmed to any level between 0.8V
and 5V. An external resistor divider, R3 and R4, is used to
set the output voltage as shown in Equation 1. The
recommended value for R4 is 500Ω to 1kΩ. R3 is then
chosen according to Equation 2:
⎛ R3
⎞
V OUT = 0.5V × ⎜ ------- + 1⎟
R
⎝ 4
⎠
(EQ. 1)
V OUT
R 3 = R 4 × ⎛ ---------------- – 1⎞
⎝ 0.5V
⎠
(EQ. 2)
External Capacitor Requirements
External capacitors are required for proper operation.
Careful attention must be paid to the layout guidelines
and selection of capacitor type and value to ensure
optimal performance.
OUTPUT CAPACITOR
The ISL80102, ISL80103 applies state-of-the-art internal
compensation to keep selection of the output capacitor
simple for the customer. Stable operation over full
temperature, VIN range, VOUT range and load extremes
are guaranteed for all capacitor types and values
assuming a 10µF X5R/X7R is used for local bypass on
VOUT. This minimum capacitor must be connected to
VOUT and Ground pins of the LDO with PCB traces no
longer than 0.5cm.
Lower cost Y5V and Z5U type ceramic capacitors are
acceptable if the size of the capacitor is larger to
compensate for the significantly lower tolerance over
X5R/X7R types. Additional capacitors of any value in
Ceramic, POSCAP or Alum/Tantalum Electrolytic types
may be placed in parallel to improve PSRR at higher
FN6660.1
March 22, 2010
ISL80102, ISL80103
frequencies and/or load transient AC output voltage
tolerances.
(Note 10)” on page 4. The power dissipation can be
calculated by using Equation 3:
INPUT CAPACITOR
P D = ( V IN – V OUT ) × I OUT + V IN × I GND
The minimum input capacitor required for proper
operation is 10µF having a ceramic dielectric. This
minimum capacitor must be connected to VIN and
ground pins of the LDO with PCB traces no longer than
0.5cm.
The maximum allowable junction temperature, TJ(MAX)
and the maximum expected ambient temperature,
TA(MAX) will determine the maximum allowable power
dissipation as shown in Equation 4:
Phase Boost Capacitor (Optional)
P D ( MAX ) = ( T J ( MAX ) – T A ) ⁄ θ JA
The ISL80102 and ISL80103 are designed to be stable
with 10µF or larger ceramic capacitor.
Applications using the ADJ versions, may see improved
performance with the addition of a small ceramic
capacitor CPB as shown in Figure 1 on page 3. The
conditions where CPB may be beneficial are: (1) VOUT >
1.5V, (2) COUT = 10µF, and (3) tight AC voltage
regulation band.
CPB introduces phase lead with the product of R3 and
CPB that results in increasing the bandwidth of the LDO.
Typical R3 x CPB should be 4μs.
For safe operation, please make sure that power
dissipation calculated in Equation 3, PD be less than the
maximum allowable power dissipation PD(MAX).
The DFN package uses the copper area on the PCB as a
heat-sink. The EPAD of this package must be soldered to
the copper plane (GND plane) for heat sinking. Figure 39
shows a curve for the θJA of the DFN package for
different copper area sizes.
46
44
The junction temperature must not exceed the range
specified in the “Recommended Operating Conditions
θJA, C/W
Current Limit Protection
Power Dissipation and Thermals
(EQ. 4)
Where θJA is the junction-to-ambient thermal
resistance.
CPB not recommended for VOUT < 1.5V.
The ISL80102, ISL80103 family of LDOs incorporates
protection against overcurrent due to short, overload
condition applied to the output and the in-rush current
that occurs at start-up. The LDO performs as a constant
current source when the output current exceeds the
current limit threshold noted in the “Electrical
Specifications” table on page 4. If the short or overload
condition is removed from VOUT, then the output returns
to normal voltage mode regulation. In the event of an
overload condition, the LDO might begin to cycle on and
off due to the die temperature exceeding the thermal
fault condition. The TO220/263 package will tolerate
higher levels of power dissipation on the die which may
never thermal cycle if the heatsink of this larger package
can keep the die temperature below the specified typical
thermal shutdown temperature.
(EQ. 3)
42
40
38
36
34
2
4
6
8
10 12 14 16 18 20 22
2
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
24
FIGURE 39. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB
WITH THERMAL VIAS θJA vs EPAD-MOUNT
COPPER LAND AREA ON PCB
Thermal Fault Protection
In the event the die temperature exceeds typically
+160°C, then the output of the LDO will shut down until
the die temperature can cool down to typically +145°C.
The level of power combined with the thermal impedance
of the package (+48°C/W for DFN) will determine if the
junction temperature exceeds the thermal shutdown
temperature.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
13
FN6660.1
March 22, 2010
ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
3/4/10
FN6660.1
CHANGE
Corrected Features on page 1 as follows:
-Changed bullet "• 185mV Dropout @ 3A, 125mV Dropout @ 2A" to "• Very Low 120mV
Dropout at 3A"
-Changed bullet "• 65dB Typical PSRR" to "• 62dB Typical PSRR"
-Deleted 0.5% Initial VOUT Accuracy
Modified Figure 1 and placed as Typical Application on Page 1.
Moved Pinout to page 3
In "Block Diagram" on page 2, corrected resistor associated with M5 from R4 to R5
Updated Block Diagram on page 2 as follows”
- Added M8 from SS to ground.
Updated Figure 1 on page 3 as follows:
-Corrected Pin 6 from SS to IRSET
-Removed Note 12 callout "Minimum cap on VIN and VOUT required for stability." Added Note
"*CSS is optional. See Note 12 on Page 5." and “** CPB is optional. See “Functional
Description” on page 12 for more information.”
Added "The 1.5V, 3.3V and 5V fixed output voltages will be released in the future." to Note 3
on page 2.
In “Thermal Information” on page 4, updated Theta JA from 45 to 48 per ASYD
In “Soft-Start Operation (Optional)” on page 12:
-Changed "The external capacitor always gets discharged to 0V at start-up of after coming out
of a chip disable." to "The external capacitor always gets discharged to ground pin potential at
start-up or enabling."
-Changed "The soft-start function effectively limits the amount of in-rush current below the
programmed current limit during start-up or an enable sequence to avoid an overcurrent fault
condition." to "The soft-start feature effectively reduces the in-rush current at power-up or
LDO enable until VOUT reaches regulation."
-Added "See Figures 25 through 27 in the “Typical Operating Performance Curves” beginning
on page 9."
-Added “RPD is the on resistance of the pull down MOSFET, M8. RPD is 300Ohms typically.”
Added "Phase Boost Capacitor (CPB)" section on page 13.
In “Typical Operating Performance” on page 11, revised figure "PSRR vs VIN" which had 3
curves with "Spectral Noise Density vs Frequency" which has one curve.
Added "FIGURE 32. LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC, NO CPB (ADJ
VERSION)" and "FIGURE 33. LOAD TRANSIENT 1A TO 3A, COUT = 10µF CERAMIC, CPB =
1500pF (ADJ VERSION)"
09/30/09
FN6660.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL80102, ISL80103
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
ISL80102, ISL80103
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
3.00
6
PIN #1 INDEX AREA
A
B
1
6
PIN 1
INDEX AREA
(4X)
3.00
2.00
8x 0.50
2
10 x 0.23
4
0.10
1.60
TOP VIEW
10x 0.35
BOTTOM VIEW
4
(4X)
0.10 M C A B
0.415
PACKAGE
OUTLINE
0.200
0.23
0.35
(10 x 0.55)
SEE DETAIL "X"
(10x 0.23)
1.00
MAX
0.10 C
BASE PLANE
2.00
0.20
C
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
C
0.20 REF
5
1.60
0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Lead width applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
15
FN6660.1
March 22, 2010
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