Intersil ISLA222S25IR1Z Dual 12-bit, 250/200/125 msps jesd204b high speed serial output adc Datasheet

DATASHEET
Dual 12-bit, 250/200/125 MSPS JESD204B High Speed
Serial Output ADC
ISLA222S
Features
The ISLA222S is a series of low-power, high-performance,
dual-channel 12-bit, analog-to-digital converters. Designed
with FemtoCharge™ technology on a standard CMOS process,
the series supports sampling rates of up to 250MSPS. The
ISLA222S is part of a pin-compatible family of 12- and 14-bit
dual-channel A/Ds with maximum sample rates ranging from
125MSPS to 250MSPS and shares the same analog core as
Intersil's proven ISLA222P series of ADCs. The family
minimizes power consumption while providing state of the art
dynamic performance, offering an optimal performance vs
power trade-off.
• JESD204A/B high-speed data interface
Differentiating the ISLA222S from the ISLA222P is its highly
configurable, JESD204B-compliant, high-speed serial output
link. The link offers data rates up to 4.375Gbps per lane and
multiple packing modes. It can be configured to use one, two,
or three lanes to transmit the conversion data, allowing for
flexibility in the receiver design. The SERDES transmitter also
provides deterministic latency and multi-chip time alignment
support to satisfy an application's complex synchronization
requirements.
A Serial Peripheral Interface (SPI) port allows for extensive
configurability of the JESD204B transmitter including access
to its built-in link and transport layer test patterns. The SPI port
also provides control for numerous additional features
including the fine gain and offset adjustments of the two ADC
cores as well as the programmable clock divider, enabling 2x
and 4x harmonic clocking.
The ISLA222S is available in a space saving 7mmx7mm 48 Ld
QFN package. The package features a thermal pad for
improved thermal performance and is specified over the full
industrial temperature range (-40°C to +85°C).
- JESD204A compliant
- JESD204B device subclass 0 compliant
- JESD204B device subclass 2 compatible
- Up to 3 JESD204 output lanes running up to 4.375Gbps
- Highly configurable JESD204 transmitter
• Multiple chip time alignment and deterministic latency
support (JESD204B device subclass 2)
• SPI programmable debugging features and test patterns
• 48-pin QFN 7mmx7mm package
Key Specifications
• SNR at 250/200/125MSPS
70.6/71.2/71.7 dBFS fIN = 30MHz
70.3/70.7/70.9 dBFS fIN = 190MHz
• SFDR at 250/200/125MSPS
87/93/95 dBc fIN = 30MHz
84/93/86 dBc fIN = 190MHz
• Total Power Consumption: 989mW at 250MSPS
Applications
• Radar and satellite antenna array processing
• Broadband communications and microwave receivers
• High-performance data acquisition
• Communications test equipment
• High-speed medical imaging
Pin-compatible Family
RESOLUTION
SPEED
(MSPS)
ISLA224S25
14
250
ISLA224S20
14
200
ISLA224S12
14
125
ISLA222S25
12
250
ISLA222S20
12
200
ISLA222S12
12
125
MODEL
FIGURE 1. SERDES DATA EYE AT 4.375Gbps
July 6, 2015
FN8302.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISLA222S
Table of Contents
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
16
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
18
18
19
19
19
19
19
20
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
JESD204 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Initial Lane Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADDRESS 0xDF - 0xF3: JESD204 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address 0xDF-0xEE: JESD204 Parameter Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
27
27
27
28
29
29
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CML Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
36
36
36
36
36
36
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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ISLA222S
CLKP
OVDD
OVDD
(PLL)
SYNC
AVDD
Block Diagram
CLOCK
GENERATION
CLKN
AINP
12-BIT
250MSPS
ADC
SHA
AINN
LANE[2:0]P
LANE[2:0]N
VREF
JESD204
TRANSMITTER
VCM
BINP
12-BIT
250MSPS
ADC
SHA
BINN
VREF
+
–
CSB
SCLK
SDIO
SDO
OVSS
SPI
CONTROL
RESETN
AVSS
(PLL)
NAPSLP
AVSS
1.25V
FIGURE 2. BLOCK DIAGRAM
Pin Configuration
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DNC
DNC
AVDD
NAPSLP
CLKDIV
SDIO
SCLK
CSB
SDO
OVDD
OVSS
OVSS
ISLA222S
(48 LD QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
VCM
1
36 OVDD
AVDD
2
35 OVSS
AVSS
3
34 LANE2N
BINP
4
33 LANE2P
BINN
5
32 OVSS
AVSS
6
31 LANE1N
AVSS
7
30 LANE1P
AINN
8
29 OVSS
AINP
9
28 LANE0N
AVSS
10
27 LANE0P
AVDD
11
DNC
12
3
26 OVSS
PAD – Exposed Paddle
13
14
15
16
17
18
19
20
21
22
23
24
RESETN
AVDD
AVDD
CLKP
CLKN
SYNCP
SYNCN
DNC
OVSS (PLL)
OVDD (PLL)
OVSS (PLL)
OVDD (PLL)
25 OVDD
FN8302.1
July 6, 2015
ISLA222S
Pin Descriptions
PIN NUMBER
NAME
FUNCTION
2, 11, 14, 15, 46
AVDD
1.8V Analog Supply
12, 20, 47, 48
DNC
Do Not Connect
3, 6, 7, 10
AVSS
Analog Ground
4, 5
BINP, BINN
B-Channel Analog Input Positive, Negative
8, 9
AINN, AINP
A-Channel Analog Input Negative, Positive
1
VCM
44
CLKDIV
16, 17
CLKP, CLKN
45
NAPSLP
Power Control (Nap, Sleep modes)
13
RESETN
Power On Reset (Active Low)
26, 29, 32, 35, 37, 38
OVSS
Output Ground
25, 36, 39
OVDD
1.8V Digital Supply
Common Mode Output
Clock Divider Control
Clock Input True, Complement
22, 24
OVDD (PLL)
1.8V Analog Supply for SERDES PLL
21, 23
OVSS (PLL)
Analog Ground Supply for SERDES PLL
18, 19
SYNCP, SYNCN
27, 28
LANE0P, LANE0N
SERDES Lane 0
30, 31
LANE1P, LANE1N
SERDES Lane 1
33, 34
LANE2P, LANE2N
SERDES Lane 2
40
SDO
SPI Serial Data Output
41
CSB
SPI Chip Select (active low)
42
SCLK
SPI Clock
43
SDIO
SPI Serial Data Input/Output
PAD
-
JESD204 SYNC Input
Exposed Paddle. Analog Ground (connect to AVSS)
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISLA222S25IR1Z
ISLA222S25 IR1Z
-40 to +85
48 Ld QFN
L48.7x7G
ISLA222S20IR1Z
ISLA222S20 IR1Z
-40 to +85
48 Ld QFN
L48.7x7G
ISLA222S12IR1Z
ISLA222S12 IR1Z
-40 to +85
48 Ld QFN
L48.7x7G
ISLA224S25IR48EV1Z
FMC Based Evaluation Board (Supports 125/200/250 speed grades), Dual 14-bit Evaluation Board, which can be
configured for 12-bit operation; Interfaces with ADCMB-HSFMCEV1Z Motherboard and Other FPGA Vendor FMC
Based Evaluation Platforms.
ADCMB-HSFMCEV1Z
FMC Based Motherboard
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA222S12, ISLA222S20, ISLA222S25. For more information on MSL
please see techbrief TB363.
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ISLA222S
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latch-up (Tested per JESD-78C; Class 2, Level A). . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
48 Ld QFN (Notes 3, 4, 5) . . . . . . . . . . . . . .
24
0.4
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
5. For solder stencil layout and reflow guidelines, please see Tech Brief. TB389
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply
across the operating temperature range, -40°C to +85°C.
ISLA222S25
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
1.9
2.00
ISLA222S20
ISLA222S12
MAX
MIN
MAX
MIN
MAX
(Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6)
UNIT
DC SPECIFICATIONS
Analog Input
Full Scale Analog Input
Range
VFS
Differential
Input Resistance
RIN
Differential
600
600
600
Ω
Input Capacitance
CIN
Differential
7.4
7.4
7.4
pF
Full Temp
115
58
58
ppm/°C
2.1
1.9
2.0
2.1
1.9
2.0
2.1
VP-P
Full Scale Range Temp.
Drift
AVTC
Input Offset Voltage
VOS
±1
±1
±1
mV
Gain Error
EG
1
1
1
%
Common-mode Output
Voltage
VCM
0.94
0.94
0.94
V
Common Mode Input
Current (per pin)
ICM
6.0
6.0
6.0
µA/MSPS
Inputs Common Mode
Voltage
0.9
0.9
0.9
V
CLKP, CLKN Swing
1.8
1.8
1.8
V
Clock Inputs
Power Requirements
1.8V Analog Supply
Voltage
AVDD
1.8
1.8
1.8
V
1.8V Digital Supply
Voltage
OVDD
1.8
1.8
1.8
V
1.8V Analog Supply
Current
IAVDD
353
397
324
365
282
316
mA
1.8V Digital Supply
Current
IOVDD
195
218
179
200
123
173
mA
Submit Document Feedback
Minimum number of
lanes active
5
FN8302.1
July 6, 2015
ISLA222S
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply
across the operating temperature range, -40°C to +85°C. (Continued)
ISLA222S25
PARAMETER
SYMBOL
Power Supply Rejection
Ratio (Note 7)
PSRR
TEST CONDITIONS
MIN
(Note 6)
TYP
ISLA222S20
ISLA222S12
MAX
MIN
MAX
MIN
MAX
(Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6)
UNIT
30MHz 200mVP-P
40
40
40
dB
1MHz 200mVP-P
47
47
47
dB
Total Power Dissipation
Normal Mode
PD
Nap Mode
PD
Sleep Mode
PD
989
1107
910
1017
731
843
mW
422
484
391
450
290
398
mW
CSB at logic high
6
12
6
12
6
12
mW
Nap Mode Wakeup
Time
Sample Clock
Running
5
5
5
µs
Sleep Mode Wakeup
Time
Sample Clock
Running
1
1
1
ms
-1.0
±0.1
LSB
-1.0
0.5
AC SPECIFICATIONS (Note 8)
Differential Nonlinearity
DNL
Integral Nonlinearity
INL
Minimum Conversion
Rate (Note 9)
fS MIN
fIN = 105MHz
No Missing Codes
-1.0
±0.15
-1.5
0.8
1.5
-1.0
±0.1
-1.0
0.4
100
ISLA222S25,
ISLA222S20
(3 Lanes, Efficient
Packing)
1.0
100
50
1.0
LSB
MSPS
ISLA222S12
(2 Lanes, Simple
Packing)
Maximum Conversion
Rate
fS MAX
Efficient Packing
Minimum Serdes Lane
Data Rate
Independent of Packing
Mode
Maximum Serdes Lane
Data Rate
(See “Lane data rate” on
page 22.)
Independent of Packing
Mode
Signal-to-noise Ratio
(Note 10)
Submit Document Feedback
250
200
125
MSPS
Simple Packing
MSPS
1.0
3.75
fIN = 30MHz
SNR
fIN = 105MHz
6
4.375
1.0
3.0
70.6
69.4
70.6
4.375
3.75
71.2
70.3
71.1
70.7
1.0
GBPS
4.375
GBPS
71.7
dBFS
71.5
dBFS
fIN = 190MHz
70.3
70.7
70.9
dBFS
fIN = 363MHz
69.4
69.5
69.3
dBFS
fIN = 495MHz
68.6
68.5
68.0
dBFS
fIN = 605MHz
67.9
67.6
66.9
dBFS
FN8302.1
July 6, 2015
ISLA222S
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply
across the operating temperature range, -40°C to +85°C. (Continued)
ISLA222S25
PARAMETER
Signal-to-noise and
Distortion (Note 10)
SYMBOL
fIN = 105MHz
ENOB
Spurious-free Dynamic
Range (Note 10)
MIN
(Note 6)
fIN = 30MHz
SINAD
Effective Number of Bits
(Note 10)
Spurious-Free Dynamic
Range Excluding H2, H3
(Note 10)
TEST CONDITIONS
SFDR
Channel-to-channel
Isolation
70.4
71.1
70.2
71.0
70.4
UNIT
71.7
dBFS
71.3
dBFS
70.0
70.5
70.7
dBFS
fIN = 363MHz
69.0
68.9
67.8
dBFS
fIN = 495MHz
65.4
64.0
61.4
dBFS
fIN = 605MHz
59.3
58.0
54.1
dBFS
fIN = 30MHz
11.42
11.52
11.61
Bits
fIN = 105MHz
11.17 11.40
11.37 11.50
11.40 11.55
Bits
fIN = 190MHz
11.34
11.42
11.46
Bits
fIN = 363MHz
11.16
11.16
10.97
Bits
fIN = 495MHz
10.57
10.34
9.91
Bits
fIN = 605MHz
9.56
9.35
8.69
Bits
fIN = 30MHz
87
93
95
dBc
87
dBc
74
83
76
89
76
fIN = 190MHz
84
93
86
dBc
fIN = 363MHz
79
88
71
dBc
fIN = 495MHz
66
85
61
dBc
fIN = 605MHz
58
83
52
dBc
87
93
98
dBc
fIN = 105MHz
89
95
96
dBc
fIN = 190MHz
88
93
90
dBc
fIN = 363MHz
84
88
85
dBc
fIN = 495MHz
85
85
82
dBc
fIN = 605MHz
88
83
81
dBc
fIN = 70MHz
-84
-82
-81
dBFS
fIN = 170MHz
-92
-99
-100
dBFS
fIN = 10MHz
88
90
100
dB
fIN = 124MHz
82
87
86
dB
10-13
10-13
675
675
SFDRX23 fIN = 30MHz
IMD
MAX
MIN
MAX
MIN
MAX
(Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6)
70.5
69.0
ISLA222S12
fIN = 190MHz
fIN = 105MHz
Intermodulation
Distortion
TYP
ISLA222S20
Word Error Rate
WER
10-13
Full Power Bandwidth
FPBW
675
MHz
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. PSRR is calculated by the equation 20*log10(A/B), where B is the amplitude of a disturber sinusoid on AVDD at the device pins, and A is the amplitude
of the spur in the captured data at the frequency of the disturber sinusoid.
8. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to “Power-on Calibration” on
page 15 and “User Initiated Reset” on page 16 for more detail.
9. The DLL Range setting must be changed via SPI for ADC core sample rates below 80MSPS. The JESD204 transmitter can support ADC sample rates
below 100MSPS, as long as the SERDES lane data rate is greater than or equal to 1Gbps.
10. Minimum specification guaranteed when calibrated at +85°C.
Submit Document Feedback
7
FN8302.1
July 6, 2015
ISLA222S
Digital Specifications
Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
1
10
µA
-12
-7
µA
4
12
µA
-600
-400
-300
µA
40
52
70
µA
1
10
µA
CMOS INPUTS
Input Current High (RESETN)
IIH
VIN = 1.8V
Input Current Low (RESETN)
IIL
VIN = 0V
Input Current High (SDIO, SCL, SDA SCLK)
IIH
VIN = 1.8V
Input Current Low (SDIO, SCL, SDA SCLK)
IIL
VIN = 0V
Input Current High (CSB)
IIH
VIN = 1.8V
Input Current Low (CSB)
IIL
VIN = 0V
Input Voltage High (SDIO, RESETN)
VIH
Input Voltage Low (SDIO, RESETN)
VIL
Input Current High (NAPSLP, CLKDIV) (Note 11)
IIH
19
Input Current Low (NAPSLP, CLKDIV)
IIL
--30
Input Capacitance
CDI
-25
1.17
V
0.63
V
25
30
µA
-25
-19
µA
4
pF
LVDS INPUTS (SYNCP, SYNCN)
Input Common Mode Range
VICM
825
1575
mV
Input Differential Swing (peak-to-peak, single-ended)
VID
250
450
mV
Input Pull-up and Pull-down Resistance
RIpu
100
kΩ
1.14
V
CML OUTPUTS
Output Common Mode Voltage
Switching Specifications
Boldface limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITION
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
ADC OUTPUT
Aperture Delay
tA
190
ps
RMS Aperture Jitter
jA
100
fs
250
µs
L
10
cycles
tOVR
1
cycles
PLL Lock Time
250
µs
PLL Bandwidth
2.2
MHz
Added Random Jitter
5
ps
RMS
Added Deterministic Jitter
7
ps P-P
5
ps rms
Synchronous Clock Divider Reset Recovery Time (Note 12)
Latency (ADC Pipeline Delay)
Overvoltage Recovery
tRSTRT
DLL recovery
time after
Synchronous
Reset
SERDES
Maximum Input Sample Clock Total Jitter to Maintain SERDES
BER <1E-12
Submit Document Feedback
8
Integrated from
1kHz to 10MHz
offset from
carrier
FN8302.1
July 6, 2015
ISLA222S
Switching Specifications
Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITION
SYNCP, SYNCN Setup Time (with Respect to the Positive Edge of
CLKP)
tRSTS
AVDD,
OVDD = 1.7V to
1.9V, TA = -40°C
to +85°C
SYNCP, SYNCN Hold Time (with respect to the positive edge of
CLKP)
tRSTH
AVDD,
OVDD = 1.7V to
1.9V, TA = -40°C
to +85°C
MIN
(Note 6)
TYP
400
75
MAX
(Note 6)
UNIT
LVDS Inputs
150
ps
350
ps
CML Outputs
Output Rise Time
tR
165
ps
Output Fall Time
tF
145
ps
Data Output Duty Cycle
50
%
Differential Output Resistance
100
Ω
Differential Output Voltage (Note 13)
760
mVP-P
SPI INTERFACE (Notes 14, 15)
SCLK Period
t
CLK
Write Operation
7
cycles
tCLK
Read Operation
16
cycles
CSBto SCLK Setup Time
tS
Read or Write
2
cycles
CSBafter SCLK Hold Time
tH
Read or Write
5
cycles
Data Valid to SCLK Setup Time
tDS
Read or Write
6
cycles
Data Valid after SCLK Hold Time
tDH
Read or Write
4
cycles
Data Valid after SCLK Time
tDVR
Read
4
cycles
NOTES:
11. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
12. The synchronous clock divider reset function is available as a (SPI-programmable) overload on the SYNC input.
13. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak single-ended swing is 1/2 of the differential swing.
14. The SPI interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be
scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
15. The SPI may operate asynchronously with respect to the ADC sample clock.
Submit Document Feedback
9
FN8302.1
July 6, 2015
ISLA222S
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS.
95
SFDR AT 125 MSPS
SFDR AT 200 MSPS
85
SFDR AT 250 MSPS
80
75
70
65
SNR AT 125 MSPS
SNR AT 250 MSPS
60
SNR AT 200 MSPS
55
50
0
100
200
HD2 AT 125 MSPS
-55
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
90
300
400
500
600
HD2 AT 200 MSPS
-65
HD2 AT 250 MSPS
-75
-85
-95
-105
0
HD3 AT 200 MSPS
HD3 AT 125 MSPS
100
INPUT FREQUENCY (MHz)
SFDR (dBFS)
500
600
-10
0
-20
SNR (dBFS)
-40
H2 AND H3
SNR AND SFDR
400
0
70
60
300
FIGURE 4. HD2 AND HD3 vs fIN
100
80
200
INPUT FREQUENCY (MHz)
FIGURE 3. SNR AND SFDR vs fIN
90
HD3 AT 250 MSPS
SFDR (dBc)
50
40
HD3 (dBc)
-60
-80
30
20
SNR (dBc)
HD2 (dBc)
HD2 (dBFS)
-100
10
0
-60
-50
-40
-30
-20
INPUT AMPLITUDE (dBFS)
-10
0
-120
-60
FIGURE 5. SNR AND SFDR vs AIN (250MSPS)
HD3 (dBFS)
-50
-40
-30
-20
INPUT AMPLITUDE (dBFS)
FIGURE 6. HD2 AND HD3 vs AIN (250MSPS)
0
100
-20
SFDR (dBFS)
SNR (dBFS)
-40
60
H2 AND H3
SNR AND SFDR
80
SFDR (dBc)
40
HD3 (dBc)
-60
-80
HD2 (dBFS)
SNR (dBc)
20
0
-60
HD2 (dBc)
-100
-50
-40
-30
-20
-10
INPUT AMPLITUDE (dBFS)
FIGURE 7. SNR AND SFDR vs AIN (125MSPS)
Submit Document Feedback
10
0
-120
-60
HD3 (dBFS)
-50
-40
-30
-20
INPUT AMPLITUDE (dBFS)
-10
0
FIGURE 8. H2 AND H3 vs AIN (125MSPS)
FN8302.1
July 6, 2015
ISLA222S
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
-75
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
90
85
SFDR
80
75
SNR
70
65
60
50
100
150
200
250
-80
H3
-85
-90
-95
H2
-100
-105
70
300
90
110
130
SAMPLE RATE (MSPS)
230
250
800
750
3500
4000
0.50
ADC CONFIGURED FOR
TWO LANE OPERATION
FOR SAMPLE RATE
≥ 160 MSPS
700
650
DNL (LSBs)
TOTAL POWER (mW)
ADC CONFIGURED FOR
SINGLE LANE OPERATION
FOR SAMPLE RATE
≤ 150 MSPS
850
0.25
0
-0.25
-0.50
600
-0.75
550
EFFICIENT PACKING
40
60
80
100 120 140 160 180
SAMPLE RATE (MSPS)
200
220
-1.00
240
0
500
1000
1500
2000 2500
CODES
3000
FIGURE 12. DIFFERENTIAL NONLINEARITY (250MSPS)
FIGURE 11. POWER vs fSAMPLE
2.0
85
SNR (dBFS) AND SFDR (dBc)
1.5
1.0
INL (LSBs)
210
0.75
900
500
190
1.00
3 LANE OPERATION
950
170
FIGURE 10. HD2 AND HD3 vs fSAMPLE
FIGURE 9. SNR AND SFDR vs fSAMPLE
1000
150
SAMPLE RATE (MSPS)
0.5
0
-0.5
-1.0
SFDR
80
75
70
SNR
65
-1.5
-2.0
0
500
1000
1500
2000
2500
3000
3500
CODES
FIGURE 13. INTEGRAL NONLINEARITY (250MSPS)
Submit Document Feedback
11
4000
60
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
INPUT COMMON MODE (V)
FIGURE 14. SNR AND SFDR vs VCM (250MSPS)
FN8302.1
July 6, 2015
ISLA222S
Typical Performance Curves
1.00
2.0
0.75
1.5
0.50
1.0
0.25
0.5
INL (LSBs)
DNL (LSBs)
All Typical Performance Characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
0
-0.25
0
-0.5
-0.50
-1.0
-0.75
-1.5
-1.00
0
500
1000
1500
2000
2500
3000
3500
-2.0
4000
0
500
1000
1500
CODES
25000
20145
-20
AMPLITUDE (dBFS)
NUMBER OF HITS
20000
15000
12588
10000
3500
4000
AIN = -2.0 dBFS
SNR = 70.7 dBFS
SFDR = 83.1 dBc
SINAD = 70.5 dBFS
-40
-60
-80
5000
-100
0
2049
0
2050
7
28
2051
2052 2053
CODE
2054
0
2055
0
0
-120
0
2056
40
60
80
100
120
FIGURE 18. SINGLE-TONE SPECTRUM AT 105MHz (250MSPS)
0
AIN = -2.0 dBFS
SNR = 70.5 dBFS
SFDR = 85.3 dBc
SINAD = 70.3 dBFS
-40
-60
-80
-100
AIN = -2.0 dBFS
SNR = 69.6 dBFS
SFDR = 81.2 dBc
SINAD = 69.4 dBFS
-20
AMPLITUDE (dBFS)
-20
20
FREQUENCY (MHz)
FIGURE 17. NOISE HISTOGRAM (250MSPS)
AMPLITUDE (dBFS)
3000
0
STDEV = 0.49 CODES
-120
2500
FIGURE 16. INTEGRAL NONLINEARITY (125MSPS)
FIGURE 15. DIFFERENTIAL NONLINEARITY (125MSPS)
0
2000
CODES
-40
-60
-80
-100
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 19. SINGLE-TONE SPECTRUM AT 190MHz (250MSPS)
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12
-120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 20. SINGLE-TONE SPECTRUM AT 363MHz (250MSPS)
FN8302.1
July 6, 2015
ISLA222S
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
25000
0
STDEV= 0.48 CODES
21035
-20
AMPLITUDE (dBFS)
NUMBER OF HITS
20000
15000
11731
10000
5000
0
AIN = -2.0 dBFS
SNR = 71.6 dBFS
SFDR = 87.2 dBc
SINAD = 71.6 dBFS
-40
-60
-80
-100
0
0
2046
2
2047
2048
2049
2050
0
2051
0
-120
2052
0
10
20
0
-60
-80
-100
-60
-80
-100
10
20
30
40
50
-120
60
0
10
20
30
40
50
60
FREQUENCY (MHz)
FIGURE 23. SINGLE-TONE SPECTRUM AT 190MHz (125MSPS)
FIGURE 24. SINGLE-TONE SPECTRUM AT 363MHz (125MSPS)
0
0
IMD3= -84 dBFS
IMD3= -92 dBFS
-20
-20
MAGNITUDE (dBFS)
MAGNITUDE (dBFS)
60
-40
FREQUENCY (MHz)
-40
-60
-80
-40
-60
-80
-100
-100
-120
50
AIN = -2.0 dBFS
SNR = 69.5 dBFS
SFDR = 71.9 dBc
SINAD = 68.1 dBFS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
AIN = -2.0 dBFS
SNR = 71.1 dBFS
SFDR = 87.3 dBc
SINAD = 71.0 dBFS
-40
-120
0
40
FIGURE 22. SINGLE-TONE SPECTRUM AT 105MHz (125MSPS)
FIGURE 21. NOISE SPECTRUM (125MSPS)
-20
30
FREQUENCY (MHz)
CODE
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 25. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz AT
-7dBFS) (250MSPS)
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13
-120
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 26. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz AT
-7dBFS) (250MSPS)
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ISLA222S
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
FIGURE 27. SERDES DATA EYE at 1.0Gbps
FIGURE 28. SERDES DATA EYE at 3.0Gbps
FIGURE 29. SERDES DATA EYE at 4.375Gbps
FIGURE 30. SERDES BATHTUB at 1.0Gbps
FIGURE 31. SERDES BATHTUB at 3.0Gbps
FIGURE 32. SERDES BATHTUB at 4.375Gbps
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FN8302.1
July 6, 2015
ISLA222S
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
FIGURE 33. SERDES HISTOGRAM at 1.0Gbps
FIGURE 34. SERDES HISTOGRAM at 3.0Gbps
FIGURE 35. SERDES HISTOGRAM at 4.375Gbps
Theory of Operation
Functional Description
The ISLA222S is based upon a 12-bit, 250MSPS ADC converter
core that utilizes a pipelined successive approximation
architecture (see Figure 36). The input voltage is captured by a
Sample-hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. Digital error correction is also
applied.
Power-on Calibration
The ADC core(s) perform a self-calibration at start-up. An internal
Power-on-reset (POR) circuit detects the supply voltage ramps
and initiates the calibration when the analog and digital supply
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voltages are above a threshold. The following conditions must be
adhered to for the power-on calibration to execute successfully:
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins must not be connected
• SDO has an internal pull-up and should not be driven externally
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
• SPI communications must not be attempted during
calibration, with the only exception of performing read
operations on the cal_done register at address 0xB6.
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
After the power supply has stabilized, the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
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ISLA222S
CLOCK
GENERATION
INP
INN
1.25V
2.5-BIT
2.5-BIT
FLASH
SHA
FLASH
+
–
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1-BIT/ STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
FIGURE 36. ADC CORE BLOCK DIAGRAM
than 0.5mA to assure exit from the reset state so calibration can
start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 37. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. During calibration the JESD204 transmitter PLL is not
locked to the ADC sample clock, so the CML outputs will toggle at
an undetermined rate. Normal operation is resumed once
calibration is complete.
At 250MSPS the nominal calibration time is 280ms, while the
maximum calibration time is 550ms.
CLKN
CLKP
CALIBRATION
TIME
RESETN
CAL_STATUS
BIT
CALIBRATION
BEGINS
CALIBRATION
COMPLETE
FIGURE 37. CALIBRATION TIMING
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User Initiated Reset
Recalibration of the ADC can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength in its high impedance
state of less than 0.5mA is recommended, as RESETN has an
internal high impedance pull-up to OVDD. As is the case during
power-on reset, RESETN and DNC pins must be in the proper
state for the calibration to successfully execute.
The performance of the ISLA222S changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the ADC under the environmental conditions at
which it will operate.
A supply voltage variation of <100mV will generally result in an
SNR change of <0.5dBFS and SFDR change of <3dBc. In
situations where the sample rate is not constant, best results will
be obtained if the device is calibrated at the highest sample rate.
Reducing the sample rate by less than 80MSPS will typically
result in an SNR change of <0.5dBFS and an SFDR change of
<3dBc.
Figures 38 through 43 show the affect of temperature on SNR
and SFDR performance with power on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated earlier. However, it can be seen
that performance drift with temperature is not a very strong
function of the temperature at which the power on calibration is
performed.
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ISLA222S
Temperature Calibration
73
95
-2dBFS, 125MSPS
-2dBFS, 125MSPS
SNR (dBFS)
-2dBFS, 200MSPS
SFDR (dBc)
-2dBFS, 250MSPS
72
-2dBFS, 250MSPS
90
-2dBFS, 200MSPS
85
-1dBFS, 250MSPS
71
-1dBFS, 200MSPS
-1dBFS, 125MSPS
-1dBFS, 125MSPS
-1dBFS, 200MSPS
80
-1dBFS, 250MSPS
70
-40
-35
-30
-25
75
-40
-20
-35
TEMPERATURE (°C)
FIGURE 38. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, fIN = 105MHz
72
-30
TEMPERATURE (°C)
-25
-20
FIGURE 39. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, fIN = 105MHz
90
-2dBFS, 125MSPS
-2dBFS, 250MSPS
-2dBFS, 200MSPS
-2dBFS, 200MSPS
-2dBFS, 125MSPS
-2dBFS, 250MSPS
SFDR (dBc)
SNR (dBFS)
85
71
80
-1dBFS, 125MSPS
-1dBFS, 125MSPS
-1dBFS, 200MSPS
-1dBFS, 250MSPS
-1dBFS, 200MSPS
-1dBFS, 250MSPS
70
5
10
15
20
25
30
TEMPERATURE (°C)
35
40
75
45
5
10
15
20
25
30
TEMPERATURE (°C)
35
40
45
FIGURE 41. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, fIN = 105MHz
FIGURE 40. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, fIN = 105MHz
90
72
-2dBFS, 125MSPS
-2dBFS, 250MSPS
-2dBFS, 125MSPS
-2dBFS, 200MSPS
-2dBFS, 200MSPS
85
SFDR (dBc)
SNR (dBFS)
71
-2dBFS, 250MSPS
80
70
-1dBFS, 125MSPS
-1dBFS, 200MSPS
-1dBFS, 200MSPS
-1dBFS, 250MSPS
-1dBFS, 125MSPS
-1dBFS, 250MSPS
69
65
67
69
71
73
75
77
79
TEMPERATURE (°C)
81
83
FIGURE 42. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, fIN = 105MHz
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85
75
65
70
75
TEMPERATURE (°C)
80
85
FIGURE 43. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, fIN = 105MHz
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ISLA222S
Analog Input
A single fully differential input (VINP/VINN) connects to the
Sample and Hold Amplifier (SHA) of each unit ADC. The ideal
full-scale input voltage is 2.0V, centered at the VCM voltage as
shown in Figure 44.
ADC
VINN
1.8
VINP
1.4
VCM
1.0V
1.0
FIGURE 47. DIFFERENTIAL AMPLIFIER INPUT
0.6
0.2
FIGURE 44. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are driven
differentially. The common mode output voltage, VCM, should be
used to properly bias the inputs as shown in Figures 45 through
47. An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate frequency
(IF) inputs. Two different transformer input schemes are shown in
Figures 45 and 46.
ADT1-1WT
ADT1-1WT
1000pF
ADC
VCM
0.1µF
FIGURE 45. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
ADTL1-12
TX-2-5-1
1000pF
ADC
A differential amplifier, as shown in the simplified block diagram
in Figure 47, can be used in applications that require
DC-coupling. In this configuration, the amplifier will typically
dominate the achievable SNR and distortion performance.
Intersil’s new ISL552xx differential amplifier family can also be
used in certain AC applications with minimal performance
degradation. Contact Intersil sales support with your needs.
When an over range occurs, the data sample output bits are held
at full scale (all 0’s or all 1’s), thus allowing the detection of this
condition in the receiver device.
Clock Input
The clock input circuit is a differential pair (see Figure 61 on
page 35). Driving these inputs with a high level (up to 1.8VP-P on
each input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, it is recommended to have high
slew rate at the zero crossing of the differential clock input
signal.
The recommended drive circuit is shown in Figure 48. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 through a Thevenin equivalent of 10kΩ to facilitate AC
coupling.
VCM
TC4-19G2+
1000pF
CLKP
1000pF
FIGURE 46. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
This dual transformer scheme is used to improve common mode
rejection, which keeps the common mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA222S is 600Ω.
The SHA design uses a switched capacitor input stage (see
Figure 60 on page 35), which creates current spikes when the
sampling capacitance is reconnected to the input voltage. This
causes a disturbance at the input, which must settle before the
next sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 2:1 or 1:1
transformer and low shunt resistance are recommended for
optimal performance.
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0.01µF
200

CLKN
1000pF
1000pF
FIGURE 48. RECOMMENDED CLOCK DRIVE
A selectable 2x or 4x frequency divider is provided in series with the
clock input. The divider can be used in the 2x mode with a sample
clock equal to twice the desired sample rate or in 4x mode with a
sample clock equal to four times the desired sample rate. Use of the
2x or 4x frequency divider enables the use of the phase slip feature,
which enables the system to be able to select the phase of the
divide by 2 or divide by 4 that causes the ADC to sample the
analog input.
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ISLA222S
Voltage Reference
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full scale range of each ADC is proportional to
the reference voltage. The nominal value of the voltage reference
is 1.25V.
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 26. A Delay-locked Loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52μs to regain lock at 250MSPS. The lock time is
inversely proportional to the sample rate.
The DLL has two ranges of operation, slow and fast. The slow
range can be used for ADC core sample rates between 40MSPS
and 100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate. The lane data
rate is related to the ADC core sample rate by a relationship that
is defined by the JESD204 transmitter configuration and has
additional frequency constraints; see“JESD204 Transmitter” on
page 20 for additional details.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (tJ) and SNR is shown in Equation 1 and is
illustrated in Figure 49.
1
SNR = 20 log 10  --------------------
 2f t 
IN J
(EQ. 1)
100
95
tj = 0.1ps
90
14 BITS
SNR (dB)
85
80
tj = 1ps
75
tj = 10ps
60
50
10 BITS
tj = 100ps
55
1M
10M
100M
INPUT FREQUENCY (Hz)
1G
FIGURE 49. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise as well. Internal aperture jitter is the uncertainty in
the sampling instant. The internal aperture jitter combines with
the input clock jitter in a root-sum-square fashion, since they are
not statistically correlated, and this determines the total jitter in
the system. The total jitter, combined with other noise sources,
then determines the achievable SNR.
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The digital outputs are in CML format, and feature analog and
digital characteristics compliant with the JESD204 standard
requirements.
Power Dissipation
The power dissipated by the device is dependent on the ADC
sample rate and the number of active lanes in the link. There is a
fixed bias current drawn from the analog supply for the ADC,
along with a fixed bias current drawn from the digital supply for
each active lane. The remaining power dissipation is linearly
related to the sample rate.
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power saving
modes are available: Nap and Sleep. Nap mode reduces power
dissipation significantly while taking a very short time to return to
functionality. Sleep mode reduces power consumption drastically
while taking longer to return to functionality.
In Nap mode the JESD204 lanes will continue to produce valid
encoded data, allowing the link to remain active and thus return to
a functional state quickly. The data transmitted over the lanes in
nap mode is the last valid ADC sample, repeated until leaving nap
mode. The 8b/10b encoder’s running disparity will prevent the
potentially long time repetition of this last valid sample from
creating DC bias on the lane. In sleep mode, the JESD204 lanes
will be deactivated to conserve power. Thus, sometime after wake
up code group alignment will be required to reestablish the link.
The input clock should remain running and at a fixed frequency
during Nap or Sleep and CSB should be high. The JESD204 link
will only remain established during nap mode if the input clock
continues to remain stable during the nap period.
12 BITS
70
65
Digital Outputs
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2. Please note
that power on calibration occurs at power-up time regardless of
the state of the NAPSLP pin; immediately following this power-on
calibration routine, the device will enter nap or sleep state if the
NAPSLP pin voltage dictates it is to do so.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Nap
AVDD
Sleep
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 26.
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ISLA222S
Data Format
.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
Output data can be presented in three formats: two’s
complement(default), Gray code and offset binary. The data
format can be controlled through the SPI port by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 26.
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
-Full Scale
0000 0000 0000
1000 0000 0000
0000 0000 0000
-Full Scale
+LSB
0000 0000 0001
1000 0000 0001
0000 0000 0001
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
Mid Scale
1000 0000 0000
0000 0000 0000
1100 0000 0000
+Full Scale
-1LSB
1111 1111 1110
0111 1111 1110
1000 0000 0001
+Full Scale
1111 1111 1111
0111 1111 1111
1000 0000 0000
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 50 shows this
operation.
BINARY
11
10
9
••••
1
0
••••
GRAY CODE
11
10
••••
9
1
0
FIGURE 50. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 51.
GRAY CODE
11
10
9
••••
1
0
Clock Divider Synchronous Reset
The function of clock divider synchronous reset is available as a
SPI-programmable overloaded function on the SYNCP and
SYNCN pins. Given that the clock divider reset and SYNC features
have the same electrical and timing requirements, this
overloading allows the system to generate only a single well
timed signal with respect to the ADC sample clock. Thus selects
the ADC’s interpretation of the signal as a SPI-programmable
option (see SPI register 0x77 description for more information).
By default the SYNCP and SYNCN pins will function as the
JESD204 SYNC~.
The use of clock divider reset function is a requirement in a
system that uses the ISLA214S50, ISLA214S35, or CLKDIV = 2
or 4 and also requires time alignment or deterministic latency of
multiple devices. Please contact Intersil sales support with your
needs about this feature and its usage.
Soft Reset
Soft reset is a function intended to be used when the power-on
reset is to be re-run. An application may decide to issue a soft
calibration command after significant temperature change or
after a change in the sample rate frequency to optimize
performance under the new condition.
Soft reset is issued by writing the soft reset bit at SPI address
0x00. Soft reset is a self-resetting bit in that will automatically
return to 0 once the power on calibration has completed.
••••
JESD204 Transmitter
Overview
••••
BINARY
11
10
9
••••
1
FIGURE 51. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats is
shown in Table 3.
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0
The conversion data is presented by a JESD204B-compliant SERDES
interface. The SERDES lane data rate supports typical speeds up to
4.375Gbps, exceeding the 3.125Gbps maximum specified by the
JESD204 rev A standard. Two packing modes are supported:
Efficient and Simple. A SYNC input is included, which is used for lane
initialization as well as time alignment of multiple converter devices.
AC coupling of the SERDES lane(s) on-the-board is required. A block
diagram of this SERDES transmitter is shown in Figure 52.
For more information about the standardized characteristics and
features of a JESD204 interface, please see JESD204 rev A and rev
B standards. For application design support, including evaluation kit
schematics and layout, reference FPGA project(s), and simulation
models for functionality and signal integrity, please contact Intersil
sales support with your needs and/or view application notes on the
Intersil website.
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ISLA222S
SERDES Block
Link Layer
Sample Data
Analog
Input
Analog
Input
Sample
Clock
Transport
Layer
Sample Data
Clock
Management
Scrambler
1+x14+x15
Encoder
8/10
Lane 0
SER
Logic
PLL
Multiply
- Code group Synchronization
- Alignment Characters
- Initial Lane Synchronization
- Etc
SYNC
Link Layer
Lane 1
Link Layer
Lane 2
FIGURE 52. SERDES TRANSMITTER BLOCK DIAGRAM
To maximize flexibility at the system level, two transport layer
packing modes are supported: simple and efficient. These two
modes allow the system designer flexibility to trade off between
the number of lanes to support a given throughput, the data rate
of these lanes and the complexity of the receiver. This translates
directly into providing system level trade-offs between cost,
power and resource usage of the receiver and complexity of the
solution.
Simple mode packs informationless bits onto each ADC sample
to form full 16-bit data. In simple mode packing, the frame clock
and ADC sample clock are the same frequency, easing frequency
scaling requirements at the system level, but decreasing the
payload efficiency of the lanes. Decreased payload efficiency of
the lanes increases the lane data rate required to support a given
throughput and may require additional lanes to support a given
configuration. The degree of payload efficiency loss is dependent
on the ADC resolution.
Efficient mode packs sequential ADC samples into a contiguous
block of an integer number of octets and then slices the block
into the octets for transport. This mode always achieves the
theoretical maximum payload of the lanes (80%) regardless of
the resolution of the ADC and the number of lanes used. This
mode provides the minimum number of lanes at the minimum
data rate that is theoretically possible given the 8b/10b
encoding used in JESD204 systems. In efficient packing mode,
frame clock and the ADC sample clock have an M/N relationship,
where M and N are small integers and vary depending on the
ADC resolution and number of lanes selected. Efficient mode
packing may require additional frequency scaling elements
(internal FPGA PLLs or discrete frequency scaling devices) to
generate the frame clock for the receiving device.
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The default configuration for this device is efficient packing
mode. Reconfiguration into the simple packing mode is
accomplished by programming the JESD204 parameters via the
SPI bus. See Table 5 on page 23 for the full list of parameters
values for each mode and product. Via SPI, the JESD204
transmitter is highly configurable, supporting efficient to simple
mode packing reconfiguration as well as “downgrading” a given
product’s JESD204 interface. For example, reconfiguring a 3-lane
product into 2 lanes (with each running faster than with 3 lanes),
or reducing the resolution of the ADC(s) to slow down the lane
data rate in systems where the full ADC resolution is not
required, are supported. Please contact Intersil sales support for
a full list of downgradeable configurations that are supported.
Signal integrity plots, including data eye, BER bathtub curves,
and edge histogram plots versus lane data rate can be found in
the “Typical Performance Curves” beginning on page 10.
Initial Lane Alignment
The link initialization process is started by asserting the SYNC~
signal to the ADC device. This assertion causes the JESD204
transmitter to generate comma characters, which are used by the
receiver to accomplish code group synchronization (bit and octet
alignment, respectively). Once code group synchronization is
detected in the receiver, it deasserts the SYNC~ signal, causing the
JESD204 transmitter to generate the Initial Lane Alignment
sequence (ILA). The ILA is comprised of 4 multiframes of data in a
standard format, with the length of each multiframe determined by
the K parameter as programmed into the SPI JESD204 parameter
table. The ILA includes standard control character markers that can
be used to perform channel bonding in the receiving device if
desired. The 2nd multiframe includes the full JESD204 parameter
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ISLA222S
data, allowing the receiver to auto-detect the lane configuration if
desired.
After completion of the ILA the JESD204 transmitter begins
transmitting ADC sample data. Continuous link and lane
alignment monitoring is accomplished via an octet substitution
scheme. The last octet in each frame, if identical to the last octet
in the previous frame, is replaced with a specific control
character. If both sides of the link support lane synchronization,
the last octet in each multiframe, if identical to the last octet in
the previous frame, is replaced with a different specific control
character. A more complete description of the link initialization
sequence including finite state machine implementation, can be
found in the JESD204 rev A standard.
LANE DATA RATE
The lane data rate for this product family is a function of the ADC
sample rate, the number of SERDES lanes used and packing
mode selected in the SERDES transmitter. Figure 53 illustrates
the relationship between ADC sample rate and SERDES lane rate
for various transmitter configurations. The SERDES can typically
operate from lane rates of 1 to over 4.375Gbs. For each ADC
speed grade, the SERDES lanes are tested at its maximum ADC
sample rate using three lane efficient packing as well as
two-lane, efficient packing for the 250 and 200MSPS speed
versions and one-lane, efficient packing for 125MSPS speed
version.
1 Lane
(Efficient Packing)
4000
LANE RATE (MBPS)
MULTI-CHIP TIME ALIGNMENT
The JESD204 standard (in various revisions) provides the
capability to time align multiple JESD204 ADC devices to a single
logic device (FPGA or ASIC). This feature is critical in many
applications that cannot tolerate the variable latency of the
JESD204 link and that must process pipeline depth correct data
from more than one ADC device.
Time alignment of multiple devices provides the capability to
align samples from multiple JESD204 ADC devices in the system
in a pipeline-depth correct manner, thus enabling the system to
analyze the ADC data from multiple devices while eliminating the
variable latency of the JESD204 link as a concern. This capability
enables configurations of JESD204 ADCs as IQ, interleave and/or
simultaneously-sampled converters.
This ADC family uses the asserted to deasserted SYNC~
transition as the absolute time event with which to generate a
known sequence of characters at the JESD204 transmitter of
equal pipeline depth between all ADC devices in the system to be
time aligned. This is consistent with the JESD204 rev B
subclass 2 device definition.
Test Patterns
4500
2 Lanes
(Simple
Packing)
3.125 GBPS
(JESD204)
3500
4.375 GBPS
3000
2500
2 Lanes
(Efficient
Packing)
2000
1500
1000
passes the lane alignment sequence through its descrambler.
Even if the receiver does not implement this detail, the 3rd and
subsequent octets can be descrambled to yield ADC data due to
the self-synchronizing nature of the scrambler used.
3 Lanes (Simple Packing)
3 Lanes (Efficient Packing)
50
70
90
110
130
150
170
190
210
230
250
ADC SAMPLE RATE (MSPS)
FIGURE 53. LANE DATA RATE AS A FUNCTION OF ADC SAMPLE
RATE, PACKING
SCRAMBLER
The bypassable scrambler is compliant with the scrambler
defined in the JESD204 rev A standard.
This implementation seeds the scrambler with the initial lane
alignment sequence, such that the first two octets following the
sequence can be properly descrambled if the receiver also
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The complexity of the JESD204 interface merits much more test
pattern capability than less complex parallel interfaces. This
device family consequently supports a much wider range of test
patterns than previous ADC families.
Supported test patterns include both transport and link layer
patterns. Transport layer patterns are passed through the
transport layer of the JESD204 transmitter, following the same
sequence of being packed and sliced into octets as the ADC
sample data. Link layer test patterns bypass the transport layer
and are injected directly into the 8b/10b encoder, serialized and
sent out of the physical media. Test pattern generation is
controlled through SPI register 0xC0.
Link layer PRBS patterns are standard PRBS patterns that can be
used with built-in standard PRBS checkers in, for example, FPGA
SERDES-capable pins.
All transport layer test patterns reinitialize their phase when the
SYNC~ deassertion occurs; consequently, a system that provides
a well timed SYNC~ signal with respect to the ADC sample clock
can expect transport layer test patterns to have consistent phase
with respect to that deassertion, which can be a significant aid
when debugging the system.
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TABLE 4. JESD204 CONFIGURATIONS AND CLOCK FREQUENCIES
ADC SAMPLE CLOCK RANGE (MHz)
LANE DATA RATE MULTIPLIER FROM
ADC SAMPLE CLOCK RATE
LANE DATA RATE (GBPS)
100 to 250 (Efficient Packing) 3 Lanes
(12-bits)*(2 ADC channels)*(10/8
encoder overhead)/(3 lanes) =
(240/24) = 10.0
1.00 to 2.50
66.67 to 250 (Efficient Packing) 2 Lanes
(12-bits)*(2 ADC channels)*(10/8
encoder overhead)/(2 lanes) =
(240/16) = 15
1.00 to 3.75
50 to 218.75(Simple Packing) 2 Lanes
(12-bits+4-bit tail)*(2 ADC
channels)*(10/8 encoder
overhead)/(2 lanes) = (320/16) = 20
1.00 to 4.375
40 to 145.8 (Efficient Packing) 1 Lane
(12-bits)*(2 ADC channels)*(10/8
encoder overhead)/(1 lane) = (240/8) =
30
1.20 to 4.375
40 to 109.375(Simple Packing) 1 Lane
(12-bits+4-bit tail)*(2 ADC
channels)*(10/8 encoder
overhead)/(1 lane) = (320/8) = 40
1.60 to 4.375
TABLE 5. JESD204 PARAMETERS
PACKING NUMBER
JESD204
MODE
OF LANES PARAMETER ENCODED
Efficient
Efficient
3
2
CF = 0
0
CS = 0
0
F=6
5
HD = 0
0
L=3
2
M=2
1
N = 12
11
N' = 12
11
S=6
5
K≥3
≥2
CF = 0
0
CS = 0
0
F=3
2
HD = 0
0
L=2
1
M=2
1
N = 12
11
N' = 12
11
S=2
1
K≥6
≥5
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JESD204 PARAMETERS AND FRAME MAP (Notes 16, 17, 18)
C0S0[11:4
C0S0[3:0]
C0S1[7:0]
C0S2[11:4]
COS1[11:8]
C0S4[11:4]
C0S4[3:0]
C1S2[3:0]
C0S5[7:0]
C1S0[11:4]
C0S0[3:0]
C1S0[3:0]
C1S1[7:0]
C1S1[11:8]
C1S3[7:0]
C1S3[11:8]
C0S0[11:4]
COS3[7:0]
COS3[11:8]
C0S5[11:8]
C1S2[11:4]
C0S2[3:0]
C1S4[11:4]
C1S4[3:0]
C1S5[7:0]
C1S5[11:8]
C0S1[7:0]
C0S1[11:8]
C1S0[11:4]
C1S0[3:0]
C1S1[7:0]
C1S1[11:8]
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TABLE 5. JESD204 PARAMETERS (Continued)
PACKING NUMBER
JESD204
MODE
OF LANES PARAMETER ENCODED
Simple
Efficient
Simple
2
1
1
CF = 0
0
CS = 0
0
F=2
1
HD = 0
0
L=2
1
M=2
1
N = 12
11
N' = 16
15
S=1
0
K≥9
≥8
CF = 0
0
CS = 0
0
F=6
5
HD = 0
0
L=1
0
M=2
1
N = 12
11
N' = 12
11
S=2
1
K≥3
≥2
CF = 0
0
CS = 0
0
F=4
3
HD = 0
0
L=1
0
M=2
1
N = 12
11
N' = 16
15
S=1
0
K≥5
≥4
JESD204 PARAMETERS AND FRAME MAP (Notes 16, 17, 18)
C0S0[11:4]
C0S0[3:0]
TTTT
C1S0[11:4]
C1S0[3:0]
TTTT
C0S0[11:4]
C0S0[3:0]
C0S1[7:0]
C1S0[11:4]
COS1[11:8]
C0S0[11:4]
C0S0[3:0]
TTTT
C1S0[3:0]
C1S1[7:0]
C1S1[11:8]
C1S0[11:4]
C1S0[3:0]
TTTT
NOTES:
16. The JESD204 parameters are shown as their actual values, with the JESD204 encoded values (i.e., the values that are programmed into the SPI
registers) in the next column over. Typically values that must always be greater than 1 are encoded as value minus 1, and so on.
17. Frame map format decoder: "CxSy[a:b]" = Converter x, Sample y, bits a through b. For example, "C0S0[13:6]" = Converter 0, Sample 0, bits 13 through
6, etc. "T" = Tail bit (information-less bit packed in the transport layer mapping to form octets).
18. The topmost lane in the graphical frame map is Lane0, followed by Lane1 and Lane 2 (for 3-lane configurations).
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CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A1
A10
A0
D7
D6
D5
D4
D3
D2
D1
D0
D2
D3
D4
D5
D6
D7
FIGURE 54. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A11
A2
A12
W0
W1
R/W
D1
D0
FIGURE 55. LSB-FIRST ADDRESSING
tDSW
CSB
tCLK
tHI
tDHW
tS
tH
tLO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
SPI WRITE
FIGURE 56. SPI WRITE
tDSW
CSB
tCLK
tHI
tS
tDHW
tH
tDVR
tLO
SCLK
WRITING A READ COMMAND
SDIO
R/W
W1
W0
A12
A11
A10
A9
A2
A1
READING DATA ( 3 WIRE MODE )
A0
D7
D6
D3
D2
D1 D0
( 4 WIRE MODE)
SDO
D7
D3
D2
D1 D0
SPI READ
FIGURE 57. SPI READ
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CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 58. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 59. N-BYTE TRANSFER
Serial Peripheral Interface
A Serial Peripheral Interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The SPI
bus consists of chip select (CSB), serial clock (SCLK) Serial Data
Output (SDO), and Serial Data Input/Output (SDIO). The maximum
SCLK rate is equal to the ADC sample rate (fSAMPLE) divided by 7
for write operations and fSAMPLE divided by 16 for reads. There is
no minimum SCLK rate.
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the Serial Data
Input/Output (SDIO) pin in three-wire mode. The state of the
SDIO pin is set automatically in the communication protocol
(described in the following). A dedicated Serial Data Output pin
(SDO) can be activated by setting 0x00[7] high to allow operation
in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the ADC functioning as a slave. Multiple slave
devices can interface to a single master in three-wire mode only,
since the SDO output of an unaddressed device is asserted in
four-wire mode.
The Chip-select Bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
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concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high-to-low
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 54 and 55 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
MSB-first mode, the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 6 on page 27). The lower 13 bits contain the
first address for the data transfer. This relationship is illustrated
in Figure 56, and timing values are given in “Switching
Specifications” on page 8.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
ADC (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed to stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
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TABLE 6. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
Figures 58 and 59 illustrate the timing relationships for 2-byte
and N-byte transfers, respectively. The operation for a 3-byte
transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various microcontrollers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. The
burst is ended by pulling the CSB pin high. Setting the burst_end
address determines the end of the transfer. During a write
operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending addresses.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
Device Information
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
ADDRESS 0X20: OFFSET_COARSE_COREA
ADDRESS 0X21: OFFSET_FINE_COREA
The input offset of the ADC core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 7. The data format is two’s complement.The
data format is two’s complement. Bit 0 in register 0xFE must be
set high to enable updates written to 0x20 and 0x21 to be used
by the ADC (see description for 0xFE).
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
TABLE 7. OFFSET ADJUSTMENTS
CoreA
CoreB
PARAMETER
0x21[7:0]
0x27[7:0]
FINE OFFSET
0x20[7:0]
0x26[7:0]
COARSE OFFSET
Steps
255
255
–Full Scale (0x00)
-133LSB (-47mV)
-5LSB (-1.75mV)
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
+Full Scale (0xFF)
+133LSB (+47mV)
+5LSB (+1.75mV)
Nominal Step Size
1.04LSB (0.37mV)
0.04LSB (0.014mV)
ADDRESS 0X22: GAIN_COARSE_COREA
ADDRESS 0X23: GAIN_MEDIUM_COREA
ADDRESS 0X24: GAIN_FINE_COREA
Gain of the ADC core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple coarse gain bits can be set for a total
adjustment range of ±4.2%. (‘0011’  -4.2% and ‘1100’  +4.2%).
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 0x23 and 0x24.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x23 and 0x24 to be used by the
ADC (see description for 0xFE).
TABLE 8. COARSE GAIN ADJUSTMENT
0x22[3:0] CoreA
0x26[3:0] CoreB
NOMINAL COARSE GAIN ADJUST
(%)
The generic die identifier and a revision number, respectively, can
be read from these two registers.
Bit 3
+2.8
Bit 2
+1.4
Device Configuration/Control
Bit 1
-2.8
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil ADC products.
Bit 0
-1.4
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TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
CoreA
CoreB
PARAMETER
0x23[7:0]
0x29[7:0]
MEDIUM GAIN
0x24[7:0]
0x2A[7:0]
FINE GAIN
Steps
256
256
–Full Scale (0x00)
-2%
-0.20%
Mid-scale (0x80)
0.00%
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to“Nap/Sleep” on page 19). This functionality
can be overridden and controlled through the SPI. This register is
not changed by a soft reset.
TABLE 10. POWER-DOWN CONTROL
0x25[2:0]
POWER DOWN MODE
VALUE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
When using the clock_divide feature, the sample clock edge that
the ADC uses to sample the analog input signal can be one of
several different edges on the incoming higher frequency sample
clock. For example, in clock_divide = 2 mode, every other
incoming sample clock edge gets used by the ADC to sample the
analog input. The phase_slip feature allows the system to control
which edge of the incoming sample clock signals gets used to
cause the sampling event, by “slipping” the sampling event by
one input clock period each time phase_slip is asserted.
The clkdivrst feature can work in conjunction with phase_slip.
After well-timed assertion of the clkdivrst signal (via overloading
on the SYNC inputs), the sampling edge position with respect to
the incoming clock rate will have been reset, allowing the system
to “slip” whatever desired number of incoming clock periods
from a known state.
ADDRESS 0X72: CLOCK_DIVIDE
The ADC has a selectable clock divider that can be set to divide
by two or one (no division). By default, CLOCK_DIVIDE is set to
divide by 1. This functionality can be overridden and controlled
through the SPI, as shown in Table 11. This register is not
changed by a soft reset.
TABLE 11. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
ADDRESS 0X27: OFFSET_FINE_COREB
000
Pin Control
The input offset of ADC CoreB can be adjusted in fine and coarse
steps in the same way that offset for CoreB can be adjusted. Both
adjustments are made via an 8-bit word as detailed in Table 7.
The data format is two’s complement. Bit 0 in register 0xFE must
be set high to enable updates written to 0x26 and 0x27 to be
used by the ADC (see description for 0xFE).
001
Divide by 1 (Default)
010
Divide by 2
other
Not Allowed
ADDRESS 0X26: OFFSET_COARSE_COREB
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
ADDRESS 0X28: GAIN_COARSE_COREB
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the logical coding of the
sample data. Data can be coded in three possible formats: two’s
complement(default), Gray code or offset binary. See Table 12.
This register is not changed by a soft reset.
TABLE 12. OUTPUT FORMAT CONTROL
VALUE
0x73[2:0]
OUTPUT FORMAT
ADDRESS 0X2A: GAIN_FINE_COREB
000
Two’s Complement (Default)
Gain of ADC CoreB can be adjusted in coarse, medium and fine
steps in the same way that CoreA can be adjusted. Coarse gain is a
4-bit adjustment while medium and fine are 8-bit. Multiple Coarse
Gain Bits can be set for a total adjustment range of ±4.2%. Bit 0 in
register 0xFE must be set high to enable updates written to 0x29
and 0x2A to be used by the ADC (see description for 0xFE).
010
Gray Code
100
Offset Binary
ADDRESS 0X29: GAIN_MEDIUM_COREB
ADDRESS 0X74: OUTPUT_MODE_B
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or slow.
Internal clock signals are generated by a Delay-locked Loop
(DLL), which has a finite operating range. Table 13 shows the
allowable sample rate ranges for the slow and fast settings.
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ADDRESS 0XC3: USER_PATT2_LSB
TABLE 13. DLL RANGES
DLL RANGE
MIN
MAX
UNIT
ADDRESS 0XC4: USER_PATT2_MSB
Slow
40
100
MSPS
Fast
80
250
MSPS
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 2
ADDRESS 0X77: SYNC_FUNCTION
ADDRESS 0XC6: USER_PATT3_MSB
BIT 0 CLKDIVRST
This bit controls the functionality of the SYNCP, SYNCN pins on
this device. By default, this bit equals ‘0’, which means that the
functionality of the SYNCP, SYNCN pins is the JESD204 SYNC.
Setting this bit equal to ‘1’ modifies the functionality of the
SYNCP, SYNCN pins to be CLKDIVRST, which is a synchronous
divider reset on all internal dividers in the device. Usage of this
CLKDIVRST functionality is required to support multichip time
alignment and deterministic latency for devices that use
interleaved product configurations (ISLA214S50 and
ISLA214S35), and for any other product configuration that uses
CLKDIV > 1. In both states, the setup and hold times with respect
to the sample clock remain the same. Contact Intersil sales
support for more details.
ADDRESS 0XB6: CALIBRATION STATUS
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete. This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which can’t be read until calibration is complete.
DEVICE TEST
The device can produce preset or user defined patterns on the
digital outputs to facilitate in-situ testing. A user can pick from
preset built-in patterns by writing to the output test mode field
[7:4] at 0xC0 or user defined patterns by writing to the user test
mode field [2:0] at 0xC0. The user defined patterns should be
loaded at address space 0xC1 through 0xD0, see the “SPI
Memory Map” on page 31 for more detail. The test mode is
enabled asynchronously to the sample clock, therefore several
sample clock cycles may elapse before the data is present on the
output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:4 Output Test Mode
These bits set the test mode according to the description in “SPI
Memory Map” on page 31.
Bits 2:0 User Test Mode
The three LSBs in this register determine the test pattern in
combination with registers 0xC1 through 0xD0. Refer to the “SPI
Memory Map” on page 31.
ADDRESS 0XC1: USER_PATT1_LSB
ADDRESS 0XC2: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 1.
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29
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 3.
ADDRESS 0XC7: USER_PATT4_LSB
ADDRESS 0XC8: USER_PATT4_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 4.
ADDRESS 0XC9: USER_PATT5_LSB
ADDRESS 0XCA: USER_PATT5_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 5.
ADDRESS 0XCB: USER_PATT6_LSB
ADDRESS 0XCC: USER_PATT6_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 6.
ADDRESS 0XCD: USER_PATT7_LSB
ADDRESS 0XCE: USER_PATT7_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XD0: USER_PATT8_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
ADDRESS 0xDF - 0xF3: JESD204 Registers
Address 0xDF-0xEE: JESD204 Parameter
Interface
This set of registers controls the JESD204 transmitter
configuration. By programming these parameters, the system
can select between efficient and simple packing, select the
number of powered up SERDES lanes, choose the ADC resolution
transmitted and so on. The JESD204 parameters for standard
dual channel products are shown in Table 4 on page 23. This is a
small subset of the total number of configurations supported;
contact Intersil sales support for details.
0xE0 through 0xED are the JESD204 parameter registers. These
parameters are written to set the transport layer mapping of the
JESD204 transmitter in this product family. These registers can
be written to shift between efficient and simple packing, to
enable or bypass scrambling, and to reduce the number of
powered up lanes used in the link. Each speed graded product
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allows downgrading of the JESD204 link (such as reducing the
number of lanes, reducing the converter resolution, etc), but not
upgrading. These parameters are communicated on every lane
of the link during the 2nd multiframe of the initial lane alignment
sequence, and therefore can be used by a generic JESD204
receiver the supports the given configuration. See the JESD204
specification for additional information on how these registers
are used in a JESD204 system, including encoding rules.
Bits 4:0 “S”, JESD204 Number of samples per converter per
frame cycle.
ADDRESS 0XDF: JESD204_UPDATE_CONFIG_START
ADDRESS 0XEA: JESD204_CONFIG_10
Bit 0 Update_start
Bit 7 “HD”, JESD204 HD indicates if a converter’s sample can be
split across multiple lanes in the link (always ‘0’ for this product
family).
This self-resetting bit is used to indicate that some or all the
JESD204 parameters (addresses 0xE0 through 0xED) are going
to be written. Writing a ‘1’ to this bit will hold the JESD204 PLL
and transmitter in a reset state while these parameters are
written, because these parameters can affect the transmitter’s
dynamic behavior (such as modifying the PLL’s frequency
multiplication). The bit will automatically reset to a ‘0’ once a ‘1’
is written to address 0xEE Bit[0] “update_config W1TC”. The
recommended sequence for modifying the JESD204 transmitter
is as follows:
1. Write a ‘1’ to 0xDF Bit[0]
2. Write some or all modified values to 0xE0 through 0xEC
3. Write a ‘1’ to 0xEE Bit[0]. Note: 0xDF Bit[0] and 0xEE Bit[0] will
automatically be reset to a ‘0’ once configuration has been
applied to the circuitry.
ADDRESS 0XE0: JESD204_CONFIG_0
Bits 7:0 “DID”, JESD204 Device ID number.
ADDRESS 0XE1: JESD204_CONFIG_1
Bits 4:0 “N”, JESD204 N is the converter resolution.
ADDRESS 0XE8: JESD204_CONFIG_8
Bits 4:0 “N’”, JESD204 N’ is the total number of bits per sample.
ADDRESS 0XE9: JESD204_CONFIG_9
Bits 4:0 “CF”, JESD204 CF is the number of control fames per
frame clock (always ‘0’ for this product family).
ADDRESS 0XEB: JESD204_CONFIG_11
Bits 7:0 “RES1”, JESD204 reserved for future use.
ADDRESS 0XEC: JESD204_CONFIG_12
Bits 7:0 “RES2”, JESD204 reserved for future use.
ADDRESS 0XED: JESD204_CONFIG_13
Bits 7:0 “FCHK” JESD204 checksum (unsigned sum MOD 256) of
all the other JESD204 parameter register values. This is a
read-only register, as the checksum is calculated by the device.
ADDRESS 0XEE:
JESD204_UPDATE_CONFIG_COMPLETE
Bit 0 Update_complete
Bits 3:0 “BID”, JESD204 Bank ID.
This self-resetting bit is used to indicate that all the modifications
to the JESD204 parameters are complete.
ADDRESS 0XE2: JESD204_CONFIG_2
ADDRESS 0XEF: JESD204_PLL_MONITOR_RESET
Bits 4:0 “LID” JESD204 Lane ID.
Bits 4:0 “L”, JESD204 L is the number of SERDES lanes in the
link.
Bit 0 “pll_lock_mon_rst”, This self resetting register resets the
state of the 0xF0 Bit[0] “latched_pll_lockn” bit. The purpose of
this pair of bits is as a debugging feature to the system designer.
The “latched_pll_lockn” bit indicates if the JESD204 transmitter
PLL inside the device has at any time lost lock since the last ‘1’
was written to the “pll_lock_mon_rst” bit. This can be used to
help identify the source of intermittent link lost errors in the
system.
ADDRESS 0XE4: JESD204_CONFIG_4
ADDRESS 0XF0: JESD204_STATUS
Bits 7:0 “F”, JESD204 Number of octets per frame period.
Bit 2 “op_cfg_wrong” indicates if the JESD204 parameters
(registers 0xE0 through 0xED) are supported by the JESD204
transmitter (a ‘1’ indicates they are not supported, a ‘0’ indicates
they are supported).
ADDRESS 0XE3: JESD204_CONFIG_3
Bit 7 “SCR”, JESD204 SCR controls if scrambling across the
SERDES lane(s) is enabled (‘1’ means enabled).
ADDRESS 0XE5: JESD204_CONFIG_5
Bits 4:0 “K” JESD204 Number of frame periods per multi-frame
period. This product family supports the full programmable range
of K (decimal 0 through 31), although note that the JESD204
standard dictates a minimum number for this parameter that is
configuration dependent.
ADDRESS 0XE6: JESD204_CONFIG_6
Bits 7:0 “M” JESD204 Number of converters per device.
ADDRESS 0XE7: JESD204_CONFIG_7
Bit 1“pll_lockn” indicates if the JESD204 transmitter PLL is
currently locked (a ‘1’ indicates it is not locked, a ‘0’ indicates it
is locked).
Bit 0 “latched_pll_lockn” indicates if the JESD204 transmitter
PLL has lost lock since the last assertion of the
“pll_lock_mon_rst” (see register 0xEF description for more
information).
Bits 7:6 “CS”, JESD204 CS is the number of control bits per
sample (Always ‘0’ for this product family).
Submit Document Feedback
30
FN8302.1
July 6, 2015
ISLA222S
ADDRESS 0XF1: JESD204_SYNC
Bit 0 “sync_req” this register provides a SPI-programmable
interface that can be used to assert and deassert the JESD204
SYNC~ functionality. Certain systems may benefit from the
elimination of SYNC~ as a separate board-level LVDS signal (and
the power, PCB space and pins it consumes), and these systems
can use this register to functionally assert and deassert SYNC~.
For this bit to have any effect, a ‘1’ must have previously been
written to the SYNC_FUNCTION (Address 0x77, bit 0).
A ‘1’ written to this bit will result in behavior identical to the
assertion of SYNC~ (comma character generation) and ‘0’ will
result in the behavior identical to the deassertion of SYNC~
(initial lane alignment sequence followed by converter data).
Usage of this SPI SYNC~ capability may compromise the
system’s ability to perform multi-chip time alignment, as the
SYNC~ asserted to deasserted transition using this register is not
well timed with respect to sample clock.
ADDRESS 0XF2: JESD204_TRANS_PAT_CONFIG
Bit 0 “no_mf_lane_sync”, By default, this device family assumes
that both sides of the link support lane synchronization. As per
the JESD204 rev A standard, in this case continuous frame
alignment monitoring via character substitution (section 5.3.3.4)
is modified such that a different control character is substituted
when the octet reoccurrence happens at the end of a multiframe.
This behavior occurs when Bit 0 is ‘0’ (the power on default).
Writing a ‘1’ to Bit 0 will inform the JESD204 transmitter than the
receiving device does not support lane synchronization, and
therefore the transmitter will no longer substitute this different
control character when reoccurrence of octets occurs at the end
of a multi-frame.
the length of the pattern. Setting Bit 1 in this register to a ‘0’ (also
the power-on default) and issuing this test pattern by writing to
0xC0 will cause the pattern to assume a “min()” interpretation of
the pattern described in section 5.1.6.2. Setting the bit to a ‘1’
will assume a “max()” interpretation of the described pattern.
ADDRESS 0XF3: JESD204_CML_POLARITY
0xF3 Bit[2:0]: “TX polarity flip lane x” This register allows the
system designer to invert the sense of the SERDES pins on a per
lane basis. For example, writing a ‘1’ to Bit[0] causes LANE0N to
functionally become LANE0P and LANE0P to become LANE0N.
This feature allows the system designer to avoid having to
crossover P and N sides of the CML pair on the board to match
pin out and layout of the transmitter and receiver. Typically, a
trace crossover would require vias, which can degrade the signal
integrity of the high-speed SERDES lanes.
ADDRESS 0XFE: OFFSET/GAIN_ADJUST_ENABLE
Bit 0 at this register must be set high to enable adjustment of
offset coarse and fine adjustments (0x20 and 0x21) and gain
medium and gain fine adjustments(0x23 and 0x24). It is
recommended that new data be written to the offset and gain
adjustment registers (0x20, 0x21, 0x23, 0x24) while Bit 0 is a
‘0’. Subsequently, Bit 0 should be set to ‘1’ to allow the values
written to the aforementioned registers to be used by the ADC.
Bit 0 should be set to a ‘0’ upon completion.
Bit 1 “trans_pat_max_len” There is some ambiguity of the proper
length of the JESD204 rev A section 5.1.6.2 required transport
layer test pattern. Specifically, that the description perhaps
should have “max()” in place of “min()” for the equation defining
SPI Memory Map
DUT Info
SPI Config/Control
ADDR.
(HEX)
PARAMETER NAME
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
00
port_config
SDO Active LSB First Soft Reset
01
Reserved
Reserved
02
burst_end
Burst end address [7:0]
03-07 Reserved
08
chip_id
09
chip_version
BIT 1
BIT 0
(LSB)
DEF. VALUE
(HEX)
Mirror
(Bit 5)
Mirror
(Bit 6)
Mirror
(Bit 7)
00h
00h
Reserved
0A-0F Reserved
Submit Document Feedback
BIT 2
Chip ID #
Read only
Chip Version #
Read only
Reserved
31
FN8302.1
July 6, 2015
ISLA222S
SPI Memory Map (Continued)
ADDR.
(HEX)
PARAMETER NAME
BIT 7
(MSB)
BIT 6
BIT 5
Device Config/Control
10-1F Reserved
20
offset_coarse_CoreA
21
offset_fine_CoreA
22
gain_coarse_CoreA
23
gain_medium_CoreA
24
gain_fine_CoreA
25
modes_CoreA
26
offset_coarse_CoreB
27
offset_fine_CoreB
28
gain_coarse_CoreB
29
gain_medium_CoreB
2A
gain_fine_CoreB
2B
modes_CoreB
Device Config/Control
skew_diff
71
phase_slip
72
clock_divide
73
output_mode_A
74
output_mode_B
BIT 1
BIT 0
(LSB)
DEF. VALUE
(HEX)
cal. value
Fine Offset
Reserved
cal. value
Coarse Gain
cal. value
Medium Gain
cal. value
Fine Gain
cal. value
Reserved
Power Down Mode CoreA [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
00h
NOT reset by
soft reset
Coarse Offset
cal. value
Fine Offset
cal. value
Reserved
Coarse Gain
cal. value
Medium Gain
cal. value
Fine Gain
Reserved
cal. value
Power Down Mode CoreB [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
00h
NOT reset by
soft reset
Reserved
Differential Skew
Reserved
80h
Next Clock
Edge
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
Other codes = Reserved
00h
01h
NOT reset by
soft reset
00h
Output Format [2:0]
000 = Two’s Complement (Default) NOT reset by
soft reset
010 = Gray Code
100 = Offset Binary
Other codes = Reserved
00h
NOT reset by
soft reset
DLL Range
0 = Fast
1 = Slow
Default=’0
’
Reserved
SYNC_function
Clkdivrst
78-B5 Reserved
B6
BIT 2
Reserved
75-76 Reserved
77
BIT 3
Coarse Offset
2C-6F Reserved
70
BIT 4
Reserved
cal_status
Reserved
Calibration
Done
Read only
B7-BF Reserved
Submit Document Feedback
32
FN8302.1
July 6, 2015
ISLA222S
SPI Memory Map (Continued)
ADDR.
(HEX)
C0
PARAMETER NAME
BIT 7
(MSB)
test_io
BIT 6
BIT 5
BIT 4
Output Test Mode [7:4]
BIT 3
JESD Test
Device Test
<7:4> = Output Test, <3> = JESD Test
JESD Test = 0
Output Test =
0x0 = Output Test Mode Off. During calibration MSB
justified constant output 0xCCCC
0x1 = Midscale adjusted by numeric format
0x2 = Plus full scale, adjusted by numeric format
0x3 = Minus full scale adjusted by numeric format
0x4 = Checkboard output - 0xAAAA, 0x5555
0x5 = reserved
0x6 = reserved
0x7 = 0xFFFF, 0x0000 all on pattern
0x8 = User pattern 8 deep, MSB justified with output
0x9 = reserved
0xA, Count-up ramp
0xB, PRBS-9
0xC, PRBS-15
0xD, PRBS-23
0xE, PRBS-31
0xF = reserved
JESD Test=1
Output Test =
0x0 = Link Layer Repeat K28.5+Lane Alignment Sequence
0x1, Link Layer Repeat K28.5
0x2, Link Layer Repeat D21.5
0x3, Link Layer Repeat K28.7
0x4, Link Layer PRBS-7
0x5, Link Layer PRBS-23
0x6, Link Layer All Zeros
0x7, Link Layer All Ones
0x8 - 0xE, reserved
0xF, JESD204 section 5.1.6.2 Transport Layer Test Pattern
C1
BIT 2
BIT 1
BIT 0
(LSB)
User Test Mode [2:0]
User Test Mode (Single ADC
products only)
0 = user pattern 1 only
1 = cycle pattern 1 through 2
2 = cycle pattern 1 through 3
3 = cycle pattern 1 through 4
4 = cycle pattern 1 through 5
5 = cycle pattern 1 through 6
6 = cycle pattern 1 through 7
7 = cycle pattern 1 through 8
User Test Mode (Dual and
interleaved ADC products only)
0 = cycle pattern 1 through 2
1 = cycle pattern 1 through 4
2 = cycle pattern 1 through 6
3 = cycle pattern 1 through 8
4 through 7 = NA
DEF. VALUE
(HEX)
00h
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C2
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C3
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C4
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C5
user_patt3_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C6
user_patt3_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C7
user_patt4_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C8
user_patt4_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C9
user_patt5_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CA
user_patt5_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CB
user_patt6_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CC
user_patt6_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CD
user_patt7_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CE
user_patt7_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CF
user_patt8_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
D0
user_patt8_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
D1-DE Reserved
Submit Document Feedback
Reserved
33
FN8302.1
July 6, 2015
ISLA222S
ADDR.
(HEX)
PARAMETER NAME
DF
JESD204_update_config_start
E0
JESD204_config_0
E1
JESD204_config_1
E2
JESD204_config_2
E3
JESD204_config_3
E4
JESD204_config_4
E5
JESD204_config_5
E6
JESD204_config_6
E7
JESD204_config_7
E8
JESD204_config_8
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
DEF. VALUE
(HEX)
update_
start
00h
DID (Device ID Number)
00h
BID (Bank ID Number)
LID (Lane ID Number)
SCR
L (Number of Lanes per Device)
F (Number of Octets per Frame)
K (Number of frames per multiframe)
M (Number of Converters per Device)
CS (Number of Control
bits per Sample)
N (Converter Resolution in bits)
N’ (Total number of bits per Sample)
S (Number of Samples per Converter per Frame)
See Description for Default Settings
JESD204 Interface
SPI Memory Map (Continued)
E9
JESD204_config_9
EA
JESD204_config_10
EB
JESD204_config_11
RES1
EC
JESD204_config_12
RES2
ED
JESD204_config_13
FCHK (Checksum)
EE
JESD204_update_config_
complete
update_
complete
00h
EF
JESD204_PLL_monitor_reset
pll_lock_
mon_rst
00h
F0
JESD204_status
latched_
pll_lockn
00h
F1
JESD204_sync
F2
JESD204_trans_pat_config
F3
JESD204_CML_polarity
HD
op_confg_ pll_lockn
wrong
sync_req
F4-FD Reserved
trans_pat_ no_mf_
max_len lane_sync
lane_2_
polarity
lane_1_
polarity
lane_0_
polarity
00h
Enable
‘1’=Enable
00h
Reserved
FE
Offset/Gain_Adjust_Enable
FF
Reserved
Submit Document Feedback
CF (Number of Control Words per Frame per Link)
Reserved
34
FN8302.1
July 6, 2015
ISLA222S
Equivalent Circuits
AVDD
AVDD
TO
CHARGE
PIPELINE
INP
E2
E1
600

AVDD
CLKP
AVDD
E3
CSAMP
4pF
11k

TO
CHARGE
PIPELINE
INN
18k

E3
E2
E1
TO
CLOCK-PHASE
GENERATION
AVDD
CSAMP
4pF
18k

AVDD 11k

CLKN
FIGURE 61. CLOCK INPUTS
FIGURE 60. ANALOG INPUTS
AVDD
AVDD
(20k PULL-UP
ON RESETN
ONLY)
AVDD
AVDD
INPUT
75k

OVDD
TO
SENSE
LOGIC
75k

280 

OVDD
OVDD
20k

INPUT
75k

TO
280
75k

LOGIC

FIGURE 63. DIGITAL INPUTS
FIGURE 62. TRI-LEVEL DIGITAL INPUTS
OVDD
50 
OVDD
50


LANE[2:0]P
AVDD
OVDD
VCM
LANE[2:0]N
1.0V
DATA
+
–
DATA
16mA
FIGURE 64. CML OUTPUTS
Submit Document Feedback
35
FIGURE 65. VCM_OUT OUTPUT
FN8302.1
July 6, 2015
ISLA222S
ADC Evaluation Platform
Intersil offers ADC Evaluation platforms, which can be used to
evaluate any of Intersil’s high speed ADC products. Each platform
consists of a FPGA based data capture motherboard and a family
of ADC daughtercards. The USB interface and evaluation
platform control software allow a user to quickly evaluate the
ADC’s performance at a user’s specific application frequency
requirements. More information is available at
http://www.intersil.com/converters/adc_eval_platform/
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Clock Input Considerations
used. Tri-level inputs (NAPSLP) accept a floating input as a valid
state and therefore should be biased according to the desired
functionality.
Definitions
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Exposed Paddle
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full scale
voltage less than 2 LSB. It is typically expressed in percent.
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins, as longer traces
between the ceramic bypass capacitors and the device pins will
increase inductance, which can result in diminished dynamic
performance. Best practices bypassing is especially important on
the AVDD and OVDD(PLL) power supply pins. Whenever possible,
each supply pin should have its own 0.1µF bypass capacitor.
Make sure that connections to ground are direct and low
impedance. Avoid forming ground loops.
CML Outputs
Output traces and connections must be designed for 50Ω (100Ω
differential) characteristic impedance. Keep traces direct and
short, and minimize bends and vias where possible. Avoid
crossing ground and power-plane breaks with signal traces. Keep
good clearance (at least 5 trace widths) between the SERDES
traces and other signals. Given the speed of these outputs and
importance of maintaining an open eye to achieve low BER,
signal integrity simulations are recommended, especially when
the data lane rate exceeds 3Gbps and/or the trace or cable
length between the ADC and the receiver gets larger than 20cm.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will
not be operated, do not require connection to ensure optimal
ADC performance. These inputs can be left floating if they are not
Submit Document Feedback
36
I2E The Intersil Interleave Engine. This highly configurable
circuitry performs estimates of offset, gain, and sample time
skew mismatches between the core converters, and updates
analog adjustments for each to minimize interleave spurs.
Integral Non-Linearity (INL) is the maximum deviation of the
ADC’s transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
Least Significant Bit (LSB) is the bit that has the smallest value or
weight in a digital word. Its value in terms of input voltage is
VFS/(2N - 1) where N is the resolution in bits.
Missing Codes are output codes that are skipped and will never
appear at the ADC output. These codes cannot be reached with
any input value.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the ADC FFT, caused by an AC signal
superimposed on the power supply voltage.
Signal-to-Noise and Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
FN8302.1
July 6, 2015
ISLA222S
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to full
scale) when the converter’s full scale input power is used as the
reference.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
July 6, 2015
FN8302.1
CHANGE
Removed Product Availability column from “Pin-compatible Family” on page 1.
Removed “Coming Soon” from parts in ordering information on page 4 and changed ADCMB-HSFMC-EV1Z to
ADCMB-HSFMCEV1Z
Changed default value for register 72 from 00h to 01h in “SPI Memory Map” on page 32.
Under “Address 0x72: clock_divide” on page 28, replaced the sentence "By default, the tri-level CLKDIV pin
selects the divisor." with the sentence "By default, CLOCK_DIVIDE is set to divide by 1.
In Table 11 on page 28, added the phrase "(Default)" to the right of "Divide by 1" in the second row.
May 1, 2012
FN8302.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
37
FN8302.1
July 6, 2015
ISLA222S
Package Outline Drawing
L48.7x7G
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 1/10
7.00
6
6
PIN #1
INDEX
AREA
4X 5.5
A
B
37
PIN 1
INDEX AREA
48
36
1
7.00
44X 0.50
(4X)
EXP. DAP
5.70 SQ.
12
25
0.15
24
13
48X 0.40
48x 0.20 4
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
1.00 MAX
0.10 C
0.08 C
SEATING PLANE
( 44X 0 . 5 )
6 .80 SQ
C
SIDE VIEW
5.70 SQ
C
0 . 2 REF
5
( 48X 0 . 20 )
0 . 00 MIN.
0 . 05 MAX.
( 48X 0 . 60 )
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.015mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
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38
FN8302.1
July 6, 2015