DAC8871
DA
C8
871
SBAS396 – JUNE 2007
16-Bit, Single-Channel, ±18V Output (Unbuffered), Ultra-Low Power, Serial Interface
DIGITAL-TO-ANALOG CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
16-Bit Resolution
Output: ±18V for ±18V Reference Input
±18V Supply Operation
Very Low Power
High Accuracy INL: 1LSB
Low Noise: 10nV/√Hz
Fast Settling: 1µs to 1LSB
Fast SPI™ Interface: Up To 50MHz
16-Pin TSSOP Package
Selectable Reset to Zero or Midscale
The DAC8871 is a 16-bit, single-channel, serial
input, voltage output digital-to-analog converter
(DAC). The output range is determined by the
reference voltage, VREFH and VREFL. By properly
selecting the reference, the output can be unipolar or
bipolar, and up to ±18V. These converters provide
excellent linearity (1LSB INL), low noise, and fast
settling (1µs to 1LSB of full scale output) over the
specified temperature range of –40°C to +105°C.
The output is unbuffered, which reduces the power
consumption and the error introduced by the buffer.
The device features a standard high-speed clock (up
to 50MHz), and a 3V or 5V SPI serial interface to
communicate with the DSP or microprocessors.
APPLICATIONS
•
•
•
•
•
For optimum performance, a set of Kelvin
connections to external reference are provided. The
DAC8871 is available in a TSSOP-16 package.
Portable Equipment
Automatic Test Equipment
Industrial Process Control
Data Acquisition Systems
Optical Networking
VSS
RSTSEL
RST
VCC
VDD
DGND
VREFH-S VREFH-F VREFL-F VREFL-S
Control
Logic
VOUT
DAC
LDAC
AGND
CS
SCLK
Serial
Interface
SDI
Input
Data
Register
DAC
Latch
DAC8871
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI DSP is a trademark of Texas Instruments.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
DAC8871
www.ti.com
SBAS396 – JUNE 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
(1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PACKAGELEAD
PACKAGE
DESIGNATOR
DAC8871B
±1
±1
–40°C to +105°C
8871
TSSOP-16
PW
DAC8871
±3
±1
–40°C to +105°C
8871
TSSOP-16
PW
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted).
DAC8871
UNIT
–0.3 to +7
V
–0.3 to (VDD + 0.3)
V
AGND to DGND
–0.3 to +0.3
V
VCC to VSS
–0.3 to +39.6
V
VCC to AGND
–0.3 to +19.8
V
VSS to AGND
+0.3 to –19.8
V
VREFH to VREFL
–0.3 to +39.6
V
VREFH to AGND
–0.3 to +19.8
V
VREFL to AGND
–19.8 to +17.5
V
Operating temperature range
–40 to +105
°C
Storage temperature range
–65 to +150
°C
+150
°C
VDD to GND
Digital input voltage to GND
Maximum junction temperature (TJ max)
Power dissipation
Thermal impedance, θJA
(1)
2
TSSOP-16
(TJ max - TA)/θJA
W
161.4
°C/W
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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SBAS396 – JUNE 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, and VDD = +5V, unless
otherwise noted; specifications subject to change without notice.
DAC8871
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
Resolution
Linearity error
16
DAC8871B
VREFH = 10V, VREFL = –5V
VREFH = 10V, VREFL = –10V
DAC8871
Differential linearity error
Gain error
TA = +25°C
±1
LSB
±1
±1.5
LSB
±1
±3
LSB
±0.25
±1
LSB
±0.5
±2
±1
TA = +25°C
±0.5
TA = +25°C
±4
LSB
ppm/°C
±2
±0.05
Zero code drift
LSB
ppm/°C
±0.1
Bipolar drift
Zero code error
±0.75
±0.1
Gain drift
Bipolar zero error
Bits
LSB
ppm/°C
OUTPUT CHARACTERISTICS
Voltage output
VREFL
Output impedance
VREFH
6.25
Settling time
To 1LSB of FS, CL = 15 pF
Slew rate (1)
CL = 15pF
Digital feedthrough (2)
Output noise
TA = +25°C
Power supply rejection
Supplies vary ±10%
V
kΩ
1
µs
40
V/µs
0.2
nV-s
10
nV/√Hz
±1
LSB
REFERENCE INPUT
VREFH
Ref high input voltage range
VREFL
Ref low input voltage range
0
–18
Ref high input current
Ref low input current
Reference input impedance (3)
Reference input capacitance
+18
VREFH – 1.25
V
V
1.3
mA
–1.3
mA
7.5
kΩ
Code = 0000h
75
pF
Code = FFFFh
120
pF
DIGITAL INPUTS
VIL
VIH
(1)
(2)
(3)
VDD = +5V
DGND
0.8
V
VDD = +3V
DGND
0.6
V
VDD = +5V
2.6
VDD
V
VDD = +3V
2.1
VDD
V
Input current
±1
µA
Input capacitance
10
pF
Input low voltage
Input high voltage
Slew Rate is measure from 10% to 90% of transition when the output changes from 0 to full scale.
Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output
does not change; CS is held high, while SCLK and DIN signals are toggled. It is specified with a full-scale code change on the SDI bus
(that is, from all 0s to all 1s and vise versa).
Reference input resistance is code-dependent, with a minimum at 8555h
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SBAS396 – JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, and VDD = +5V, unless
otherwise noted; specifications subject to change without notice.
DAC8871
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VCC
+13.5
+15
+19.8
V
VSS
–19.8
–15
–13.5
V
VDD
+2.7
POWER SUPPLY
+5.5
V
ICC
0.01
2
µA
ISS
–0.01
–2
µA
IDD
3
10
µA
15
30
µW
+105
°C
Power
TEMPERATURE RANGE
Specified performance
4
–40
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SBAS396 – JUNE 2007
PIN CONFIGURATION (NOT TO SCALE)
PW PACKAGE
TSSOP-16
(TOP VIEW)
VOUT
1
16
DGND
VCC
2
15
LDAC
VSS
3
14
SDI
AGND
4
13
SCLK
DAC8871
VREFH-F
5
12
CS
VREFH-S
6
11
RST
VREFL-S
7
10
RSTSEL
VREFL-F
8
9
VDD
TERMINAL FUNCTIONS
TERMINAL
NO.
DESCRIPTION
NAME
1
VOUT
Analog output of the DAC
2
VCC
Positive analog power supply: +15V
3
VSS
Negative analog power supply: –15V
4
AGND
Analog ground
5
VREFH-F
VREFH reference input (Force). Connect to external VREFH.
6
VREFH-S
VREFH reference input (Sense). Connect to external VREFH.
7
VREFL-S
VREFL reference input (Sense). Connect to external VREFL.
8
VREFL-F
VREFL reference input (Force). Connect to external VREFL.
9
VDD
Digital power. +5V for 5V interface logic; +3V for 3V logic.
10
RSTSEL
Power-On-Reset select. Determines VOUT after power-on reset. If tied to VDD, the DAC latch is set to mid-scale
after power-on, and VOUT is (VREFH– VREFL)/2. If tied to DGND, the DAC latch is cleared ('0'), and VOUT is VREFL.
11
RST
Reset (active low)
12
CS
Chip select input (active low). Data are not clocked into SDI unless CS is low.
13
SCLK
Serial clock input
14
SDI
Serial data input. Data are latched into input register on the rising edge of SCLK.
15
LDAC
Load DAC control input (active low). When LDAC is low, the DAC latch is simultaneously updated with the content
of the input register.
16
DGND
Digital ground
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SBAS396 – JUNE 2007
TIMING DIAGRAMS
tTD
CS
tDelay
DAC
Updated
tSCK
tLead
tLag
tWSCK
tWSCK
tDSCLK
SCLK
tSU
Bit 15 (MSB)
SDI
LDAC
tHO
Bit 14
Bit 13, ..., Bit 1
Bit 0
LOW
tRST
RST
-- Don’t Care
Figure 1. Case 1—LDAC Tied Low
tTD
CS
tDelay
tSCK
tLead
tWSCK
tLag
tWSCK
tDSCLK
SCLK
tSU
tHO
Bit 15 (MSB)
SDI
Bit 14
Bit 13, ..., Bit 1
Bit 0
tDLADC
HIGH
LDAC
DAC
Updated
tRST
RST
-- Don’t Care
Figure 2. Case 2—LDAC Active
6
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SBAS396 – JUNE 2007
TIMING CHARACTERISTICS: VDD = +5V
(1) (2)
At –40°C to +105°C, unless otherwise noted.
PARAMETER
MIN
MAX
UNIT
tSCK
SCLK period
20
ns
tWSCK
SCLK high or low time
10
ns
tDelay
Delay from SCLK high to CS low
10
ns
tLead
CS enable lead time
10
ns
tLag
CS enable lag time
10
ns
tDSCLK
Delay from CS high to SCLK high
10
ns
tTD
CS high between active period
30
ns
tSU
Data setup time (input)
10
ns
tHO
Data hold time (input)
0
ns
tWLDAC
LDAC width
30
ns
tDLDAC
Delay from CS high to LDAC low
30
ns
tRST
Reset (RST) low
10
ns
VDD high to CS low (power-up delay)
10
µs
(1)
(2)
Assured by design. Not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
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SBAS396 – JUNE 2007
TYPICAL CHARACTERISTICS
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +25°C
VREFH = 10V
VREFL = -5V
0.75
0.50
0.25
0
-0.25
0.50
0
-0.25
-0.50
-0.75
-0.75
-1.00
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
TA = -40°C
VREFH = 10V
VREFL = -5V
0.75
0.50
0.50
DNL (LSB)
0.25
0
-0.25
TA = -40°C
VREFH = 10V
VREFL = -5V
0.75
0.25
0
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 5.
Figure 6.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +105°C
VREFH = 10V
VREFL = -5V
0.75
0.50
0
-0.25
TA = +105°C
VREFH = 10V
VREFL = -5V
0.75
0.50
DNL (LSB)
0.25
0.25
0
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 7.
8
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 3.
1.00
INL (LSB)
0.25
-0.50
-1.00
INL (LSB)
TA = +25°C
VREFH = 10V
VREFL = -5V
0.75
DNL (LSB)
INL (LSB)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 8.
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SBAS396 – JUNE 2007
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
TA = +25°C
0.75
0.50
0.50
DNL (LSB)
INL (LSB)
0.25
0
-0.25
-0.50
-0.75
0
-0.25
-0.75
-1.25
-1.50
-1.00
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 9.
Figure 10.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = -40°C
0.75
TA = -40°C
0.75
0.50
0.50
DNL (LSB)
0.25
INL (LSB)
0.25
-0.50
-1.00
0
-0.25
-0.50
-0.75
0.25
0
-0.25
-0.50
-1.00
-0.75
-1.25
-1.50
-1.00
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 11.
Figure 12.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
TA = +105°C
0.75
TA = +105°C
0.75
0.50
0.50
DNL (LSB)
0.25
INL (LSB)
TA = +25°C
0.75
0
-0.25
-0.50
-0.75
0.25
0
-0.25
-0.50
-1.00
-0.75
-1.25
-1.50
-1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 13.
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
1.00
VREFH = 10V
VREFL = 0V
0.50
0.50
0.25
0.25
0
-0.25
-0.25
-0.50
-0.75
-0.75
-1.00
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 16.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.00
VCC = +18V
VSS = -18V
VREFH = +18V
VREFL = -18V
1.50
1.00
0.75
0.50
DNL (LSB)
0.50
0
-0.50
0.25
0
-0.25
-1.00
-0.50
-1.50
-0.75
-2.00
VCC = +18V
VSS = -18V
VREFH = +18V
VREFL = -18V
-1.00
0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 17.
Figure 18.
INTEGRAL NONLINEARITY ERROR
vs REFERENCE VOLTAGE
DIFFERENTIAL NONLINEARITY ERROR
vs REFERENCE VOLTAGE
2.0
1.0
VCC = +18V
VSS = -18V
1.5
VCC = +18V
VSS = -18V
0.8
0.6
1.0
0.4
DNL (LSB)
0.5
0
-0.5
0.2
0
-0.2
-0.4
-1.0
-0.6
-1.5
-0.8
-2.0
-1.0
5
6
7
8
9
10 11 12 13 14 15 16 17 18
±Reference (V)
5
Figure 19.
10
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 15.
2.00
INL (LSB)
0
-0.50
-1.00
INL (LSB)
VREFH = 10V
VREFL = 0V
0.75
DNL (LSB)
INL (LSB)
0.75
6
7
8
9
10 11 12 13 14 15 16 17 18
±Reference (V)
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
INTEGRAL NONLINEARITY ERROR
vs ANALOG SUPPLY VOLTAGE
DIFFERENTIAL NONLINEARITY ERROR
vs ANALOG SUPPLY VOLTAGE
2.0
1.0
1.5
0.8
0.6
0.4
0.5
DNL (LSB)
INL (LSB)
1.0
0
-0.5
0.2
0
-0.2
-0.4
-1.0
-0.6
-1.5
-0.8
-2.0
-1.0
12
13
14
16
17
18
12
14
15
±Supply (V)
16
Figure 22.
GAIN ERROR
vs TEMPERATURE
ZERO-CODE ERROR
vs TEMPERATURE
0.5
0.75
0.4
VCC = 15V
VSS = -15V
VREFH = 10V
VREFL = 0V
0.25
VCC = 15V
VSS = 0V
VREFH = 10V
VREFL = 0V
0
-0.25
VCC = 15V
VSS = -15V
VREF = ±10V
-0.75
Zero-Code Error (LSB)
1.00
-0.50
0.3
0.2
0.1
17
18
Bipolar Mode
VCC = 15V
VSS = -15V
VREF = ±10V
Unipolar Mode
VCC = 15V
VSS = -15V
VREFH = 10V
VREFL = 0V
0
-0.1
-0.2
Unipolar Mode (Single Supply)
VCC = 15V VREFH = 10V
VSS = 0V
VREFL = 0V
-0.3
-0.4
-1.00
-0.5
-60
-40
-20
0
20
40
60
80
Temperature (°C)
100
120 140
-60
-40
-20
0
20
40
60
80
Temperature (°C)
100
Figure 23.
Figure 24.
BIPOLAR ZERO ERROR
vs TEMPERATURE
SUPPLY CURRENT
vs DIGITAL INPUT VOLTAGE
0
120 140
2.5
VCC = 15V
VSS = -15V
VREF = ±10V
Digital Input Code = 8000h
2.0
VDD = +5V
-0.25
IDD (mA)
BPZ Error (LSB)
13
Figure 21.
0.50
Gain Error (LSB)
15
±Supply (V)
1.5
1.0
-0.50
0.5
VDD = +3V
0
-0.75
-60
-40
-20
0
20
40
60
80
Temperature (°C)
100
120 140
0
Figure 25.
1
2
3
Digital Input Voltage (V)
4
5
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
DUAL REFERENCE CURRENT
vs CODE
SINGLE REFERENCE CURRENT
vs CODE
0
8192
VREFH Current (mA)
0
-250
-500
-750
-1000
-1250
-1500
800
700
600
500
400
300
200
100
0
VREFL Current (mA)
VREFH Current (mA)
VREFL Current (mA)
VREFH = +10V, VREFL = -10V
1500
1250
1000
750
500
250
0
0
-100
-200
-300
-400
-500
-600
-700
-800
VREFH = +10V, VREFL = 0V
0
16384 24576 32768 40960 49152 57344 65536
8192
16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Digital Input Code
Figure 27.
Figure 28.
SUPPLY CURRENTS
vs TEMPERATURE
DIGITAL SUPPLY CURRENT
vs DIGITAL SUPPLY VOLTAGE
5
4.0
3.5
Digital Supply Current (mA)
Supply Currents (mA)
4
IDD (VDD = 5V, VLOGIC = 5V)
3
2
IDD (VDD = 3V, VLOGIC = 3V)
1
ICC (VCC = 15V)
0
3.0
2.5
2.0
1.5
1.0
0.5
ISS (VSS = -15V)
0
-5
-60
-40
-20
0
20
40
60
80
Temperature (°C)
100
120 140
2.7
3.0
3.3
3.6 3.9 4.2 4.5 4.8 5.1 5.4
Digital Supply Voltage (V)
Figure 29.
Figure 30.
ANALOG SUPPLY CURRENT
vs ANALOG SUPPLY VOLTAGE
SUPPLY CURRENTS
vs REFERENCE VOLTAGES
5.7
6.0
18
20
5
0.10
4
0.06
Supply Currents (mA)
Analog Supply Current (mA)
0.08
0.04
0.02
ICC
0
ISS
-0.02
-0.04
-0.06
IDD (VDD = +5V)
3
2
IDD (VDD = +3V)
1
ICC (VCC = +18V)
0
-0.08
ISS (VSS = -18V)
-5
-0.10
10
11
12
13
14
15
16
±Analog Supply Voltage (V)
17
18
0
Figure 31.
12
2
4
6
8
10
12 14
±Reference Voltages (V)
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL =–10V, unless otherwise noted.
MAJOR CARRY GLITCH
(FALLING)
5V/div
MAJOR CARRY GLITCH
(RISING)
5V/div
LDAC
LDAC
VOUT
VOUT
200mV/div
200mV/div
Time (0.5ms/div)
Time (0.5ms/div)
Figure 33.
Figure 34.
DAC SETTLING TIME
(FALLING)
DAC SETTLING TIME
(RISING)
5V/div
5V/div
LDAC
LDAC
5V/div
VOUT
VOUT
5V/div
Time (0.5ms/div)
Time (0.5ms/div)
Figure 35.
Figure 36.
Noise Voltage (50mV/div)
BROADBAND
NOISE
BW = 10kHz
Code = 8000h
Time (10ms/div)
Figure 37.
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DAC8871
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THEORY OF OPERATION
GENERAL DESCRIPTION
The DAC8871 is a 16-bit, single-channel, serial-input, voltage-output DAC. It operates from a dual power supply
ranging from ±13.5V to ±19.8V, and typically consumes 10µA. The output range is from VREFL to VREFH. Data are
written to this device in a 16-bit word format, via an SPI serial interface. To ensure a known power-up state, the
DAC8871 is designed with a power-on reset function. After power on, the state of the RSTSEL pin sets the
value of the input register and DAC latch, which sets the output state of the VOUT pin. Refer to the Power-On
Reset and Hardware Reset section for more details.
Kelvin sense connections for the reference and analog ground are also included.
DIGITAL-TO-ANALOG SECTIONS
The DAC architecture consists of two matched DAC sections and is segmented. A simplified circuit diagram is
shown in Figure 38. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each
of these switches connects one of 15 matched resistors to either AGND or VREF. The remaining 12 bits of the
data word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.
R
R
VOUT
2R
2R
S0
2R
S1
2R
S11
2R
E1
2R
E2
2R
E15
VREFH-F
VREFH-S
VREFL-F
VREFL-S
12-Bit R-2R Ladder
Four MSBs Decoded into
15 Equal Segments
Figure 38. DAC Architecture
OUTPUT RANGE
The output of the DAC is:
(V
* VREFL) Code
V OUT + REFH
65536 ) V REFL
(1)
Where Code is the decimal data word loaded to the DAC latch.
For example, if VREFH is +10V, and VREFL is –10V, the range of VOUT is from –10V (code = 0000h) to +10V (code
= FFFFh).
The range of VREFL is from –18V to (VREFH – 1.25V), and the range of VREFH is 0V to +18V. The output from the
DAC8871 can be unipolar (from 0V to +18V) or bipolar by setting the proper VREFL and VREFH values.
14
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DAC8871
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SBAS396 – JUNE 2007
THEORY OF OPERATION (continued)
POWER-ON RESET AND HARDWARE RESET
The DAC8871 has a power-on reset function. When the RSTSEL pin is low (tied to DGND), and after power-on
or a hardware reset signal is applied to the RST pin, the DAC latch is cleared ('0') and the VOUT pin is set to
negative full-scale. When RSTSEL is high, the DAC latch and VOUT are set to mid-scale.
SERIAL INTERFACE
The DAC8871 digital interface is a standard 3-wire connection compatible with SPI, QSPI™, Microwire™ and TI
DSP™ interfaces, which can operate at speeds up to 50 Mbits/second. The data transfer is framed by the chip
select (CS) signal. The DAC works as a bus slave. The bus master generates the synchronize clock (SCLK) and
initiates the transmission. When CS is high, the DAC is not accessed, and SCLK and SDI are ignored. The bus
master accesses the DAC by driving CS low. Immediately following the high-to-low transition of CS, the serial
input data on the SDI pin are shifted out from the bus master synchronously on the falling edge of SCLK and
latched on the rising edge of SCLK into the input shift register, MSB first. The low-to-high transition of CS
transfers the content of the input shift register to the input register.
All data registers are 16 bits. It takes 16 SCLK cycles to transfer one data word to the device. To complete a
whole data word, CS must be taken high immediately after the 16th SCLK is clocked in. If more than 16 SCLK
cycles are applied while CS is low, the last 16 bits are transferred into the input register on the rising edge of
CS. However, if CS is not kept low during the entire 16 SCLK cycles, the data are corrupted. In this case, reload
the DAC latch with a new 16-bit word.
The DAC8871 has an LDAC pin that allows the DAC latch to be updated asynchronously by bringing LDAC low
after CS goes high. In this case, LDAC must be kept high while CS is low. If LDAC is permanently tied low, the
DAC latch will be updated immediately after the input register is loaded (caused by the low-to-high transition of
CS).
EXTERNAL AMPLIFIER SELECTION
The output of the DAC8871 is unbuffered. The output impedance is approximately 6.2kΩ. If the applications
require an external buffer amplifier, the selected amplifier must have a low-offset voltage (1LSB = 305µV for
±10V output range), eliminating the need for output offset trims. Input bias current should also be low because
the bias current multiplied by the DAC output impedance (approximately 6.25kΩ) adds to the zero-code error.
Rail-to-rail input and output performance is required. For fast settling, the slew rate of the operational amplifier
should not impede the settling time of the DAC. The output impedance of the DAC is constant and
code-independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as
high as possible. The amplifier should also have a 3dB bandwidth of 1MHz or greater. The amplifier adds
another time constant to the system, thus increasing the settling time of the output. A higher 3dB amplifier
bandwidth results in a shorter effective settling time of the DAC and amplifier combination.
VSS
RSTSEL
RST
VCC
VDD
DGND
VREFH-S VREFH-F VREFL-F VREFL-S
+V
Control
Logic
DAC
VOUT
OPA277
or
OPA211
LDAC
AGND
CS
SCLK
SDI
-V
Serial
Interface
Input
Data
Register
6.2kW
DAC
Latch
LOAD
DAC8871
Figure 39. DAC8871 with External Amplifier
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SBAS396 – JUNE 2007
APPLICATION INFORMATION
REFERENCE INPUT
The DAC full-scale output voltage is determined by the reference voltage, as shown in the Output Range
section.
Reference input VREFH can be any voltage from 0V to +18V. Reference input VREFL can be any voltage from
–18V to 0V. The current into the VREFH input and out of VREFL depends on the DAC output voltages. Refer to
Figure 27 and Figure 28 for details. The reference input appears as a varying load to the reference. If the
reference can sink or source the required current, a reference buffer is not required. The DAC8871 features a
reference drive (force) and sense connection that minimizes the internal errors caused by the changing
reference current and the circuit impedances. Figure 40 shows a typical reference configuration.
DAC8871
VREFH
OPA2277
VREFH-F
VREFH-S
VREFL
OPA2277
VREFL-F
VREFL-S
Figure 40. Buffered Reference Connection
POWER SUPPLY BYPASSING
For accurate, high-resolution performance, bypassing the supply pins with a 10µF tantalum capacitor in parallel
with a 0.1µF ceramic capacitor is recommended.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC8871SBPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
DAC8871SBPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
DAC8871SBPWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
DAC8871SBPWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
DAC8871SPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
DAC8871SPWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
DAC8871SPWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
DAC8871SPWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
Call TI
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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