Renesas HD49335HNP Cds/pga & 10-bit a/d tg converter Datasheet

HD49335NP/HNP
CDS/PGA & 10-bit A/D TG Converter
REJ03F0097-0100Z
Rev.1.0
Feb.12.2004
Description
The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip.
There are address map and timing generator charts besides this specification. May be contacted to our sales department
if examining the details.
Functions
•
•
•
•
•
•
•
Correlated double sampling
PGA
Serial interface control
10-bit ADC
Timing generator
Operates using only the 3 V voltage
Corresponds to switching mode of power dissipation and operating frequency
Power dissipation: 220 mW (Typ), maximum frequency: 36 MHz (HD49335HNP)
Power dissipation: 150 mW (Typ), maximum frequency: 25 MHz (HD49335NP)
• ADC direct input mode
• QFN 64-pin package
Features
• Suppresses low-frequency noise, which output from CCD by the correlated double sampling.
• The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and
registers.
• High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier.
• PGA, pulse timing, standby mode, etc., is achieved via a serial interface.
• High precision is provided by a 10-bit-resolution A/D converter.
• Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization
(wave pattern). It is patented by Renesas.
• Timing generator generates the all of pulse which are needed for CCD driving.
Rev.1.0, Feb.12.2004, page 1 of 29
HD49335NP/HNP
VRM
VRT
VRB
BIAS
ADC_in
AVSS
DVSS3
STROB
SUB_PD
SUB_SW
XSUB
CH4
CH3
CH2
CH1
XV4
Pin Arrangement
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
49
31
50
30
51
29
52
28
53
27
54
26
55
25
56
24
57
23
58
22
59
21
60
20
61
19
62
18
63
17
64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
XV3
XV2
XV1
DVDD3
DVDD4
1/4clk_o
H2A
DVSS4
DVSS4
1/2clk_o
H1A
DVDD4
DVDD3
RG
Reset
VD_in
ID
DVSS1,2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DVDD2
DVSS3
CLK_in
HD_in
AVDD
BLKC
CDS_in
AVDD
BLKFB
BLKSH
AVSS
Test2
Test1
DLL_C
DVDD1
MON
41cont
CS
SDATA
SCK
(Top view)
Pin Description
Pin No.
Symbol
Description
I/O
Analog(A) or
Digital(D)
Remarks
1
ID
Odd/even number line detecting pulse output pin
O
D
2 mA/10 pF
2
DVSS1,2
CDS Digital ground + ADC output buffer ground (0 V)
—
D
3 to 12
D0 to D9
Digital output (D0; LSB, D9; MSB)
O
D
13
DVDD2
ADC output buffer power supply (3 V)
—
D
14
DVSS3
General ground for TG (0 V)
—
D
15
CLK_in
CLK input (max 72 MHz)
I
D
16
HD_in
HD input
I/O
D
17
VD_in
VD input
I/O
D
18
Reset
Hardware reset (for DLL reset)
I
D
Schmitt trigger
19
RG
Reset gate pulse output
O
D
3 mA/10 pF
20
DVDD3
General power supply for TG (3 V)
—
D
21
DVDD4
H1 buffer power supply (3 V)
—
D
22
H1A
H.CCD transfer pulse output-1A
O
D
30 mA/165 pF
23
1/2clk_o
CLK_in 2 divided output. 3 divided output at 3 divided mode
O
D
2 mA/10 pF
24
DVSS4
H1 buffer ground (0 V)
—
D
25
DVSS4
H1 buffer ground (0 V)
—
D
26
H2A
H.CCD transfer pulse output-2A
O
D
30 mA/165 pF
27
1/4clk_o
CLK_in 4 divided output. 6 divided output at 3 divided mode
O
D
2 mA/10 pF
28
DVDD4
H2 buffer power supply (3 V)
—
D
29
DVDD3
General power supply for TG (3 V)
—
D
Rev.1.0, Feb.12.2004, page 2 of 29
2 mA/10 pF
HD49335NP/HNP
Pin Description (cont.)
Pin No.
Symbol
Description
I/O
Analog(A) or
Digital(D)
30
XV1
V.CCD transfer pulse output-1
O
D
2 mA/10 pF
31
XV2
V.CCD transfer pulse output-2
O
D
2 mA/10 pF
32
XV3
V.CCD transfer pulse output-3
O
D
2 mA/10 pF
33
XV4
V.CCD transfer pulse output-4
O
D
2 mA/10 pF
34
CH1
Read out pulse output-1
O
D
2 mA/10 pF
35
CH2
Read out pulse output-2
O
D
2 mA/10 pF
36
CH3
Read out pulse output-3
O
D
2 mA/10 pF
37
CH4
Read out pulse output-4/XV6 at stripe mode
O
D
2 mA/10 pF
38
XSUB
Pulse output for electronic shutter
O
D
2 mA/10 pF
39
SUB_SW
SUB voltage control output-1. ADCK input
I/O
D
2 mA/10 pF
40
SUB_PD
SUB voltage control output-2/ XV5 at stripe mode
O
D
2 mA/10 pF
2 mA/10 pF
41
STROB
Flash control output. Input Vgate at Hi of pin 61
I/O
D
42
DVSS3
General ground for TG (0 V)
—
D
43
AVSS
Analog ground (0 V)
—
A
44
ADC_in
AD converter input pin
I
A
45
BIAS
Bias standard resistance
—
A
46
VRB
ADC bottom standard voltage (0.1 µF for GND)
—
A
47
VRT
ADC top standard voltage (0.1 µF for GND)
—
A
48
VRM
ADC middle standard voltage (0.1 µF for GND)
—
A
49
AVDD
Analog power supply (3 V)
—
A
50
BLKC
Black level C pin (1000 pF for GND)
—
A
51
CDS_in
CDS input pin
I
A
52
AVDD
Analog power supply (3 V)
—
A
53
BLKFB
Black level FB pin (1 µF between BLKFB and BLKSH)
I
A
54
BLKSH
Black level S/H pin
O
A
55
AVSS
Analog ground (0 V)
—
A
56
Test2
H: Normal operation, L: CDS single operation mode
Input 36; PBLK at testing, Input 37; OBP, Input 38; CPDM,
Input 39; ADCK, Input 40; SP2, Input 41; SP1
I
D
57
Test1
L: Slave mode, H: Master mode
I
D
58
DLL_C
Analog delay DLL external C pin (100 pF for GND)
O
A
59
DVDD1
Digital power supply (3 V) CDS, PAG, ADC part
—
D
60
MON
Pulse monitor (SP1, SP2, ADCK, OBP, CPDM, PBLK input)
O
D
61
41cont
Input STROB = pin 41, Input SUB_SW = pin 39 at Low
Input Vgate = pin 41, Input ADCK = pin 39 at Hi
I
D
62
CS
Serial data CS at CDS part
I
D
63
SDATA
Input serial data
I
D
64
SCK
Input serial clock
I
D
Rev.1.0, Feb.12.2004, page 3 of 29
Remarks
2 mA/10 pF
HD49335NP/HNP
Input/Output Equivalent Circuit
Pin Name
Digital output
Equivalent Circuit
D0 to D9, HD_in, VD_in,
H1A, H2A, 1/2clk_o,
1/4clk_o, 41cont,
SUB_SW, SUB_PD
DVDD
DIN
Digital
output
ENABLE
DVDD
ID, RG, MON, XV1 to XV4,
CH1 to CH4, XSUB
Digital
output
DIN
Digital input
DVDD
CLK_in, HD_in, VD_in,
ADCLK, OBP, SPBLK,
SPSIG, CS, SCK, SDATA,
PBLK, OEB, Reset, Test1,
Test2, SUB_SW, STROB
Digital
input
*1
Note: Only OEB is pulled down to about 70 kΩ.
Analog
Internally
connected
to VRT
CDS_in
AVDD
CDS_in
ADC_in
AVDD
Internally
connected
to VRT
ADC_in
BLKSH, BLKFB, BLKC
AVDD
+
−
BLKFB
BLKSH
BLKC
VRT, VRM, VRB
+
−
VRT
VRB
AVDD
BIAS
Rev.1.0, Feb.12.2004, page 4 of 29
AVDD
+
−
+
−
BIAS
VRM
HD49335NP/HNP
SUB_SW
SUB_PD
AVSS
Timing
generator
DLL
DVSS1 to 4
STROB
SP1
SP2
ADCLK
OBP
CPDM
PBLK
Reset
ADC_in
BLKSH
D9
D8
CDS
10bit
ADC
PGA
Output latch circuit
CDS_in
BLKC
BLKFB
DVDD1 to 4
AVDD
CLK_in
HD_in
VD_in
RG
H1A
1/2clk_o
H2A
1/4clk_o
XV1
XV2
XV3
XV4
CH1
CH2
CH3
CH4
XSUB
Block Diagram
DC offset
compensation
circuit
Serial
interface
Bias
generator
D7
D6
D5
D4
D3
D2
D1
Rev.1.0, Feb.12.2004, page 5 of 29
VRB
VRM
VRT
BIAS
CS
SDATA
SCK
DLL_C
MON
ID
D0
HD49335NP/HNP
Internal Functions
Functional Description
• CDS input
 CCD low-frequency noise is suppressed by CDS (correlated double sampling).
 The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *1
 Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *2
• ADC input
 The center level of the input signal is clamped at 512 LSB (Typ).
 Gain can be adjusted using 8 bits of register (0.01784 times steps, register settings) within the range from 0.57
times (–4.86 dB) to 5.14 times (14.22 dB). *2
• Automatic offset calibration of PGA and ADC
• DC offset compensation feedback for CCD and CDS
• Pre-blanking
 Digital output is fixed at clamp level
• Digital outputs enable function
Note: 1. It is not covered by warranty when 14LSB settings
2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Operating Description
Figure 1 shows CDS/PGA + ADC function block.
ADC_in
SP2
PG
AMP
CDS
AMP
C2
CDS_in
SP1
SP1
SH
C1 AMP
Gain setting
(register)
Current
DAC
VRT
D0 to D9
10bit
ADC
DAC
Clamp data
(register)
Offset
calibration
logic
DC offset
feedback
logic
BLKC
BLKFB
BLKSH
C4
C3
OBP
Figure 1 CDS/PGA Functional Block Diagram
1. CDS (Correlated Double Sampling) Circuit
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SP1 pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SP2 pulse, and then provided to CDSAMP (see figure 1).
The difference between these two signal levels is extracted by the CDSAMP, which also operates as a
programmable gain amplifier at the previous stage. The CDS input is biased with VRT (2 V). During the PBLK
period, the above sampling and bias operation are paused.
2. PGA Circuit
The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain
using 8 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 255.
In CDSIN mode: Gain = (–2.36 dB + 0.033 dB) × N (LOG linear).
In ADCIN mode: Gain = (0.57 times + 0.001784 times) × N (linear).
Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Rev.1.0, Feb.12.2004, page 6 of 29
HD49335NP/HNP
3. Automatic Offset Calibration Function and Black-Level Clamp Data Settings
The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration.
The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data
(14 LSB to 76 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts automatically after the RESET mode set by register is cancelled and
terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).
4. DC Offset Compensation Feedback Function
Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC (see figure 1).
The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is
the one cycle of the OBP.
∆Gain/∆H = 0.078/(fclk × C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)
Example: When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039
When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 2 times, 4 times, 8
times, or 16 times by changing the register settings (see table 1). Note that the open-loop differential gain
(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.
The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be
selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 16 LSB, the high-speed lead-in operation continues,
and when the offset error is 16 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4
H, or 8 H depending on the register settings. (Refer to table 2.)
Table 1 Loop Gain Multiplication Factor during
High-Speed Lead-In Operation
HGain-Nsel
(register settings)
[0]
[1]
L
L
H
L
L
H
H
H
Multiplication
Factor N
4
8
16
32
Table 2 High-Speed Lead-In Operation
Cancellation Time
HGstop-Hsel
(register settings)
[0]
[1]
L
L
H
L
L
H
H
H
Cancellation
Time
1H
2H
4H
8H
5. Pre-Blanking Function
During the PBLK input period, the CSD input operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp data (14 to 76 LSB).
Rev.1.0, Feb.12.2004, page 7 of 29
HD49335NP/HNP
PBLK
MINV
X
L
LINV
TEST0
H
L
TEST1
STBY
6. ADC Digital Output Control Function
The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output functions and the codes.
Table 3
ADC Digital Output Functions
D9
D8
ADC Digital Output
D7 D6 D5 D4
X
X
X Hi-Z
L
L
L Same as in table 4.
L
H
L D9 is inverted in table 4.
H
L
L D8 to D0 are inverted in table 4.
H
H
L D9 to D0 are inverted in table 4.
X
X
H Output code is set up to Clamp Level.
H
L
L
L Same as in table 5.
L
H
L D9 is inverted in table 5.
H
L
L D8 to D0 are inverted in table 5.
H
H
L D9 to D0 are inverted in table 5.
X
X
H Output code is set up to Clamp Level.
H
L
H
L
H
H
X
L
L
X
L
L
H
L
H
L
H
X
H
H
L
H
L
H
L
X
L
H
L
H
L
H
H
X
Note: 1. STBY, TEST, LINV, and MINV are set by register.
Table 4
D2
D1
D0
Operating Mode
Low-power wait state
Normal operation
Pre-blanking
Normal operation
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
Pre-blanking
Test mode
ADC Output Code (Binary)
Output Pin
Output Steps
codes
Table 5
D3
X
L
3
4
5
6
D9
L
L
L
L
D8
L
L
L
L
D7
L
L
L
L
D6
L
L
L
L
D5
L
L
L
L
D4
L
L
L
L
D3
L
L
L
L
D2
L
H
H
H
D1
H
L
L
H
D0
H
L
H
L
511
512
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
1020
1021
1022
1023
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
3
4
5
6
D9
L
L
L
L
D8
L
L
L
L
D7
L
L
L
L
D6
L
L
L
L
D5
L
L
L
L
D4
L
L
L
L
D3
L
L
L
L
D2
L
H
H
H
D1
H
H
H
L
D0
L
L
H
H
511
512
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1020
1021
1022
1023
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
H
H
L
ADC Output Code (Gray)
Output Pin
Output Steps
codes
Rev.1.0, Feb.12.2004, page 8 of 29
HD49335NP/HNP
7. Adjustment of Black-Level S/H Response Frequency Characteristics
The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the
register settings, as shown in table 6.
Table 6
SHSW CR Time Constant Setting
SHSW-fsel (Register setting)
[0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3]
L L L L H L L L L H L L H H L L L L H L H L H L L H H L H H H L
CR Time Constant (Typ) 2.20 nsec 2.30 nsec 2.51 nsec 2.64 nsec 2.93 nsec 3.11 nsec 3.52 nsec 3.77 nsec
(cutoff frequency conversion) (72 MHz) (69 MHz) (63 MHz) (60 MHz) (54 MHz) (51 MHz) (45 MHz) (42 MHz)
SHSW-fsel (Register setting)
[0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3]
L L L H H L L H L H L H H H L H L L H H H L H H L H H H H H H H
CR Time Constant (Typ) 4.40 nsec 4.80 nsec 5.87 nsec 6.60 nsec 8.80 nsec 10.6 nsec 17.6 nsec 26.4 nsec
(cutoff frequency conversion) (36 MHz) (33 MHz) (27 MHz) (24 MHz) (18 MHz) (15 MHz) (9 MHz)
(6 MHz)
8. The SHAMP frequency characteristics can be adjusted by changing the register settings
and the C4 value of the external pin.
The settings are shown in table 7.
Values other than those shown in the table 7 cannot be used.
BLKC
31
C
Recommendation value of C is 1000 pF
Table 7
SHAMP Frequency Characteristics Setting
LoPwr
(Register setting)
"Lo"
[0]
L
[1]
L
SHA-fsel (Register setting)
[1]
[0]
[1]
L
L
H
116 MHz
75 MHz
10000 pF
13000 pF
(270 pF)
(300 pF)
32 MHz
49 MHz
22000 pF
15000 pF
(750 pF)
(620 pF)
[0]
H
230 MHz
6800 pF
(240 pF)
"Hi"
100 MHz
10000 pF
(560 pF)
Note: Upper line : SHAMP cutoff frequency (Typ)
Middle line : Standard value of C4 (maximum value is not defined)
Lower line : Minimum value of C4 (do not set below this value)
Rev.1.0, Feb.12.2004, page 9 of 29
[0]
H
[1]
H
56 MHz
18000 pF
(360 pF)
24 MHz
27000 pF
(820 pF)
HD49335NP/HNP
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
0
1
2
~
9
10
11
• When CDS_in input mode is used
CDS_in
N
N+1
N+2
N+9
N+10
N−10
N−9
N−8
N−1
N
N+11
SP1
SP2
ADCLK
D0 to D9
• When ADC_in input mode is used
N+1
N
ADC_in
N+11
N+10
N+2
N+9
N+8
ADCLK
D0 to D9
N−9
N−8
N−1
N
N+1
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used
• The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes.
• Pipe-line delay is ten clock cycles when CDSIN is used and nine when ADCIN is used.
• In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.
Rev.1.0, Feb.12.2004, page 10 of 29
HD49335NP/HNP
Detailed Timing Specifications
Detailed Timing Specifications when CDSIN Input Mode is Used
Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.
Black
level
Signal
level
CDS_in
(2)
(3)
(1)
SP1
Vth
(5)
(4)
SP2
Vth
(6)
(7)
(8)
ADCLK
Vth
(9)
(10)
D0 to D9
(11)
(12)
(13)
H1
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used
Table 8
No.
(1)
(2)
(3)
(4)
(5)
(6)
(7), (8)
(9)
(10)
(11)
(12)
(13)
Timing Specifications when the CDSIN Input Mode is Used
Timing
Black-level signal fetch time
SP1 ‘Hi’ period
Signal-level fetch time
SP2 ‘Hi’ period
SP1 falling to SP2 falling time
SP1 falling to ADCLK rising inhibit time
ADCLK tWH min./tWL min
ADCLK rising to digital output holding time
ADCLK rising to digital output delay time
H1 rising to ADCLK rising time
H1 rising to SPSIG falling time
H1 rising to SPBLK falling time
Symbol
tCDS1
tCDS2
tCDS3
tCDS4
tCDS5
tCDS6
tCDS7, 8
tCHLD9
tCOD10
tCDS11
tCDS12
tCDS13
Min
—
Typ × 0.8
—
Typ × 0.8
Typ × 0.85
—
11
—
—
—
—
—
Typ
(1.5)
1/4fCLK
(1.5)
1/4fCLK
1/2fCLK
(5)
—
(7)
(16)
(1/4fCLK)
(1/fCLK)
(1/2fCLK)
Max
—
Typ × 1.2
—
Typ × 1.2
Typ × 1.15
—
—
—
—
—
—
—
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black
signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard).
OB period *1
CDS_in
N
N+1
N+5
N+12
OBP
OB pulse > 2 clock cycles
Note: 1. Shifts ±1 clock cycle depending on the OBP input timing.
Figure 4 OBP Detailed Timing Specifications
Rev.1.0, Feb.12.2004, page 11 of 29
N+13
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HD49335NP/HNP
Detailed Timing Specifications at Pre-Blanking
Figure 5 shows the pre-blanking detailed timing specifications.
PBLK
Vth
VOH
Digital output
(D0 to D9)
ADC
data
ADC
data
Clamp Level
VOL
ADCLK × 2 clock
ADCLK × 10 clock
Figure 5 Detailed Timing Specifications at Pre-Blanking
Detailed Timing Specifications when ADCIN Input Mode is Used
Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
ADC_in
(1)
(2)
(3)
ADCLK
Vth
(4)
(5)
D0 to D9
VDD/2
Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used
Table 9
Timing Specifications when ADCIN Input Mode is Used
No.
Timing
Symbol
Min
Typ
Max
Unit
(1)
(2), (3)
Signal fetch time
ADCLK tWH min./tWL min.
tADC1
tADC2, 3
—
Typ × 0.85
(6)
1/2fADCLK
—
Typ × 1.15
ns
ns
(4)
(5)
ADCLK rising to digital output hold time
ADCLK rising to digital output delay time
tAHLD4
tAOD5
—
—
(14.5)
(23.5)
—
—
ns
ns
Rev.1.0, Feb.12.2004, page 12 of 29
HD49335NP/HNP
Dummy Clamp
It adjusts the mis-clamp which occurs when taking the photo under the highlight conditions. (Like a sun) Normally it
woks with the OB clamp, however when black level is out of the range caused by hightlight enter to OB part, it changes
to clamp processing by dummy bit level. Resister settings are follows.
D12, D11, D10 of address H'F7 (Dummy CP)
0, 0, 0 ; OFF
0, 0, 1 ; +32
0, 1, 0 ; +64
0, 1, 1 ; +96
:
:
1, 1, 1 ; +224
The amount of offset are changes automatically
depends on PGA gain in the LSI.
D8, D8 of address H'F7 (DMCG)
The amount of feed back current can be
reduced with only dummy clamp.
Data = 0:1/4
1:1/8
2:1/16
3:1/32
SP2
CDS_in
CDS
AGC
SP1
SP1
SH
AMP
BLKFB
ADC
D8 to D9 of address H'F7
Current
cell
VRT
BLKSH
Detect 8clk
from OBP edge Digital output
−
+
)−(
Dummy Detect 4clk
DET from OPDM edge
)+(
+
−
+
on/off
Clamp level
D10 to D12 of address H'F7
Note: OB/Dummy switching part has 1/8 hysteresis of threshold value.
Figure 7 Internal Bias Circuitry
Rev.1.0, Feb.12.2004, page 13 of 29
OB
DET
HD49335NP/HNP
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Ratings
Unit
Power supply voltage
Analog input voltage
VDD
VIN
4.1
–0.3 to AVDD +0.3
V
V
Digital input voltage
Operating temperature range
VI
Ta
–0.3 to DVDD +0.3
–10 to +75
V
°C
Power dissipation
Storage temperature
Pt
Tstg
750
–55 to +125
mW
°C
Power supply voltage
Vopr
2.70 to 3.30
V
Note: AVDD, AVSS are analog power source systems of CDS, PGA, and ADC.
DVDD1, DVSS1 are digital power source systems of CDS, PGA and ADC.
DVDD2, DVSS2 are buffer power source systems of ADC output.
DVDD3, DVSS3 are general digital power source systems of TG.
DVDD4, DVSS4 are buffer power source systems of H1 and H2.
• Pin 2 multi bonds the DVSS1 and DVSS2
• When pin 64 is set to Low, pin 41 = STROB output, pin 39 = SUB_SW output
When Hi, pin 41 = Vgate input, pin 39 = ADCK input
Electrical Characteristics
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
• Items Common to CDSIN and ADCIN Input Modes
Item
Symbol
Min
Typ
Max
Unit
Power supply voltage
range
VDD
2.70
3.00
3.30
V
Conversion frequency
fCLK hi
20
—
36
MHz
LoPwr = low *2
HD49335HNP
fCLK low
5.5
—
25
MHz
LoPwr = high *2
HD49335NP
VIH2
DVDD
2.25 × 3.0
—
DVDD
V
VIL2
0
—
DVDD
0.6 × 3.0
V
VOH
DVDD –0.5
—
—
V
IOH = –1 mA
VOL
—
—
0.5
V
IOL = +1 mA
Digital input current
IIH
—
—
50
µA
VIH = 3.0 V
IIL
–50
—
—
µA
VIL = 0 V
ADC resolution
RES
10
10
10
bit
Digital input voltage
Digital output voltage
Test Conditions
Remarks
CS, SCK, SDATA
ADC integral linearity
INL
—
(2)
—
LSBp-p
fCLK = 25 MHz
ADC differential linearity+
DNL+
—
0.3
0.99
LSB
fCLK = 25 MHz
*1
ADC differential linearity–
DNL–
–0.99
–0.3
—
LSB
fCLK = 25 MHz
*1
Sleep current
ISLP
–100
0
100
µA
Digital input pin is
set to 0 V, output
pin is open
Standby current
ISTBY
—
3
5
mA
Digital I/O pin is set
to 0 V
Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes.
2. 2 divided mode: fCLK = 1/2CLK_in
3 divided mode: fCLK = 1/3CLK_in
3. Values within parentheses ( ) are for reference.
Rev.1.0, Feb.12.2004, page 14 of 29
HD49335NP/HNP
Electrical Characteristics (cont.)
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
• Items for CDSIN Input Mode
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Remarks
Consumption current (1)
IDD1
—
84
96.6
mA
fCLK = 36 MHz
CDSIN mode
LoPwr = low
Consumption current (2)
IDD2
—
58
66.7
mA
fCLK = 20 MHz
CDSIN mode
LoPwr = high
CCD offset tolerance range
VCCD
(–100)
—
(100)
mV
Timing specifications (1)
tCDS1
—
(1.5)
—
ns
Timing specifications (2)
tCDS2
Typ × 0.8
1/4fCLK
Typ × 1.2
ns
Timing specifications (3)
tCDS3
—
(1.5)
—
ns
Timing specifications (4)
tCDS4
Typ × 0.8
1/4fCLK
Typ × 1.2
ns
Timing specifications (5)
tCDS5
Typ × 0.85
1/2fCLK
Typ × 1.15
ns
Timing specifications (6)
tCDS6
1
5
9
ns
Timing specifications (7)
tCDS7
—
1/2fCLK
—
ns
Timing specifications (8)
tCDS8
—
1/2fCLK
—
ns
Timing specifications (9)
tCHLD9
—
(7)
—
ns
CL = 10 pF
Timing specifications (10)
tCOD10
—
(16)
—
ns
CL = 10 pF
Timing specifications (11)
tCDS11
—
(1/4fCLK)
—
ns
Timing specifications (12)
tCDS12
—
(1/fCLK)
—
ns
Timing specifications (13)
tCDS13
—
(1/2fCLK)
—
ns
Clamp level
CLP(00)
—
(14)
—
LSB
CLP(09)
—
(32)
—
LSB
CLP(31)
—
(76)
—
LSB
AGC(0)
–4.4
–2.4
–0.4
dB
AGC(63)
4.1
6.1
8.1
dB
AGC(127)
12.5
14.5
16.5
dB
AGC(191)
21.0
23.0
25.0
dB
AGC(255)
29.4
31.4
33.4
dB
DLL_2
11
—
25
MHz
*2
DLL_3
7
—
11
MHz
*3
DLL_4
5.5
—
7
MHz
*4
T/G 3/1divided operation
frequency range
CLK_in3
28.6
—
28.6
MHz
fCLK = 1/3CLK_in3
H Buffer output voltage
VOH
2.94
2.97
—
V
30 mA Buff, IOH = –5 mA
VOL
—
22
47
MV
30 mA Buff, IOL = +5 mA
VOH
2.89
2.94
—
V
14 mA Buff, IOH = –5 mA
VOL
—
50
112
MV
14 mA Buff, IOL = +5 mA
VOH
2.91
2.96
—
V
10 mA Buff, IOH = –3 mA
VOL
—
36
78
MV
10 mA Buff, IOL = +3 mA
VOH
2.85
2.93
—
V
4 mA Buff, IOH = –2 mA
VOL
—
60
129
MV
4 mA Buff, IOL = +2 mA
VOH
2.69
2.86
—
V
2 mA Buff, IOH = –2 mA
VOL
—
115
262
mV
2 mA Buff, IOL = +2 mA
VOH
2.81
2.90
—
V
IOH = –2 mA
VOL
—
78
141
mV
IOL = +2 mA
PGA gain at CDS input
DLL operation frequency
RG output voltage
Notes: 1.
2.
3.
4.
5.
Define digital output full scall with 1 V input as 0 dB.
Number of master steps: 60 steps, DLL current High
Number of master steps: 40 steps, DLL current Low
Number of master steps: 60 steps, DLL current Low
Values within parentheses ( ) are for reference.
Rev.1.0, Feb.12.2004, page 15 of 29
Refer to table 8
*1
HD49335NP/HNP
Electrical Characteristics (cont.)
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
• Items for ADCIN Input Mode
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Remarks
Consumption current (3)
IDD3
—
32
38.4
mA
fCLK = 36 MHz
ADCIN mode
LoPwr = low
Consumption current (4)
IDD4
—
22
27.5
mA
fCLK = 25 MHz
ADCIN mode
LoPwr = high
Timing specifications (14)
tADC1
—
(6)
—
ns
Timing specifications (15)
tADC2
Typ × 0.85
1/2fADCLK
Typ × 1.15
ns
Timing specifications (16)
tADC3
Typ × 0.85
1/2fADCLK
Typ × 1.15
ns
Timing specifications (17)
tAHLD4
—
(14.5)
—
ns
CL = 10 pF
Timing specifications (18)
tAOD5
—
(23.5)
—
ns
CL = 10 pF
Input current at ADC input
IINCIN
–110
—
110
µA
VIN = 1.0 to 2.0 V
Clamp level at ADC input
OF2
—
(512)
—
LSB
PGA gain at ADC input
GSL(0)
0.45
0.57
0.72
Times
GSL(63)
1.36
1.71
2.16
Times
GSL(127)
2.27
2.86
3.60
Times
GSL(191)
3.18
4.00
5.04
Times
GSL(255)
4.08
5.14
6.47
Times
Note : Values within parentheses ( ) are for reference.
Rev.1.0, Feb.12.2004, page 16 of 29
Refer to table 9
HD49335NP/HNP
Serial Interface Specifications
Timing Specifications
Data is determined
at CS rising edge
tINT2
tINT1
Latches SDATA
at SCK rising edge
CS
fSCK
SCK
tsu
SDATA
tho
D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
STD2(Upper data)
STD1(Lower data)
address(address)
Figure 8 Serial Interface Timing Specifications
Item
Min
Max
fSCK
tINT1,2
—
50 ns
5 MHz
—
tsu
tho
50 ns
50 ns
—
—
Notes: 1.
2.
3.
4.
5.
3 byte continuous communications.
Input SCK with 24 clock when CS is Low.
It becomes invalid when data communications are stopped on the way.
Data becomes a default with hardware reset.
Input more than double frequency of SCK to the CLK_in when transfer
the serial data.
The Kind of Data
Data address has 256 type. H’00 to H’FF
H’00
:
:
H’EF
Data at timing generator part
H’F0
:
:
H’FF
Data at CDS part
Address map of each data referred to other sheet.
Details of timing generator refer to the timing chart on the other sheet together with this specification.
This specification only explains about the data of CDS part.
Rev.1.0, Feb.12.2004, page 17 of 29
HD49335NP/HNP
Explanation of Serial Data of CDS Part
Serial data of CDS part are assigned to address H’F0 to H’F8. Functions are follows.
1
1
1
Address
1
0
0
0
0
STD1[7:0] (L)
STD2[15:8] (H)
D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13
PGA gain
test_I1
• PGA gain (D0 to D7 of address H’F0)
Details are referred to page 5 block diagram.
At CDS_in mode: –2.36 dB + 0.132 dB × N (Log linear)
At ADC_in mode: 0.57 times + 0.01784 times × N (Times linear)
∗: Full-scale digital output is defined as 0 dB when 1 V is input.
Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then
PGA outputs the 2 V full-range, and also ADC out puts the full code (1023).
This mean offset gain of PGA has 6 dB – 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add
on.
(1.0 V)
(1023)
(2.0 V)
(1.0 V)
CDS
PGA
ADC
0 dB when set N = 18 which correspond to 2.36 dB
(1) Level dia explain
2V
CDS
PGA
1023
ADC
(CDS = 0 dB)
3.64 dB + 0.132 dB × N
(2) Level dia on the circuit
Figure 9 Level Dia of PGA
• Test_I1 (D13 to D15 of address H’F0)
It controls the standard current of analog amplifier systems of CDS, PGA. Use data = 4 (D15 = 1) normally.
When data = 0, 50% current value with default
When data = 4, default
When data = 7, 150% current value with default
SLP
1
STBY
0
LINV
0
MINV
1
STD1[7:0] (L)
STD2[15:8] (H)
D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
test0
1
Address
1
1
0
test_I2
SHSW_fsel
SHA_fsel
• SLP and STBY (D0, D1 of address H’F1)
SLP:
Stop the all circuit. Consumption current of CDS part is less than 10 µA.
Start up from offset calibration when recover is needed.
STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA.
Allow 50 H time for feedback clamp is stabilized until recover.
Rev.1.0, Feb.12.2004, page 18 of 29
HD49335NP/HNP
• Output mode (D2 to D4 of address H’F1 and address H’F4 of D6)
It is a test mode. Combination details are table 3 to 5. Normally set to all 0.
• SHA-fsel (D8 to D9 of address H’F1)
It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 8. To get rough idea, set the
double cut off frequency point with using.
• SHSW-fsel (D10 to D13 of address H’F1)
It is a time constant which sampling the black level of SH amplifier. Frequency characteristics are referred to page
8. To get rough idea, set the double cut off frequency point with using. S/N changes by this data, so find the
appropriate point with set data to up/down.
• Test_I2 (D14 to D15 of address H’F1)
Current of ADC analog part can be set minutely. Normally use data = 0.
0: Default (100%)
1: 150%
2: 50%
3: 80%
0
1
STD1[7:0] (L)
D4 D3 D2
0
D1
Clamp level
STD2[15:8] (H)
D0 D15 D14 D13 D12 D11 D10 D9
Low_pwr
Address
1
0
CDS_buff
1
AD_sel
1
Reset
1
D8
HGain-Nsel
HGstop-Hsel
• Clamp (D0 to D4 of address H’F2)
Determine the OB part level with digital code of ADC output.
Clamp level = setting data × 2 + 14
Default data is 9 = 32 LSB.
• HGstop-Hsel, HGain-Nsel (D8 to D11 of address H’F2)
Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch
the high speed leading mode. Transfer the gain +1/–1 to previous field, its switch to high speed leading mode.
• Low_PWR (D12 of address H’F2)
Switch circuit current and frequency characteristic.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
• ADSEL (D14 of address H’F2)
Data = 0: Select CDS_in
Data = 1: Select ADC_in
• Reset (D15 of address H’F2)
Software reset.
Data = 1: Normal
Data = 0: Reset
Offset calibration should be done when starting up with using this bit. Details are referred to page 23.
1
1
1
Address
1
0
0
1
1
STD1[7:0] (L)
STD2[15:8] (H)
D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
• Address H'F3 are all testing data.
Normally set to all 0., or do not transfer the data.
Rev.1.0, Feb.12.2004, page 19 of 29
HD49335NP/HNP
1
1
1
Address
1
0
1
0
STD1[7:0] (L)
D7 D6 D5 D4 D3 D2 D1 D0
0
VD latch
H12_Buff
MON
• MON (D0 to D2 of address H’F4)
Select the pulse which output to pin MON (pin 60).
When D0 to D2: 0, Fix to Low
When 1, ADCLK
When 2, SP1
When 3, SP2
When 4, OBP
When 5, PBLK
When 6, CPDM
When 7, DLL_test
• H12Baff (D3 to D6 of address H’F4)
Select the buffer size which output to pin H1A, H2A (pin 22, 26).
D3: 2 mA buffer
D4: 4 mA buffer
D5: 10 mA buffer
D6: 14 mA buffer
Above data can be on/off individually. Default is D6 can be on only. (18 mA buffer)
• VD latch (D7 of address H’F4)
Data = 0: Gain data is determined when CS rising
Data = 1: Gain data is determined when VD falling
Differential Code and Gray Code (D8 to D12 of address H’F4)
• Gray code (D8 to D9 of address H’F4)
DC output code can be change to following type.
Gray Code [1]
Gray Code [0]
Output Code
0
0
0
1
Binary code
Gray code
1
1
0
1
Differential encoded binary
Differential encoded gray
• Serial data setting items (D10 to D12 of address H’F4)
Setting Bit
Setting Contents
Gray_test[0]
Gray_test[1]
Standard data output timing control signal
(Refer to the following table)
Gray_test[2]
ADCLK polar with OBP. (Lo→Positive edge, HI→Negative edge)
• Standard data output timing
Gray_test[1]
Gray_test[0]
Standard Data Output Timing
Low
Low
Third and fourth
Low
High
Fourth and fifth
High
High
Low
High
Fifth and sixth
Sixth and seventh
Rev.1.0, Feb.12.2004, page 20 of 29
STD2[15:8] (H)
D12 D11 D10 D9 D8
Gray_test
Gray code
HD49335NP/HNP
Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in
parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss
quantization) occurs to the image.
Differential code and gray code are recommended for this countermeasure.
Figure 10 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital
output bit can be reduced and easily to reduce the ripple using this function.
This function is especially effective for longer the settings of sensor more than clk = 30 kHz, and ADC output.
Figure 11 indicates the timing specifications.
10
Differential SW(D9)
ADC
+
−
2clk_DL
Carry bit
round
Standard data
control signal
(D12,D11,D10)
Gray SW(D8)
Standard
data
selector
10-bit
output
Gray→Binary
conversion
Figure 10 Differential Code, Gray Code Circuit
(In case of select the positive edge of ADCLK with D12)
ADCLK
OBP
(In case of select the positive polar)
(Beginning edge of OBP and standard edge of ADCLK should be exept ±5 ns)
1
Digital output
2
Differential data
3
4
5
6
Standard
data
7
8
9
10
11
Differential data
Figure 11 Differential Code Timing Specifications
To use differential code, complex circuit is necessary at DSP side.
From ADC
Gray →
Binary
D11
Carry bit
round
Standard
data
selector
Standard data
control signal
2clk_DL
D10
D11
D10
D9
D9
D0
D0
(2) Gray → Binary conversion
(1) Differential coded
Figure 12 Complex Circuit Example
1
1
1
Address
1
0
1
0
1
STD1[7:0] (L)
D7 D6 D5 D4 D3 D2 D1 D0
P_RG
1
1
1
Address
1
1
0
0
0
D6
P_ADCLK
STD1[7:0] (L)
D5 D4
D2
P_SP2
Rev.1.0, Feb.12.2004, page 21 of 29
P_SP2
P_SP1
D1
STD2[15:8] (H)
D12 D11 D10 D9 D8
DLL
current
DLL
steps
STD2[15:8] (H)
D0 D15 D14 D13 D12
D10 D9 D8
P_SP1 2,3 divided
select
P_RG
P_ADCLK
HD49335NP/HNP
• Address H’F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page. And D15 of address
H’F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid.
D15 of address H’F8 = 0
D15 of address H’F8 = 1
Divided mode
2 divided, 1/4 phase select
3 divided, 1/6 phase select
D0 to D7 of address H’F5
Valid
Invalid
D0 to D14 of address H’F8
Invalid
Valid
• Phase settings of high speed pulse (address H’F5 to H’F8)
(1) Select the 1/4 phase from figure 13 at 2 divided mode (D15 = 0 of address H’F8).
Select the 1/6 phase from figure 14 at 3 divided mode (D15 = 1 of address H’F8).
·····P_SP1, P_SP2, P_ADCLK, P_RG
(2) Then select the necessary delay time from figure 15.
·····DL_SP1, DL_SP2, DL_RG, DL_ADCLK
RG can be set both of rising / falling edge optionally.
H1
H1
Data = 0
Data = 1
P_SP1
P_SP2
Data = 2
Data = 0
Data = 1
P_ADCLK
P_RG
Data = 2
Data = 3
Data = 3
Figure 13 2 Divided Mode, 1/4 Phase Select (Valid at D15 = 0 of address H’F8)
H1
H1
Data = 5
Data = 0
Data = 0
Data = 1
Data = 1
P_SP1
P_SP2
Data = 2
Data = 2
P_ADCLK
P_RG
Data = 3
Data = 3
Data = 4
Data = 4
Data = 5
Figure 14 3 Divided Mode, 1/6 Phase Select (Valid at D15 = 1 of address H’F8)
Default Value of Each Phases
P_SP1
P_SP2
P_ADCLK
P_RG
2 divided mode
1
2
1
0
3 divided mode
0
3
1
5
Note: 50% of duty pulse makes tr, tf of RG by DLL.
1
1
1
Address
1
0
1
1
0
STD1[7:0] (L)
D7 D6 D5 D4 D3 D2 D1 D0
DL_SP2
1
1
1
Address
1
0
1
1
1
STD1[7:0] (L)
D7 D6 D5 D4 D3 D2 D1 D0
DL_RG_f
Rev.1.0, Feb.12.2004, page 22 of 29
DL_SP1
DL_RG_r
STD2[15:8] (H)
D12 D11 D10 D9 D8
CDS_test
DL_ADCLK
STD2[15:8] (H)
D12 D11 D10 D9 D8
Dummy
clamp th
Dummy
clamp current
HD49335NP/HNP
(3) Setting method of DLL
1. DLL step decides the how many divide the 1
cycle of sensor CLK. For reference,
set 1 ns(when 2 ns DLL_current bit = 0,
ADCLK(0)
when 1 set to 1 ns)
(In phase with H1)
Can be set 16 to 64 steps by 4 steps.
Steps = 4 + (4 × N); possible to set N = 3 to 15
Recommended steps is clk_in = when 11 to 14 MHz: H'0E(60 steps)
when 14 to 22MHz: H'09(40 steps)
when 22 to 50MHz: H'1E(60 steps)
P_ADCLK
when 50 to 72MHz: H'19(40 steps)
2. Can be change each 4 type of pulse 0 to 15 steps with
1 step. (1 ns or 2 ns divide)
3. Select the 2 ns divide when sensor CLK is less than
15 MHz.
P_SP1
Control voltage
DLL = 64 steps
PC
DLL = 15 steps
DL_ADCLK
DLL = 15 steps
H1
DL_SP1
DL_RG
P_SP2
10
DL_SP1
DLL = 15 steps
DL_SP2
DL_SP2
ADCLK
(0, 0)
DL_ADCLK
0
14
42
28
∗Default
DLL = 15 steps
(Falling)
56
(Rising)
Figure 15 Analog Delay (DLL) Circuit Block.
• CDS_test (D12 of address H’F6)
It is testing data. Normally set to 0.
• Dummy clamp current (D9 to 8 of address H’F7)
Data = When 0, 1/4
When 1, 1/8
When 2, 1/16
When 3, 1/32
Details are refer to page 12.
• Dummy clamp threshold (D12 to 10 of address H’F7)
Data = When 0, off
When 1, +32
When 2, +64
When 3, +96
When 4, +128
When 5, +160
When 6, +192
When 7, +224
Details are refer to page 12.
Rev.1.0, Feb.12.2004, page 23 of 29
AND
DL_RG
DLL_C
HD49335NP/HNP
Operation Sequence at Power On
Must be stable within the operating
power supply voltage range
VDD
CLK_in
3clk or more
Hardware
Reset
Note: At 2 divided mode: ADCLK = 1/2CLK_in
At 3 divided mode: ADCLK = 1/3CLK_in
6clk or more
HD49335
serial data transfer
2ms or more
(Charge of external C)
(1) (2) (3)
40,000ADCLK or more
(offset calibration)
(5)
(4)
SP1
Start control SP2
ADCLK
of TG and
camera DSP OBP
etc.
RESET bit
Automatic offset
calibration
CDS_Reset = Low
Automatic adjustment taking
40,000ADCLK period after
Reset cancellation
The following describes the above serial data transfer. For details of resistor settings are referred to serial data
function table.
(1) Resistor transfer of TG part
: Wait more than 6clk after release the hardware Reset and then transfer
the necessary data to TG part.
(2) DLL data transfer of CDS part : Transfer the phase data of RG, SP1, SP2, ADCLK of CDS part.
(3) Reset=L of CDS part
: Transfer Reset bit = 0 of address H'F2.
(4) Reset=H of CDS part
: Transfer Reset bit = 1 of address H'F2. (Reset release)
(5) Other data of CDS part
: Transfer the SH_SW_fsel and other PGA.
∗ Before transfer the Reset bit = 0, TG series pulse need to be settled, so address
H'00 to H'EF of TG part and H'F4 to H7F7 of CDS part should transfer in advance.
Rev.1.0, Feb.12.2004, page 24 of 29
HD49335NP/HNP
Timing Specifications of High Speed Pulse
• H1, H2, RG waveform
tr
twh
tf
H2
90%
50%
10%
H1
two
tr
twh
twl
tf
tH1DL
90%
50%
10%
RG
twl
twh
twl
tr
tf
Load
Unit capacitance
min
typ
max
min
typ
max
min
typ
max
min
typ
max
H1/H2
14
20
—
14
20
—
—
8.0
14
—
8.0
14
ns
165 pF
RG
7
10
—
—
37
—
—
4.0
—
—
4.0
—
ns
15 pF
XV1 to 4
—
—
—
—
—
—
—
20
—
—
20
—
ns
15 pF
CH1 to 4
—
—
—
—
—
—
—
20
—
—
20
—
ns
15 pF
XSUB/SUB_SW
—
—
—
—
—
—
—
20
—
—
20
—
ns
15 pF
Item
two
Item
H1/H2 overlap
min
typ
max
Unit
12
20
—
ns
Rev.1.0, Feb.12.2004, page 25 of 29
Power supply specification of H1, H2, RG are 3.0 V to 3.3 V.
Values are sensor CLK = when 18 MHz.
HD49335NP/HNP
Notice for Use
1. Careful handling is necessary to prevent damage due to static electricity.
2. This product has been developed for consumer applications, and should not be used in non-consumer applications.
3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to
prevent latchup, a ceramic capacitor of 0.1 µF or more and an electrolytic capacitor of 10 µF or more should be
inserted between the ground and power supply.
4. Common connection of AVDD and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise filter,
the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation.
5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure
below.
Analog
+3.0V
Digital
+3.0V
Noise filter
AVDD
DVDD1 to 4
Noise filter
DVDD1 to 4
HD49335
AVSS
Example of noise filter
AVDD
HD49335
DVSS
DVSS
AVSS
100 µH
0.01 µF
0.01 µF
6. Connect AVSS and DVSS off-chip using a common ground. If there are separate analog system and digital system
set grounds, connect to the analog system.
7. When VDD is specified in the data sheet, this indicates AVDD and DVDD.
8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be connected to power
supply or ground pins or left open to prevent crosstalk in adjacent analog pins.
9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is less tolerant of
bending than Fe-type lead material, careful handling is necessary.
10. The infrared reflow soldering method should be used to mount the chip. Note that general heating methods such as
solder dipping cannot be used.
11. Serial communication should not be performed during the effective video period, since this will result in degraded
picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA signals used in the
HD49330AF. If ports are to be shared with another IC, picture quality should first be thoroughly checked.
12. At power-on, automatic adjustment of the offset voltage generated from PGA, ADC, etc., must be implemented in
accordance with the power-on operating sequence (see page 24).
13. Ripple noise of DC/DC converter which generates the voltage of analog part should set under –50 dB with power
supply voltage.
Rev.1.0, Feb.12.2004, page 26 of 29
HD49335NP/HNP
Example of Recommended External Circuit
Pin 57
• Slave mode
Pin 57(Test1 = Low)
to CCD
47µ
3.0V
47µ
47/6
+
Specification
Mode
Low
Slave mode
CLK, HD, VD input from SSG.
Hi
Master mode
HD, VD output
∗ Pin 56 = Low: TESTIN mode. Please do not use.
Reset(Normally Hi)
0.1
0.1
33 XV4
to V.Baff
34 CH1
XV2
XV1
DVDD3
DVDD4
1/4clk_o
H2A
DVSS4
DVSS4
1/2clk_o
H1A
DVDD4
DVDD3
RG
Reset
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
XV3
35 CH2
36 CH3
37 CH4
38 XSUB
39 SUB_SW/ADCK_in
to CCD
40 SUB_PD
HD49335
41 STROB/Vgate
42 DVSS3
43 AVSS
33k
45 BIAS
0.1
46 VRB
0.1
47 VRT
0.1
48 VRM
AVDD
BLKC
CDS_in
AVDD
BLKFB
BLKSH
AVSS
Test2
Test1
DLL_C
DVDD1
MON
41pin_cont
CS
Sdata
44 ADC_in
VD_in
HD_in
CLK_in
DVSS3
DVDD2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DVSS1,2
ID
from
Pulse generator
16
15
14
13
12
11
10
9
7
6
5
4
3
2
ID pulse
1
SCK
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
∗ 61pin = Low: Pin 41 is STROB output
Pin 39 is SUB_SW output
61pin = Hi: Pin 41 is Vgate output
47/6
Pin 39 is Hiz
+
47µ
to
Camera
signal
processor
8
+
47/6
0.1
1µ
1µ
1000p
CCD signal input
0.1
100p
Serial data input
• Master mode
Pin 57(Test1 = Hi)
to CCD
47µ
3.0V
47µ
47/6
+
Reset(Normally Hi)
0.1
0.1
to
Camera
signal
processor
33 XV4
to V.Baff
34 CH1
XV2
XV1
DVDD3
DVDD4
1/4clk_o
H2A
DVSS4
DVSS4
1/2clk_o
H1A
DVDD4
DVDD3
RG
Reset
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
XV3
35 CH2
36 CH3
37 CH4
38 XSUB
39 SUB_SW/ADCK_in
to CCD
40 SUB_PD
HD49335
41 STROB/Vgate
42 DVSS3
43 AVSS
33k
45 BIAS
0.1
46 VRB
0.1
47 VRT
0.1
48 VRM
AVDD
HD_in
CLK_in
DVSS3
DVDD2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DVSS1,2
ID
BLKC
CDS_in
AVDD
BLKFB
BLKSH
AVSS
Test2
Test1
DLL_C
DVDD1
MON
41pin_cont
CS
Sdata
44 ADC_in
VD_in
16
from
Pulse generator
15
14
13
12
11
10
9
to
Camera
signal
processor
8
7
6
5
4
3
2
ID pulse
1
SCK
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
+
47µ
0.1
+
47/6
CCD signal input
1000p
1µ
1µ
0.1
100p
Serial data input
Rev.1.0, Feb.12.2004, page 27 of 29
47/6
∗ 61pin = Low: Pin 41 is STROB output
Pin 39 is SUB_SW output
61pin = Hi: Pin 41 is Vgate output
Pin 39 is Hiz
Unit: R: Ω
C: F
HD49335NP/HNP
• CDS single operating mode
Pin 56(Test2 = Low) ∗Pin 57 is "Don't care" in this mode.
47µ
3.0V
+
47/6
47µ
Reset(Normally Hi)
0.1
0.1
Reset
DVDD4
DVDD3
33
DVSS4
DVSS4
DVDD3
DVDD4
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
16
34
15
DVSS3
DVDD2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DVSS1,2
35
36 PBLK
37 OBP
38 CP_DM
39 ADCK
40 SP2
HD49335
41 SP1
42 DVSS3
43 AVSS
33k
45 BIAS
0.1
46 VRB
0.1
47 VRT
0.1
48 VRM
AVDD
BLKC
CDS_in
AVDD
BLKFB
BLKSH
AVSS
Test2
Test1
DLL_C
DVDD1
MON
41pin_cont
CS
Sdata
44 ADC_in
ADC_in
14
13
12
11
10
9
to
Camera
signal
processor
8
7
6
5
4
3
2
1
SCK
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
+
47µ
0.1
+
47/6
CCD signal input
1µ
1µ
0.1
1000p
∗Pin changes are not effective with pin61.
47/6
100p
Unit: R: Ω
C: F
Serial data input
Serial data when CDS single operation mode are following resister specifications.
(Latch timing specification is same as normal mode)
CS
fsck
tINT1
tINT2
SCK
tsu
SDATA
Resister 0
tho
D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15
Resister 1
Resister 2
Resister 3
Resister 4
Resister 5
Resister 6
Resister 7
D00
Low
0
High
1
Low
0
High
1
Low
0
High
1
Low
0
High
1
D01
Low
0
Low
0
High
1
High
1
Low
0
Low
0
High
1
High
1
D02
Low
0
Low
0
Low
0
Low
0
High
1
High
1
High
1
High
1
D03
X
Normal
0 SLP Low:
High: Sleep 0 Clamp(0)
1
0 MON(0)
0 P_SP1(0)
1 DL_SP1(0)
0 DL_RG_r(0)
0
D04
X
Normal
0 STBY Low:
High: Standby 0 Clamp(1)
0
0 MON(1)
0 P_SP1(1)
0 DL_SP1(1)
0 DL_RG_r(1)
0
D05 PGA(0) LSB
0 Output mode(LINV) 0 Clamp(2)
0
0 MON(2)
0 P_SP2(0)
1 DL_SP1(2)
0 DL_RG_r(2)
0
D06 PGA(1)
0 Output mode(MINV) 0 Clamp(3)
1
0 H12Baff(0)
0 P_SP2(1)
1 DL_SP1(3)
0 DL_RG_r(3)
0
D07 PGA(2)
0 Output mode(Test0) 0 Clamp(4)
0
0 H12Baff(1)
0 P_ADCLK(0)
1 DL_SP2(0)
0 DL_RG_f(0)
0
D08 PGA(3)
0 SHA-fsel(0)
0 HGstop-Hsel(0) 0
0 H12Baff(2)
0 P_ADCLK(1)
0 DL_SP2(1)
0 DL_RG_f(1)
1
D09 PGA(4)
0 SHA-fsel(1)
0 HGstop-Hsel(1) 0
0 H12Baff(3)
1 P_RG(0)
0 DL_SP2(2)
0 DL_RG_f(2)
0
D10 PGA(5)
0 SHSW-fsel(0)
0 HGain-Nsel(0) 0
0 VD latch
0 P_RG(1)
0 DL_SP2(3)
0 DL_RG_f(3)
1
D11 PGA(6)
0 SHSW-fsel(1)
0 HGain-Nsel(1) 0
0 Gray1
0 DLL_CK(0)
1 DL_ADCLK(0) 0 DMCG(0)
0
D12 PGA(7) MSB
0 SHSW-fsel(2)
0 Gray2
0 DLL_CK(1)
0 DL_ADCLK(1) 0 DMCG(1)
0
D13 Test_I1 (0)
0 SHSW-fsel(3)
Normal
0 LoPwr Low:
High: Low power 1
0
X
0
0 Gray_ts(0)
0 DLL_CK(2)
1 DL_ADCLK(2) 0 Dummy CP(0) 0
D14 Test_I1 (1)
0 Test_I2 (0)
0 ADSEL Low:CDSin
High:ADin 0
0 Gray_ts(1)
0 DLL_CK(3)
1 DL_ADCLK(3) 0 Dummy CP(1) 0
D15 Test_I1 (2)
1 Test_I2 (1)
Reset 1
0 Reset Low:
High: Normal
0 Gray_ts(2)
0 DLL_current
1 CDS_test
Rev.1.0, Feb.12.2004, page 28 of 29
test
0 Dummy CP(2) 0
HD49335NP/HNP
Package Dimensions
Unit: mm
9.00 ± 0.1
8.80
C
Part A
(0
0
.2
)
)
.1
6
(0
2
.8
0.50
)
0.65
.2)
(φ0
(3
C0.50
Index
1
8.80
9.00 ± 0.1
B
0.65
A
9
0.40 ± 0.1
0.20 ± 0.05
0.05 M S A-B C
S
10
0.
C
0.20 ± 0.05
0.80 Max
0.05 S
0.40 ± 0.1
Enlargement of Part A
Rev.1.0, Feb.12.2004, page 29 of 29
Package Code
JEDEC
JEITA
Mass (reference value)
TNP-64AV
—
—
0.14 g
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