M87C257 ADDRESS LATCHED 256K (32K x 8) UV EPROM and OTP EPROM INTEGRATED ADDRESS LATCH FAST ACCESS TIME: 45ns LOW POWER “CMOS” CONSUMPTION: – Active Current 30mA – Standby Current 100µA PROGRAMMING VOLTAGE: 12.75V ELECTRONIC SIGNATURE for AUTOMATED PROGRAMMING PROGRAMMING TIMES of AROUND 3sec. (PRESTO II ALGORITHM) 28 1 FDIP28W (F) PLCC32 (C) Figure 1. Logic Diagram DESCRIPTION The M87C257 is a high speed 262,144 bit UV erasable and electrically programmable EPROM. The M87C257 incorporates latches for all address inputs to minimize chip count, reduce cost, and simplify the design of multiplexed bus systems. The Window Ceramic Frit-Seal Dual-in-Line package has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M87C257 is offered in Plastic Leaded Chip Carrier, package. VCC 15 8 A0-A14 E Q0-Q7 M87C257 G Table 1. Signal Names A0 - A14 Address Inputs Q0 - Q7 Data Outputs E Chip Enable G Output Enable ASVPP Address Strobe / Program Supply VCC Supply Voltage VSS Ground June 1996 ASVPP VSS AI00928B 1/13 M87C257 VCC A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3 AI00929 1 32 A6 A5 A4 A3 A2 A1 A0 NC Q0 9 M87C257 25 A8 A9 A11 NC G A10 E Q7 Q6 17 VSS DU Q3 Q4 Q5 28 1 27 2 26 3 25 4 24 5 23 6 22 7 M87C257 21 8 20 9 19 10 18 11 17 12 13 16 14 15 A7 A12 ASVPP DU VCC A14 A13 ASVPP A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS Figure 2B. LCC Pin Connections Q1 Q2 Figure 2A. DIP Pin Connections AI00930 Warning: NC = Not Connected, DU = Dont’t Use. Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit Ambient Operating Temperature –40 to 125 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C Input or Output Voltages (except A9) –2 to 7 V Supply Voltage –2 to 7 V A9 Voltage –2 to 13.5 V Program Supply Voltage –2 to 14 V TA VIO (2) VCC VA9 (2) VPP Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. DEVICE OPERATION The modes of operation of the M87C257 are listed in the Operating Modes. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature. 2/13 Read Mode The M87C257 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should M87C257 Table 3. Operating Modes Mode E G A9 ASVPP Q0 - Q7 Read (Latched Address) VIL VIL X VIL Data Out Read (Applied Address) VIL VIL X VIH Data Out Output Disable VIL VIH X X Hi-Z VIL Pulse VIH X VPP Data In Verify VIH VIL X VPP Data Out Program Inhibit VIH VIH X VPP Hi-Z Standby VIH X X X Hi-Z Electronic Signature VIL VIL VID VIL Codes Program Note: X = VIH or VIL, VID = 12V ± 0.5V Table 4. Electronic Signature Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h Device Code VIH 1 0 0 0 0 0 0 0 80h be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable (AS = VIH) or latched (AS = VIL), the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. The M87C257 reduces the hardware interface in multiplexed address-data bus systems. The processor multiplexed bus (AD0-AD7) may be tied to the M87C257’s address and data pins. No separate address latch is needed because the M87C257 latches all address inputs when AS is low. Standby Mode The M87C257 has a standby mode which reduces the active current from 30mA to 100µA (Address Stable). The M87C257 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device. 3/13 M87C257 Table 5. AC Measurement Conditions High Speed Standard Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V 1.5V 0.8V and 2V Input and Output Timing Ref. Voltages Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V High Speed 1N914 3V 1.5V 3.3kΩ 0V DEVICE UNDER TEST Standard 2.4V OUT CL = 30pF or 100pF 2.0V 0.8V 0.4V CL = 30pF for High Speed CL = 100pF for Standard AI01822 CL includes JIG capacitance AI01823 Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol CIN COUT Parameter Test Condition Input Capacitance Output Capacitance Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: 1. Sampled only, not 100% tested. System Considerations The power switching characteristics of Advance CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of this transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line 4/13 output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. M87C257 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current ICC1 Supply Current (Standby) TTL ICC2 Test Condition Max Unit 0V ≤ VIN ≤ VCC ±10 µA 0V ≤ VOUT ≤ VCC ±10 µA E = VIL, G = VIL, IOUT = 0mA, f = 5MHz 30 mA E = VIH, ASVPP = VIH, Address Switching 10 mA E = VIH, ASVPP = VIL, Address Stable 1 mA E ≥ VCC – 0.2V, ASVPP ≥ VCC – 0.2V, Address Switching 6 mA E ≥ VCC – 0.2V, ASVPP = VSS, Address Stable 100 µA VPP = VCC 100 µA Supply Current (Standby) CMOS Min IPP Program Current VIL Input Low Voltage –0.3 0.8 V Input High Voltage 2 VCC + 1 V 0.4 V VIH (2) VOL Output Low Voltage IOL = 2.1mA VOH Output High Voltage IOH = –1mA VCC – 0.8V V Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V. Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Symbol Alt Parameter Test Condition M87C257 -45 (3) -60 -70 Unit -80 Min Max Min Max Min Max Min Max Address Valid to Output Valid tAVQV tACC E = VIL, G = VIL 45 tAVASL tAL Address Valid to Address Strobe Low tASHASL tLL Address Strobe High to Address Strobe Low 35 tASLAX tLA Address Strobe Low to Address Transition tASLGL tLOE Address Strobe Low to Output Enable Low tELQV tCE Chip Enable Low to Output Valid tGLQV tOE (2) 7 70 80 ns 7 7 ns 35 35 35 ns 20 20 20 20 ns 20 20 20 20 ns G = VIL 45 60 70 80 ns Output Enable Low to Output Valid E = VIL 25 30 35 40 ns tDF Chip Enable High to Output Hi-Z G = VIL 0 25 0 30 0 30 0 40 ns tGHQZ (2) tDF Output Enable High to Output Hi-Z E = VIL 0 25 0 30 0 30 0 40 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 tEHQZ 7 60 0 0 0 ns Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. In case of 45ns speed see High Speed AC measurement conditions. 5/13 M87C257 Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Symbol Alt M87C257 Test Condition Parameter -90 -10 -12 -15/-20 Unit Min Max Min Max Min Max Min Max Address Valid to Output Valid tAVQV tACC tAVASL tAL Address Valid to Address Strobe Low 7 7 7 7 ns tASHASL tLL Address Strobe High to Address Strobe Low 35 35 35 35 ns tASLAX tLA Address Strobe Low to Address Transition 20 20 20 20 ns tASLGL tLOE Address Strobe Low to Output Enable Low 20 20 20 20 ns tELQV tCE Chip Enable Low to Output Valid G = VIL 90 100 120 150 ns tGLQV tOE Output Enable Low to Output Valid E = VIL 40 40 50 60 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 40 0 30 0 40 0 40 ns (2) tDF Output Enable High to Output Hi-Z E = VIL 0 40 0 30 0 40 0 40 ns tOH Address Transition to Output Transition E = VIL, G = VIL 0 tGHQZ tAXQX E = VIL, G = VIL 90 100 0 120 0 150 0 Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. Figure 5. Read Mode AC Waveforms A0-A14 VALID tASLAX tAXQX tAVASL ASVPP tASHASL tASLGL tAVQV E tGLQV tEHQZ G tELQV tGHQZ Hi-Z Q0-Q7 DATA OUT AI00931 6/13 ns ns M87C257 Table 9. Programming Mode DC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol Parameter Test Condition Min VIL ≤ VIN ≤ VIH Max Unit ±10 µA 50 mA 50 mA ILI Input Leakage Current ICC Supply Current IPP Program Current VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage TTL IOH = –1mA VID A9 Voltage E = VIL VCC -0.8V 11.5 V 12.5 V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Table 10. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol Alt Parameter Test Condition Min Max tAVEL tAS Address Valid to Chip Enable Low 2 µs tQVEL tDS Input Valid to Chip Enable Low 2 µs tVPHEL tVPS VPP High to Chip Enable Low 2 µs tVCHEL tVCS VCC High to Chip Enable Low 2 µs tELEH tPW Chip Enable Program Pulse Width 95 tEHQX tDH Chip Enable High to Input Transition 2 µs tQXGL tOES Input Transition to Output Enable Low 2 µs tGLQV tOE Output Enable Low to Output Valid tGHQZ tDFP Output Enable High to Output Hi-Z 0 tGHAX tAH Output Enable High to Address Transition 0 105 Unit µs 100 ns 130 ns ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP Programming When delivered (and after each erasure for UV EPROM), all bits of the M87C257 are in the "1" state. Data is introduced by selectively programming "0"s into the desired bit locations. Although only "0"s will be programmed, both "1"s and "0"s can be present in the data word. The only way to change a "0" to a "1" is by die exposition to ultraviolet light (UV EPROM). The M87C257 is in the programming mode when VPP input is at 12.75V, G is at VIH and E is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25 V ± 0.25 V. 7/13 M87C257 Figure 6. Programming and Verify Modes AC Waveforms VALID A0-A14 tAVEL Q0-Q7 DATA IN tQVEL DATA OUT tEHQX ASVPP tVPHEL tGLQV tGHQZ VCC tVCHEL tGHAX E tELEH tQXGL G PROGRAM VERIFY AI00557 Figure 7. Programming Flowchart VCC = 6.25V, VPP = 12.75V n=0 E = 100µs Pulse NO ++n = 25 YES FAIL NO VERIFY ++ Addr YES Last Addr NO YES CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V AI00760B 8/13 PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows to program the whole array with a guaranteed margin, in a typical time of 3.5 seconds. Programming with PRESTO II involves the application of a sequence of 100µs program pulses to each byte until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides necessary margin to each programmed cell. Program Inhibit Programming of multiple M87C257s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M87C257 may be common. A TTL low level pulse applied to a M87C257’s E input, with VPP at 12.75V, will program that M87C257. A high level E input inhibits the other M87C257s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with G at VIL, E at VIH, VPP at 12.75V and VCC at 6.25V. M87C257 Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M87C257. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M87C257, with VCC = VPP = 5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from V IL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0=VIL) represents the manufacturer code and byte 1 (A0=VIH) the device identifier code. When A9 = VID, AS need not be toggled to latch each identifier address. For the SGS-THOMSON M87C257, these two identifier bytes are given in Table 4 and can be read-out on outputs Q0 to Q7. ERASURE OPERATION (applies for UV EPROM) The erasure characteristics of the M87C257 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M87C257 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M87C257 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M87C257 window to prevent unintentional erasure. The recommended erasure procedure for the M87C257 is exposure to short wave ultraviolet light which has wavelength 2537Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 µW/cm2 power rating. The M87C257 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure. 9/13 M87C257 ORDERING INFORMATION SCHEME Example: Speed (1) M87C257 -70 X VCC Tolerance C 1 Package X Temperature Range 45 ns X ± 5% F FDIP28W 1 0 to 70 °C -60 60 ns blank ± 10% C PLCC32 6 –40 to 85 °C -70 70 ns 7 –40 to 105 °C -80 80 ns 3 –40 to 125 °C -45 -90 90 ns -10 100 ns -12 120 ns -15 150 ns -20 200 ns Option X TR Additional Burn-in Tape & Reel Packing Note: 1. High Speed, see AC Characteristics section for further information. For a list of available options (Speed, VCC Tolerance, Package, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. 10/13 M87C257 FDIP28W - 28 pin Ceramic Frit-seal DIP, with window mm Symb Typ inches Min Max A Typ Min 5.71 Max 0.225 A1 0.50 1.78 0.020 0.070 A2 3.90 5.08 0.154 0.200 B 0.40 0.55 0.016 0.022 B1 1.17 1.42 0.046 0.056 C 0.22 0.31 0.009 0.012 D 38.10 E E1 15.40 15.80 1.500 0.606 0.622 13.05 13.36 0.514 0.526 e1 2.54 – – 0.100 – – e3 33.02 – – 1.300 – – eA 16.17 18.32 0.637 0.721 L 3.18 4.10 0.125 0.161 1.52 2.49 0.060 0.098 – – – – α 4° 15° 4° 15° N 28 S ∅ 7.11 0.280 28 FDIP28W A2 A1 B1 B A L α e1 eA C e3 D S N ∅ E1 E 1 FDIPW-a Drawing is not to scale 11/13 M87C257 PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular mm Symb Typ inches Min Max A 2.54 A1 Min Max 3.56 0.100 0.140 1.52 2.41 0.060 0.095 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 – – – – e 1.27 Typ 0.050 N 32 32 Nd 7 7 Ne 9 9 CP 0.10 0.004 PLCC32 D D1 A1 1 N B1 E1 E Ne e D2/E2 B A Nd PLCC Drawing is not to scale 12/13 CP M87C257 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1996 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 13/13