LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 LM8330 I2C-Compatible Keypad Controller with GPIO, PWM, and IEC61000 ESD Protection Check for Samples: LM8330 FEATURES 1 • 2 • KEY FEATURES – Keypad Matrices of up to of 8 x 12 Keys, Plus 8 Special Function (SF) Keys, for a Full 104 Key Support. – Supports General-purpose I/O Expansion on Pins Not Otherwise Used for Keypad or PWM Output. – Keypad Matrix and Dedicated Key Support: – 16-Event Keycode Buffer – 4-Event Multiple Key Storage Registers – Internal Oscillator, No External Clock Required. – I2C-compatible ACCESS.bus Slave Interface Standard (100 kHz) and Fast (400 kHz) Modes: – 7-bit and 10-bit Addressing – Programmable Slave Address – (Default 7-bit 0x88, 10-bit 0x088) – Three Host-programmable PWM Outputs – Smooth LED Brightness Modulation – Dedicated 31-command Script Bugger – Register-based Command Interpreter with Auto-increment Addressing – Key Events, Errors, and Dedicated Hardware Interrupts, Request Host Service by Asserting an IRQ Output – Ultra-Low-Power Operation – Automatic HALT Mode: 1.5 µA (typ.) – Active Supply Current: 23 µA (typ.) – Configurable Wake-Up from HALT Operation – IEC61000-4-2 ESD Protection on KPX[7:0] and KPY[10:0] pins – ESD Glitch Filter on RESETN Input – External Reset for System Control HOST-CONTROLLED FEATURES – Reset Input for System Control – PWM Scripting for Three PWM Outputs – Period of Inactivity That Triggers Entry into HALT Mode • – Debounce Time for Reliable Key Event Polling – Configuration of General Purpose I/O Ports – Various Initialization Options (Keypad Size, etc.) KEY DEVICE FEATURES – 1.8V ±10% Single-supply Operation – On-chip Power-on Reset (POR) – −30°C to +85°C Temperature Range – Robust IEC ESD Protection: ±8 kV Direct Contact on KPX[7:0] and KPY[10:0] Pins – 25-pin DSBGA Package Size: 2 mm x 2 mm x 0.6 mm (0.4 mm Pitch) APPLICATIONS: • • • Mobile Phones Qwerty Keyboard Universal Remote DESCRIPTION The LM8330 I/O - Expander and Keypad Controller is a dedicated device designed to unburden a host processor from scanning a matrix-addressed keypad and to provide flexible and general purpose, host programmable input/output functions. Three independent Pulse Width Modulation (PWM) timer outputs are provided for dynamic LED brightness modulation. It communicates with a host processor through an I2C-compatible ACCESS.bus serial interface. It can communicate in Standard (100 kHz) and Fast-Mode (400 kHz) in slave Mode only. All available input/output pins can alternately be used as an input or an output in a keypad matrix or as a host-programmable general-purpose input or output. Any pin programmed as an input can also sense hardware interrupts. The interrupt polarity (“high-tolow” or “low-to-high” transition) is thereby programmable. The LM8330 follows a predefined register-based set of commands. Upon startup (power-on) a configuration file must be sent from the host to set up the hardware of the device. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com DESCRIPTION (CONTINUED) The LM8330 is available in a 25-bump lead-free DSBGA package size 2.0 mm x 2.0 mm x 0.6 mm (0.4 mm pitch). The LM8330 has integrated ASIP (Application Specific Integrated Passives) on the KPX[7:0] and KPY[10:0] pins. These pins are designed to tolerate IEC61000-4-2 level 4 ESD: ±8 kV direct contact. LM8330 FUNCTION BLOCKS 1.8V (typ) 0.1 PF (required) VCC LM8330 SCL SDA Main processing device Internal OSC ACCESS.bus IRQN RESETN DIV Command Interpreter Keypad Matrix 32 kHz Reference Clock ASIP ESD Protection Input/Output Sleep Control General Purpose Inputs/Outputs Key-Scan Control PWM Generator Wake-Up Control Input/Output Expansion ASIP ESD Protection PWM0 NOTE: This diagram illustrates IO configuration 3 with IRQN enabled PWM2 PWM1 PACKAGE MARKING 1 2 3 4 5 A B C D E Figure 1. LM8330 Pinout - Top View (balls underneath) 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 SIGNAL DESCRIPTIONS Primary and Alternate Functions of All Device Pins Ball Function 0 (1) Function 1 (1) Function 2 (1) Function 3 (1) Pin Count Ball Name Reset Active Low Input 1 RESETN D3 Supply Voltage 1 VCC A4 ACCESS.bus Clock 1 SCL A5 ACCESS.bus Data 1 SDA A3 E1 Keypad-I/O X0 GPIO0 1 KPX0 D2 Keypad-I/O X1 GPIO1 1 KPX1 B4 Keypad-I/O X2 GPIO2 1 KPX2 B5 Keypad-I/O X3 GPIO3 1 KPX3 A1 Keypad-I/O X4 GPIO4 1 KPX4 A2 Keypad-I/O X5 GPIO5 1 KPX5 C1 Keypad-I/O X6 GPIO6 1 KPX6 D1 Keypad-I/O X7 GPIO7 1 KPX7 E4 Keypad-I/O Y0 GPIO8 1 KPY0 E3 Keypad-I/O Y1 GPIO9 1 KPY1 E2 Keypad-I/O Y2 GPIO10 1 KPY2 D4 Keypad-I/O Y3 GPIO11 1 KPY3 B2 Keypad-I/O Y4 GPIO12 1 KPY4 B1 Keypad-I/O Y5 GPIO13 1 KPY5 C2 Keypad-I/O Y6 GPIO14 1 KPY6 B3 Keypad-I/O Y7 GPIO15 1 KPY7 C4 Keypad-I/O Y8 GPIO16 PWM2 (2) 1 KPY8 D5 Keypad-I/O Y9 GPIO17 PWM1 1 KPY9 E5 Keypad-I/O Y10 GPIO18 PWM0 1 KPY10 C5 Keypad-I/O Y11 GPIO19 PWM2 (2) 1 IRQN 1 GND C3 Interrupt Ground Total (1) (2) 25 This table describes the alternate pin function and not the actual BALLCFG assignments. Refer to Table 49 for actual BALLCFG Assignments. PWM2 functionality is mutually exclusive - one pin at a time only (KPY8 or KPY11) depending on interrupt enable Bit 4 of IOCFG. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 3 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) −0.3V to 2.2V Supply Voltage (VCC) −0.2V to VCC +0.2V Voltage at Generic I/Os −0.3V to +.2.2V Voltage at Backdrive I/Os Junction Temperature +150°C −40°C to +140°C Storage Temperature Range Lead Temperature (TL) (Soldering, 10 sec.) +260°C ESD Protection Level Human Body Model: IEC61000-4-2, 330Ω, 150 pF: (1) (2) 2000V Machine Model: 200V Charge Device Model: 500V Direct Contact (ASIP I/O only): ±8kV Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and test conditions, see the Electrical Characteristics tables. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. OPERATING RATINGS VCC Supply Voltage Min Max 1.62 1.98 V 50 mVpp Supply Noise Units −30°C to +85°C Operating Ambient Temperature DC ELECTRICAL CHARACTERISTICS Datasheet min/max specification limits are specified by design, test, or statistical analysis. Temperature: −30°C ≤ TA ≤ +85°C, VCC = 1.8V ±10%, unless otherwise specified Symbol VCC Parameter Conditions Operating Voltage ICCDYN1 ICCDYN2 ICCHALT (1) (2) 4 Supply Current (1) Sleep Mode HALT Current Min Core Supply Voltage (2) Typ 1.62 Max Units 1.98 V No load on any Output pin, VCC = 1.8V, TA = 25°C Active 8x7 Keypad matrix, ACCESS.Bus frequency = 400 Khz, No key pressed, PWM Inactive 23 30 No load on any Output pin, VCC = 1.8V, TA = 25°C All GPIO Mode - outputs toggling, ACCESS.Bus frequency = 400 Khz, PWM Inactive 18 25 VCC = 1.8V, TA = 25°C Internal Clock = OFF, no internal functional blocks running 1.5 3.0 µA Supply current is measured with inputs connected to VCC and outputs driven low but not connected to a load. In sleep mode, the internal clock is switched off. Supply current in sleep mode is measured with inputs connected to VCC and outputs driven low but not connected to a load. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 AC ELECTRICAL CHARACTERISTICS Datasheet min/max specification limits are specified by design, test, or statistical analysis. Temperature: −30°C ≤ TA ≤ +85°C, VCC = 1.8V ±10%, unless otherwise specified. Symbol Parameter fOSC Internal Oscillator Frequency tOSC Internal Oscillator Period Conditions 1.62V ≤ VCC ≤ 1.98V Min Typ Max Units 51.2 64 76.8 KHz μS 15.625 ACCESS.bus Signal Timing fSCL ACCESS.bus Clock Frequency tBUF 400 1.62V ≤ VCC ≤ 1.98V KHz 1.3 tCSTOsi SCL Setup Time Before Stop Condition 0.6 tSCLhigh SCL High Time After SCL Rising Edge 0.6 tSCLlow SCL Low Time After SCL Falling Edge 1.0 tCSTRhi SCL Hold Time Repeated-Start Condition 0.6 tDHC SDA Setup Time Before SCL Rising Edge 0.1 tSDAhi SDA Hold Time After SCL Falling Edge 0.3 tSPIKE RST Input Glitch Filter () 0 < VIN < VDD μS RESETN Timing 50 100 nS GENERAL GPIO DC CHARACTERISTICS Characteristics for pins KPX[7:0], KPY[10:0]. Datasheet min/max specification limits are specified by design, test, or statistical analysis. Temperature: −30°C ≤ TA ≤ +85°C, VCC = 1.8V ±10%, unless otherwise specified. Symbol Parameter VIH Min. Input High Voltage VIL Max. Input Low Voltage Conditions Min Typ Max Units 0.35x VCC V 0.65xVCC ISource VCC = 1.62 VOH = 0.65xVCC −4.5 mA ISink VCC = 1.62 VOL = 0.35xVCC 4.5 mA Allowable Sink Current per pin (1) 6.5 mA IPU Weak pullup Current VOUT = 0V −160 −30 IPD Weak pulldown Current VOUT = VCC 30 160 IOZ Input Leakage Current GPIO output disabled −1 +1 (1) µA The sum of all I/O sink/source current must not exceed 100 ma maximum total current into VCC and out of GND. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 5 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com BACKDRIVE/OVERVOLTAGE I/O DC CHARACTERISTICS Characteristics for pins RESETN, IRQN, SDA and SCL. Datasheet min/max specification limits are specified by design, test, or statistical analysis. Temperature: −30°C ≤ TA ≤ +85°C, VCC = 1.8V ±10%, unless otherwise specified. Symbol Parameter Conditions VIH Min RESETN, SCL, SDA VIL Max Units 0.35xVC V C ISource IRQN VCC = 1.62V VOH = 1.17V ISink1 IRQN VCC = 1.62V VOL = 0.45V 16 VCC = 1.62V VOL = 0.4V 3 VCC = 1.62V VOL = 0.6V 6 ISink2 SDA ISink3 IPU IPD IOZ1 −16 mA IRQN pin as GPIO11 (1) VOUT = 0V −160 −30 IRQN pin as GPIO11 (1) VOUT = VCC 30 160 GPIO output disabled 1.62V ≤ VCC ≤ 1.98V 0 ≤ External pin voltage ≤ VCC −1 +1 GPIO output disabled 1.62V ≤ VCC ≤ 1.98V 0 ≤ External pin voltage ≤ 2.2V −5 +5 0 ≤ VCC ≤ 0.5V 0 ≤ External pin voltage ≤ 2.2V −5 +5 Input Leakage Current IOZ2 (1) Typ 0.65xVCC Input Backdrive Leakage Current µA µA This is the internal weak pullup (pulldown) current when driver output is disabled. If enabled, during receiving mode, this is the current required to switch the input from one state to another. BACKDRIVE I/O AC CHARACTERISTICS Characteristics for pins SDA and SCL. Datasheet min/max specification limits are specified by design, test, or statistical analysis. Temperature: −30°C ≤ TA ≤ +85°C, VCC = 1.8V ±10%, unless otherwise specified. Symbol Parameter Conditions (1) tRise/Fall Max. Rise and Fall time tFall Max. Fall Time ACCESS.bus, SDA, SCL (1) (1) 6 Min CLOAD = 50 pF @ 1MHz CLOAD = 10 pF to 100 pF VIHmin to VILmax Typ Max Units 70 20 300 ns Specified by design, not tested. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 PIN CONFIGURATION AFTER RESET Upon power-up or RESET the LM8330 will have defined states on all pins. The following table provides a comprehensive overview of the states of all functional pins. Pin Configuration after Reset Pins Pin States KPX0 KPX1 KPX2 KPX3 KPX4 Full Buffer mode with an on-chip pullup resistor enabled. KPX5 KPX6 KPX7 KPY0 KPY1 KPY2 KPY3 KPY4 KPY5 Full Buffer mode with an on-chip pulldown resistor enabled. KPY6 KPY7 KPY8 KPY9 KPY10 (1) IRQN Open Drain mode with no pull resistor enabled, driven low. (1) SCL SDA Open Drain mode with no pull resistor enabled. The IRQN is driven low after Power-On Reset due to PORIRQ signal. The value 0x01 must be written to the RSTINTCLR register (0x84) to release the IRQN pin. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 7 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com TYPICAL APPLICATION SETUP 1.8V (typ) 0.1 PF (required) VCC SDA Main processing device KPY3 SCL KPY2 IRQN/KPY11 KPY1 RESETN KPY0 KPX0 Up KPX1 Down KPX2 LM8330 Genio12 Output Genio13 Output Genio14 Input Genio15 Input KPY4 Sel KPX3 Left Rght KPX4 Soft Send End Lft Soft Rt KPX5 1 4 7 * KPX6 2 5 8 0 KPX7 3 6 9 # KPY5 KPY6 KPY7 KPY8/PWM2 KPY9/PWM1 KPY10/PWM0 GND Color LED Figure 2. LM8330 in a Typical Setup with Standard Handset Keypad FEATURES The following features are supported with the application example shown in example above: Hardware Hardware • 4 x 8 keys and 8 Special Function (SF) keys for 40 keys. • ACCESS.bus interface for communication with a host device. – - Communication speeds supported are: 100 kHz and 400 kHz fast mode of operation. • Interrupt signal (IRQN) to indicate any keypad or hardware interrupt events to the host. • Sophisticated PWM function block with 3 independent channels to control color LED. • External reset input for system control. • Two host-programmable dedicated general-purpose output pins (GPIOs) supporting IO-expansion capabilities for host device. • Two host-programmable dedicated general-purpose input pins with wake-up supporting IO-expansion capabilities for host device. Communication Layer • Versatile register-based command integration supported from on-chip command interpreter. • Keypad event storage. • Individual PWM script file storage and execution control for 3 PWM channels. 8 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 HALT MODE HALT MODE DESCRIPTION The fully static architecture of the LM8330 allows stopping the internal RC clock in Halt mode, which reduces power consumption to the minimum level. Halt mode is entered when no key-press event or key-release event is detected for a certain period of time (by default, 1020 milliseconds). The mechanism for entering Halt mode is enabled by default and can be disabled refer to Table 46. The period of inactivity which triggers entry into Halt mode using the auto-sleep function is programmable refer to Table 47. ACCESS.BUS ACTIVITY When the LM8330 is in Halt mode an ACCESS.bus access to its Slave Address will not cause the LM8330 to exit from Halt mode. All internal registers are available via ACCESS.bus while in HALT Mode. The LM8330 will acknowledge all bus cycles to its Slave Address while in Halt mode and will not require the host to repeat the cycle. LM8330 PROGRAMMING INTERFACE The LM8330 operation is controlled from a host device by a complete register set, accessed via the I2Ccompatible ACCESS.bus interface. The ACCESS.bus communication is based on a READ/WRITE structure, following the I2C-compatible transmission protocol. All functions can be controlled by configuring one or multiple registers. Configuration registers defined as word ACCESS size must have the entire word written in a continuous ACCESS.bus data transfer for the values to take effect. Reading write only registers will always return the value of 0. Please refer to and in LM8330 Registers for the complete register set. ACCESS.BUS COMMUNICATION The LM8330 will only be driven in slave mode. The maximum communication speed supported is Fast Mode (FS) which is 400 kHz. Figure 3 shows a typical 7-bit address Read cycle initiated by the host. Figure 3. Master/Slave Serial Communication (Host to LM8330) Table 1. Definition of Terms used in Serial Command Example Term Bits S Description START Condition (always generated from the master device). ADDRESS 7 Slave address of LM8330 sent from the host (7-bit address mode). R/W 1 This bit determines if the following data transfer is from master to slave (data write) or from slave to master (data read). 0: Write 1: Read ACK 1 An acknowledge bit is mandatory and must be appended on each byte transfer. The Acknowledge status is actually provided from the slave and indicates to the master that the byte transfer was successful. REG 8 The first byte after sending the slave address is the REGISTER byte which contains the physical address the host wants to read from or write to. RS Repeated START condition. DATA 8 The DATA field contains information to be stored into a register or information read from a register. NACK 1 Not Acknowledge Bit. The Not Acknowledge status is assigned from the Master receiving data from a slave. The NACK status will actually be assigned from the master in order to signal the end of a communication cycle transfer. P STOP condition (always generated from the master device). Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 9 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com All actions associated with the non-shaded boxes in Figure 3 are controlled from the master (host) device. All actions associated with the shaded boxes in Figure 3 are controlled from the slave (LM8330) device. The master device can send subsequent REGISTER addresses separated by Repeated START conditions. A STOP condition must be set from the master at the very end of a communication cycle. It is recommended to use Repeated START conditions in multi-Master systems when sending subsequent REGISTER addresses. This technique will make sure that the master device communicating with the LM8330 will not lose bus arbitration. STARTING A COMMUNICATION CYCLE There are two reasons for the host device to start communication to the LM8330: 1. The LM8330 device has set the IRQN line low in order to signal a key event or any other condition which initializes a hardware interrupt from LM8330 to the host. 2. The host device wants to set a GPIO port, read from a GPIO port, configure a GPIO port, and read the status from a register or initialize any other function which is supported from the LM8330. In case a GPIO shall be read it will be most likely that the LM8330 device will be residing in “sleep mode”. In this mode the system clock will be off to establish the lowest possible current consumption. If the host device starts the communication under this condition, the LM8330 device will acknowledge the first byte if it matches its programmed slave address. AUTO INCREMENT In order to improve multi-byte register access, the LM8330 supports the auto increment of the address pointer. A typical read-access sequence to the LM8330 starts with the I2C-compatible ACCESS.bus address, followed by the REG write of the register to access (see Figure 3). After a REPEATED START condition the host reads/writes a data byte from/to this address location. The LM8330 automatically increments the address pointer by one until a STOP condition is received. The LM8330 always uses auto increments unless otherwise noted. Please refer to Table 2 and Table 3 for the typical ACCESS.bus flow of reading and writing multiple data bytes. RESERVED REGISTERS AND BITS The LM8330 includes reserved registers for future implementation options. Writing to the reserved locations is not allowed and could result in abnormal device behavior. GENERAL CALL RESET The LM8330 does not support the Global Call Reset as defined in the NXP (Philips) I2C Specification UM10204 rev 0.3 from 2007. DEVICE ID The LM8330 does not support the Device ID as defined in the NXP (Philips) I2C Specification UM10204 rev 0.3 from 2007. 7-BIT and 10-BIT ADDRESSING MODES The LM8330 supports both the 7-bit and 10-bit addressing modes as defined in the NXP (Philips) I2C Specification UM10204 rev 0.3 from 2007. The default 7-bit slave address is 0x88, and the default 10-bit slave address is 0x088. NOTE The upper three address bits in 10-bit mode are hard tied to 0. 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 Table 2. Multi-Byte Write with Auto Increment 2 Step Master/Slave I C Com. 1 M S Value 2 M ADDR 0x88 3 M R/W 0 4 S ACK 5 M REG Address Pointer Comment START condition I2C-compatible ACCESS.bus Address Write Acknowledge 0xAA 0xAA Register Address, used as Address Pointer 6 S ACK 0xAA Acknowledge 7 M DATA 0x01 0xAA Write Data to Address in Pointer 8 S ACK 0 0xAB Acknowledge, Address pointer incremented 9 M DATA 0x05 0xAB Write Data to address 0xAB 10 S ACK 0 0xAC Acknowledge, Address pointer incremented 11 M P STOP condition Table 3. Multi-Byte Read with Auto Increment 2 Step Master/Slave I C Com. 1 M S Value 2 M ADDR 0x88 3 M R/W 0 Address Pointer Comment START condition I2C-compatible ACCESS.bus Address Write 4 S ACK 5 M REG Acknowledge 6 S ACK 7 M RS 8 M ADDR. 0x88 9 M R/W 1 10 S ACK 0 0xAA Acknowledge 11 S DATA 0x01 0xAA Read Data from Address in Pointer 12 M ACK 0 0xAB Acknowledge, Address Pointer incremented 13 S DATA 0x05 0xAB Read Data from Address in Pointer 14 M NACK 0 0xAC No Acknowledge, stops transmission 15 M P 0xAA 0xAA Register Address, used as Address pointer 0xAA Acknowledge 0xAA Repeated Start 0xAA I2C-compatible ACCESS.bus Address Read STOP condition Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 11 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com KEYSCAN OPERATION KEYSCAN INITIALIZATION Figure 4. Keyscan Initialization KEYSCAN INITIALIZATION EXAMPLE Table 4 shows all the LM8330 register configurations to initialize keyscan: • Keypad matrix configuration is 8 rows x 8 columns. Table 4. Keyscan Initialization Example 12 Register name adress Access Type Value Comment KBDSETTLE 0x01 byte 0x80 Set the keyscan settle time to 12 msec. KBDBOUNCE 0x02 byte 0x80 Set the keyscan debounce time to 12 msec. KBDSIZE 0x03 byte 0x88 Set the keyscan matrix size to 8 rows x 8 columns. KBDDEDCFG 0x04 word 0xFC3F Configure KPX[7:2] and KPY[7:2] pins as keyboard matrix. IOCFG 0xA7 byte 0xF8 IOPC0 0xAA word 0xAAAA Write default value to enable all pins as keyboard matrix. Configure pullup resistors for KPX[7:0]. IOPC1 0xAC word 0x5555 Configure pulldown resistors for KPY[7:0]. KBDIC 0x08 byte 0x03 clear any pending interrupts. KBDMSK 0x09 byte 0x03 Enable keyboard interrupts. CLKEN 0x8A byte 0x01 Enable keyscan clock. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 KEYSCAN PROCESS The LM8330 keyscan functionality is based on a specific scanning procedure performed in a 4ms interval. On each scan all assigned key matrix pins are evaluated for state changes. In case a key event has been identified, the event is stored in the key event FIFO, accessible via the EVTCODE register. A key event can either be a key press or a key release. In addition, key presses are also stored in the KBDCODE[3:0] registers. As soon as the EVTCODE FIFO includes a event, the device sets the RAW keyboard event interrupt REVTINT. The RSINT interrupt is set anytime the keyboard status has changed. Depending on the interrupt masking for the keyboard events (KBDMSK) and the masked interrupt handling (KBDMIS), the pin IRQN will follow the IRQST.KBDIRQ status, which is set as soon as one interrupt in KBDRIS is set. Figure 5 shows the basic flow of a scanning process and which registers are affected. Figure 5. Example Keyscan Operation for 1 Key Press and Release READING KEYSCAN STATUS BY THE HOST In order to keep track of the keyscan status, the host either needs to regularly poll the IRQST register or needs to react on the Interrupt signaled by the IRQN pin, in case the ball is configured for interrupt functionality. (See GPIO FEATURE CONFIGURATION). Figure 6 gives an example on which registers to read to get the keyboard events from the LM8330 and how they influence the interrupt event registers. The example is based on the assumption that the LM8330 has indicated the keyboard event by the IRQN pin. Since the interrupt pin has various sources, the host first checks the IRQST register for the interrupt source. If KBDIRQ is set, the host can check the KBDMIS register to define the exact interrupt source. KBDMIS contains the masked status of KBDRIS and reflects the source for raising the interrupt pin. The interrupt mask is defined by KBDMSK. The complete status of all pending keyboard interrupts is available in the raw interrupt register KBDRIS. After evaluating the interrupt source the host starts reading the EVTCODE or KBDCODE register. In this example the host first reads the KBDCODE to get possible key press events and afterwards reads the complete event list by reading the EVTCODE register until all events are captured (0x7F indicates end of buffer). Reading KBDCODE clears the RSINT interrupt bit if all keyboards events are emptied. In the same way, REVTINT is cleared in case the EVTCODE FIFO reaches its empty state on read. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 13 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com The event buffer content and the REVTINT and RELINT (lost event) interrupt bits are also cleared if the KBDIC.EVTIC bit is set. Interrupt bits in the masked interrupt register KBDMIS follow the masked KBDRIS status. In order to support efficient Multi-byte reads from EVTCODE, the auto-increment feature is turned off for this register. Therefore the host can continuously read the complete EVTCODE buffer by sending one command. Figure 6. Example Host Reacting to Interrupt for Keypad Event MULTIPLE KEY PRESSES The LM8330 supports up to four simultaneous key presses. Any time a single key is pressed KBDCODE0 is set with the appropriate key code. If a second key is pressed, the key is stored in KBDCODE1 and the MULTIKEY flag of KBDCODE0 is set. Additional key presses are stored in KBDCODE2 and KBDCODE3 accordingly. The four registers signal the last multi key press events. All events are stored in parallel in the EVTCODE register for the complete set of events. All KBDCODE[3:0] registers are cleared on read. 14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 Figure 7. Example Keyscan Operation for 2 Key Press Events and 1 Key Release Event PWM TIMER The LM8330 supports a timer module dedicated to smooth LED control techniques. The Pulse Modulation Width (PWM) timer module consists of three independent timer units of which each can generate a PWM output with a fixed period and automatically incrementing or decrementing variable duty cycle. The timer units are all clocked with a slow (32 kHz) clock. OVERVIEW OF PWM FEATURES • Each PWM can establish fixed - or variable - duty-cycle signal sequences on its output. • Each PWM can trigger execution of any pre-programmed task on another PWM channel. • The execution of any pre-programmed task is self-sustaining and does not require further interaction from the host. • 31-instruction script buffer for each PWM. • Direct addressing within script buffer to support multiple PWM tasks in one buffer. OVERVIEW ON PWM SCRIPT COMMANDS The commands listed in Table 5 are dedicated to the slow PWM timers. NOTE If the last address in the PWM script buffer is reached, and that command is not an END command, an END command with INT & RST enabled will be forced and the PWM operation will be terminated.Please note: The PWM Script commands are not part of the command set supported by the LM8330 command interpreter. These commands must be transferred from the host with help of the register-based command set. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 15 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com Table 5. PWM Script Commands Command RAMP SET_PWM GO_TO_ START BRANCH END TRIGGER 15 0 0 14 PRESCALE 1 13 12 11 10 STEPTIME 0 9 8 7 SIGN 6 5 4 3 INCREMENT PWM VALUE 2 1 0 0 1 1 1 0 1 1 1 0 1 LOOPCOUNT RST WAITTRIGGER INT ADDR X STEPNUMBER X SENDTRIGGER 0 RAMP Command A RAMP command will vary the duty cycle of a PWM output in either direction (up or down). The INCREMENT field specifies the amount of steps for the RAMP. The maximum amount of steps which can be executed with one RAMP Command is 126 which is equivalent to 50%. The SIGN bit field determines the direction of a RAMP (up or down). The STEPTIME field and the PRESCALE bit determine the duration of one step. Based on a 32 kHz clock, the minimum time resulting from these options would be 0.49 milliseconds and the maximum time for one step would be 1 second. Table 6. RAMP Command Bit and Building Fields 15 0 14 PRESCALE 13 12 11 10 STEPTIME 9 8 7 SIGN 6 5 4 3 2 INCREMENT 1 0 Table 7. Description of Bit and Building Fields of the RAMP Command Bit or Field Value PRESCALE STEPTIME Description 0 Divide the 32 kHz clock by 16. 1 Divide the 32 kHz clock by 512. 1 - 63 SIGN INCREMENT Number of prescaled clock cycles per step. 0 Increment RAMP counter. 1 Decrement RAMP counter. Number of steps executed by this instruction; a value of 0 functions as a WAIT determined by STEPTIME. 0 - 126 SET_PWM Command The SET_PWM command does not allow generation of a PWM output with a fixed duty cycle between 0% and 100%. This command will set the starting duty cycle MIN SCALE or FULL SCALE (0% or 100%). A RAMP command following the SET_PWM command will finally establish the desired duty cycle on the PWM output. Table 8. SET_PWM Command Bit and Building Fields 15 0 14 1 13 0 12 0 11 0 10 0 9 0 8 0 7 6 5 4 3 DUTYCYCLE 2 1 0 Table 9. Description of Bit and Building Fields of the SET_PWM Command Bit or Field Value Description 0 DUTYCYCLE Duty cycle is 0%. 255 Duty cycle is 100%. GO_TO_START Ccommand The GO_TO_START command jumps to the first command in the script command file. Table 10. GO_TO_START Command Bit and Building Fields 15 16 14 13 12 11 10 9 8 0 7 Submit Documentation Feedback 6 5 4 3 2 1 0 Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 BRANCH Command The BRANCH command jumps to the specified command in the script command file. The branch is executed with either absolute or relative addressing. In addition, the command gives the option of looping for a specified number of repetitions. NOTE Nested loops are not allowed. Table 11. BRANCH Command Bit and Building Fields 15 1 14 0 13 1 12 11 10 9 LOOPCOUNT 8 7 6 ADDR 5 X 4 3 STEPNUMBER 2 1 0 Table 12. Description of Bit and Building Fields of the BRANCH Command Bit or Field Value Description 0 LOOPCOUNT Loop until a STOP PWM SCRIPT command is issued by the host. 1 - 63 ADDR STEPNUMBER Number of loops to perform. 0 Absolute addressing 1 Relative addressing Depending on ADDR: ADDR=0: Addr to jump to ADDR=1: Number of backward steps 0 - 31 TRIGGER Command Triggers are used to synchronize operations between PWM channels. A TRIGGER command that sends a trigger takes sixteen 32 kHz clock cycles, and a command that waits for a trigger takes at least sixteen 32 kHz clock cycles. A TRIGGER command that waits for a trigger (or triggers) will stall script execution until the trigger conditions are satisfied. On trigger it will clear the trigger(s) and continue to the next command. When a trigger is sent, it is stored by the receiving channel and can only be cleared when the receiving channel executes a TRIGGER command that waits for the trigger. Table 13. TRIGGER Command Bit and Building Fields 15 1 14 1 13 1 12 11 10 9 WAITTRIGGER 8 7 6 5 4 3 SENDTRIGGER 2 1 0 0 Table 14. Description of Bit and Building Fields Field WAITTRIGGER SENDTRIGGER Value Description 000xx1 Wait for trigger from channel 0 000x1x Wait for trigger from channel 1 0001xx Wait for trigger from channel 2 000xx1 Send trigger to channel 0 000x1x Send trigger to channel 1 0001xx Send trigger to channel 2 END COMMAND The END command terminates script execution. It will only assert an interrupt to the host if the INT bit is set to '1'. When the END command is executed, the PWM output will be set to the level defined by PWMCFG.PWMPOL for this channel. Also, the script counter is reset back to the beginning of the script command buffer. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 17 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com NOTE If a PWM channel is waiting for the trigger (last executed command was "TRIGGER"), and the script execution is halted, then the "END" command can’t be executed because the previous command is still pending. This is an exception - in this case the IRQ signal will not be asserted. Table 15. END Command Bit and Building Fields 15 1 14 1 13 0 12 INT 11 RST 10 9 8 7 6 5 4 3 2 1 0 0 Table 16. Description of Bit and Building Fields of the END Command Field Value INT RST Description 0 No interrupt will be sent. 1 Set TIMRIS.CDIRQ for this PWM channel to notify that program has ended. 0 The PWM Output is set Low. 1 The PWM Output is set according to PWMCFG.PWMPOL. LM8330 REGISTER SET KEYBOARD REGISTERS AND KEYBOARD CONTROL Keyboard selection and control registers are mapped in the address range from 0x01 to 0x09. This paragraph describes the functions of the associated registers down to the bit level. KBDSETTLE - Keypad Settle Time Register Table 17. KBDSETTLE - Keypad Settle Time Register Register - Name Address Type KBDSETTLE 0x01 R/W Bit - Name Bit Default Register Function Initial time for keys to settle, before the key-scan process is started. The Keypad settle time will be imposed under the following conditions: a. A wake-up event on the keypad input (if KBDEN=1) b. The MODCTL register bit is written to transition from “halt” to “operational” mode (if KBDEN=1). Bit Function The default value 0x80 : 0xBF sets a time target of 12 msec. Further time targets are as follows: 0xC0 - 0xFF: 16 msec WAIT[7:0] 7:0 0x80 0x80 - 0xBF: 12 msec 0x40 - 0x7F: 8 msec 0x01 - 0x3F: 4 msec 0x00 : no settle time KBDBOUNCE - Debounce Time Register Table 18. KBDBOUNCE - Debounce Time Register 18 Register - Name Address Type KBDBOUNCE 0x02 R/W Bit - Name Bit Default Register Function Time between first detection of key and final sampling of key. Submit Documentation Feedback Bit Function Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 Table 18. KBDBOUNCE - Debounce Time Register (continued) Register - Name Address Type Register Function The default value 0x80 : 0xBF sets a time target of 12 msec. Further time targets are as follows: 0xC0 - 0xFF: 16 msec WAIT[7:0] 7:0 0x80 0x80 - 0xBF: 12 msec 0x40 - 0x7F: 8 msec 0x01 - 0x3F: 4 msec 0x00: no debouncing time KBDSIZE - Set Keypad Size Register Table 19. KBDSIZE - Set Keypad Size Register Register - Name Address Type KBDSIZE 0x03 R/W Bit - Name Bit Default Register Function Defines the physical keyboard matrix size. Bit Function Number of rows in the keyboard matrix: ROWSIZE[3:0] 7:4 0x2 0x0: free all rows to become GPIO, KPX[1:0] used as dedicated key inputs if scanning is enabled by CLKEN.KBEN: 0x1: (illegal value) 0x2 - 0x8: Number of rows in the matrix Number of columns in the keyboard matrix: COLSIZE[3:0] 3:0 0x2 0x0: free all rows to become GPIO, KPY[1:0] used as dedicated key inputs if scanning is enabled by CLKEN.KBEN 0x1: (illegal value) 0x2 - 0xC: Number of columns in the matrix KBDDEDCFG - Dedicated Key Register Table 20. KBDDEDCFG - Dedicated Key Register Register - Name Address Type KBDDEDCFG 0x04 R/W Bit - Name Bit Default Register Function Defines if a key is used as a standard keyboard/GPIO pin or whether it is used as dedicated key input. Bit Function Each bit in ROW [7:2] corresponds to ball KPX7 : KPX2. Bit=0: the dedicated key function applies. ROW[7:2] 15:10 0x3F Bit=1: no dedicated key function is selected. The standard GPIO functionality applies according to register IOCFG or defined keyboard matrix. Each bit in COL [11:10] corresponds to ball KPY11 : KPY10. Bit=0: the dedicated key function applies. COL[11:10] 9:8 0x03 Bit=1: no dedicated key function is selected. The standard GPIO functionality applies according to register IOCFG or defined keyboard matrix. Each bit in COL [9:2] corresponds to ball KPY9 : KPY2 and can be configured individually. COL[9:2] 7:0 0xFF Bit=0: the dedicated key function applies. Bit=1: no dedicated key function is selected. The standard GPIO functionality applies according to register IOCFG or defined keyboard matrix. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 19 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com KBDRIS - Keyboard Raw Interrupt Status Register Table 21. KBDRIS - Keyboard Raw Interrupt Status Register Register - Name Address Type KBDRIS 0x06 R Bit - Name Bit Default (reserved) 7:4 Register Function Returns the status of stored keyboard interrupts. Bit Function (reserved) Raw event lost interrupt. RELINT 3 0x0 REVTINT 2 0x0 More than 16 keyboard events have been detected and caused the event buffer to overflow. This bit is cleared by setting bit EVTIC of the KBDIC register. Raw keyboard event interrupt. At least one key press or key release is in the keyboard event buffer. Reading from EVTCODE until the buffer is empty will clear this interrupt. Raw key lost interrupt indicates a lost key-code. RKLINT 1 0x0 This interrupt is asserted when RSINT has not been cleared upon detection of a new key press or key release, or when more than 4 keys are pressed simultaneously. Raw scan interrupt. RSINT 0 0x0 Interrupt generated after keyboard scan, if the keyboard status has changed. Reading from KBDCODE until the buffer is empty will clear this interrupt. KBDMIS - Keypad Masked Interrupt Status Register Table 22. KBDMIS - Keypad Masked Interrupt Status Register Register - Name Address Type KBDMIS 0x07 R Bit - Name Bit Default (reserved) 7:4 Register Function Returns the status on masked keyboard interrupts after masking with the KBDMSK register. Bit Functions (reserved) Masked event lost interrupt. MELINT 3 0x0 MEVTINT 2 0x0 More than 16 keyboard events have been detected and caused the event buffer to overflow. This bit is cleared by setting bit EVTIC of the KBDIC register. Masked keyboard event interrupt. At least one key press or key release is in the keyboard event buffer. Reading from EVTCODE until the buffer is empty will clear this interrupt. Masked key lost interrupt. MKLINT 1 0x0 Indicates a lost key-code. This interrupt is asserted when RSINT has not been cleared upon detection of a new key press or key release, or when more than 4 keys are pressed simultaneously. Masked scan interrupt. MSINT 0 0x0 Interrupt generated after keyboard scan, if the keyboard status has changed, after masking process. Reading from KDBCODE until the buffer is empty will clear this interrupt. KBDIC - Keypad Interrupt Clear Register Table 23. KBDIC - Keypad Interrupt Clear Register 20 Register - Name Address Default KBDIC 0x08 W Bit - Name Bit Default Register Function Setting these bits clears Keypad active Interrupts Submit Documentation Feedback Bit Function Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 Table 23. KBDIC - Keypad Interrupt Clear Register (continued) Register - Name Address Default Register Function Switches off scanning of special function (SF) keys, when keyboard has no special function layout: SFOFF 7 0: keyboard layout and SF keys are scanned 1: only keyboard layout is scanned, SF keys are not scanned (reserved) 6:2 (reserved) EVTIC 1 Clear EVTCODE FIFO and corresponding interrupts REVTINT and RELINT by writing a 1 to this bit position. Note: Any key data in the EVTCODE FIFO will be lost when this bit is set; it is the users responsibility to ensure that all key data is read prior to asserting this bit. If a key is pressed while EVTIC is asserted/de-asserted the EVTCODE FIFO will be updated with only the key release code when the key is released. KBDIC 0 Clear RSINT and RKLINT interrupt bits by writing a '1' to this bit position. Note The KBDCODE registers are not cleared when setting this bit. KBDMSK - Keypad Interrupt Mask Register Table 24. KBDMSK - Keypad Interrupt Mask Register Register - Name Address Type Register Function Configures masking of keyboard interrupts. Masked interrupts do not trigger an event on the Interrupt output. KBDMSK 0x09 R/W Bit - Name Bit Default (reserved) 7:4 MSKELINT 3 0x0 MSKEINT 2 0x0 MSKLINT 1 0x1 MSKSINT 0 0x1 In case the interrupt processes registers KBDCODE[3:0], MSKELINT and MSKEINT should be set to '1'. When the Event FIFO is processed, MSKLINT and MSKSINT should be set. For keyboard polling operations, all bits should be set and the polling operation consists of reading out the IRQST. Bit Function (reserved) 0: keyboard event lost interrupt RELINT triggers IRQ line 1: keyboard event lost interrupt RELINT is masked 0: keyboard event interrupt REVINT triggers IRQ line 1: keyboard event interrupt REVINT is masked 0: keyboard lost interrupt RKLINT triggers IRQ line 1: keyboard lost interrupt RKLINT is masked 0: keyboard status interrupt RSINT triggers IRQ line 1: keyboard status interrupt RSINT is masked KEYBOARD CODE DETECT REGISTERS The key code detected by the keyboard scan can be read from the registers KBDCODE0: KBDCODE3. Up to 4 keys can be detected simultaneously. Each KBDCODE register includes a bit (MULTIKEY) indicating if another key has been detected. NOTE Reading out all key code registers (KBDCODE0 to KBDCODE3) will automatically reset the keyboard scan interrupt RSINT the same way as an active write access into bit KBDIC of the interrupt clear register does. Reading 0x7F from the KBDCODE0 register means that no key was pressed. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 21 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com KBDCODE0 - Keyboard Code Register 0 Table 25. KBDCODE0 - Keyboard Code Register 0 Register - Name Address Default KBDCODE0 0x0B R Register Function Holds the row and column information of the first detected key. Bit - Name Bit Default MULTIKEY 7 0x0 If this bit is 1 another key is available in KBDCODE1 register. Bit Function KEYROW[2:0] 6:4 0x7 ROW index of detected key (0 to 7). KEYCOL[3:0] 3:0 0xF Column index of detected (0 to 11, 12 for special function key and 13 & 14 for dedicated KPY key). KBDCODE1 - Keyboard Code Register 1 Table 26. KBDCODE1 - Keyboard Code Register 1 Register - Name Address Default KBDCODE1 0x0C R Register Function Holds the row and column information of the second detected key. Bit - Name Bit Default MULTIKEY 7 0x0 If this bit is 1 another key is available in KBDCODE2 register. Bit Function KEYROW[2:0] 6:4 0x7 ROW index of detected key (0 to 7). KEYCOL[3:0] 3:0 0xF Column index of detected key (0 to 11, 12 for special function key and 13 & 14 for dedicated KPY key). KBDCODE2 - Keyboard Code Register 2 Table 27. KBDCODE2 - Keyboard Code Register 2 Register - Name Address Default KBDCODE2 0x0D R Bit - Name Bit Default Register Function Holds the row and column information of the third detected key. Bit Function MULTIKEY 7 0x0 if this bit is 1 another key is available in KBDCODE3 register. KEYROW[2:0] 6:4 0x7 ROW index of detected key (0 to 7). KEYCOL[3:0] 3:0 0xF Column index of detected key (0 to 11, 12 for special function key and 13 & 14 for dedicated KPY key). KBDCODE3 - Keyboard Code Register 3 Table 28. KBDCODE3 - Keyboard Code Register 3 22 Register - Name Address Default KBDCODE3 0x0E R Register Function Holds the row and column information of the forth detected key. Bit - Name Bit Default MULTIKEY 7 0x0 if this bit is set to '1' then more than 4 keys are pressed simultaneously. Bit Function KEYROW[2:0] 6:4 0x7 ROW index of detected key (0 to 7). KEYCOL[3:0] 3:0 0xF Column index of detected key (0 to 11, 12 for special function key and 13 & 14 for dedicated KPY key). Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 EVTCODE - Key Event Code Register Table 29. EVTCODE - Key Event Code Register Register - Name Address Default Bit Function With this register a FIFO buffer is addressed storing up to 15 consecutive events. EVTCODE 0x10 R Reading the value 0x7F from this address means that the FIFO buffer is empty. See further details below. NOTE: Auto increment is disabled on this register. Multi-byte read will always read from the same address. Bit - Name Bit Default Bit Function This bit indicates whether the keyboard event was a key press or a key release event: RELEASE 7 0x0 KEYROW[2:0] 6:4 0x7 Row index of key that is pressed or released. KEYCOL[3:0] 3:0 0xF Column index of detected key that is pressed (0 to 11, 12 for special function key or and 13 & 14 for dedicated key) or released. 0: key was pressed 1: key was released PWM TIMER CONTROL REGISTERS The LM8330 provides three host-programmable PWM outputs useful for smooth LED brightness modulation. All PWM timer control registers are mapped in the range from 0x60 to 0x7F. This paragraph describes the functions of the associated registers down to the bit level. TIMCFGx - PWM Timer 0, 1 and 2 Configuration Register Table 30. TIMCFGx - PWM Timer 0, 1 and 2 Configuration Register Register - Name Address TIMCFG0 0x60 TIMCFG1 0x68 TIMCFG2 0x70 Bit - Name (x = 0, 1 or 2) Bit Type Register Function R/W This register configures interrupt masking of the associated PWM channel. Default Bit Function Interrupt mask for PWM CYCIRQx (see register TIMRIS): CYCIRQxMSK 4 0x0 (reserved) 3:0 0x0 0: interrupt enabled 1: interrupt masked (reserved) PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Register Table 31. PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Register Register - Name Address Type Register Function This register defines interrupt masking and the output behavior for the associated PWM channel. PWMCFG0 0x61 PWMCFG1 0x69 PWMCFG2 0x71 Bit - Name (x = 0, 1 or 2) Bit Default CDIRQxMSK 3 0x0 R/W PGEx is used to start and stop the PWM script execution. PWMENx sets the PWM output to either reflect the generated pattern or the value configured in PWMPOLx. Bit Function Mask for CDIRQ: 0: CDIRQ enabled 1: CDIRQ disabled/masked Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 23 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com Table 31. PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Register (continued) Register - Name Address Type PGEx 2 0x0 PWMENx 1 0x0 Register Function Pattern Generator Enable. Start/Stop PWM command processing for this channel. Script execution is started always from beginning. 0: Pattern Generator disabled 1: Pattern Generator enabled Notes: 1) This bit will be cleared when the PWM completes execution of END command and END.RST = 1. 2) The PWM will complete execution of an active script command if this bit is set to 0 by the host. 0: PWM disabled. PWM timer output assumes value programmed in PWMPOL. 1: PWM enabled Off-state of PWM output, when PWMEN = 0: PWMPOLx 0 0x0 0: PWM off-state is low 1: PWM off-state is high TIMSWRES - PWM Timer Software Reset Registers Table 32. TIMSWRES - PWM Timer Software Reset Registers Register - Name Address Type Register Function Reset control on all PWM timers. TIMSWRES 0x78 W A reset forces the pattern generator to fetch the first pattern and stops it. Each reset stops all state-machines and timer. Patterns stored in the pattern configuration register remain unaffected. Interrupts on each timer are not cleared, they need to be cleared writing into register TIMIC. Bit - Name Bit (reserved) 7:3 SWRES2 2 Default Bit Function (reserved) Software reset of timer 2: 0: no action 1: Software reset on timer 2, needs not to be written back to 0. Software reset of timer 1 SWRES1 1 0: no action 1: Software reset on timer 1, needs not to be written back to 0. Software reset of timer 0: SWRES0 0 0: no action 1: software reset on timer 0, needs not to be written back to '0'. TIMRIS - PWM Timer Interrupt Status Register Table 33. TIMRIS - PWM Timer Interrupt Status Register Register - Name Address Type Register Function This register returns the raw interrupt status from the PWM timers 0,1 and 2. TIMRIS 0x7A R CYCIRQx - Interrupt from the timers when PWM cycle is complete (applies to the current PWM command residing in the active command register of a PWM block). CDIRQx - Interrupt from the pattern generator when PWM pattern code is complete (applies to a completed task residing in the script buffer of a PWM block). 24 Bit - Name Bit (reserved) 7:6 Default Bit Functions (reserved) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 Table 33. TIMRIS - PWM Timer Interrupt Status Register (continued) Register - Name Address Type Register Function Raw interrupt status for CDIRQ timer2: CDIRQ2 5 0x0 0: no interrupt pending 1: unmasked interrupt generated Raw interrupt status for CDIRQ timer1: CDIRQ1 4 0x0 0: no interrupt pending 1: unmasked interrupt generated Raw interrupt status for CDIRQ timer0: CDIRQ0 3 0x0 0: no interrupt pending 1: unmasked interrupt generated Raw interrupt status for CYCIRQ timer2: CYCIRQ2 2 0x0 0: no interrupt pending 1: unmasked interrupt generated Raw interrupt status for CYCIRQ timer1: CYCIRQ1 1 0x0 0: no interrupt pending 1: unmasked interrupt generated Raw interrupt status for CYCIRQ timer0: CYCIRQ0 0 0x0 0: no interrupt pending 1: unmasked interrupt generated TIMMIS - PWM Timer Masked Interrupt Status Register Table 34. TIMMIS - PWM Timer Masked Interrupt Status Register Register - Name Address Type Register Function This register returns the masked interrupt status from the PWM timers 0, 1 and 2. The raw interrupt status (TIMRIS) is masked with the associated TIMCFGx.CYCIRQxMSK and PWMCFGx.CDIRQxMSK bits to get the masked interrupt status of this register. TIMMIS 0x7B R CYCIRQ - Interrupt from the timers when PWM cycle is complete (applies to the current PWM command residing in the active command register of a PWM block). CDIRQ - Interrupt from the pattern generator when PWM pattern code is complete (applies to a completed task residing in the script buffer of a PWM block). Bit - Name Bit (reserved) 7:6 Default Bit Function (reserved) Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CDIRQ timer2: CDIRQ2 5 0x0 0: no interrupt pending 1: interrupt generated Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CDIRQ timer1: CDIRQ1 4 0x0 0: no interrupt pending 1: interrupt generated Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CDIRQ timer0: CDIRQ0 3 0x0 0: no interrupt pending 1: interrupt generated Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CYCIRQ timer2: CYCIRQ2 2 0x0 0: no interrupt pending 1: interrupt generated Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 25 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com Table 34. TIMMIS - PWM Timer Masked Interrupt Status Register (continued) Register - Name Address Type Register Function Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CYCIRQ timer1: CYCIRQ1 1 0x0 0: no interrupt pending 1: interrupt generated Interrupt after masking, indicates active contribution to the interrupt ball, when set. Status for CYCIRQ timer0: CYCIRQ0 0 0x0 0: no interrupt pending 1: interrupt generated TIMIC - PWM Timer Interrupt Clear Register Table 35. TIMIC - PWM Timer Interrupt Clear Register Register - Name Address Type Register Function This register clears timer and pattern interrupts. TIMIC 0x7C W CYCIRQ - Interrupt from the timers when PWM cycle is complete (applies to the current PWM command residing in the active command register of a PWM block). CDIRQ - Interrupt from the pattern generator when PWM pattern code is complete (applies to a completed task residing in the script buffer of a PWM block). Bit - Name Bit (reserved) 7:6 CDIRQ2 5 Default Bit Function (reserved) Clears interrupt CDIRQ timer2: 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 Clears interrupt CDIRQ timer1: CDIRQ1 4 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 Clears interrupt CDIRQ timer0: CDIRQ0 3 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 Clears interrupt CYCIRQ timer2: CYCIRQ2 2 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 Clears interrupt CYCIRQ timer1: CYCIRQ1 1 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 Clears interrupt CYCIRQ timer0: CYCIRQ0 0 0: no effect 1: interrupt is cleared. Does not need to be written back to 0 PWMWP - PWM Timer Pattern Pointer Register Table 36. PWMWP - PWM Timer Pattern Pointer Register Register - Name Address Type Register Function Pointer to the pattern position inside the configuration register, which will be overwritten by the next write access to be PWMCFG register. 26 PWMWP 0x7D R/W Bit - Name Bit Default NOTE: 1 pattern consists of 2 bytes and not the byte position (low or high). It is incremented by 1 every time a full PWMCFG register access (word) is performed. Submit Documentation Feedback Bit Function Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 Table 36. PWMWP - PWM Timer Pattern Pointer Register (continued) Register - Name Address Type (reserved) 7 0x0 Register Function (reserved) 0 ≤ POINTER < 32 : timer0 patterns 0 to 31 POINTER[6:0] 6:0 0x0 32 ≤ POINTER < 64 : timer1 patterns 0 to 31 64 ≤ POINTER < 96 : timer2 patterns 0 to 31 96 ≤ POINTER < 128: not valid PWMCFG - PWM Script Register Table 37. PWMCFG - PWM Script Register Register - Name Address Type Register Function Two-byte pattern storage register for a PWM script command indexed by PWMWP. PWMWP is automatically incremented. PWMCFG 0x7E W To be applied by two consecutive parameter bytes in one I2C Write Transaction. NOTE: Auto-increment is disabled on this register. Address will stay at 0x7E for each word access. Bit - Name Bit Default Bit Function CMD[15:8] 15:8 High byte portion of a PWM script command CMD[7:0] 7:0 Low byte portion of a PWM script command INTERFACE CONTROL REGISTERS The following section describes the functions of special control registers provided for the main controller. The manufacturer code MFGCODE and the software revision number SWREV tell the main device which configuration file has to be used for this device. NOTE I2CSA and MFGCODE use the same address. They just differentiate in the access type: • • Write - I2CSA Read - MFGCODE I2CSA - I2C-Compatible ACCESS.bus 10-Bit & 7-Bit Slave Address Register Table 38. I2CSA - I2C-Compatible ACCESS.bus 10-Bit & 7-Bit Slave Address Register Register - Name Address Type I2CSA 0x80 W Bit - Name Bit Default SLAVEADDR[7:1] 7:1 (reserved) 0 0x44 Register Function I2C-compatible ACCESS.bus Slave Address. The address is internally applied after the next I2C STOP. Bit Function 10-bit & 7-bit address field for the I2C-compatible ACCESS.bus slave address (10-bit: upper three bits = 0). (reserved) MFGCODE - Manufacturer Code Register Table 39. MFGCODE - Manufacturer Code Register Register - Name Address Type MFGCODE 0x80 R Bit - Name Bit Default MFGBIT 7:0 0x00 Register Function Manufacturer code of the LM8330. Bit Function 8-bit field containing the manufacturer code. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 27 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com SWREV - Software Revision Register Table 40. SWREV - Software Revision Register Register - Name Address Type SWREV 0x81 R Bit - Name Bit Default SWBIT 7:0 0x84 Register Function Software revision code of the LM8330. NOTE: writing the SW revision with the inverted value triggers a reset (see SWRESET - Software Reset). Bit Function 8 - bit field containing the SW Revision number. SWRESET - Software Reset Table 41. SWRESET - Software Reset Register Register - Name Address Type Register Function Software reset SWRESET 0x81 W NOTE: the reset is only applied if the supplied parameter has the inverted value as SWBIT. Reading this register provides the software revision (see SWREV Software Revision Register). Bit - Name Bit SWBIT 7:0 Default Bit Function Reapply inverted value for software reset. RSTCTRL - System Reset Register This register allows resetting specific blocks of the LM8330. These bits are not self-clearing and must be written to a value of '0' to release the block specific reset. All registers associated with the block specific reset will be initialized to their default value. During an active reset of a module, the LM8330 will not block the access to the module registers. A read will return the default value, write commands may or may not be ignored. (Refer to each block-specific reset bit for additional details.) Table 42. RSTCTRL - System Reset Register Register - Name Address Type Register Function RSTCTRL 0x82 R/W Software reset of specific parts of the LM8330. Bit - Name Bit Default (reserved) 7:5 IRQRST 4 Bit Function (reserved) 0x0 Interrupt controller reset. Does not change status on IRQN ball. Only controls IRQ module register. An interrupt status register read when this bit is set will return a value of 0 even if there is an Interrupt Status bit set. Pending interrupts will be accumulated and held until IRQRST bit is released. Any interrupt can be cleared while IRQRST is active: 0: interrupt controller not reset 1: interrupt controller reset Timer reset for Timers 0, 1, 2: TIMRST 3 0x0 0: timer not reset 1: timer is reset (reserved) 2 0x0 KBDRST 1 0x0 (reserved) Keyboard interface reset: 0: keyboard is not reset 1: keyboard is reset GPIO reset: GPIRST 0 0x0 0: GPIO not reset 1: GPIO is reset. 28 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 RSTINTCLR - Clear NO Init/Power-On Interrupt Register Table 43. RSTINTCLR - Clear NO Init/Power-On Interrupt Register Register - Name Address Type RSTINTCLR 0x84 W Bit - Name Bit Default reserved 7:1 IRQCLR 0 Register Function This register is used to clear the PORIRQ Interrupt. This interrupt is set every time the device returns from RESET (either POR, HW or SW Reset). Bit Function (reserved) 1: Clears the PORIRQ Interrupt signalled in IRQST register. 0: is ignored CLKMODE - Clock Mode Register Table 44. CLKMODE - Clock Mode Register Register - Name Address Type Register Function CLKMODE 0x88 R/W Bit - Name Bit Default (reserved) 7:2 (reserved) 1:0 Writing to 00 forces the device to immediately enter sleep mode, regardless of any auto-sleep configuration. Reading this bit returns the current operating mode. NOTE: Any active PWM Outputs will be turned off when the LM8330 is transitioned from Operation Mode to Sleep Mode: MODCTL[1:0] 0x01 This register controls the current operating mode of the LM8330 device. Bit Function 00: SLEEP Mode 01: Operation Mode 1x: Future modes CLKEN - Clock Enable Register Table 45. CLKEN - Clock Enable Register Register - Name CLKEN Address Type 0x8A R/W Bit - Name Bit Default (reserved) 7:3 TIMEN 2 (reserved) 1 KBDEN 0 Register Function Controls the clock to different functional units. It is used to enable the functional blocks globally and independently. Bit Function (reserved) PWM Timer 0, 1, 2 clock enable: 0x0 0: Timer 0, 1, 2 clock disabled 1: Timer 0, 1, 2 clock enabled. (reserved) Keyboard clock enable (enables/disables key scan): 0x0 0: Keyboard clock disabled 1: Keyboard clock enabled AUTOSLIP - Auto-sleep Enable Register Table 46. AUTOSLIP - Auto-sleep Enable Register Register - Name Address Type AUTOSLP 0x8B R/W Bit - Name Bit Default (reserved) 7:1 Register Function This register controls the Auto-Sleep function of the LM8330 device. Bit Function (reserved) Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 29 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com Table 46. AUTOSLIP - Auto-sleep Enable Register (continued) Register - Name Address Type Register Function Enables automatic sleep mode after a defined activity time stored in the AUTOSLPTI register: ENABLE 0 0x00 1: Enable entering auto-sleep mode 0: Disable entering auto-sleep mode AUTOSLPTI - Auto-Sleep Time Register Table 47. AUTOSLPTI - Auto-Sleep Time Register Register - Name Address Type Register Function This register defines the activity time. If this time passes without any processing events then the device enters into sleep-mode, but only if AUTOSLP.ENABLE bit is set to 1. AUTOSLPTIL AUTOSLPTIH 0x8C 0x8D R/W Bit - Name Bit Default (reserved) 15:11 (reserved) 10:8 7:0 Values of UPTIME[10:0] match to multiples of 4ms: 0x00: no autosleep, regardless if AUTOSLP.ENABLE is set 0x01: 4ms 0x02: 8ms 0x7A: 500 ms 0xFF: 1020 ms (default after reset) 0x100: 1024 ms 0x7FF: 8188 ms UPTIME[10:8] UPTIME[7:0] 0x00 0xFF Bit Function IRQST - Interrupt Global Interrupt Status Register Table 48. IRQST - Interrupt Global Interrupt Status Register Register - Name Address Type IRQST 0x91 R Bit - Name Bit Default Register Function Returns the interrupt status from various on-chip function blocks. If any of the bits is set and an IRQN line is configured, the IRQN line is asserted active. Bit Function Supply failure on VCC. PORIRQ 7 0x1 Also power-on is considered as an initial supply failure. Therefore, after power-on, the bit is set: 0: no failure recorded 1: Failure - device was completely reset and requires re-programming. Keyboard interrupt (further key selection in keyboard module): KBDIRQ 6 (reserved) 5:4 0x0 0: inactive 1: active (reserved) Timer2 expiry (CDIRQ or CYCIRQ): TIM2IRQ 3 0x0 0: inactive 1: active Timer1 expiry (CDIRQ or CYCIRQ): TIM1IRQ 2 0x0 0: inactive 1: active Timer0 expiry (CDIRQ or CYCIRQ): TIM0IRQ 1 0x0 0: inactive 1: active GPIO interrupt (further selection in GPIO module): GPIOIRQ 0 0x0 0: inactive 1: active 30 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 GPIO FEATURE CONFIGURATION GPIO Feature Mapping The LM8330 has a flexible I/O structure which allows flexibility in the assignment of different functionality to each ball. This flexibility is implemented in several registers that are used to configure the balls for function (Keypad Matrix, Dedicated Key, GPIO, PWM, or Interrupt). Each ball can also be configured for direction, internal pull resistor, and output buffer type (full, open drain, open source). The functionality of each ball is determined according to the following configuration priority: In general the following priority is given: 1. Keypad 2. GPIO/PWM/Interrupt Each ball that is configured as part of a Keypad Matrix or Dedicated Keypad input will automatically configure the ball direction, pull resistor and output buffer type. Any ball not configured as part of the keypad matrix will be available as GPIO, PWM or interrupt output (IRQN) and must be configured accordingly. The configuration for Keypad, PGIO, PWM, or interrupt usages is defined by the following register priority: • 1st Priority: KBDSIZE • 2nd Priority: KBDDEDCFG • 3rd Priority: IOCFG • 4th Priority: GPIODIR/GPIOME/GPIOMS/IOPC When there is a conflict between any of these registers the ball will be configured according the priority above. Below are several example programming conflicts and the resulting configuration. • If KBDSIZE selects 8x8 matrix, but KBDDEDCFG selects KPX2 as a Dedicated Input Key, the KBDSIZE takes priority and the ball will be configured as a Keypad Matrix Input. • If KBDSIZE selects 8x8 matrix, but IOPC selects KPX[7:0] pins to have no pullup resistor enabled, the KBDSIZE takes priority and the pullup resistors will automatically be enabled on all KPX[7:0] pins. Likewise, the KPY[7:0] pins will be automatically configured to have no pullup or pulldown resistor enabled irregardless of the settings in the IOPC registers since that behavior is required for Keyboard Matrix Outputs (i.e. KBDSIZE has priority). • When there is a conflict between KBDSIZE settings and the GPIODIR, GPIOMS, or GPIOME settings, KBDSIZE takes priority and the pins selected as Keyboard Matrix pins are automatically configured into the proper direction, pullup/down configuration, and IO buffer configuration consistent with the required operation as matrix pins. • If the IOCFG register selects a pin to be a PWM output, but the GPIODIR register selects the pin to be an input, the IOCFG register takes priority and the pin will behave as a PWM output. Table 49. Ball Configuration Options Module connectivity BALL GPIOSEL BALLCFG 0x0 0x2 X Keypad Matrix or GPIO [7:0] KPY[7:0] X Keypad Matrix or GPIO [15:8] KPY8 0 1 KPY8/ GPIO16 KPY9 X KPY9/ GPIO17 KPY10 X KPY10/ GPIO18 0 KPY11/ GPIO19 IRQN 1 (1) (2) 0x1 KPX[7:0] KPY8/ GPIO16 - (2) - PWM2 PWM1 - PWM0 - 0x3 0x4 0x5 0x6 0x7 Reserved (1) PWM2 (2) IRQN BALLCFG 0x3 thru 0x7 are invalid and can result in indeterminate behavior. PWM2 functionality is mutally exclusive — one pin at a time only (KPY8 or KPY11) depending on interrupt enable Bit 4 of IOCFG. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 31 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com IOCGF - Input/Output Pin Mapping Configuration Register Table 50. IOCGF - Input/Output Pin Mapping Configuration Register Register - Name Address Type IOCFG 0xA7 W Bit - Name Bit Default (reserved) 7:5 GPIOSEL 4 (reserved) 3 BALLCFG 2:0 Register Function Configures usage of KPY[11:8] if not used for Keypad. (Refer to Table 49 for appropriate BALLCFG setting.) Bit Function (reserved, set to (reserved, set to zero) zero) Configures KPY11 as the IRQN output: 1= IRQN enabled 0 = BALLCFG Mapping (reserved, set to zero) Select column to configure — refer to Table 49. IOPC0 - Pull Resistor Configuration Register 0 Table 51. IOPC0 - Pull Resistor Configuration Register 0 Register - Name Address Type IOPC0 (1) OxAA R/W Bit - Name Bit Default Register Function Defines the pull resistor configuration for balls KPX[7:0]. Bit Function Resistor enable for KPX7 ball: KPX7PR[1:0] 15:14 0x2 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPX6 ball: KPX6PR[1:0] 13:12 0x2 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPX5 ball: KPX5PR[1:0] 11:10 0x2 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPX4 ball: KPX4PR[1:0] 9:8 0x2 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPX3 ball: KPX3PR[1:0] 7:6 0x2 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPX2 ball: KPX2PR[1:0] 5:4 0x2 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPX1 ball: KPX1PR[1:0] 3:2 0x2 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed (1) 32 Written values of 0x2 and 0x3 will always be read back as 0x3. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 Table 51. IOPC0 - Pull Resistor Configuration Register 0 (continued) Register - Name Address Type Register Function Resistor enable for KPX0 ball: KPX0PR[1:0] 1:0 0x2 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed IOPC1 - Pull Resistor Configuration Register 1 Table 52. IOPC1 - Pull Resistor Configuration Register 1 Register - Name Address Type IOPC1 (1) 0xAC R/W Bit - Name Bit Default Register Function Defines the pull resistor configuration for balls KPY[7:0]. Bit Function Resistor enable for KPY7 ball: KPY7PR[1:0] 15:14 0x1 00: no pull resistor at ball 01 :pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPY6 ball: KPY6PR[1:0] 13:12 0x1 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPY5 ball: KPY5PR[1:0] 11:10 0x1 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPY4 ball: KPY4PR[1:0] 9:8 0x1 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPY3 ball: KPY3PR[1:0] 7:6 0x1 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPY2 ball: KPY2PR[1:0] 5:4 0x1 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPY1 ball: KPY1PR[1:0] 3:2 0x1 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPY0 ball: KPY0PR[1:0] 1:0 0x1 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed (1) Written values of 0x2 and 0x3 will always be read back as 0x3. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 33 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com IOPC2 - Pull Resistor Configuration Register 2 Table 53. IOPC2 - Pull Resistor Configuration Register 2 Register - Name IOPC2 (1) Address Type Register Function Defines the pull resistor configuration for balls KPY[11:8]. 0xAE R/W Bit - Name Bit Default (reserved) 15:8 0x5A Bit Function (reserved) Resistor enable for KPY11 ball: KPY11PR[1:0] 7:6 0x0 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPY10 ball: KPY10PR[1:0] 5:4 0x1 00: no pull resistor at ball 01 pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPY9 ball: KPY9PR[1:0] 3:2 0x1 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed Resistor enable for KPY8 ball: KPY8PR[1:0] 1:0 0x1 00: no pull resistor at ball 01: pulldown resistor programmed 1x: pullup resistor programmed (1) Written values of 0x2 and 0x3 will always be read back as 0x3. GPIOOME0 - GPIO Open Drain Mode Enable Register 0 Table 54. GPIOOME0 - GPIO Open Drain Mode Enable Register 0 Register - Name Address Type GPIOOME0 0xE0 R/W Bit - Name Bit Default Register Function Configures KPX[7:0] for Open Drain or standard output functionality. The Open Drain drive source is configured by GPIOOMS0. Bit Function Open Drain Enable on KPX[7:0]: KPX[7:0]ODE 7:0 0x0 0: full buffer 1: open drain functionality GPIOOMS0 - GPIO Open Drain Mode Select Register 0 Table 55. GPIOOMS0 - GPIO Open Drain Mode Select Register 0 Register - Name Type GPIOOMS0 0xE1 R/W Bit - Name Bit Default KPX[7:0]ODM 34 Address 7:0 0x0 Register Function Configures the Open Drain drive source on KPX[7:0] if selected by GPIOOME0. Bit Function 0: Only nmos transistor is active in output driver stage. Output can be driven to GND or Hi-Z. 1: Only pmos transistor is active in output driver stage. Output can be driven to VCC or Hi-Z. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 GPIOOME1 - GPIO Open Drain Mode Enable Register 1 Table 56. GPIOOME1 - GPIO Open Drain Mode Enable Register 1 Register - Name Address Type GPIOOME1 0xE2 R/W Bit - Name Bit Default KPY[7:0]ODE 7:0 0x0 Register Function Configures KPY[7:0] for Open Drain or standard output functionality. The Open Drain drive source is configured by GPIOOMS1. Bit Function Open Drain Enable on KPY[7:0] 0: full buffer 1: open drain functionality GPIOOMS1 - GPIO Open Drain Mode Select Register 1 Table 57. GPIOOMS1 - GPIO Open Drain Mode Select Register 1 Register - Name Address Type GPIOOMS1 0xE3 R/W Bit - Name Bit Default KPY[7:0]ODM 7:0 0x0 Register Function Configures the Open Drain drive source on KPY[7:0] if selected by GPIOOME1. Bit Function 0: Only nmos transistor is active in output driver stage. Output can be driven to GND or Hi-Z. 1: Only pmos transistor is active in output driver stage. Output can be driven to VCC or Hi-Z. GPIOOME2 - GPIO Open Drain Mode Enable Register 2 Table 58. GPIOOME2 - GPIO Open Drain Mode Enable Register 2 Register - Name Type Register Function 0xE4 R/W Configures KPY[11:8] for Open Drain or standard output functionality. The Open Drain drive source is configured by GPIOOMS2. Bit - Name Bit Default (reserved) 7:4 0x0 GPIOOME2 Address Bit Function (reserved) Open Drain Enable on KPY[11:8]: KPY[11:8]ODE 3:0 0x8 0: full buffer 1: open drain functionality Note: IRQN ball defaults to Open Drain Mode Enable after reset. GPIOOMS2 - GPIO Open Drain Mode Select Register 2 Table 59. GPIOOMS2 - GPIO Open Drain Mode Select Register 2 Register - Name GPIOOMS2 Address Type 0xE5 R/W Bit - Name Bit Default (reserved 7:4 KPY[11:8]ODM 3:0 Register Function Configures the Open Drain drive source on KPY[11:8] if selected by GPIOOME2. Bit Function (reserved) 0x0 0: Only nmos transistor is active in output driver stage. Output can be driven to GND or Hi-Z. 1: Only pmos transistor is active in output driver stage. Output can be driven to VCC or Hi-Z. Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 35 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com GPIO DATA INPUT/OUTPUT GPIOPDATA0 - GPIO Data Register 0 Table 60. GPIOPDATA0 - GPIO Data Register 0 Register - Name Address Type Register Function This register controls GPIO Data & Mask on KPX[7:0]. GPIODATA0 0xC0 R/W If one I/O is defined as output (see Table 63), the values written to this register are masked with MASK and then applied to the associated pin. Any I/O defined as an input (see Table 63) will return the value of the associated pin regardless of the MASK value when read. Bit - Name Bit Default KPX[7:0]MASK 15:8 0x0 Bit Function Mask Bits for KPX[7:0] when configured as GPIO Output: 1: output is not masked 0: output is masked (unchanged) KPX[7:0] 7:0 0xFC KPX[7:0] Pin State when configured as GPIO: WRITE: Pin State = DATA if not Masked READ: DATA = Current Pin State GPIOPDATA1 - GPIO Data Register 1 Table 61. GPIOPDATA1 - GPIO Data Register 1 Register - Name Address Type Register Function This register controls GPIO Data & Mask on KPY[7:0]. GPIODATA1 0xC2 R/W If any I/O is defined as output (see Table 64), the value written to this register are masked with MASK and then applied to the associated pin. Any I/O defined as an input (see Table 64) will return the value of the associated pin regardless of the MASK value when read. Bit - Name Bit Default Bit Function Mask Bits for KPY[7:0] when configured as GPIO Output: KPY[7:0]MASK 15:8 0x0 1: output is not masked 0: output is masked (unchanged) KPY[7:0] 7:0 0x00 KPY[7:0] Pin State when configured as GPIO: WRITE: Pin State = DATA if not Masked READ: DATA = Current Pin State GPIOPDATA2 - GPIO Data Register 2 Table 62. GPIOPDATA2 - GPIO Data Register 2 Register - Name Address Type Register Function This register controls GPIO Data & Mask on KPY[11:8]. GPIODATA2 0xC4 R/W If any I/O is defined as an output (see Table 65) the value written to this register is masked with MASK and then applied to the associated pin. Any I/O defined as an input (see Table 65) will return the value of the associated pin regardless of the MASK value when read. Bit - Name 36 Bit Default Submit Documentation Feedback Bit Function Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 Table 62. GPIOPDATA2 - GPIO Data Register 2 (continued) Register - Name Address Type (reserved) 15:12 0x0 KPY[11:8] 11:8 0x0 Register Function (reserved) Mask Status for KPY[11:8] when enabled as GPIO: 1: Output is not masked 0: Output is masked. reserved 7:4 0x0 (reserved) KPY[11:8]DATA 3:0 0x0 KPY [11:8] Pin State when configured as GPIO : WRITE: Pin State = DATA if not Masked READ: DATA = Current Pin State GPIOPDIR0 - GPIO Port Direction Register 0 Table 63. GPIOPDIR0 - GPIO Port Direction Register 0 Register - Name Address Type GPIODIR0 0xC6 R/W Bit - Name Bit Default Register Function Port direction for KPX[7:0]. Bit Function Direction bits for KPX[7:0]: KPX[7:0]DIR 7:0 0x00 0: input mode 1: output mode GPIOPDIR1 - GPIO Port Direction Register 1 Table 64. GPIOPDIR1 - GPIO Port Direction Register 1 Register - Name Address Type Register Function GPIODIR1 0xC7 R/W Port direction for KPY[7:0] Bit - Name Bit Default Bit Function Direction bits for KPY[7:0]: KPY[7:0]DIR 7:0 0x00 0: input mode 1: output mode GPIOPDIR2 - GPIO Port Direction Register 2 Table 65. GPIOPDIR2 - GPIO Port Direction Register 2 Register - Name Address Type GPIODIR2 0xC8 R/W Bit - Name Bit Default (reserved) 7:4 KPY[11:8]DIR 3:0 Register Function Port direction for KPY[11:8]: Bit Function (reserved) Direction bits for KPY[11:8] 0x08 0: input mode 1: output mode GPIO INTERRUPT CONTROL GPIOIS0 - Interrupt Sense Configuration Register 0 Table 66. GPIOIS0 - Interrupt Sense Configuration Register 0 Register - Name Address Type GPIOIS0 0xC9 R/W Bit - Name Bit Default Register Function Interrupt type on KPX[7:0]. Bit Function Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 37 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com Table 66. GPIOIS0 - Interrupt Sense Configuration Register 0 (continued) Register - Name Address Type Register Function Interrupt type bits for KPX[7:0]: KPX[7:0]IS 7:0 0x0 0: edge sensitive interrupt 1: level sensitive interrupt GPIOIS1 - Interrupt Sense Configuration Register 1 Table 67. GPIOIS1 - Interrupt Sense Configuration Register 1 Register - Name Address Type GPIOIS1 0xCA R/W Bit - Name Bit Default KPY[7:0]IS 7:0 0x0 Register Function Interrupt type on KPY[7:0] Bit Function Interrupt type bits for KPY[7:0]: 0: edge sensitive interrupt 1: level sensitive interrupt GPIOIS2 - Interrupt Sense Configuration Register 2 Table 68. GPIOIS2 - Interrupt Sense Configuration Register 2 Register - Name Address Type GPIOIS2 0xCB R/W Bit - Name Bit Default (reserved) 7:4 Register Function Interrupt type on KPY[11:8] Bit Function (reserved) Interrupt type bits for KPY[11:8]: KPY[11:8]IS 3:0 0x0 0: edge sensitive interrupt 1: level sensitive interrupt GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0 Table 69. GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0 Register - Name Address Type Register Function Defines whether an interrupt on KPX[7:0] is triggered on either edge or on a single edge. See Table 72 for the edge configuration. GPIOIBE0 0xCC R/W Bit - Name Bit Default Bit Function Interrupt both edges bits for KPX[7:0]: KPX[7:0]IBE 7:0 0x0 0: interrupt generated at the active edge 1: interrupt generated after either edge. GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1 Table 70. GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1 Register - Name Address Type Register Function GPIOIBE1 0xCD R/W Defines whether an interrupt on KPY[7:0] is triggered on either edge or on a single edge. See Table 73 for the edge configuration. Bit - Name Bit Default Bit Function Interrupt both edges bits for KPY[7:0]: KPY[7:0]IBE 7:0 0x0 0: interrupt generated at the active edge. 1: interrupt generated after either edge. 38 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2 Table 71. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2 Register - Name Address Type Register Function GPIOIBE2 0xCE R/W Defines whether an interrupt on KPY[11:8] was triggered on either edge or on a single edge. See Table 74 for the edge configuration. Bit - Name Bit Default Bit Function (reserved 7:4 KPY[11:8]IBE 3:0 (reserved) Interrupt both edges bits for KPY[11:8]: 0x0 0: interrupt generated at the active edge. 1: interrupt generated after either edge. GPIOIEV0 - GPIO Interrupt Edge Select Register 0 Table 72. GPIOIEV0 - GPIO Interrupt Edge Select Register 0 Register - Name Address Type Register Function GPIOIEV0 Bit - Name 0xCF R/W Select Interrupt edge for KPX[7:0]. Bit Default Bit Function Interrupt edge select from KPX[7:0]: KPX[7:0]EV 7:0 0xFF 0: interrupt at low level or falling edge 1: interrupt at high level or rising edge GPIOIEV1 - GPIO Interrupt Edge Select Register 1 Table 73. GPIOIEV1 - GPIO Interrupt Edge Select Register 1 Register - Name Address Type Register Function GPIOIEV1 0xD0 R/W Select Interrupt edge for KPY[7:0]. Bit - Name Bit Default Bit Function Interrupt edge select from KPY[7:0]: KPY[7:0]EV 7:0 0xFF 0: interrupt at low level or falling edge 1: interrupt at high level or rising edge GPIOIEV2 - GPIO Interrupt Edge Select Register 2 Table 74. GPIOIEV2 - GPIO Interrupt Edge Select Register 2 Register - Name Address Type Register Function GPIOIEV2 0xD1 R/W Select Interrupt edge for KPY[11:8]. Bit - Name Bit Default (reserved) 7:4 KPY[11:8]EV 3:0 Bit Function (reserved) Interrupt edge select from KPY[11:8]: 0xFF 0: interrupt at low level or falling edge 1: interrupt at high level or rising edge GPIOIE0 - GPIO Interrupt Enable Register 0 Table 75. GPIOIE0 - GPIO Interrupt Enable Register 0 Register - Name Address Type GPIOIE0 0xD2 R/W Bit - Name Bit Default Register Function Enable/disable interrupts on KPX[7:0]. Bit Function Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 39 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com Table 75. GPIOIE0 - GPIO Interrupt Enable Register 0 (continued) Register - Name Address Type Register Function Interrupt enable on KPX[7:0]: KPX[7:0]IE 7:0 0x0 0: disable interrupt 1: enable interrupt GPIOIE1 - GPIO Interrupt Enable Register 1 Table 76. GPIOIE1 - GPIO Interrupt Enable Register 1 Register - Name Address Type GPIOIE1 0xD3 R/W Bit - Name Bit Default KPY[7:0]IE 7:0 0x0 Register Function Enable/disable interrupts on KPY[7:0]. Bit Function Interrupt enable on KPY[7:0]: 0: disable interrupt 1: enable interrupt GPIOIE2 - GPIO Interrupt Enable Register 2 Table 77. GPIOIE2 - GPIO Interrupt Enable Register 2 Register - Name Address Type GPIOIE2 0xD4 R/W Bit - Name Bit Default (reserved) 7:4 Register Function Enable/disable interrupts on KPY[11:8]. Bit Function (reserved) Interrupt enable on KPY[11:8]: KPY[11:8]IE 3:0 0x0 0: disable interrupt 1: enable interrupt GPIOIC0 - GPIO Clear Interrupt Register 0 Table 78. GPIOIC0 - GPIO Clear Interrupt Register 0 Register - Name Address Type GPIOIC0 0xDC W Bit - Name Bit Default KPX[7:0]IC 7:0 Register Function Clears the interrupt on KPX[7:0]. Bit Function Clear Interrupt on KPX[7:0]: 0: no effect 1: Clear corresponding interrupt GPIOIC1 - GPIO Clear Interrupt Register 1 Table 79. GPIOIC1 - GPIO Clear Interrupt Register 1 Register - Name Address Type GPIOIC1 0xDD W Bit - Name Bit Default Register Function Clears the interrupt on KPY[7:0]. Bit Function Clear Interrupt on KPY[7:0]: KPY[7:0]IC 7:0 0: no effect 1: Clear corresponding interrupt 40 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 GPIOIC2 - GPIO Clear Interrupt Register 2 Table 80. GPIOIC2 - GPIO Clear Interrupt Register 2 Register - Name Address Type GPIOIC2 0xDE W Bit - Name Bit Default (reserved) 7:4 KPY[11:8]IC 3:0 Register Function Clears the interrupt on KPY[11:8]. Bit Function (reserved) Clear Interrupt on KPY[11:8]: 0: no effect 1: Clear corresponding interrupt GPIO INTERRUPT STATUS GPIORIS0 - Raw Interrupt Status Register 0 Table 81. GPIORIS0 - Raw Interrupt Status Register 0 Register - Name Address Type GPIORIS0 0xD6 R Bit - Name Bit Default Register Function Raw interrupt status on KPX[7:0] Bit Function Raw Interrupt status data on KPX[7:0]: KPX[7:0]RIS 7:0 0x0 0: no interrupt condition at GPIO 1: interrupt condition at GPIO GPIORIS1 - Raw Interrupt Status Register 1 Table 82. GPIORIS1 - Raw Interrupt Status Register 1 Register - Name Address Type GPIORIS1 0xD7 R Bit - Name Bit Default KPY[7:0]RIS 7:0 0x0 Register Function Raw interrupt status on KPY[7:0]. Bit Function Raw Interrupt status data on KPY[7:0]: 0: no interrupt condition at GPIO 1: interrupt condition at GPIO GPIORIS2 - Raw Interrupt Status Register 2 Table 83. GPIORIS2 - Raw Interrupt Status Register 2 Register - Name Address Type GPIORIS2 0xD8 R Bit - Name Bit Default (reserved) 7:4 Register Function Raw interrupt status on KPY[11:8]. Bit Function (reserved) Raw Interrupt status data on KPY[11:8]: KPY[11:8]RIS 3:0 0x0 0: no interrupt condition at GPIO 1: interrupt condition at GPIO GPIOMIS0 - Masked Interrupt Status Register 0 Table 84. GPIOMIS0 - Masked Interrupt Status Register 0 Register - Name Address Type GPIOMIS0 0xD9 R Bit - Name Bit Default Register Function Masked interrupt status on KPX[7:0]. Bit Function Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 41 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com Table 84. GPIOMIS0 - Masked Interrupt Status Register 0 (continued) Register - Name Address Type Register Function Masked Interrupt status data on KPX[7:0]: KPX[7:0]MIS 7:0 0x0 0: no interrupt contribution from GPIO 1: interrupt GPIO is active GPIOMIS1 - Masked Interrupt Status Register 1 Table 85. GPIOMIS1 - Masked Interrupt Status Register 1 Register - Name Address Type GPIOMIS1 0xDA R Bit - Name Bit Default KPY[7:0]MIS 7:0 0x0 Register Function Masked interrupt status on KPY[7:0]. Bit Function Masked Interrupt status data on KPY[7:0]: 0: no interrupt contribution from GPIO 1: interrupt GPIO is active GPIOMIS2 - Masked Interrupt Status Register 2 Table 86. GPIOMIS2 - Masked Interrupt Status Register 2 Register - Name Address Type GPIOMIS2 0xDB R Bit - Name Bit Default (reserved) 7:4 Register Function Masked interrupt status on KPY[11:8]. Bit Function (reserved) Masked Interrupt status data on KPY[11:8]: KPY[11:8]MIS 3:0 0x0 0: no interrupt contribution from GPIO 1: interrupt GPIO is active GPIO WAKE-UP CONTROL GPIOWAKE0 - GPIO Wake-Up Register 0 Table 87. GPIOWAKE0 - GPIO Wake-Up Register 0 Register - Name Address Type GPIOWAKE0 0xE9 R/W Bit - Name Bit Default KPX[7:0]WAKE 7:0 0x0 Register Function Configures wake-up conditions for KPX[7:0]. Each bit corresponds to a ball. When a bit is set, the corresponding ball contributes to wakeup from auto-sleep mode. Bit Function Wake up from auto sleep on KPY[7:0] 0: wake up from auto sleep disabled 1: wake up from auto sleep enabled GPIOWAKE1 - GPIO Wake-Up Register 1 Table 88. GPIOWAKE1 - GPIO Wake-Up Register 1 Register - Name Address Type Register Function Configures wake-up conditions for KPY[7:0]. GPIOWAKE1 0xEA R/W Bit - Name Bit Default KPY[7:0]WAKE 42 7:0 0x0 Each bit corresponds to a ball. When a bit is set, the corresponding ball contributes to wakeup from auto-sleep mode. Bit Function Wake up from Auto sleep on KPY[7:0] 0: wake up from auto sleep disabled 1: wake up from auto sleep enabled Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 GPIOWAKE2 - GPIO Wake-Up Register 2 Table 89. GPIOWAKE2 - GPIO Wake-Up Register 2 Register - Name Address Type GPIOWAKE2 0xEB R/W Bit - Name Bit Default (reserved) 7:4 KPY[11:8]WAKE 3:0 Register Function Configures wake-up conditions for KPY[11:8]. Each bit corresponds to a ball. When a bit is set, the corresponding ball contributes to wakeup from auto-sleep mode. Bit Function (reserved) 0x0 Wake up from auto sleep on KPY[11:8] 0: wake up from auto sleep disabled 1: wake up from auto sleep enabled REGISTERS REGISTER MAPPING Registers defined as word access size must have both the lower and upper bytes written in one ACCESS.Bus cycle before the internal register will be updated. If these registers are written as separate bytes, the value will be discarded, and the internal register will be unchanged. Registers defined as byte access can be written individually. Keyboard Registers shows the register map for keyboard functionality. In addition to RESET_N,POR or Software Reset using SWRESET (see Table 41) or Software Reset using SWRESET (see Table 41), these registers are reset to default values by a module reset using RSTCTRL.KBDRST and should be rewritten for desired settings (see Table 42). Register Map for Keyboard Functionality Register Name Description Register File Address Register Type ACCESS Size Default value Next RF Address KBDSETTLE Keypad Settle Time 0x01 R/W byte 0x80 0x02 KBDBOUNCE Keypad Debounce Time 0x02 R/W byte 0x80 0x03 KBDSIZE Keypad Size Configuration 0x03 R/W byte 0x22 0x04 KBDDEDCFG0 Keypad Dedicated Key 0 0x04 R/W byte 0xFF 0x05 KBDDEDCFG1 Keypad Dedicated Key 1 0x05 R/W byte 0xFF 0x06 KBDRIS Keypad Raw Interrupt Status 0x06 R byte 0x00 0x07 KBDMIS Keypad Masked Interrupt Status 0x07 R byte 0x00 0x08 KBDIC Keypad Interrupt Clear 0x08 W byte KBDMSK Keypad Interrupt Mask 0x09 R/W byte 0x03 0x0A KBDCODE0 Keypad Code 0 0x0B R byte 0x7F 0x0C KBDCODE1 Keypad Code 1 0x0C R byte 0x7F 0x0D KBDCODE2 Keypad Code 2 0x0D R byte 0x7F 0x0E KBDCODE3 Keypad Code 3 0x0E R byte 0x7F 0x0F EVTCODE Key Event Code 0x10 R byte 0x7F 0x10 0x09 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 43 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com PWM Timer Registers shows the register map for PWM Timer functionality. In addition to RESET_N, POR and software reset using SWRESET (see Table 41), these registers are reset to default values by a module reset using RSTCTRL.TIMRST (see RSTCTRL - System Reset Register). Register Map for PWM Timer Functionality Register Name Description Register File Address Register Type ACCESS Size Default value Next RF Address TIMCFG0 PWM Timer Configuration 0 0x60 R/W byte 0x00 0x61 PWMCFG0 PWM Configuration 0 0x61 R/W byte 0x00 0x62 TIMCFG1 PWM Timer Configuration 1 0x68 R/W byte 0x00 0x69 PWMCFG1 PWM Configuration 1 0x69 R/W byte 0x00 0x6A TIMCFG2 PWM Timer Configuration 2 0x70 R/W byte 0x00 0x71 PWMCFG2 PWM Configuration 2 0x71 R/W byte 0x00 0x72 TIMSWRES PWM Timer SW Reset 0x78 W byte TIMRIS PWM Timer Interrupt Status 0x7A R byte 0x00 0x7B TIMMIS PWM Timer Masked Int. Status 0x7B R byte 0x00 0x7C TIMIC Timer Interrupt Clear 0x7C W byte PWMWP PWM Command Write Pointer 0x7D R/W byte PWMCFG PWM Command Script 0x7E W word 0x79 0x7D 0x00 0x7E 0x7F System Registers shows the register map for general system registers. These registers are not affected by any of the module resets addressed by RSTCTRL (see Table 42). These registers can only be reset to default values by a Global Call Reset (see GENERAL CALL RESET) or by a complete Software Reset using SWRESET (see Table 41). Register Map for System Control Functionality 44 Register Name Description Register File Address Register Type ACCESS Size Default value Next RF Address I2CSA I2C-compatible ACCESS.bus Slave Address 0x80 W byte 0x88 0x81 MFGCODE Manufacturer Code 0x80 R byte 0x00 0x81 SWREV SW Revision 0x81 R byte 0x84 0x82 SWRESET SW Reset 0x81 W byte RSTCTRL System Reset 0x82 R/W byte RSTINTCLR Clear No Init/Power On Interrupt 0x84 W byte CLKMODE Clock Mode 0x88 R/W byte 0x00 0x82 0x00 0x83 0x85 0x89 CLKEN Clock Enable 0x8A R/W byte 0x00 0x8B AUTOSLP Auto-Sleep Enable 0x8B R/W byte 0x00 0x8C AUTOSLPTI Auto-Sleep Time 0x8C R/W word 0x00FF 0x8D Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 Global Interrupt Registers shows the register map for global interrupt functionality. This register is reset to the default value by RESET_N, POR or Software Reset using SWRESET (see Table 41). This register is not affected by a module reset using RSTCTRL.IRQRST (see Table 42). Any interrupt that occurs while RSTCTRL.IRQRST is active will still be captured. Register Map for Global Interrupt Functionality Register Name IRQST Description Register File Address Register Type ACCESS Size Default value Next RF Address Global Interrupt Status 0x91 R byte 0x80 0x92 GPIO Registers shows the register map for GPIO functionality. In addition to RESET_N, POR and software reset using SWRESET (see Table 41), these registers are reset to default values by a module reset using RSTCTRL.GPIRST (see Table 42). Register Map for GPIO Functionality Register Name Description Register File Address Register Type ACCESS Size IOCFG I/O Pin Mapping Configuration 0xA7 W byte IOPC0 Pull Resistor Configuration 0 0xAA R/W word 0xAAAA 0xAB IOPC1 Pull Resistor Configuration 1 0xAC R/W word 0x5555 0xAD IOPC2 Pull Resistor Configuration 2 0xAE R/W word 0x5A15 0xAF 0xFC 0xC1 GPIODATA0 GPIO I/O Data 0 0xC0 R/W byte GPIOMASK0 GPIO I/O Mask 0 0xC1 W byte GPIODATA1 GPIO I/O Data 1 0xC2 R/W byte GPIOMASK1 GPIO I/O Mask 1 0xC3 W byte Default value Next RF Address 0xA8 0xC2 0x00 0xC3 0xC4 GPIODATA2 GPIO I/O Data 2 0xC4 R/W byte GPIOMASK2 GPIO I/O Mask 2 0xC5 W byte 0x00 0xC5 GPIODIR0 GPIO I/O Direction 0 0xC6 R/W byte 0x00 0xC7 GPIODIR1 GPIO I/O Direction 1 0xC7 R/W byte 0x00 0xC8 GPIODIR2 GPIO I/O Direction 2 0xC8 R/W byte 0x08 0xC9 GPIOIS0 GPIO Int Sense Config 0 0xC9 R/W byte 0x00 0xCA GPIOIS1 GPIO Int Sense Config 1 0xCA R/W byte 0x00 0xCB GPIOIS2 GPIO Int Sense Config 2 0xCB R/W byte 0x00 0xCC GPIOIBE0 GPIO Int Both Edges Config 0 0xCC R/W byte 0x00 0xCD GPIOIBE1 GPIO Int Both Edges Config 1 0xCD R/W byte 0x00 0xCE GPIOIBE2 GPIO Int Both Edges Config 2 0xCE R/W byte 0x00 0xCF GPIOIEV0 GPIO Int Edge Select 0 0xCF R/W byte 0xFF 0xD0 GPIOIEV1 GPIO Int Edge Select 1 0xD0 R/W byte 0xFF 0xD1 0xC6 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 45 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com Register Map for GPIO Functionality (continued) Register Name Description Register File Address Register Type ACCESS Size Default value Next RF Address GPIOIEV2 GPIO Int Edge Select 2 0xD1 R/W byte 0x0F 0xD2 GPIOIE0 GPIO Interrupt Enable 0 0xD2 R/W byte 0x00 0xD3 GPIOIE1 GPIO Interrupt Enable 1 0xD3 R/W byte 0x00 0xD4 GPIOIE2 GPIO Interrupt Enable 2 0xD4 R/W byte 0x00 0xD5 GPIORIS0 GPIO Raw Int Status 0 0xD6 R byte 0x00 0xD7 GPIORIS1 GPIO Raw Int Status 1 0xD7 R byte 0x00 0xD8 GPIORIS2 GPIO Raw Int Status 2 0xD8 R byte 0x00 0xD9 GPIOMIS0 GPIO Masked Int Status 0 0xD9 R byte 0x00 0xDA GPIOMIS1 GPIO Masked Int Status 1 0xDA R byte 0x00 0xDB GPIOMIS2 GPIO Masked Int Status 2 0xDB R byte 0x00 0xDC GPIOIC0 GPIO Interrupt Clear 0 0xDC W byte 0xDD GPIOIC1 GPIO Interrupt Clear 1 0xDD W byte 0xDE GPIOIC2 GPIO Interrupt Clear 2 0xDE W byte 0xDF GPIOOME0 GPIO Open Drain Mode Enable 0 0xE0 R/W byte 0x00 0xE1 GPIOOMS0 GPIO Open Drain Mode Select 0 0xE1 R/W byte 0x00 0xE2 GPIOOME1 GPIO Open Drain Mode Enable 1 0xE2 R/W byte 0x00 0xE3 GPIOOMS1 GPIO Open Drain Mode Select 1 0xE3 R/W byte 0x00 0xE4 GPIOOME2 GPIO Open Drain Mode Enable 2 0xE4 R/W byte 0x08 0xE5 GPIOOMS2 GPIO Open Drain Mode Select 2 0xE5 R/W byte 0x00 0xE6 GPIOWAKE0 GPIO Wakeup Enable 0 0xE9 R/W byte 0x00 0xEA GPIOWAKE1 GPIO Wakeup Enable 1 0xEA R/W byte 0x00 0xEB GPIOWAKE2 GPIO Wakeup Enable 2 0xEB R/W byte 0x00 0xEC REGISTER LAYOUT - Control Bits in LM8330 Registers Register Addr. KBDSETTLE 0x01 KBDBOUNCE 0x02 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COLSIZE3 COLSIZE2 COLSIZE1 COLSIZE0 Wait[7:0] Wait[7:0] ROWSIZE3 ROWSIZE2 ROWSIZE1 ROWSIZE0 KBDSIZE 0x03 KBDDEDCFG0 0x04 COL9 COL8 COL7 COL6 COL5 COL4 COL3 COL2 KBDDEDCFG1 0x05 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 COL11 COL10 KBDRIS 0x06 RELINT REVTINT RKLINT RSINT 46 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 REGISTER LAYOUT - Control Bits in LM8330 Registers (continued) Register Addr. KBDMIS 0x07 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MELINT MEVTINT MKLINT MSINT EVTIC KBDIC MSKELINT MSKEINT MSKLINT MSKSINT KBDIC 0x08 KBDMSK 0x09 KBDCODE0 0x0B MULTIKEY KEYROW2 KEYROW1 KEYROW0 KEYCOL3 KEYCOL2 KEYCOL1 KEYCOL0 KBDCODE1 0x0C MULTIKEY KEYROW2 KEYROW1 KEYROW0 KEYCOL3 KEYCOL2 KEYCOL1 KEYCOL0 KBDCODE2 0x0D MULTIKEY KEYROW2 KEYROW1 KEYROW0 KEYCOL3 KEYCOL2 KEYCOL1 KEYCOL0 KBDCODE3 0x0E MULTIKEY KEYROW2 KEYROW1 KEYROW0 KEYCOL3 KEYCOL2 KEYCOL1 KEYCOL0 EVTCODE 0x10 RELEASE KEYROW2 KEYROW1 KEYROW0 KEYCOL3 KEYCOL2 KEYCOL1 KEYCOL0 TIMCFG0 0x60 PWMCFG0 0x61 TIMCFG1 0x68 PWMCFG1 0x69 TIMCFG2 0x70 PWMCFG2 0x71 SFOFF CYCIRQ0MASK START CDIRQ0MASK PGE PWMEN CYCIRQ1MASK PWMPOL START CDIRQ1MASK PGE PWMEN CYCIRQ2MASK PWMPOL START CDIRQ2MASK PGE PWMEN PWMPOL TIMSWRES 0x78 SWRES2 SWRES1 SWRES0 TIMRIS 0x7A CDIRQ2 CDIRQ1 CDIRQ0 CICIRQ2 CICIRQ1 CICIRQ0 TIMMIS 0x7B CDIRQ2 CDIRQ1 CDIRQ0 CICIRQ2 CICIRQ1 CICIRQ0 TIMIC 0x7C CDIRQ2 CDIRQ1 CDIRQ0 CICIRQ2 CICIRQ1 CICIRQ0 PWMWP 0x7D PWMCFG(Low ) 0x7E CMD[7:0] PWMCFG(Hig h) 0x7F CMD[15:8] I2CSA 0x80 MFGCODE 0x80 MFGBIT[7:0] SWREV 0x81 SWBIT[7:0] SWRESET 0x81 RSTCTRL 0x82 RSTINTCLR 0x84 CLKMODE 0x88 CLKEN 0x8A AUTOSLP 0x8B AUTOSLPTI (Low) 0x8C AUTOSLPTI (High) 0x8D IRQST 0x91 IOCFG 0xA7 0 PWMWP[6:0] SLAVEADDR[7:1] 0 SWBIT[7:0] IRQRST TIMRST KBDRST GPIRST IRQCLR MOD-CTL[1:0] TIMEN KBDEN ENABLE UP-TIME [7:0] UP-TIME [15:8] PORIRQ KBD1RQ TIM2IRQ TIM1IRQ TIM01RQ GPIIRQ IOCFGPM [7:0] IOPC0 (Low) 0xAA KPX3PR[1:0] KPX2PR[1:0] KPX1PR[1:0] KPX0PR[1:0] IOPC0 (High) 0xAB KPX7PR[1:0] KPX6PR[1:0] KPX5PR[1:0] KPX4PR[1:0] IOPC1 (Low) 0xAC KPY3PR[1:0] KPY2PR[1:0] KPY1PR[1:0] KPY0PR[1:0] IOPC1 (High) 0xAD KPY7PR[1:0] KPY6PR[1:0] KPY5PR[1:0] KPY4PR[1:0] IOPC2 (Low) 0xAE KPY11PR[1:0] KPY10PR[1:0] KPY9PR[1:0] KPY8PR[1:0] IOPC2 (High) 0xAF reserved Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 47 LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com REGISTER LAYOUT - Control Bits in LM8330 Registers (continued) Register Addr. BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GPIODATA0 0xC0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GPIOMASK0 0xC1 MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0 GPIODATA1 0xC2 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 GPIOMASK1 0xC3 MASK15 MASK14 MASK13 MASK12 MASK11 DATA10 DATA9 DATA8 GPIODATA2 0xC4 DATA19 DATA18 DATA17 DATA16 GPIOMASK2 0xC5 MASK19 MASK18 MASK17 MASK16 GPIODIR0 0xC6 KPX7DIR KPX6DIR KPX5DIR KPX4DIR KPX3DIR KPX2DIR KPX1DIR KPX0DIR GPIODIR1 0xC7 KPY7DIR KPY6DIR KPY5DIR KPY4DIR KPY3DIR KPY2DIR KPY1DIR KPY0DIR GPIODIR2 0xC8 KP11DIR KPY10DIR KPY9DIR KPY8DIR GPIOIS0 0xC9 KPX7IS KPX6IS KPX5IS KPX4IS KPX3IS KPX2IS KPX1IS KPX0IS GPIOIS1 0xCA KPY7IS KPY6IS KPY5IS KPY4IS KPY3IS KPY2IS KPY1IS KPY0IS GPIOIS2 0xCB KPY11IS KPY10IS KPY9IS KPY8IS GPIOIBE0 0xCC KPX7IBE KPX6IBE KPX5IBE KPX4IBE KPX3IBE KPX2IBE KPX1IBE KPX0IBE GPIOIBE1 0xCD KPY7IBE KPY6IBE KPY5IBE KPY4IBE KPY3IBE KPY2IBE KPY1IBE KPY0IBE GPIOIBE2 0xCE KPY11IBE KPY10IBE KPY9IBE KPY8IBE GPIOIEV0 0xCF KPX7EV KPX6EV KPX5EV KPX4EV KPX3EV KPX2EV KPX1EV KPX0EV GPIOIEV1 0xD0 KPY7EV KPY6EV KPY5EV KPY4EV KPY3EV KPY2EV KPY1EV KPY0EV GPIOIEV2 0xD1 KPY11IEV KPY10IEV KPY9IEV KPY8IEV GPIOIE0 0xD2 KPX7IE KPX6IE KPX5IE KPX4IE KPX3IE KPX2IE KPX1IE KPX0IE GPIOIE1 0xD3 KPY7IE KPY6IE KPY5IE KPY4IE KPY3IE KPY2IE KPY1IE KPY0IE GPIOIE2 0xD4 KPY11IE KPY10IE KPY9IE KPY8IE GPIORIS0 0xD6 KPX7RIS KPX6RIS KPX5RIS KPX4RIS KPX3RIS KPX2RIS KPX1RIS KPX0RIS GPIORIS1 0xD7 KPY7RIS KPY6RIS KPY5RIS KPY4RIS KPY3RIS KPY2RIS KPY1RIS KPY0RIS GPIORIS2 0xD8 KPY11RIS KPY10RIS KPY9RIS KPY8RIS GPIOMIS0 0xD9 KPX7MIS KPX6MIS KPX5MIS KPX4MIS KPX3MIS KPX2MIS KPX1MIS KPX0MIS GPIOMIS1 0xDA KPY7MIS KPY6MIS KPY5MIS KPY4MIS KPY3MIS KPY2MIS KPY1MIS KPY0MIS GPIOMIS2 0xDB KPY11MIS KPY10MIS KPY9MIS KPY8MIS GPIOIC0 0xDC KPX7IC KPX6IC KPX5IC KPX4IC KPX3IC KPX2IC KPX1IC KPX0IC GPIOIC1 0xDD KPY7IC KPY6IC KPY5IC KPY4IC KPY3IC KPY2IC KPY1IC KPY0IC GPIOIC2 0xDE KPY11IC KPY10IC KPY9IC KPY8IC GPIOOME0 0xE0 KPX7ODE KPX6ODE KPX5ODE KPX4ODE KPX3ODE KPX2ODE KPX1ODE KPX0ODE GPIOOMS0 0xE1 KPX7ODM KPX6ODM KPX5ODM KPX4ODM KPX3ODM KPX2ODM KPX1ODM KPX0ODM GPIOOME1 0xE2 KPY7ODE KPY6ODE KPY5ODE KPY4ODE KPY3ODE KPY2ODE KPY1ODE KPY0ODE GPIOOMS1 0xE3 KPY7ODM KPY6ODM KYY5ODM KPY4ODM KPY3ODM KPY2ODM KPY1ODM KPY0ODM GPIOOME2 0xE4 KPY11 ODE KPY10 ODE KPY9 ODE KPY8 ODE GPIOOMS2 0xE5 KPY11 ODM KPY10 ODM KPY9 ODM KPY8 ODM GPIOWAKE0 0xE9 KPX7 WAKE KPX6 WAKE KPX5 WAKE KPX4 WAKE KPX3 WAKE KPX2 WAKE KPX1 WAKE KPX0 WAKE GPIOWAKE1 0xEA KPY7 WAKE KPY6 WAKE KPY5 WAKE KPY4 WAKE KPY3 WAKE KPY2 WAKE KPY1 WAKE KPY0 WAKE GPIOWAKE2 0xEB KPY11 WAKE KPY10 WAKE KPY9 WAKE KPY8 WAKE 48 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 LM8330 www.ti.com SNVS839A – JUNE 2012 – REVISED MARCH 2013 REVISION HISTORY Changes from Original (March 2013) to Revision A • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 45 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 49 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) LM8330TME NOPB ACTIVE LM8330TME/NOPB ACTIVE LM8330TMX NOPB ACTIVE LM8330TMX/NOPB ACTIVE Package Type Package Pins Package Drawing Qty 25 DSBGA YFQ 25 250 25 DSBGA YFQ 25 3000 Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) TBD Call TI Call TI Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TBD Call TI Call TI Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (4) -30 to 85 8330 -30 to 85 8330 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM8330TME/NOPB DSBGA YFQ 25 250 178.0 8.4 LM8330TMX/NOPB DSBGA YFQ 25 3000 178.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.08 2.08 0.76 4.0 8.0 Q1 2.08 2.08 0.76 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM8330TME/NOPB DSBGA YFQ LM8330TMX/NOPB DSBGA YFQ 25 250 210.0 185.0 35.0 25 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YFQ0025xxx D 0.600 ±0.075 E TMD25XXX (Rev C) D: Max = 2.04 mm, Min = 1.98 mm E: Max = 2.04 mm, Min = 1.98 mm 4215084/A NOTES: A. All linear dimensions are in millimeters. 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